Starting circuit adopting charge pump to drive two-stage NMOS (N-channel metal oxide semiconductor) to realize reverse flow prevention and backward flow prevention of power supply

Abstract

The invention discloses a starting circuit adopting a charge pump to drive a two-stage NMOS (N-channel metal oxide semiconductor) to realize reverse and backward flow prevention of a power supply, which comprises a two-stage NMOS reverse and backward flow prevention circuit module, a gate drive control circuit module, a charge pump charging circuit module, a power supply starting switch circuit module, a power supply input VIN, a power supply output VOUT and a switch SW, the two-stage NMOS anti-reverse and anti-backflow circuit module is used for preventing current from flowing backwards to impact an input power supply; the gate drive control circuit module is used for controlling the on and off of the two-stage NMOS; the charge pump charging circuit module is used for providing a voltage higher than VIN for the grid electrode of the two-stage NMOS so as to ensure that the two-stage NMOS can be normally conducted during working; and the power supply starting switch circuit is used for receiving high and low level switching signals input by the SW to realize the work of the power supply starting circuit of the controller so as to control the conduction of the two-stage NMOS. Compared with a single-stage NMOS (N-channel Metal Oxide Semiconductor) circuit in a shutdown state, the leakage current is lower, and the starting speed is higher; and heating is weaker than that of a PMOS circuit.

Description

Technical Field

[0001] This invention relates to the field of engine controller hardware circuit technology, mainly to control the power input startup process of the engine controller, and in particular to a startup circuit that uses a charge pump to drive a dual-stage NMOS to achieve power reverse and backflow prevention. Background Technology

[0002] Current engine controllers typically use either a single-stage NMOS or a dual-stage PMOS transistor for input power. Using a single-stage NMOS transistor results in high leakage current when the controller is off due to control logic limitations. Using a dual-stage PMOS transistor, limitations in manufacturing processes prevent the PMOS on-resistance from being as low as that of the NMOS transistor, leading to a large on-voltage drop and significant heat generation under high current conditions during normal operation. Designing a reverse current protection circuit effectively addresses the issue of electronic component burnout caused by reverse power connection and prevents backflow caused by energy release from internal energy storage components when the controller is powered off. Furthermore, to meet the requirements of China VII emission standards, using a dual-stage NMOS control circuit reduces overall controller power consumption and heat generation, resulting in optimal controller performance.

[0003] The above background information is provided only to aid in understanding the concept and technical solution of this invention. It does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above information was disclosed on the filing date of this patent application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0004] The main purpose of this invention is to propose a startup circuit that uses a charge pump to drive a dual-stage NMOS to prevent reverse current flow and backflow of power supply. This solves the problem of electronic components burning out due to reverse power supply connection. On the other hand, it can also prevent backflow of current caused by the release of energy by the internal energy storage element when the controller power is turned off.

[0005] Therefore, this invention proposes a startup circuit that uses a charge pump to drive a dual-stage NMOS to achieve power supply reverse and backflow prevention.

[0006] Preferably, the present invention may also have the following technical features:

[0007] A startup circuit employing a charge pump to drive a dual-stage NMOS transistor to achieve reverse current and reverse current protection includes a dual-stage NMOS reverse current and reverse current protection circuit module, a gate drive control circuit module, a charge pump charging circuit module, a power startup switch circuit module, a power input VIN, a power output VOUT, and a switch SW. The dual-stage NMOS reverse current and reverse current protection circuit module is used to prevent current reverse current from impacting the input power supply; the gate drive control circuit module is used to control the conduction and disconnection of the dual-stage NMOS transistors; the charge pump charging circuit module is used to provide a voltage higher than VIN to the gate of the dual-stage NMOS transistors to ensure that the dual-stage NMOS transistors can conduct normally during operation; the power startup switch circuit is used to receive high and low level switching signals from the SW input to enable the controller power startup circuit to operate, thereby controlling the conduction of the dual-stage NMOS transistors.

[0008] Furthermore, the dual-stage NMOS reverse-current protection circuit module includes NMOS Q1 and NMOS Q2. The source of NMOS Q1 is connected to VIN, and the drains of Q1 and Q2 are connected. The source of Q2 is connected to VOUT.

[0009] Furthermore, the gate drive control circuit module includes a first-stage circuit, a second-stage circuit, and a protection circuit. One end of the first-stage circuit is connected to the gate of Q1, and the other end is connected to the output terminal of the charge pump charging circuit module. The first-stage circuit includes resistors R2 and R8 and diode D4. The anode of diode D4 is connected to the output terminal of the charge pump charging circuit module, and the cathode is connected to resistors R8 and R2. The other end of resistor R8 is grounded (GND). The other end of resistor R2 is connected to the gate of Q1.

[0010] Furthermore, the second-stage circuit includes resistors R1, R3, R4, and R7, as well as diode D3, transistor Q3, and NMOS Q5. The source of Q5 is grounded to GND, its gate is connected to the output terminal of the power-on switch circuit module, and its drain is connected to one end of resistor R4. The other end of R4 is connected to resistor R3 and the base of transistor Q3. The collector of Q3 is connected to the gate of Q2 and resistor R1, and the other end of resistor R1 is connected to the source of Q2. The emitter of Q3 is connected to the other end of R3 and one end of resistor R7, and the other end of R7 is connected to the cathode of diode D3. The anode of diode D3 is connected to the output terminal of the charge pump charging circuit module.

[0011] Furthermore, the protection circuit includes a resistor R5, a transistor Q4, and a diode D1. The collector of the transistor Q4 is connected between the gate of Q1 and the resistor R2; the base of Q4 is connected to one end of the resistor R5, and the other end of R5 is grounded to GND; the emitter of Q4 is connected to the positive terminal of the diode D1, and the negative terminal of the diode D1 is connected between Q1 and VIN.

[0012] Furthermore, the charge pump charging circuit module includes a charging circuit and a non-0V ground circuit. The charging circuit includes an NMOS Q8, resistors R12, R11, R10, and R9, as well as a diode D5, a PMOS Q6, an inverter U1, and capacitors C1, C2, C3, and C4. The gate of the NMOS Q8 is connected to the output terminal of the power-on switch circuit module, the source is grounded to GND, and the drain is connected to one end of resistor R12. The other end of resistor R12 is connected to resistors R10 and R11. The other end of R10 is connected to the gate of the PMOS Q6, and the other end of R11 is connected to the source of the PMOS Q6. Q6 drain capacitor C3 and the VCC terminal of inverter U1. Terminal A of inverter U1 is connected to one end of capacitor C2 and resistor R9. The other end of resistor R9 is connected to the Y terminal of inverter U1. The Y terminal of inverter U1 is also connected to capacitor C1. The other end of capacitor C1 is connected to pin 3 of diode D5. The two ends of capacitor C4 are connected to pins 1 and 2 of diode D5, respectively. Pin 2 of diode D5 is also connected to diodes D3 and D4.

[0013] Furthermore, the non-0V ground circuit includes transistor Q7, resistor R13, and Zener diode D6. The GND terminal of inverter U1 is connected to the other ends of capacitors C2 and C3, and also to the emitter of transistor Q7. The base of Q7 is connected to resistor R13 and one end of Zener diode D6. The other end of D6 is connected between the drain of Q6 and C3. The collector of Q7 is connected to the other end of R13, and then grounded to GND. Generally, normal low-voltage circuits should use 0V ground, but the charge pump circuit of this invention uses a non-0V ground.

[0014] Furthermore, the diode D5 is composed of diode I and diode II connected in series, with the positive terminal of diode I being pin 1 and the negative terminal of diode II being connected to the positive terminal of diode II; the negative terminal of diode II being pin 2; and pin 3 extending from between diode I and diode II and connected to capacitor C1.

[0015] Furthermore, the working principle of the startup circuit is as follows:

[0016] STEP1: VIN power input is 24V power input, and the voltage Vo through the NMOS Q1 body diode is also 24V;

[0017] STEP2: Connect SW to high level;

[0018] STEP3: The high level on the SW pin reaches the gates of NMOS Q5 and Q8 through the ordinary diode D2 and the current-limiting resistor R6, at which point Q5 and Q8 are turned on.

[0019] STEP4: After Q8 is turned on, R12 and R11 form a series voltage divider circuit. The voltage at the intermediate node between R12 and R11 is lower than Vo. At this time, PMOS Q6 is turned on, and Vo supplies power to inverter U1. After Q5 is turned on, the base of transistor Q3 will be pulled low through the pull-down resistor R4, and transistor Q3 will be turned on.

[0020] STEP 5: Vo stabilizes the base voltage of U1 chip VCC-Q7 at a fixed value through the Zener diode D6, and stabilizes the GND voltage of U1 chip at a voltage value that is about 0.7V higher than the base voltage of Q7 through the transistor Q7.

[0021] STEP 6: When A and Y in U1 are always in opposite states, capacitor C2 will be repeatedly charged and discharged through resistor R9, forming a periodic high and low level.

[0022] STEP7: Vo forms a charging pump circuit using ordinary diodes D5, C1, and C4, which will pump the voltage at pin 1 of C4 to a higher voltage value than Vo.

[0023] STEP8: The voltage after pumping will flow to the gates of NMOS Q1 and Q2 through ordinary diodes D4 and D3. At this time, Q1 and Q2 are turned on, and the dual-stage NMOS circuit is started.

[0024] The beneficial effects of this invention compared to existing technologies include: Reverse current and reverse current protection are achieved through a dual-stage diode. When the power supply is reversed, current forms a loop through resistors R7, R2, Q3, and D1. If Q1 is conducting, Q2 is cut off, thus achieving the protection function. When the circuit is off, the energy storage element flows to Vo through the body diode of Q2, at which point Q1 is cut off, achieving the reverse current protection function. Compared to a single-stage NMOS circuit, the dual-stage NMOS circuit used in this invention has lower leakage current and faster startup speed in the off state. Compared to a dual-stage PMOS circuit, it has lower MOS power consumption and less heat generation during operation, resulting in higher overall system stability. Attached Figure Description

[0025] Figure 1 This is the circuit schematic diagram of the present invention.

[0026] Figure 2 This is a circuit topology block diagram of the present invention. Detailed Implementation

[0027] The present invention will now be described in further detail with reference to specific embodiments and the accompanying drawings. It should be emphasized that the following description is merely exemplary and is not intended to limit the scope or application of the present invention.

[0028] Non-limiting and non-exclusive embodiments will be described with reference to the following figures, wherein the same reference numerals denote the same parts unless otherwise specifically stated.

[0029] like Figures 1-2 The circuit shown employs a charge pump to drive a dual-stage NMOS transistor to achieve reverse current and reverse current protection. It includes a dual-stage NMOS reverse current and reverse current protection circuit module, a gate drive control circuit module, a charge pump charging circuit module, a power start-up switch circuit module, a power input VIN, a power output VOUT, and a switch SW. The dual-stage NMOS reverse current and reverse current protection circuit module prevents current backflow from impacting the input power supply and prevents damage to components on the board from reversed DC power connection. The gate drive control circuit module controls the on / off state of the dual-stage NMOS transistors, providing current limiting protection. The charge pump charging circuit module provides a voltage higher than VIN to the gate of the dual-stage NMOS transistors, ensuring normal conduction during operation. The power start-up switch circuit receives high and low level switching signals from the SW input, enabling the controller power start-up circuit to operate, thereby controlling the conduction of the dual-stage NMOS transistors.

[0030] The dual-stage NMOS anti-reverse and anti-backflow circuit module includes NMOS Q1 and NMOS Q2. The source of NMOS Q1 is connected to VIN, the drain of Q1 is connected to the drain of Q2, and the source of Q2 is connected to VOUT.

[0031] The gate drive control circuit module includes a first-stage circuit, a second-stage circuit, and a protection circuit. One end of the first-stage circuit is connected to the gate of Q1, and the other end is connected to the output terminal of the charge pump charging circuit module. The first-stage circuit includes resistors R2 and R8 and a diode D4. The anode of diode D4 is connected to the output terminal of the charge pump charging circuit module, and the cathode is connected to resistors R8 and R2. The other end of resistor R8 is grounded (GND). The other end of resistor R2 is connected to the gate of Q1.

[0032] The second-stage circuit includes resistors R1, R3, R4, and R7, as well as diode D3, transistor Q3, and NMOS Q5. The source of Q5 is grounded to GND, its gate is connected to the output of the power-on switch circuit module, and its drain is connected to one end of resistor R4. The other end of R4 is connected to resistor R3 and the base of transistor Q3. The collector of Q3 is connected to the gate of Q2 and resistor R1, and the other end of resistor R1 is connected to the source of Q2. The emitter of Q3 is connected to the other end of R3 and one end of resistor R7, and the other end of R7 is connected to the cathode of diode D3. The anode of diode D3 is connected to the output of the charge pump charging circuit module. When Q5 is turned on, the pull-down resistor R4 pulls the base of transistor Q3 low, at which point transistor Q3 is turned on.

[0033] The protection circuit includes a resistor R5, a transistor Q4, and a diode D1. The collector of transistor Q4 is connected between the gate of Q1 and resistor R2; the base of Q4 is connected to one end of resistor R5, and the other end of R5 is grounded (GND); the emitter of Q4 is connected to the anode of diode D1, and the cathode of diode D1 is connected between Q1 and VIN. Reverse current and reverse current protection are achieved through a double-stage diode. When the power supply polarity is reversed, current forms a loop through resistors R7, R2, Q3, and D1. In this case, if Q1 is conducting, Q2 is cut off, thus achieving the protection function.

[0034] The charge pump charging circuit module includes a charging circuit and a non-0V ground circuit. The charging circuit includes an NMOS Q8, resistors R12, R11, R10, and R9, as well as a diode D5, a PMOS Q6, an inverter U1, and capacitors C1, C2, C3, and C4. The gate of the NMOS Q8 is connected to the output terminal of the power-on switch circuit module, its source is grounded to GND, and its drain is connected to one end of resistor R12. The other end of resistor R12 is connected to resistors R10 and R11. The other end of R10 is connected to the gate of PMOS Q6, and the other end of R11 is connected to the source of PMOS Q6. The drain capacitor C3 of PMOS Q6 is connected to the VCC terminal (pin 5) of inverter U1. The A terminal (pin 2) of inverter U1 is connected to one end of capacitor C2 and resistor R9. The other end of resistor R9 is connected to the Y terminal (pin 4) of inverter U1. The Y terminal of inverter U1 is also connected to capacitor C1. The other end of capacitor C1 is connected to pin 3 of diode D5. The two ends of capacitor C4 are connected to pins 1 and 2 of diode D5, respectively. Pin 2 of diode D5 is also connected to diodes D3 and D4. Preferably, diode D5 is formed by diode I and diode II connected in series, with the anode of diode I connected to pin 1 and the cathode connected to the anode of diode II; the cathode of diode II is connected to pin 2; pin 3 extends from between diode I and diode II and is connected to capacitor C1.

[0035] Normally, an NMOS needs a gate voltage higher than the source voltage to turn on. However, in this design, the NMOS is used as a high-side power switch, and there is no voltage higher than the 24V power supply in the circuit. Therefore, a voltage pump circuit is designed using an inverter to raise the voltage, thereby starting the NMOS and ensuring that the switch is open.

[0036] The non-0V ground circuit includes transistor Q7, resistor R13, and Zener diode D6. The GND terminal of inverter U1 is connected to the other ends of capacitors C2 and C3, and also to the emitter of transistor Q7. The base of Q7 is connected to resistor R13 and one end of Zener diode D6. The other end of D6 is connected between the drain of Q6 and C3. The collector of Q7 is connected to the other end of R13, and then grounded to GND.

[0037] The power-on switch circuit includes a resistor R6 and a diode D2, wherein one end of the resistor R6 is connected to the negative terminal of the diode D2, and the other end is connected to NMOS Q8 and NMOS Q5.

[0038] Specifically, the working principle of the startup circuit is as follows:

[0039] STEP1: VIN power input is 24V power input, and the voltage Vo through the NMOS Q1 body diode is also 24V;

[0040] STEP2: Connect SW to high level;

[0041] STEP3: The high level on the SW pin reaches the gates of NMOS Q5 and Q8 through the ordinary diode D2 and the current-limiting resistor R6, at which point Q5 and Q8 are turned on.

[0042] STEP4: After Q8 is turned on, R12 and R11 form a series voltage divider circuit. The voltage at the intermediate node between R12 and R11 is lower than Vo. At this time, PMOS Q6 is turned on, and Vo supplies power to inverter U1. After Q5 is turned on, the base of transistor Q3 will be pulled low through the pull-down resistor R4, and transistor Q3 will be turned on.

[0043] STEP 5: Vo stabilizes the base voltage of U1 chip VCC-Q7 at a fixed value through the Zener diode D6, and stabilizes the GND voltage of U1 chip at a voltage value that is about 0.7V higher than the base voltage of Q7 through the transistor Q7, thereby enabling U1 to work stably.

[0044] STEP 6: When A and Y in U1 are always in opposite states, capacitor C2 will be repeatedly charged and discharged through resistor R9, forming a periodic high and low level.

[0045] STEP7: Vo forms a charging pump circuit using ordinary diodes D5, C1, and C4, which will pump the voltage at pin 1 of C4 to a higher voltage value than Vo.

[0046] STEP8: The voltage after pumping will flow to the gates of NMOS Q1 and Q2 through ordinary diodes D4 and D3. At this time, Q1 and Q2 are turned on, and the dual-stage NMOS circuit is started.

[0047] Those skilled in the art will recognize that numerous variations are possible with respect to the above description, and the embodiments and figures are merely for describing one or more specific implementations.

[0048] Although exemplary embodiments of the invention have been described and illustrated, those skilled in the art will understand that various changes and substitutions can be made thereto without departing from the spirit of the invention. Furthermore, many modifications can be made to adapt specific situations to the doctrine of the invention without departing from the central concepts of the invention described herein. Therefore, the invention is not limited to the specific embodiments disclosed herein, but may include all embodiments and equivalents that fall within the scope of the invention.

Claims

1. A startup circuit that uses a charge pump to drive a dual-stage NMOS transistor to achieve reverse power supply protection and backflow prevention, characterized in that: The system includes a dual-stage NMOS reverse current protection and backflow prevention circuit module, a gate drive control circuit module, a charge pump charging circuit module, a power-on switch circuit module, a power input VIN, a power output VOUT, and a switch SW. The dual-stage NMOS reverse current protection and backflow prevention circuit module is used to prevent current backflow from impacting the input power supply. The gate drive control circuit module is used to control the conduction and disconnection of the dual-stage NMOS. The charge pump charging circuit module is used to provide a voltage higher than VIN to the gate of the dual-stage NMOS to ensure that the dual-stage NMOS can conduct normally during operation. The power-on switch circuit is used to receive high and low level switching signals from the SW input to enable the controller power-on circuit to operate, thereby controlling the conduction of the dual-stage NMOS.

2. The startup circuit as described in claim 1, characterized in that: The dual-stage NMOS anti-reverse and anti-backflow circuit module includes NMOS Q1 and NMOS Q2. The source of NMOS Q1 is connected to VIN, and the drains of Q1 and Q2 are connected. The source of Q2 is connected to VOUT.

3. The startup circuit as described in claim 1, characterized in that: The gate drive control circuit module includes a first-stage circuit, a second-stage circuit, and a protection circuit. One end of the first-stage circuit is connected to the gate of Q1, and the other end is connected to the output terminal of the charge pump charging circuit module. The first-stage circuit includes resistors R2 and R8 and diode D4. The anode of diode D4 is connected to the output terminal of the charge pump charging circuit module, and the cathode is connected to resistors R8 and R2. The other end of resistor R8 is grounded (GND). The other end of resistor R2 is connected to the gate of Q1.

4. The startup circuit as described in claim 3, characterized in that: The second-stage circuit includes resistors R1, R3, R4, and R7, as well as diode D3, transistor Q3, and NMOS Q5. The source of Q5 is grounded to GND, its gate is connected to the output of the power-on switch circuit module, and its drain is connected to one end of resistor R4. The other end of R4 is connected to resistor R3 and the base of transistor Q3. The collector of Q3 is connected to the gate of Q2 and resistor R1, and the other end of resistor R1 is connected to the source of Q2. The emitter of Q3 is connected to the other end of R3 and one end of resistor R7, and the other end of R7 is connected to the cathode of diode D3. The anode of diode D3 is connected to the output of the charge pump charging circuit module.

5. The startup circuit as described in claim 3, characterized in that: The protection circuit includes a resistor R5, a transistor Q4, and a diode D1. The collector of the transistor Q4 is connected between the gate of Q1 and the resistor R2; the base of Q4 is connected to one end of the resistor R5, and the other end of R5 is grounded to GND; the emitter of Q4 is connected to the positive terminal of the diode D1, and the negative terminal of the diode D1 is connected between Q1 and VIN.

6. The startup circuit as described in claim 1, characterized in that: The charge pump charging circuit module includes a charging circuit and a non-0V ground circuit. The charging circuit includes an NMOS Q8, resistors R12, R11, R10, and R9, as well as a diode D5, a PMOS Q6, an inverter U1, and capacitors C1, C2, C3, and C4. The gate of the NMOS Q8 is connected to the output terminal of the power-on switch circuit module, the source is grounded to GND, and the drain is connected to one end of resistor R12. The other end of resistor R12 is connected to resistors R10 and R11. The other end of R10 is connected to the gate of the PMOS Q6, and the other end of R11 is connected to the source of the PMOS Q6. Q6 drain capacitor C3 and the VCC terminal of inverter U1. Terminal A of inverter U1 is connected to one end of capacitor C2 and resistor R9. The other end of resistor R9 is connected to the Y terminal of inverter U1. The Y terminal of inverter U1 is also connected to capacitor C1. The other end of capacitor C1 is connected to pin 3 of diode D5. The two ends of capacitor C4 are connected to pins 1 and 2 of diode D5, respectively. Pin 2 of diode D5 is also connected to diodes D3 and D4.

7. The startup circuit as described in claim 6, characterized in that: The non-0V ground circuit includes transistor Q7, resistor R13, and Zener diode D6. The GND terminal of inverter U1 is connected to the other end of capacitors C2 and C3, and to the emitter of transistor Q7. The base of Q7 is connected to resistor R13 and one end of Zener diode D6. The other end of D6 is connected between the drain of Q6 and C3. The collector of Q7 is connected to the other end of R13, and then grounded to GND.

8. The startup circuit as described in claim 6, characterized in that: The diode D5 is composed of diode I and diode II connected in series. The positive terminal of diode I is pin 1, and the negative terminal is connected to the positive terminal of diode II. The negative terminal of diode II is pin 2. Pin 3 extends from between diode I and diode II and is connected to capacitor C1.

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