High-precision phase interpolation circuit of integrated temperature compensation delay unit

Abstract

The invention provides a high-precision phase interpolation circuit integrated with a temperature compensation delay unit, and the circuit comprises a temperature compensation module which is used for generating a compensation voltage VTEMP according to the temperature characteristic of a triode Q3 and a resistor array R1; a delay unit connected with the temperature compensation module and used for generating a plurality of delayed output signals FOUT according to the plurality of input signals FIN, a capacitor C0 and an input inverter I0, and changing a temperature compensation variable capacitor C1 by using a compensation voltage VTEMP so as to adjust the delay time of the plurality of delayed output signals FOUT and obtain a plurality of target delay signals; and the phase interpolation module is connected with the delay unit and is used for taking the plurality of target delay signals as a plurality of target input signals, performing phase difference operation on the plurality of target input signals and generating a phase interpolation output signal V0. Therefore, the compensation adjustment capability can be improved, the dynamic power consumption can be obviously reduced, and excellent high-speed performance and low clock jitter are realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-digital mixed integrated circuits, and in particular to a high-precision phase interpolation circuit integrated with a temperature-compensated delay unit. BACKGROUND

[0002] In a complementary metal-oxide-semiconductor (CMOS) integrated circuit, a delay chain is a common circuit structure, which is usually used to generate a specific time delay and is widely used in the fields of clock generation, data synchronization and signal processing. The basic principle of the delay chain is to realize the overall time delay by connecting multiple inverters or other delay units in series and using the signal propagation delay of each delay unit. The main reason for the delay is that the channel capacitance formed between the gate and the substrate of the MOS tube needs to be charged and discharged, and the equivalent resistance of the upper MOS tube forms an RC delay structure. With the change of temperature, the delay characteristics in the CMOS circuit will also change. This is because the size of the parasitic capacitance between devices is greatly affected by temperature. At high temperatures, the parasitic capacitance between devices increases, which increases the propagation delay; at low temperatures, the parasitic capacitance between devices decreases, which reduces the propagation delay. This temperature drift will affect the timing requirements of the circuit, especially in high-precision and high-frequency applications. The core idea of temperature compensation is to introduce a temperature-dependent compensation term to offset the temperature drift of the main delay chain. In modern high-speed chips (such as processors and communication chips), accurate control of the phase of the clock signal is a core challenge to achieve high-speed data transmission. CMOS phase interpolation (PI) technology is mainly used to adjust the phase of the clock signal, which can dynamically generate an arbitrary intermediate phase clock between two input clocks with a fixed phase difference (for example, a 0° phase clock and a 90° phase clock), and realize fine adjustment of the phase.

[0003] At present, temperature compensation usually adopts RC network and inverter hybrid compensation, as well as digital calibration and adaptive adjustment. However, when RC delay units are alternately inserted in the inverter chain to compensate for the positive temperature coefficient of the inverter with the negative temperature coefficient of the RC, the RC hybrid compensation design is difficult, the RC hybrid compensation is highly dependent on the core performance, it is difficult to accurately control the absolute parameters of RC, and it lacks compensation adjustment ability, and the performance stability is low; using a digital signal processor or a field programmable gate array to dynamically adjust the bias current or resistance value of the delay chain, but the digital calibration power consumption and delay are large, which cannot meet the demand of high speed and low power consumption; the circuit using PI technology is extremely sensitive to element accuracy, and needs to overcome the influence of process deviation, and the hybrid process may introduce additional clock jitter, resulting in high clock jitter. SUMMARY

[0004] The embodiment of the present application aims to provide a high-precision phase interpolation circuit integrated with temperature compensation delay units, which solves the problems of lack of compensation adjustment capability, low performance stability, high clock jitter and inability to adapt to high speed and low power consumption in the prior art.

[0005] To solve the above technical problems, the embodiment of the present application provides the following technical scheme: The embodiment of the present application provides a high-precision phase interpolation circuit integrated with temperature compensation delay units, which comprises: A temperature compensation module is configured to generate a compensation voltage V TEMP according to the temperature characteristics of a triode Q3 and a resistor array R1. A delay unit is connected with the temperature compensation module and configured to generate a plurality of delayed output signals F IN according to a plurality of input signals F OUT , a capacitor C0 and an input inverter I0. TEMP The compensation voltage V OUT is used to change a temperature compensation variable capacitor C1, so as to adjust the delay time of the plurality of delayed output signals F TEMP , and obtain a plurality of target delay signals, which are the delay signals after the adjustment of the delay time. A phase interpolation module is connected with the delay unit and configured to take the plurality of target delay signals as a plurality of target input signals, perform a phase difference operation on the plurality of target input signals, and generate a phase interpolation output signal V0.

[0006] Compared with the prior art, the high-precision phase interpolation circuit integrated with temperature compensation delay units provided by the present application comprises: a temperature compensation module configured to generate a compensation voltage V TEMP according to the temperature characteristics of a triode Q3 and a resistor array R1; and a delay unit connected with the temperature compensation module and configured to generate a plurality of delayed output signals F IN according to a plurality of input signals F OUT , a capacitor C0 and an input inverter I0. TEMP The compensation voltage V OUTdelay time to obtain a plurality of target delay signals, the plurality of target delay signals being the delay signals after the delay time is adjusted; a phase interpolation module, connected with the delay unit, configured to take the plurality of target delay signals as a plurality of target input signals, and perform a phase difference operation on the plurality of target input signals to generate a phase interpolation output signal V0, the number of the temperature compensation modules and the number of the delay units being the same as the number of input ends of the phase interpolation module. In this way, the resistance array R1 integrated in the temperature compensation module can provide a plurality of different compensation strength options, improving the compensation adjustment capability; the structure of the phase interpolation module has excellent high-speed performance and low clock jitter, can effectively suppress the peak discharge current, and significantly reduces the dynamic power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other objects, features and advantages of the exemplary embodiments of the present application will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which several embodiments of the present application are shown by way of example, and wherein like reference numerals refer to like elements throughout. The embodiments of the present application will be described with the understanding that the present application is not limited to the embodiments described and illustrated, and are presented herein for purposes of illustration and description only. Figure 1 A structure diagram of a high-precision phase interpolation circuit integrated with a temperature compensation delay unit is schematically shown; Figure 2 A structure diagram of a temperature compensation module is schematically shown; Figure 3 A simplified structure diagram of a temperature compensation module is schematically shown; Figure 4 A schematic diagram of output voltage slope variation under different switch settings is schematically shown; Figure 5 A schematic diagram of delay variation of the temperature compensation module before and after temperature compensation is schematically shown; Figure 6 A structure diagram of a delay unit is schematically shown; Figure 7 A structure diagram of a temperature compensation variable capacitor C1 is schematically shown; Figure 8 A structure diagram of a phase interpolation module is schematically shown; Figure 9 A phase vector synthesis diagram is schematically shown; Figure 10 A schematic diagram of a phase interpolation principle is schematically shown; Figure 11 A schematic diagram of a phase interpolation simulation result is schematically shown. DETAILED DESCRIPTION

[0008] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of the present invention by way of example, but should not be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0009] The following is a detailed description of a high-precision phase interpolation circuit with an integrated temperature compensation delay unit in an embodiment of the present invention.

[0010] See Figure 1 As shown, Figure 1 The schematic diagram illustrates the structure of a high-precision phase interpolation circuit with an integrated temperature-compensated delay unit. This embodiment of the invention proposes a high-precision phase interpolation circuit with an integrated temperature-compensated delay unit, comprising: The temperature compensation module is used to generate a compensation voltage V based on the temperature characteristics of transistor Q3 and resistor array R1. TEMP ; The delay unit, connected to the temperature compensation module, is used to adjust the input signals F based on multiple input signals. IN The capacitor C0 and the input inverter I0 generate multiple delayed output signals F. OUT Using compensation voltage V TEMP The temperature compensation variable capacitor C1 is changed to adjust the output signal F after multiple delays. OUT The delay time is used to obtain multiple target delay signals, which are delay signals after adjusting the delay time; The phase interpolation module, connected to the delay unit, is used to take multiple target delay signals as multiple target input signals, perform phase difference operation on the multiple target input signals, and generate a phase interpolation output signal V0. The number of temperature compensation modules and the number of delay units are the same as the number of input terminals of the phase interpolation module.

[0011] For example, if the phase interpolation module has two input terminals, then there are two temperature compensation modules and two delay units. The input signal corresponding to the two delay units is input signal F. IN1 and input signal F IN2 The output signal corresponding to the two delay units is the delayed output signal F. OUT1 and the delayed output signal F OUT2 Correspondingly, the multiple target input signals corresponding to the two phase interpolation modules include the first target input signal V1 and the second target input signal V2.

[0012] In this embodiment, Figure 2 A schematic diagram of the temperature compensation module is shown below. Figure 2As shown, the temperature compensation module comprises a triode Q3, a resistor array R1, a programmable resistance voltage dividing network, a low-pass filter, a clamping operational amplifier I1, a MOS transistor M1, a MOS transistor M2, a resistor R2 and a resistor R3; The non-inverting input terminal of the clamping operational amplifier I1 is connected with the programmable resistance voltage dividing network, the inverting input terminal of the clamping operational amplifier I1 is connected with a voltage V BIAS1 The output terminal of the clamping operational amplifier I1 is connected with one end of the resistor array R1, one end of the resistor R2, the gate of the MOS transistor M1 and the input terminal of the low-pass filter, the source of the MOS transistor M1 is connected with a power supply, the drain of the MOS transistor M1 is connected with the output terminal of the low-pass filter and the gate of the MOS transistor M2, the source of the MOS transistor M2 is connected with the power supply, the drain of the MOS transistor M2 is connected with one end of the resistor R3, the other end of the resistor R3 is grounded, and the connection node of the drain of the MOS transistor M2 and one end of the resistor R3 is connected with a compensation voltage V TEMP The other end of the resistor array R1 is connected with the collector of the triode Q3 and the base of the triode Q3, and the emitter of the triode Q3 is grounded, and the other end of the resistor R2 is grounded.

[0013] In the embodiment, the programmable resistance voltage dividing network comprises a resistor R4, a resistor R5, a resistor R6, a resistor R7, a switch SW0, a switch SW1 and a switch SW2. One end of the resistor R4 is connected with a power supply, and the other end of the resistor R4 is connected with one end of the switch SW0; the other end of the switch SW0 is connected with one end of the resistor R5, and the other end of the resistor R5 is connected with one end of the switch SW1; the other end of the switch SW1 is connected with one end of the resistor R6, and the other end of the resistor R6 is connected with one end of the switch SW2; the other end of the switch SW2 is connected with one end of the resistor R7, and the other end of the resistor R7 is grounded; and the non-inverting input terminal of the clamping operational amplifier I1 is connected with the connection node of the switch SW0, the switch SW1 and the switch SW2.

[0014] In the embodiment, the resistor array R1 comprises a resistor R101, a resistor R102, a resistor R103, a resistor R104, a resistor R105, a switch SW3, a switch SW4, a switch SW5, a switch SW6 and a switch SW7. One end of the resistor R101, one end of the resistor R102, one end of the resistor R103, one end of the resistor R104 and one end of the resistor R105 are connected with each other and are commonly connected to the collector of the triode Q3. The other end of the resistor R101 is connected to the output of the clamp operational amplifier I1 through the switch SW3, the other end of the resistor R102 is connected to the output of the clamp operational amplifier I1 through the switch SW4, the other end of the resistor R103 is connected to the output of the clamp operational amplifier I1 through the switch SW5, the other end of the resistor R104 is connected to the output of the clamp operational amplifier I1 through the switch SW6, and the other end of the resistor R105 is connected to the output of the clamp operational amplifier I1 through the switch SW7.

[0015] In the embodiment, the low-pass filter comprises a resistor R0 and a capacitor C2. One end of the resistor R0 is connected to the drain of the MOS transistor M1, and the other end of the resistor R0 is connected to one end of the capacitor C2 and the gate of the MOS transistor M2, and the other end of the capacitor C2 is grounded.

[0016] In the embodiment, the resistor array R1 is a 4-bit digital programmable resistor array, and the resistor array R1 adopts a binary weighted resistance structure.

[0017] Specifically, referring to Figure 2 As shown in the figure, the structure of the temperature compensation module mainly comprises a clamp operational amplifier I1, MOS transistors M1 and M2, a bipolar junction transistor (BJT) triode Q3, and resistors R0, R1, R2, R3, R4, R5, R6 and R7. Among them, the MOS transistor M1 and the MOS transistor M2 form a current mirror, which plays a role of copying current; I1 is a clamp operational amplifier, which clamps the voltage V BIAS to V1, so that they are equal; the resistor R0 and the capacitor C0 constitute a low-pass filter to filter out high-frequency noise in the circuit; the bipolar transistor Q3 generates a voltage negatively related to temperature; the resistor array R1 is a 4-bit digital programmable resistor array, which adopts a binary weighted resistance structure and can provide 16 different compensation strength options. At the same time, the resistors R4, R5, R6 and R7 and the switches SW0, SW1 and SW2 constitute a programmable resistance voltage dividing network. By configuring the switch state, the reference voltage of the negative phase input end of the clamp operational amplifier I1 can be set to V3. Changing V3 changes the voltage V BIAS1 , thereby affecting the current flowing through R2, and ultimately achieving coarse adjustment of the overall amplitude. TEMP

[0018] Figure 3 The simplified structure diagram of the temperature compensation module is schematically shown, referring to Figure 3 For the sake of clear explanation of the working principle, the temperature compensation module of Figure 2 is simplified, and the simplified temperature compensation module is determined, and the working principle thereof is as follows: The clamp operational amplifier I1 clamps V​BIAS1 Stabilized at the reference voltage V3 (i.e., the op-amp is virtual shorted, causing V to stabilize at the reference voltage V3) BIAS1 = V3), therefore the current flowing through resistor R2 is: ; The base-emitter voltage of BJT transistor Q3 is V. BE Therefore, the current flowing through the resistor array R1 can be expressed as: ; Therefore, the total current of MOSFET M1 can be obtained as follows: ; Since MOSFETs M1 and M2 form a current mirror (mirror ratio k = width-to-length ratio of M2 / M1), the current in the branch of MOSFET M2 is... (Ignoring channel length modulation effects). This current The entire flow passes through resistor R3, therefore: ; Therefore, the compensation voltage V TEMP The expression is (k is the W / L ratio of M2 and M1): ; Given the forward conduction voltage V of the bipolar transistor BE It has a negative temperature coefficient, V TEMP A positive temperature correlation is observed: as temperature increases, V TEMP It increases accordingly.

[0019] Figure 4 The diagram schematically illustrates the output voltage slope variation under different switching settings. (See attached image) Figure 4 As shown, Figure 4 The horizontal axis represents temperature, and the vertical axis represents the compensation voltage V. TEMP A 4-bit programmable switch resistor array is integrated at resistor array R1. By configuring the switch state, the equivalent resistance value of the circuit can be dynamically adjusted, thereby precisely regulating V. TEMP The slope of voltage change with temperature. Figure 4 The multiple straight lines in the diagram represent the temperature compensation voltage V under different switch settings. TEMP The slope as a function of temperature.

[0020] Figure 5 The diagram schematically illustrates the change in the temperature compensation module delay before and after temperature compensation. (See attached image) Figure 5 As shown, Figure 5 (a) shows the characteristics of the temperature compensation module delay as a function of temperature before and after temperature compensation. Figure 5(b) shows the temperature compensation module delay characteristics after temperature compensation. After integrating the temperature compensation module, the temperature drift of the delay time is significantly reduced from 16ps to 2ps within the temperature range of -40°C to +120°C, which greatly enhances the temperature stability of the temperature compensation module.

[0021] In this embodiment, Figure 6 A schematic diagram of the delay unit is shown below. Figure 6 As shown, the delay unit includes capacitor C0, temperature-compensated variable capacitor C1, input inverter I0, capacitor C3, and resistor R8. Input signal F IN The input terminal of the inverter I0 is connected to the input terminal of the input inverter I0. The output terminal of the input inverter I0 is connected to one end of capacitor C0 and one end of capacitor C3. The other end of capacitor C0 is grounded. The other end of capacitor C3 is connected to one end of resistor R8 and one end of temperature compensation variable capacitor C1. The other end of resistor R8 is connected to the bias voltage V. BIAS2 Connect the other end of the temperature compensation variable capacitor C1 to the compensation voltage V. TEMP1 The connection point between the other end of capacitor C3 and one end of resistor R8 and one end of temperature-compensated variable capacitor C1 provides the delayed output signal F. OUT Compensation voltage V TEMP1 With compensation voltage V TEMP connect.

[0022] In this embodiment, the temperature-compensated variable capacitor C1 includes a P-type substrate, an N-well, a source, and a gate, wherein the source is composed of multiple N+ doped active regions.

[0023] For details, see Figure 6 As shown, the delay unit consists of an input inverter I0, a delay capacitor C0, a temperature-compensated variable capacitor C1, an AC coupling capacitor C3, and a bias resistor R8. IN For the input signal, F OUT V is the delayed output signal. TEMP1 V is the compensation voltage generated by the temperature compensation module. BIAS2 This is the bias voltage. Figure 7 A schematic diagram of the temperature-compensated variable capacitor C1 is shown below. Figure 7 As shown, the cross-section of the physical structure of the temperature-compensated variable capacitor C1 includes: a P-type substrate (P-sub), an N-well, and multiple N+ doped active regions. The multiple N+ doped active regions constitute the source, and the two layers located between the multiple N+ doped active regions serve as the gate. The capacitance value of this temperature-compensated variable capacitor C1 is controlled by the voltage difference VGS between the gate (G) and the source (S). When VGS increases, the capacitance value of the temperature-compensated variable capacitor C1 exhibits a monotonically decreasing characteristic.

[0024] According to the physical characteristics of the device, the temperature rise will cause the capacitance C0 and the node parasitic capacitance to increase, which in turn increases the output delay of the F OUT . To offset this effect, the present application introduces a temperature compensation variable capacitance C1 and a compensation voltage V TEMP1 : when the temperature rises, V TEMP1 increases accordingly (V BIAS2 remains constant), resulting in a decrease in the gate-source voltage V GS (= V BIAS2 -V TEMP1 ) of the temperature compensation variable capacitance C1, and the capacitance value decreases. As part of the delay chain load capacitance, the decrease in the capacitance value of the temperature compensation variable capacitance C1 will change the RC delay variation of the node, resulting in a negative temperature coefficient delay component. This negative temperature coefficient component is designed to offset the net positive temperature drift caused by the combined effect of the increase in capacitance C0 / parasitic capacitance (positive temperature coefficient) and the increase in transistor current (negative temperature coefficient, reducing delay), and ultimately to maintain the delay substantially constant within the target temperature range.

[0025] By precisely calibrating the voltage variation slope of V TEMP1 and the capacitance value parameter of the temperature compensation variable capacitance C1, the delay drift caused by temperature can be dynamically adjusted to achieve the constant delay target. In addition, the AC coupling capacitance C3 is used to block the DC component of the signal path, ensuring that the temperature compensation variable capacitance C1 is only controlled by the bias voltage V BIAS2 and the compensation voltage V TEMP1 , avoiding the interference of the signal common-mode voltage.

[0026] In this embodiment, Figure 8 a structural diagram of a phase interpolation module is schematically shown, as shown in Figure 8 , the plurality of target input signals include a first target input signal V1 and a second target input signal V2, and the phase interpolation module includes MOS tubes M3, M4, M5, M6, resistors R9, R10, R11, R12 and a capacitor C4. The first target input signal V1 is connected with the gate of MOS tube M3 and the gate of MOS tube M4, the drain of MOS tube M3 is connected with one end of resistor R9, the other end of resistor R9 is connected with one end of resistor R10, the other end of resistor R10 is connected with the drain of MOS tube M4, and the source of MOS tube M4 is grounded; the second target input signal V2 is connected with the gate of MOS tube M5 and the gate of MOS tube M6, the drain of MOS tube M5 is connected with one end of resistor R11, the other end of resistor R11 is connected with one end of resistor R12, the other end of resistor R12 is connected with the drain of MOS tube M6, and the source of MOS tube M6 is grounded; the connection node of the other end of resistor R9 and one end of resistor R10 and the connection node of the other end of resistor R11 and one end of resistor R12 are connected with each other and then connected with one end of capacitor C4, the other end of capacitor C4 is grounded, and one end of capacitor C4 is connected with the phase interpolation output signal V0; the first target input signal V1 and the second target input signal V2 are connected with the delayed output signal F OUT .

[0027] Specifically, the core structure of the phase interpolation module mainly comprises MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, resistor R9, resistor R10, resistor R11, resistor R12 and capacitor C4. Among them, V1 and V2 are input signals with different phases, and V0 is a phase interpolation output signal. Figure 9 The phase vector synthesis diagram is schematically shown, referring to Figure 9 As shown, the horizontal coordinate is the phase component V I of active voltage, and the vertical coordinate is the phase component V Q of reactive voltage. The phases of input signals V1 and V2 are different, and vector synthesis is performed through the phase interpolation mechanism to finally generate the phase interpolation output signal V0, so as to realize fine phase adjustment.

[0028] Figure 10 The phase interpolation principle diagram is schematically shown, referring to Figure 10As shown, the input signals V1 and V2 are two different phase signals, in the time period of 0~t1, V1 and V2 are both low, MOS tube M3 and MOS tube M5 are turned on, MOS tube M4 and MOS tube M6 are turned off, and the phase interpolation output signal V0 is high. In the time period of t1~t2, V1 becomes high, V2 remains low, MOS tube M4 and MOS tube M5 are turned on, MOS tube M3 and MOS tube M6 are turned off, and capacitor C4 starts discharging along MOS tube M4, and the voltage of the phase interpolation output signal V0 starts to decrease. In the time period of t2~t3, V1 and V2 both become high, MOS tube M4 and MOS tube M6 are turned on, MOS tube M3 and MOS tube M5 are turned off, and capacitor C4 starts discharging along MOS tube M4 and MOS tube M6, the discharging rate becomes faster, and the slope of the voltage of the phase interpolation output signal V0 decreases. After the time period of t3, capacitor C4 is discharged, and the phase interpolation output signal V0 remains low.

[0029] Referring to Figure 10 As shown, the input signals V1 and V2 are two clock signals with a fixed phase difference. They are divided into the following time periods: Stage 0~t1: V1 and V2 are both low. At this time, Figure 8 MOS tube M3 and MOS tube M5 are turned on, MOS tube M4 and MOS tube M6 are turned off, and the phase interpolation output signal V0 is pulled up to high.

[0030] Stage t1~t2: V1 jumps to high, and V2 remains low. At this time, MOS tube M4 and MOS tube M5 are turned on, and MOS tube M3 and MOS tube M6 are turned off. Capacitor C1 starts to discharge, and the voltage of the phase interpolation output signal V0 starts to decrease.

[0031] Stage t2~t3: V1 and V2 both become high. At this time, MOS tube M4 and MOS tube M6 are turned on, and MOS tube M3 and MOS tube M5 are turned off. The discharging path of capacitor C1 becomes through MOS tube M4 and MOS tube M6 in parallel, the equivalent discharging resistance decreases, the discharging rate accelerates, and therefore the slope of the voltage of the phase interpolation output signal V0 increases.

[0032] After stage t3: capacitor C1 is discharged, and the phase interpolation output signal V0 is stably maintained at low (the input V1 and V2 remain high).

[0033] By adjusting the size ratio of MOS tube M3, MOS tube M4, MOS tube M5 and MOS tube M6, the weighting coefficients of the input signals V1 and V2 in the phase interpolation can be changed, so as to realize accurate control of the phase interpolation output signal V0.

[0034] Figure 8The resistances R9, R10, R11 and R12 of the phase interpolation module mainly play a current limiting role: limiting the charging and discharging rate of the capacitor C4, helping to obtain a smoother and more controllable output voltage variation slope, thereby improving the accuracy of phase interpolation. Figure 10 The peak discharge current in the t1-t2 time period (when the MOS tube M4 and the MOS tube M5 are turned on to form a low-resistance path) is effectively suppressed, and the dynamic power consumption of the phase interpolation module is significantly reduced.

[0035] Figure 11 The phase interpolation simulation result schematic diagram is schematically shown, referring to Figure 11 As shown, the abscissa is time, the ordinate is voltage, the red curve is the first target input signal V1, the blue curve is the second target input signal V2, the green curve is the phase interpolation output signal V0, the relative delay of the first target input signal V1 and the second target input signal V2 is 8ps, and the phase interpolation output signal V0 with a delay of 4ps is obtained after phase interpolation.

[0036] The beneficial effects of the high-precision phase interpolation circuit integrated with the temperature compensation delay unit of the application are as follows: 1. The temperature compensation module of the application has an excellent energy efficiency ratio. Under the premise of strictly ensuring key performance indicators (such as high precision, low noise, wide bandwidth, and high linearity), the temperature compensation module realizes ultra-low static and dynamic power consumption (typical working current can be as low as 200μA order of magnitude). The simple architecture of the temperature compensation module not only significantly reduces the number of transistors and the complexity of passive devices, but also saves chip area, significantly improves the integration density and cost-effectiveness of the overall chip.

[0037] 2. The temperature compensation module of the application innovatively adopts a reference compensation network constructed based on a proportional to absolute temperature (PTAT) current source, and is supplemented by a high-precision digital programmable resistance array. The reference compensation network includes a MOS tube M1, a voltage V BIAS1, switch SW7, resistor R105, triode Q3 and resistor R2. The core compensation mechanism is that a PTAT voltage, which varies linearly with temperature, is generated by a PTAT current source and used to control the capacitance of the variable capacitor. By precisely adjusting the amplitude and slope of the PTAT voltage and the parameters of the variable capacitor, a constant delay time at different temperatures can be achieved. Meanwhile, a 4-bit digitally programmable resistance array is integrated. The resistance array adopts a binary-weighted resistance structure and can provide 16 different compensation strength options. This combined design can adapt to a wide range of working condition changes (such as an industrial temperature range of -40°C to 125°C, significant power supply voltage fluctuations or process corner deviations) in real time, ensuring high consistency and reliability of the compensation effect.

[0038] 3. The phase interpolation module realized by the present application significantly reduces the additional jitter level (typically less than 5fs RMS) under the premise of ensuring the integrity of the core function by adopting a simplified and optimized circuit topology. At the same time, the phase interpolation module has excellent high-speed performance, supports a working frequency of up to 12GHz, and has the advantages of low power consumption and high stability. These characteristics enable it to be widely used in high-speed serial communication interfaces, clock data recovery systems, and precision measurement equipment, etc. in scenes with strict requirements on timing accuracy and speed.

[0039] Although some specific embodiments of the present application have been described in detail by examples, those skilled in the art should understand that the above examples are only for illustration, not for limiting the scope of the present application. Those skilled in the art should understand that the above embodiments can be modified or some technical features can be replaced equivalently without departing from the scope and spirit of the present application. In particular, as long as there is no structural conflict, each technical feature mentioned in each embodiment can be combined in any way.

[0040] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A high-precision phase interpolation circuit integrated with a temperature-compensated delay unit, characterized by, The method comprises the following steps: a temperature compensation module for generating a compensation voltage V TEMP ; The delay unit, connected to the temperature compensation module, is used to adjust the input signals F based on multiple input signals F. IN The capacitor C0 and the input inverter I0 generate multiple delayed output signals F. OUT Using the compensation voltage V TEMP The temperature compensation variable capacitor C1 is changed to adjust the multiple delayed output signals F. OUT The delay time is used to obtain multiple target delay signals, wherein the multiple target delay signals are delay signals after adjusting the delay time; The phase interpolation module is connected with the delay unit, and is configured to take the plurality of target delay signals as a plurality of target input signals, perform phase difference operation on the plurality of target input signals, and generate a phase interpolation output signal V0.

2. The high precision phase interpolator circuit integrating temperature compensated delay cells according to claim 1, characterized in that, The temperature compensation module comprises the triode Q3, the resistor array R1, a programmable resistor voltage dividing network, a low-pass filter, a clamping operational amplifier I1, MOS tubes M1 and M2, resistors R2 and R3. The inverting input terminal of the clamping operational amplifier I1 is connected with the programmable resistance voltage dividing network, the non-inverting input terminal of the clamping operational amplifier I1 is connected with the voltage V BIAS1 The output terminal of the clamping operational amplifier I1 is connected with one end of the resistance array R1, one end of the resistance R2, the gate of the MOS transistor M1 and the input terminal of the low-pass filter, the source of the MOS transistor M1 is connected with the power supply, the drain of the MOS transistor M1 is connected with the output terminal of the low-pass filter and the gate of the MOS transistor M2, the source of the MOS transistor M2 is connected with the power supply, the drain of the MOS transistor M2 is connected with one end of the resistance R3, the other end of the resistance R3 is grounded, the connection node of the drain of the MOS transistor M2 and one end of the resistance R3 is connected with the compensation voltage V TEMP The other end of the resistance array R1 is connected with the collector of the triode Q3 and the base of the triode Q3, the emitter of the triode Q3 is grounded, and the other end of the resistance R2 is grounded.

3. The high precision phase interpolator circuit integrating temperature compensated delay cells according to claim 2, characterized in that, The programmable resistor voltage dividing network comprises resistors R4, R5, R6, R7, switches SW0, SW1 and SW2. One end of the resistor R4 is connected with the power supply, and the other end of the resistor R4 is connected with one end of the switch SW0; the other end of the switch SW0 is connected with one end of the resistor R5, and the other end of the resistor R5 is connected with one end of the switch SW1; the other end of the switch SW1 is connected with one end of the resistor R6, and the other end of the resistor R6 is connected with one end of the switch SW2; the other end of the switch SW2 is connected with one end of the resistor R7, and the other end of the resistor R7 is grounded; and the inverting input end of the clamping operational amplifier I1 is connected with the connection node of the switches SW0, SW1 and SW2.

4. The high precision phase interpolator circuit integrating temperature compensated delay cells of claim 2, wherein, The resistor array R1 comprises resistors R101, R102, R103, R104, R105, switches SW3, SW4, SW5, SW6 and SW7. One end of the resistor R101, one end of the resistor R102, one end of the resistor R103, one end of the resistor R104 and one end of the resistor R105 are connected with each other and are commonly connected to the collector of the triode Q3. The other end of the resistor R101 is connected to the output end of the clamping operational amplifier I1 through the switch SW3, the other end of the resistor R102 is connected to the output end of the clamping operational amplifier I1 through the switch SW4, the other end of the resistor R103 is connected to the output end of the clamping operational amplifier I1 through the switch SW5, the other end of the resistor R104 is connected to the output end of the clamping operational amplifier I1 through the switch SW6, and the other end of the resistor R105 is connected to the output end of the clamping operational amplifier I1 through the switch SW7.

5. The high precision phase interpolator circuit integrating temperature compensated delay cells according to claim 3, wherein, The low-pass filter comprises a resistor R0 and a capacitor C2. One end of the resistor R0 is connected with the drain of the MOS tube M1, and the other end of the resistor R0 and the gate of the MOS tube M2 are both connected with one end of the capacitor C2; the other end of the capacitor C2 is grounded.

6. The high precision phase interpolator circuit integrating temperature-compensated delay cells of claim 2, wherein, The delay unit comprises the capacitor C0, the temperature compensation variable capacitor C1, the input inverter I0, a capacitor C3 and a resistor R8. The input signal F IN connected with the input end of the input inverter I0, the output end of the input inverter I0 is connected with one end of the capacitor C0 and one end of the capacitor C3, the other end of the capacitor C0 is grounded, the other end of the capacitor C3 is connected with one end of the resistor R8 and one end of the temperature compensation variable capacitor C1, the other end of the resistor R8 is connected with the bias voltage V BIAS2 , the other end of the temperature compensation variable capacitor C1 is connected with the compensation voltage V TEMP1 , the other end of the capacitor C3 is connected with the connection point of one end of the resistor R8 and one end of the temperature compensation variable capacitor C1 to provide the delayed output signal F OUT , the compensation voltage V TEMP1 is connected with the bias voltage V TEMP .

7. The high precision phase interpolator circuit integrating temperature-compensated delay cells according to claim 6, wherein, The multiple target input signals include a first target input signal V1 and a second target input signal V2, and the phase interpolation module includes MOS tubes M3, M4, M5, M6, resistors R9, R10, R11, R12, and a capacitor C4. The first target input signal V1 is connected with the gate of the MOS transistor M3 and the gate of the MOS transistor M4, the drain of the MOS transistor M3 is connected with one end of the resistor R9, the other end of the resistor R9 is connected with one end of the resistor R10, the other end of the resistor R10 is connected with the drain of the MOS transistor M4, and the source of the MOS transistor M4 is grounded; the second target input signal V2 is connected with the gate of the MOS transistor M5 and the gate of the MOS transistor M6, the drain of the MOS transistor M5 is connected with one end of the resistor R11, the other end of the resistor R11 is connected with one end of the resistor R12, the other end of the resistor R12 is connected with the drain of the MOS transistor M6, and the source of the MOS transistor M6 is grounded; the connection node of the other end of the resistor R9 and one end of the resistor R10 and the connection node of the other end of the resistor R11 and one end of the resistor R12 are connected with each other and then connected with one end of the capacitor C4, the other end of the capacitor C4 is grounded, and one end of the capacitor C4 is connected with the phase interpolation output signal V0; the first target input signal V1 and the second target input signal V2 are connected with the delayed output signal F OUT connection.

8. The high precision phase interpolator circuit integrating temperature-compensated delay cells of claim 1, wherein, The resistor array R1 is a 4-bit digital programmable resistor array, and the resistor array R1 adopts a binary weighted resistor structure.

9. The high precision phase interpolator circuit integrating temperature-compensated delay cells of claim 1, wherein, The temperature-compensated variable capacitor C1 includes a P-type substrate, an N-well, a source, and a gate, wherein the source is composed of multiple N+ doped active regions.

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