Fully differential closed-loop modulation circuit, circuit architecture and electronic equipment

Abstract

The invention provides a fully-differential closed-loop modulation circuit, circuit architecture and electronic equipment, and the circuit architecture comprises a fully-differential integrator, a subtracter, a comparator, a power amplification module and a feedback module, and the subtracter carries out the subtraction of a first integral signal and a second integral signal outputted by the fully-differential integrator, so as to obtain a differential signal. The residual PWM high-frequency signal between the first integral signal and the second integral signal is greatly suppressed, so that harmonic distortion caused by a harmonic component generated when the residual PWM high-frequency signal is compared with the carrier triangular wave signal is avoided. A driving unit and a half-bridge unit in the power amplification module output a first amplification signal according to a pulse width modulation signal output by a comparator, the driving unit and the half-bridge unit are both connected with positive and negative power supplies, and the positive and negative power supplies are opposite in polarity and equal in size, so that the first amplification signal is an alternating current, and a blocking capacitor does not need to be arranged; therefore, the quality of the output audio signal is improved while the system cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more particularly to fully differential closed-loop modulation circuits, circuit architectures, and electronic devices. Background Technology

[0002] In various applications, modulation circuits with high linearity and high driving capability are frequently required. Class D audio amplifiers and motor drivers are two common applications. Motor drivers are used in industrial robots, medical equipment, and other applications requiring motors, while Class D audio amplifiers are used in various speaker drivers and sound-producing devices. Our subsequent explanations will use Class D audio amplifiers in audio equipment as an example, but are not limited to this application.

[0003] In practical applications, structures requiring high current driving capability are divided into two types: open-loop and closed-loop. Entry-level motor drives often use open-loop modulation mode, but the control accuracy and linearity of this mode are difficult to guarantee.

[0004] Commonly used structures in Class D audio amplifiers include fully differential closed-loop modulation, open-loop modulation, and single-ended closed-loop modulation circuits.

[0005] The advantage of a single-ended closed-loop modulation circuit lies in its simple circuit structure. However, the single-ended signal of the modulation circuit is susceptible to power supply noise, resulting in weak anti-interference capability, small dynamic range, large output ripple current, and high static power consumption.

[0006] Compared to single-ended closed-loop modulation circuits, fully differential closed-loop modulation circuits have stronger anti-interference capabilities and a larger dynamic range, thus effectively suppressing the influence of power supply noise and harmonic distortion on the signal.

[0007] Furthermore, existing fully differential closed-loop modulation circuits still suffer from harmonic distortion due to residual high-frequency PWM signals aliasing into the audio band. Additionally, the cost of existing fully differential closed-loop modulation circuits doubles because they use an H-bridge structure at the power output. Summary of the Invention

[0008] This invention provides a fully differential closed-loop modulation circuit, circuit architecture, and electronic device to solve the above-mentioned technical problems, so as to effectively suppress harmonic distortion in the fully differential closed-loop modulation circuit at low cost.

[0009] According to a first aspect of the present invention, a fully differential closed-loop modulation circuit is provided, comprising: A fully differential integrator is used to integrate a received first input signal, a received second input signal, a feedback first amplified signal, and a feedback second amplified signal, and output a first integrated signal and a second integrated signal. A subtractor is used to subtract the first integral signal and the second integral signal output by the full differential integrator to obtain a differential signal and output it. A comparator is used to compare the carrier triangular wave signal and the differential signal, and output a pulse width modulation signal based on the comparison result; A power amplification module includes a drive unit and a half-bridge unit. The drive unit processes the pulse width modulation signal and outputs a first drive control signal and a second drive control signal. The half-bridge unit outputs the first amplified signal according to the first drive control signal and the second drive control signal. The power supply terminal of the half-bridge unit is connected to a first positive power supply voltage, and the ground terminal of the half-bridge unit is connected to a first negative power supply voltage. The first positive power supply voltage and the first negative power supply voltage have opposite polarities and equal magnitudes. The feedback module is used to feed back the first amplified signal output by the power amplification module and the power ground as the second amplified signal to the fully differential integrator.

[0010] Optionally, the fully differential integrator includes a first-stage integration unit; The first input terminal of the first-stage integration unit serves as the first input terminal of the fully differential integrator, and the second input terminal of the first-stage integration unit serves as the second input terminal of the fully differential integrator. The first-stage integration unit is used to integrate the first input signal, the second input signal, and the first amplified signal and / or the second amplified signal fed back by the feedback module, and outputs the first integrated signal and the second integrated signal. The first-stage integrator unit includes a first input resistor, a second input resistor, a first filter capacitor, a second filter capacitor, and a first operational amplifier. The first input resistor is connected between the first input terminal of the first-stage integrator unit and the inverting input terminal of the first operational amplifier. The second input resistor is connected between the second input terminal of the first-stage integrator unit and the non-inverting input terminal of the first operational amplifier. The first filter capacitor is connected between the first input terminal and the second output terminal of the first operational amplifier. The second output terminal of the first operational amplifier outputs the first integrated signal, and the first output terminal of the first operational amplifier outputs the second integrated signal.

[0011] Optionally, the fully differential integrator further includes a two-level architecture of a first-level integration unit and a second-level integration unit; The first input terminal of the first-stage integration unit serves as the first input terminal of the fully differential integrator, and the second input terminal of the first-stage integration unit serves as the second input terminal of the fully differential integrator. The first-stage integration unit is used to perform one integration process on the first input signal and the second input signal, and output the third integration signal and the fourth integration signal. The first input terminal of the second-stage integrator is connected to the third integral signal output by the first-stage integrator, and the second input terminal of the second integrator is connected to the fourth integral signal output by the first-stage integrator. The second-stage integrator is used to perform another integration process on the third integral signal and the fourth integral signal, and outputs the first integral signal from its first output terminal and the second integral signal from its second output terminal. The second-stage integrator includes a third input resistor, a fourth input resistor, a first filter resistor, a second filter resistor, a third filter capacitor, a fourth filter capacitor, and a second operational amplifier. The third input resistor is connected between the first input terminal of the second-stage integrator and the first input terminal of the second operational amplifier. The fourth input resistor is connected between the second input terminal of the second-stage integrator and the second input terminal of the second operational amplifier. The first filter resistor and the third filter capacitor are connected in series and then connected across the first input terminal and the inverting output terminal of the second operational amplifier. The second filter resistor and the fourth filter capacitor are connected in series and then connected across the second input terminal and the non-inverting output terminal of the second operational amplifier.

[0012] Optionally, it also includes a first input capacitor and a second input capacitor; a first terminal of the first input capacitor is connected to the first input signal, and a second terminal of the first input capacitor is connected to the first input terminal of the fully differential integrator; a first terminal of the second input capacitor is connected to the second input signal, and a second terminal of the second input capacitor is connected to the second input terminal of the fully differential integrator, wherein the second input signal includes the differential mode signal or ground signal of the first input signal.

[0013] Optionally, the half-bridge unit includes a first power amplification MOSFET and a second power amplification MOSFET. The first terminal of the first power amplification MOSFET is connected to the first positive power supply voltage. The second terminal of the first power amplification MOSFET outputs the first amplified signal and is connected to the first terminal of the second power amplification MOSFET. The second terminal of the second power amplification MOSFET is connected to the first negative power supply voltage.

[0014] Optionally, the half-bridge unit includes a first power amplification GaN device and a second power amplification GaN device. The first terminal of the first power amplification GaN device is connected to the first positive power supply voltage. The second terminal of the first power amplification GaN device outputs the first amplified signal and is connected to the first terminal of the second power amplification GaN device. The second terminal of the second power amplification GaN device is connected to the first negative power supply voltage.

[0015] Optionally, the feedback module includes a first feedback resistor and a second feedback resistor; the first end of the first feedback resistor is connected to the output terminal of the half-bridge unit, and the second end of the first feedback resistor is connected to the first input terminal of the fully differential integrator; the first end of the second feedback resistor is connected to the power ground terminal, and the second end of the second feedback resistor is connected to the second input terminal of the fully differential integrator.

[0016] According to a second aspect of the present invention, a circuit architecture is provided, including the fully differential closed-loop modulation circuit provided in the first aspect of the present invention.

[0017] According to a third aspect of the present invention, an electronic device is provided, comprising the circuit architecture provided in the second aspect of the present invention.

[0018] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the fully differential closed-loop modulation circuit provided by this invention, the subtractor subtracts the first and second integral signals output by the fully differential integrator to obtain a differential signal. This greatly suppresses the residual PWM high-frequency signal between the first and second integral signals, thereby avoiding new high-frequency interference caused by intermodulation between the residual PWM high-frequency signal and the carrier triangular wave signal. This effectively suppresses harmonic distortion caused by the residual PWM high-frequency signal. Since the output stage in the power amplifier module is a half-bridge unit, and only two power amplifier MOSFETs are used in the half-bridge unit, the circuit cost is greatly reduced. Furthermore, because the power supply terminal of the half-bridge unit in the power amplifier module is connected to the first positive power supply voltage, and the ground terminal of the half-bridge unit is connected to the first negative power supply voltage, and the first positive and first negative power supply voltages have opposite polarities and equal magnitudes, the first amplified signal output by the half-bridge unit is AC, thus eliminating the need for an additional DC blocking capacitor. This further reduces the circuit cost while ensuring the signal quality of the first amplified signal. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 Schematic diagram of the fully differential closed-loop modulation circuit provided in the first embodiment Figure 1 ; Figure 2 Schematic diagram of the fully differential closed-loop modulation circuit provided in the first embodiment Figure 2 ; Figure 3 A schematic diagram of the circuit structure of the fully differential closed-loop modulation circuit provided in the second embodiment; Figure 4 A schematic diagram of the circuit structure of the fully differential closed-loop modulation circuit provided in the third embodiment. Detailed Implementation

[0021] As described in the background section, existing fully differential closed-loop modulation circuits still suffer from harmonic distortion due to residual high-frequency PWM signals aliasing into the audio band. Furthermore, the use of an H-bridge structure at the power output terminal increases the circuit cost of existing fully differential closed-loop modulation circuits.

[0022] In view of this, the technical solution of the present invention provides a novel fully differential closed-loop modulation circuit, including a fully differential integrator, a subtractor, a comparator, a power amplifier module, and a feedback module. The subtractor subtracts the first and second integrated signals output by the fully differential integrator to obtain a differential signal, which greatly suppresses the residual PWM high-frequency signal between the first and second integrated signals, thereby avoiding harmonic distortion caused by the residual PWM high-frequency signal and harmonic components generated when compared with the carrier triangular wave signal. The drive unit and half-bridge unit in the power amplifier module output a first amplified signal according to the pulse width modulation signal output by the comparator. Since the drive unit and half-bridge unit are both connected to positive and negative power supplies with opposite polarities and equal magnitudes, the first amplified signal is AC, thus eliminating the need for a DC blocking capacitor, thereby reducing circuit cost while improving the quality of the first amplified signal.

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0026] [First Embodiment] Figure 1 A schematic diagram of the fully differential closed-loop modulation circuit provided in this embodiment. Figure 1 .

[0027] Please refer to Figure 1 The fully differential closed-loop modulation circuit provided in this embodiment includes a fully differential integrator 10, a subtractor 20, a comparator Comp, a power amplifier module 30, and a feedback module 40.

[0028] The fully differential integrator 10 is used to integrate the received first input signal VIN+, the received second input signal VIN-, the feedback first amplified signal VOUT+, and the feedback second amplified signal (VOUT-), and output the first integrated signal V1 and the second integrated signal V2.

[0029] The subtractor 20 is used to subtract the first integral signal V1 and the second integral signal V2 output by the full differential integrator 10 to obtain the differential signal Vdiff and output it.

[0030] The comparator Comp is used to compare the carrier triangular wave signal Vtri and the differential signal Vdiff, and outputs the pulse width modulation signal Vpwm based on the comparison result.

[0031] The power amplification module 30 includes a drive unit 31 and a half-bridge unit 32. The drive unit 31 processes the pulse width modulation signal Vpwm and outputs a first drive control signal and a second drive control signal. The half-bridge unit 32 outputs the first amplified signal VOUT+ based on the first and second drive control signals. The power supply terminal of the half-bridge unit 32 is connected to a first positive power supply voltage VCC1, and the ground terminal of the half-bridge unit 32 is connected to a first negative power supply voltage -VCC1. The first positive power supply voltage VCC1 and the first negative power supply voltage -VCC1 have opposite polarities and equal magnitudes. The drive unit is a corresponding drive circuit designed according to the requirements of the half-bridge unit.

[0032] The feedback module 40 is used to feed back the first amplified signal VOUT+ output by the power amplification module 30 and the power ground as the second amplified signal (VOUT-) to the fully differential integrator 10.

[0033] Compared to existing closed-loop fully differential modulation circuits that use a full-bridge structure and a single power supply system for the power output stage, adopting a half-bridge structure (i.e., half-bridge unit 32) for the power output stage can significantly reduce circuit costs. However, because the output signal of half-bridge unit 32 has a large DC component, when the subsequent load is an inductive load such as a speaker, it can cause DC components at the speaker terminals, leading to load damage. Therefore, existing technology requires an additional DC blocking capacitor between half-bridge unit 32 and the subsequent load. This DC blocking capacitor not only attenuates the low-frequency signal in the first amplified signal VOUT+, but also causes phase distortion and waveform distortion in the first amplified signal VOUT+.

[0034] In this embodiment, the power supply terminal of the half-bridge unit 32 is connected to the first positive power supply voltage VCC1, and the ground terminal of the half-bridge unit 32 is connected to the first negative power supply voltage -VCC1. Furthermore, the first positive power supply voltage VCC1 and the first negative power supply voltage -VCC1 have opposite polarities and equal magnitudes. Therefore, the first amplified signal VOUT+ output by the half-bridge unit 32 is AC, eliminating the need for an additional DC blocking capacitor and ensuring the signal quality of the first amplified signal VOUT+. It should be noted that the specific values ​​of the first positive power supply voltage VCC1 and the first negative power supply voltage -VCC1 can be adjusted according to actual applications and are not limited here.

[0035] Specifically, the half-bridge unit 32 includes a first power amplifier MOSFET P1 and a second power amplifier MOSFET N1. The first terminal of the first power amplifier MOSFET P1 is connected to the first positive power supply voltage VCC1. The second terminal of the first power amplifier MOSFET P1 outputs the first amplified signal VOUT+ and is connected to the first terminal of the second power amplifier MOSFET N1. The second terminal of the second power amplifier MOSFET N1 is connected to the first negative power supply voltage -VCC1. The control terminal of the first power amplifier MOSFET P1 is connected to the first drive control signal, and the control terminal of the second power amplifier MOSFET N1 is connected to the second drive control signal.

[0036] Furthermore, in this embodiment, the first power amplifier MOSFET P1 is a PMOS transistor, therefore, the first terminal of the first power amplifier MOSFET P1 is the source of the PMOS transistor, and the second terminal of the first power amplifier MOSFET P1 is the drain of the PMOS transistor. The second power amplifier MOSFET N1 is an NMOS transistor, therefore, the first terminal of the second power amplifier MOSFET N1 is the drain of the NMOS transistor, and the second terminal of the second power amplifier MOSFET N1 is the drain of the NMOS transistor.

[0037] The first power amplifier MOSFET P1 can also be replaced with an NMOS transistor. Therefore, the first terminal of the first power amplifier MOSFET P1 is the drain of the NMOS transistor, and the second terminal of the first power amplifier MOSFET P1 is the source of the NMOS transistor. The second power amplifier MOSFET N1 is an NMOS transistor, therefore, the first terminal of the second power amplifier MOSFET N1 is the drain of the NMOS transistor, and the second terminal of the second power amplifier MOSFET N1 is also the drain of the NMOS transistor.

[0038] The first power amplifier MOSFET P1 can also be replaced with a GaN device, which is not limited here.

[0039] Specifically, the driving unit 31 includes a logic operation circuit and a level shifting circuit. The logic operation circuit performs logical operations on the input signal. The level shifting circuit shifts the output signal of the logic operation circuit and outputs it. Since both the logic operation circuit and the level shifting circuit can be selected from the logic operation circuit and level shifting circuit integrated in the power stage of an existing fully differential modulation circuit, further details about the logic operation circuit and the level shifting circuit are omitted here. Please refer to the following for further information. Figure 1 and Figure 2 Specifically, the fully differential integrator 10 includes a first-stage integration unit 11.

[0040] The first input terminal of the first-stage integration unit 11 serves as the first input terminal of the fully differential integrator 10, and the second input terminal of the first-stage integration unit 11 serves as the second input terminal of the fully differential integrator 10. The first-stage integration unit 11 is used to integrate the first input signal VIN+ and the second input signal VIN-, and output the first integrated signal V1 and the second integrated signal V2.

[0041] Please continue to refer to this. Figure 2 Furthermore, the first-stage integration unit 11 includes a first input resistor Rin1, a second input resistor Rin2, a first filter capacitor C1, a second filter capacitor C2, and a first operational amplifier OA1; the first end of the first input resistor Rin1 serves as the first input terminal of the first-stage integration unit 11, and the second end of the first input resistor Rin1 is connected to the first input terminal of the first operational amplifier OA1; the first end of the second input resistor Rin2 serves as the second input terminal of the first-stage integration unit 11, and the second end of the second input resistor Rin2 is connected to the second input terminal of the first operational amplifier OA1; the first end of the first filter capacitor C1 is connected to the first input terminal of the first operational amplifier OA1, and the second end of the first filter capacitor C1 is connected to the second output terminal of the first operational amplifier OA1; the second output terminal of the first operational amplifier OA1 outputs the first integration signal V1, and the first output terminal of the first operational amplifier OA1 outputs the second integration signal V2. In this embodiment, the first input terminal of the first operational amplifier OA1 is a non-inverting input terminal, the second input terminal of the first operational amplifier OA1 is an inverting input terminal, the second output terminal of the first operational amplifier OA1 is an inverting output terminal, and the first output terminal of the first operational amplifier OA1 is a non-inverting output terminal.

[0042] The feedback PWM signal is attenuated to some extent by the fully differential integrator 10 mentioned above. However, due to the limited bandwidth and first-order structure of the integrator, a residual high-frequency PWM signal remains in the integrator's output signal. This residual high-frequency PWM signal further aliased with the carrier triangular wave signal, generating harmonic signals within the audio band. Consequently, the final system output contains low-frequency harmonic distortion.

[0043] To suppress residual PWM high-frequency signals in the first integral signal V1 and the second integral signal V2, this embodiment uses a subtractor 20 to subtract the first integral signal V1 and the second integral signal V2, obtaining the differential signal Vdiff between them. Since the residual PWM high-frequency signals in the first integral signal V1 and the second integral signal V2 have the same amplitude and polarity, subtracting the first integral signal V1 and the second integral signal V2 by the subtractor 20 can eliminate the residual PWM high-frequency signals in the first integral signal V1 and the second integral signal V2. This avoids intermodulation between the residual PWM high-frequency signals and the subsequent carrier triangular wave signal Vtri, thus preventing new high-frequency interference and effectively suppressing harmonic distortion caused by the residual PWM high-frequency signals.

[0044] Specifically, the subtractor 20 includes a differential amplifier. The first input terminal of the differential amplifier is connected to the first output terminal of the fully differential integrator 10, and the second input terminal of the differential amplifier is connected to the second output terminal of the fully differential integrator 10. The bias terminal of the differential amplifier is grounded to GND. The differential amplifier differentially amplifies the first integral signal V1 and the second integral signal V2 to obtain the differential signal Vdiff and output it.

[0045] In this embodiment, the subtractor 20 can be powered by a positive power supply, such as 0 to 12V, or by a positive and negative power supply, such as -12V to 12V, without limitation.

[0046] The second input terminal of the comparator Comp is connected to the output terminal of the subtractor 20, and the first input terminal of the comparator Comp is connected to the carrier triangular wave signal Vtri. The comparator Comp is used to compare the carrier triangular wave signal Vtri and the differential signal Vdiff, and outputs the pulse width modulation signal Vpwm according to the comparison result.

[0047] In this embodiment, the comparator Comp can be powered by a positive power supply, such as 0 to 12V, or by a positive and negative power supply, such as -12V to 12V, without limitation.

[0048] In this embodiment, the carrier triangular wave signal Vtri can be realized by linear control of capacitor charging and discharging, or it can be generated by digital signal processing technology using a microprocessor or dedicated waveform generator chip, and then converted into an analog waveform by a digital-to-analog converter. No limitation is made here.

[0049] Specifically, the feedback module 40 includes a first feedback resistor Rfb1 and a second feedback resistor Rfb2.

[0050] The first end of the first feedback resistor Rfb1 is connected to the second end of the first power amplifier MOS transistor P1, and the second end of the first feedback resistor Rfb1 is connected to the first input terminal of the first operational amplifier OA1, thereby providing feedback to the first amplified signal VOUT+ through the first feedback resistor Rfb1.

[0051] The first end of the second feedback resistor Rfb2 is connected to ground GND, and the second end of the second feedback resistor Rfb2 is connected to the second input terminal of the first operational amplifier OA1.

[0052] In summary, in the fully differential closed-loop modulation circuit provided in this embodiment, the subtractor subtracts the first and second integral signals output by the fully differential integrator to obtain a differential signal. This greatly suppresses the residual PWM high-frequency signal between the first and second integral signals, thereby avoiding new high-frequency interference caused by the intermodulation of the residual PWM high-frequency signal and the carrier triangular wave signal. This effectively suppresses harmonic distortion caused by the residual PWM high-frequency signal. Since the output stage in the power amplifier module is a half-bridge unit, and only two power amplifier MOSFETs are used in the half-bridge unit, the circuit cost is significantly reduced. Furthermore, because the power supply terminal of the half-bridge unit in the power amplifier module is connected to the first positive power supply voltage, and the ground terminal of the half-bridge unit is connected to the first negative power supply voltage, and the first positive and first negative power supply voltages have opposite polarities and equal magnitudes, the first amplified signal output by the half-bridge unit is AC, thus eliminating the need for an additional output DC blocking capacitor. This further reduces the circuit cost while ensuring the signal quality of the first amplified signal.

[0053] [Second Embodiment] This embodiment is a supplementary embodiment to the first embodiment. Please refer to it. Figure 3 The difference between this embodiment and the first embodiment is that this embodiment further includes a second-stage integration unit 12. The first-stage integration unit 11 performs first-stage integration processing on the first input signal VIN+ and the second input signal VIN-, and outputs a third-stage integration signal and a fourth-stage integration signal.

[0054] The first input terminal of the second-stage integration unit 12 is connected to the third integration signal, and the second input terminal of the second integration unit is connected to the fourth integration signal. The second-stage integration unit 12 is used to perform two-stage integration processing on the third integration signal and the fourth integration signal, and outputs the first integration signal V1 from its first output terminal and the second integration signal V2 from its second output terminal.

[0055] Please continue to refer to this. Figure 3Specifically, the second-stage integration unit 12 includes a third input resistor Rin3, a fourth input resistor Rin4, a first filter resistor Rf1, a second filter resistor Rf2, a third filter capacitor C3, a fourth filter capacitor C4, and a second operational amplifier OA2. The first terminal of the third input resistor Rin3 serves as the first input terminal of the second-stage integration unit 12, and the second terminal of the third input resistor Rin3 is connected to the first input terminal of the second operational amplifier OA2. The first terminal of the fourth input resistor Rin4 serves as the second input terminal of the second-stage integration unit 12, and the second terminal of the fourth input resistor Rin4 is connected to the second input terminal of the second operational amplifier OA2. The first filter resistor Rf1 and the third filter capacitor C3 are connected in series and then connected across the non-inverting input terminal and the inverting output terminal of the second operational amplifier OA2. The second filter resistor Rf2 and the fourth filter capacitor C4 are connected in series and then connected across the inverting input terminal and the first output terminal of the second operational amplifier OA2. The second output terminal of the second operational amplifier OA2 serves as the first output terminal of the second-stage integration unit 12. In this embodiment, the first input terminal of the second operational amplifier OA2 is a non-inverting input terminal, the second input terminal of the second operational amplifier OA2 is an inverting input terminal, the second output terminal of the second operational amplifier OA2 is an inverting output terminal, and the first output terminal of the second operational amplifier OA2 is a non-inverting output terminal.

[0056] In this embodiment, the power supply terminal of the second operational amplifier is connected to the second positive power supply voltage VCC2, and the ground terminal of the second operational amplifier is connected to the second negative power supply voltage -VCC2, thereby also improving the output range of the first operational amplifier.

[0057] [Third Embodiment] This embodiment is a variation of the first embodiment; please refer to it. Figure 4 The difference between this embodiment and the first embodiment is that this embodiment replaces the differential input of the first embodiment with a single-ended input, and additionally sets a first input capacitor C7 and a second input capacitor C8. The first terminal of the first input capacitor C7 is connected to the first input signal VIN+, and the second terminal of the first input capacitor C7 is connected to the first input terminal of the fully differential integrator 10; the first terminal of the second input capacitor C8 is connected to the second input signal, and the second terminal of the second input capacitor C8 is connected to the second input terminal of the fully differential integrator 10. The second input signal is either the differential mode signal or the ground signal of the first input signal, which is not limited here.

[0058] Other embodiments also provide a circuit architecture including the fully differential closed-loop modulation circuit provided in the above embodiments.

[0059] Other embodiments also provide an electronic device including the circuit architecture provided in the above embodiments.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fully differential closed-loop modulation circuit, characterized in that, include: A fully differential integrator is used to integrate a received first input signal, a received second input signal, a feedback first amplified signal, and a feedback second amplified signal, and output a first integrated signal and a second integrated signal. A subtractor is used to subtract the first integral signal and the second integral signal output by the full differential integrator to obtain a differential signal and output it. A comparator is used to compare the carrier triangular wave signal and the differential signal, and output a pulse width modulation signal based on the comparison result; A power amplification module includes a drive unit and a half-bridge unit. The drive unit processes the pulse width modulation signal and outputs a first drive control signal and a second drive control signal. The half-bridge unit outputs the first amplified signal according to the first drive control signal and the second drive control signal. The power supply terminal of the half-bridge unit is connected to a first positive power supply voltage, and the ground terminal of the half-bridge unit is connected to a first negative power supply voltage. The first positive power supply voltage and the first negative power supply voltage have opposite polarities and equal magnitudes. The feedback module is used to feed back the first amplified signal output by the power amplification module and the power ground as the second amplified signal to the fully differential integrator.

2. The modulation circuit with fully differential closed loop according to claim 1, characterized in that, The fully differential integrator includes a first-stage integration unit; The first input terminal of the first-stage integration unit serves as the first input terminal of the fully differential integrator, and the second input terminal of the first-stage integration unit serves as the second input terminal of the fully differential integrator. The first-stage integration unit is used to integrate the first input signal, the second input signal, and the first amplified signal and / or the second amplified signal fed back by the feedback module, and outputs the first integrated signal and the second integrated signal. The first-stage integration unit includes a first input resistor, a second input resistor, a first filter capacitor, a second filter capacitor, and a first operational amplifier; The first input resistor is connected between the first input terminal of the first-stage integrator and the inverting input terminal of the first operational amplifier; the second input resistor is connected between the second input terminal of the first-stage integrator and the non-inverting input terminal of the first operational amplifier; the first filter capacitor is connected between the first input terminal and the second output terminal of the first operational amplifier; the second filter capacitor is connected between the second input terminal and the first output terminal of the first operational amplifier; the second output terminal of the first operational amplifier outputs the first integrated signal, and the first output terminal of the first operational amplifier outputs the second integrated signal.

3. The modulation circuit with a fully differential closed loop according to claim 1, characterized in that, The fully differential integrator also includes a two-level architecture of a first-level integration unit and a second-level integration unit; The first input terminal of the first-stage integration unit serves as the first input terminal of the fully differential integrator, and the second input terminal of the first-stage integration unit serves as the second input terminal of the fully differential integrator. The first-stage integration unit is used to perform one integration process on the first input signal and the second input signal, and output the third integration signal and the fourth integration signal. The first input terminal of the second-stage integrator is connected to the third integral signal output by the first-stage integrator, and the second input terminal of the second integrator is connected to the fourth integral signal output by the first-stage integrator. The second-stage integrator is used to perform another integration process on the third integral signal and the fourth integral signal, and outputs the first integral signal from its first output terminal and the second integral signal from its second output terminal. The second-stage integration unit includes a third input resistor, a fourth input resistor, a first filter resistor, a second filter resistor, a third filter capacitor, a fourth filter capacitor, and a second operational amplifier; The third input resistor is connected between the first input terminal of the second-stage integrator and the first input terminal of the second operational amplifier; the fourth input resistor is connected between the second input terminal of the second-stage integrator and the second input terminal of the second operational amplifier; the first filter resistor and the third filter capacitor are connected in series and then connected across the first input terminal and the inverting output terminal of the second operational amplifier; the second filter resistor and the fourth filter capacitor are connected in series and then connected across the second input terminal and the non-inverting output terminal of the second operational amplifier.

4. The modulation circuit with a fully differential closed loop according to claim 1, characterized in that, It also includes a first input capacitor and a second input capacitor; the first end of the first input capacitor is connected to the first input signal, and the second end of the first input capacitor is connected to the first input terminal of the fully differential integrator; the first end of the second input capacitor is connected to the second input signal, and the second end of the second input capacitor is connected to the second input terminal of the fully differential integrator, wherein the second input signal includes the differential mode signal or the ground signal of the first input signal.

5. The modulation circuit with a fully differential closed loop according to claim 1, characterized in that, The half-bridge unit includes a first power amplifier MOSFET and a second power amplifier MOSFET. The first terminal of the first power amplifier MOSFET is connected to the first positive power supply voltage. The second terminal of the first power amplifier MOSFET outputs the first amplified signal and is connected to the first terminal of the second power amplifier MOSFET. The second terminal of the second power amplifier MOSFET is connected to the first negative power supply voltage.

6. The modulation circuit with a fully differential closed loop according to claim 1, characterized in that, The half-bridge unit includes a first power amplification GaN device and a second power amplification GaN device. The first terminal of the first power amplification GaN device is connected to the first positive power supply voltage. The second terminal of the first power amplification GaN device outputs the first amplified signal and is connected to the first terminal of the second power amplification GaN device. The second terminal of the second power amplification GaN device is connected to the first negative power supply voltage.

7. The modulation circuit with a fully differential closed loop according to claim 1, characterized in that, The feedback module includes a first feedback resistor and a second feedback resistor; the first end of the first feedback resistor is connected to the output terminal of the half-bridge unit, and the second end of the first feedback resistor is connected to the first input terminal of the fully differential integrator; the first end of the second feedback resistor is connected to the power ground terminal, and the second end of the second feedback resistor is connected to the second input terminal of the fully differential integrator.

8. A circuit architecture, characterized in that, The modulation circuit includes the fully differential closed-loop modulation circuit as described in any one of claims 1 to 7.

9. An electronic device, characterized in that, Includes the circuit architecture described in claim 8.

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