Universal input / output circuit and artificial intelligence chip

Abstract

The invention provides a universal input and output circuit and an artificial intelligence chip. The universal input / output circuit comprises a transmitting end circuit. The transmitting end circuit comprises a first switching circuit, a second switching circuit, a first protection circuit, a second protection circuit and a resistor. The first protection circuit is electrically connected with the first switch circuit. The second protection circuit is electrically connected with the second switch circuit and the first protection circuit. The first end of the resistor is electrically connected with the first protection circuit and the second protection circuit, and the second end of the resistor is electrically connected with the input / output end of the universal input / output circuit. The universal input and output circuit and the artificial intelligence chip can be realized by a small circuit layout area.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic circuits, and in particular to a general-purpose input / output circuit and an artificial intelligence chip. BACKGROUND

[0002] A conventional general-purpose input / output (GPIO) circuit needs to convert or transmit the voltage of a data signal provided to an external device through a level shifter or design an input / output device with high voltage resistance. However, with the evolution of process technology and the reduction of chip size, the large circuit layout area required by the level shifter and the input / output device with high voltage resistance is not conducive to the reduction of chip size, thus posing new challenges to the design of the GPIO circuit. SUMMARY

[0003] The present application is directed to a general-purpose input / output circuit and an artificial intelligence chip, which can effectively realize the input / output transmission function of signals and can be realized by a small circuit layout area.

[0004] According to an embodiment of the present application, the general-purpose input / output circuit includes a sending end circuit. The sending end circuit includes a first switch circuit, a second switch circuit, a first protection circuit, a second protection circuit, and a resistor. The first protection circuit is electrically connected to the first switch circuit. The second protection circuit is electrically connected to the second switch circuit and the first protection circuit. The first end of the resistor is electrically connected to the first protection circuit and the second protection circuit. The second end of the resistor is electrically connected to the input / output end of the general-purpose input / output circuit.

[0005] In the general-purpose input / output circuit according to the embodiment of the present application, the first protection circuit includes a first protection transistor. The first end of the first protection transistor is electrically connected to the first switch circuit. The second end of the first protection transistor is electrically connected to the first end of the resistor. The second protection circuit includes a second protection transistor. The first end of the second protection transistor is electrically connected to the first end of the resistor. The second end of the second protection transistor is electrically connected to the second switch circuit.

[0006] In the general-purpose input / output circuit according to the embodiment of the present application, the control end of the first protection transistor receives a first protection signal. The control end of the second protection transistor receives a second protection signal. The first protection transistor and the second protection transistor respectively operate in a linear region mode according to the first protection signal and the second protection signal, respectively.

[0007] In a general-purpose input / output circuit according to an embodiment of the present invention, the first protection transistor is a P-type transistor, and the second protection transistor is an N-type transistor.

[0008] In a general-purpose input / output circuit according to an embodiment of the present invention, the transmitting circuit further includes a driving circuit. The driving circuit is electrically connected to a first switching circuit and a second switching circuit, and is used to receive input data and a drive intensity control signal. The driving circuit controls the first switching circuit and the second switching circuit according to the drive intensity control signal and the input data.

[0009] In a general-purpose input / output circuit according to an embodiment of the present invention, the first switching circuit, the second switching circuit, the first protection circuit, the second protection circuit, and the resistor operate in the high voltage domain, while the drive circuit operates in the low voltage domain.

[0010] In a general-purpose input / output circuit according to an embodiment of the present invention, a first switching circuit includes at least one first switching transistor. A first terminal of the at least one first switching transistor is electrically connected to a first operating voltage. A second terminal of the at least one first switching transistor is electrically connected to a first protection circuit. A control terminal of the at least one first switching transistor is electrically connected to a drive circuit. A second switching circuit includes at least one second switching transistor. A first terminal of the at least one second switching transistor is electrically connected to a second protection circuit. A second terminal of the at least one second switching transistor is electrically connected to ground. A control terminal of the at least one second switching transistor is electrically connected to a drive circuit.

[0011] In a general-purpose input / output circuit according to an embodiment of the present invention, at least one first switching transistor is a P-type transistor. At least one second switching transistor is an N-type transistor.

[0012] In a general-purpose input / output circuit according to an embodiment of the present invention, the driving circuit includes at least one driving unit. Each of the at least one driving unit is electrically connected to a control terminal corresponding to at least one first switching transistor and a corresponding to at least one second switching transistor.

[0013] In a general-purpose input / output circuit according to an embodiment of the present invention, each of at least one driving unit includes a NAND gate and an AND gate. The first input terminal of the NAND gate receives input data. The second input terminal of the NAND gate receives an enable signal, and the output terminal of the NAND gate is electrically connected to a corresponding first switching transistor. Alternatively, the first input terminal of the NAND gate receives input data, and the second input terminal of the AND gate receives an enable signal. The output terminal of the AND gate is electrically connected to a corresponding second switching transistor. The enable signal is determined according to a drive strength control signal.

[0014] In a general-purpose input / output circuit according to an embodiment of the present invention, the general-purpose input / output circuit further includes a receiving circuit. The receiving circuit includes a first inverter circuit and a second inverter circuit. The input terminal of the first inverter circuit is electrically connected to the input / output terminal of the general-purpose input / output circuit. The input terminal of the second inverter circuit is electrically connected to the output terminal of the first inverter circuit.

[0015] In a general-purpose input / output circuit according to an embodiment of the present invention, the first inverter circuit operates in the high voltage domain, and the second inverter circuit operates in the low voltage domain.

[0016] In a general-purpose input / output circuit according to an embodiment of the present invention, the first inverter circuit includes a third switching transistor, a third protection circuit, a fourth protection circuit, and a fourth switching transistor. The first terminal of the third switching transistor is electrically connected to a first operating voltage. The control terminal of the third switching transistor is electrically connected to the input / output terminal of the general-purpose input / output circuit. The third protection circuit is electrically connected to the third switching transistor and the second inverter circuit. The fourth protection circuit is electrically connected to the third protection circuit and the second inverter circuit. The first terminal of the fourth switching transistor is electrically connected to the fourth protection circuit. The second terminal of the fourth switching transistor is electrically connected to ground voltage. The control terminal of the fourth switching transistor is electrically connected to the input / output terminal of the general-purpose input / output circuit.

[0017] In the general-purpose input / output circuit according to an embodiment of the present invention, the third switching transistor is a P-type transistor. The fourth switching transistor is an N-type transistor.

[0018] In a general-purpose input / output circuit according to an embodiment of the present invention, a third protection circuit includes a third protection transistor. The first terminal of the third protection transistor is electrically connected to the second terminal of the third switching transistor. The second terminal of the third protection transistor is electrically connected to a second inverter circuit. A fourth protection circuit includes a fourth protection transistor. The first terminal of the fourth protection transistor is electrically connected to the second inverter circuit. The second terminal of the fourth protection transistor is electrically connected to the first terminal of the fourth switching transistor.

[0019] In a general-purpose input / output circuit according to an embodiment of the present invention, the control terminal of the third protection transistor receives a third protection signal. The control terminal of the fourth protection transistor receives a fourth protection signal. The third protection transistor is a P-type transistor. The fourth protection transistor is an N-type transistor. The third and fourth protection transistors operate in linear region mode respectively according to the third and fourth protection signals.

[0020] In a general-purpose input / output circuit according to an embodiment of the present invention, the second inverter circuit includes a fifth switching transistor, a fifth protection circuit, a sixth protection circuit, and a sixth switching transistor. The first terminal of the fifth switching transistor is electrically connected to a second operating voltage. The control terminal of the fifth switching transistor is electrically connected to the first inverter circuit. The fifth protection circuit is electrically connected to the fifth switching transistor and the data output terminal of the general-purpose input / output circuit. The sixth protection circuit is electrically connected to the fifth protection circuit and the data output terminal of the general-purpose input / output circuit. The first terminal of the sixth switching transistor is electrically connected to the sixth protection circuit. The second terminal of the sixth switching transistor is electrically connected to ground voltage. The control terminal of the sixth switching transistor is electrically connected to the first inverter circuit.

[0021] In the general-purpose input / output circuit according to an embodiment of the present invention, the fifth switching transistor is a P-type transistor. The sixth switching transistor is an N-type transistor.

[0022] In a general-purpose input / output circuit according to an embodiment of the present invention, a fifth protection circuit includes a fifth protection transistor. The first terminal of the fifth protection transistor is electrically connected to the second terminal of the fifth switching transistor. The second terminal of the fifth protection transistor is electrically connected to the data output terminal of the general-purpose input / output circuit. A sixth protection circuit includes a sixth protection transistor. The first terminal of the sixth protection transistor is electrically connected to the data output terminal of the general-purpose input / output circuit. The second terminal of the sixth protection transistor is electrically connected to the first terminal of the sixth switching transistor.

[0023] In a general-purpose input / output circuit according to an embodiment of the present invention, the control terminal of the fifth protection transistor receives a fifth protection signal. The control terminal of the sixth protection transistor receives a sixth protection signal. The fifth switching transistor is a P-type transistor. The sixth switching transistor is an N-type transistor. The fifth and sixth protection transistors operate in linear region mode according to the fifth and sixth protection signals, respectively.

[0024] According to embodiments of the present invention, the artificial intelligence chip includes a core circuit, a general-purpose input / output circuit, and input / output pads. The general-purpose input / output circuit is electrically connected to the core circuit and has input / output terminals. The input / output pads are electrically connected to the input / output terminals. The general-purpose input / output circuit includes a transmitting circuit. The transmitting circuit includes a first switching circuit, a second switching circuit, a first protection circuit, a second protection circuit, and a resistor. The first protection circuit is electrically connected to the first switching circuit. The second protection circuit is electrically connected to the second switching circuit and the first protection circuit. The first terminal of the resistor is electrically connected to the first protection circuit and the second protection circuit. The second terminal of the resistor is electrically connected to the input / output terminals.

[0025] Based on the above, the general-purpose input / output circuit of the present invention and the artificial intelligence chip having the general-purpose input / output circuit can provide effective voltage protection through the first protection circuit and the second protection circuit.

[0026] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a general-purpose input / output circuit according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of a general-purpose input / output circuit according to another embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the driving unit according to an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention.

[0031] Explanation of icon numbers

[0032] 100: First general-purpose input / output circuit;

[0033] 200: Second general-purpose input / output circuit;

[0034] 420: Third general-purpose input / output circuit;

[0035] 101: Input / output terminal 1;

[0036] 201: Second input / output terminal;

[0037] 102: First data output terminal;

[0038] 202: Second data output terminal;

[0039] 110: First transmitting circuit;

[0040] 210: Second transmitting circuit;

[0041] 111: Switching circuit number 1_1;

[0042] 211: Switching circuit No. 2_1;

[0043] 112: Switch circuit 1-2;

[0044] 212: Switching circuit number 2_2;

[0045] 113: Protection circuit number 1_1;

[0046] 213: Protection Circuit No. 2_1;

[0047] 114: Protection circuit 1_2;

[0048] 214: Protection Circuit No. 2_2;

[0049] 115: First resistor;

[0050] 215: Second resistor;

[0051] 116: First driving circuit;

[0052] 216: Second drive circuit;

[0053] 120: First receiving circuit;

[0054] 220: Second receiving circuit;

[0055] 121: Inverter circuit No. 1_1;

[0056] 221: Inverter circuit No. 2_1;

[0057] 122: Inverter circuit 1-2;

[0058] 222: Inverter circuit number 2_2;

[0059] 2161: Drive unit;

[0060] 2161_1: First drive unit;

[0061] 2161_M: The Mth driving unit;

[0062] 2211: Third protection circuit;

[0063] 2212: Fourth protection circuit;

[0064] 2221: Fifth protection circuit;

[0065] 2222: Sixth protection circuit;

[0066] 301: NAND gate;

[0067] 302: AND gate;

[0068] 400: Artificial intelligence chip;

[0069] 410: Core circuit;

[0070] 430: Input / output pads;

[0071] Ts1: First switching transistor;

[0072] Ts1_1: Switch transistor number 1_1;

[0073] Ts1_M: The first_M switching transistor;

[0074] Ts2: Second switching transistor;

[0075] Ts2_1: The second_1st switching transistor;

[0076] Ts2_M: The second_M switching transistor;

[0077] Ts3: Third switching transistor;

[0078] Ts4: Fourth switching transistor;

[0079] Ts5: Fifth switching transistor;

[0080] Ts6: Sixth switching transistor;

[0081] Tp1: First protection transistor;

[0082] Tp2: Second protection transistor;

[0083] Tp3: Third protection transistor;

[0084] Tp4: Fourth protection transistor;

[0085] Tp5: Fifth protection transistor;

[0086] Tp6: Sixth protection transistor;

[0087] C1: First protection signal;

[0088] C2: Second protection signal;

[0089] C3: Third protection signal;

[0090] C4: Fourth protection signal;

[0091] C5: Fifth protection signal;

[0092] C6: Sixth protection signal;

[0093] Din: Input data;

[0094] DSC: Drive intensity control signal;

[0095] Dout: Output data;

[0096] EN: Enable signal. Detailed Implementation

[0097] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0098] Figure 1 This is a schematic diagram of a general-purpose input / output circuit according to an embodiment of the present invention. (See reference) Figure 1 The first general-purpose input / output circuit 100 includes a first transmitting circuit 110 and a first receiving circuit 120. In this embodiment, the first transmitting circuit 110 includes a first-first switching circuit 111, a first-second switching circuit 112, a first-first protection circuit 113, a first-second protection circuit 114, a first resistor 115, and a first driving circuit 116. Figure 1 In the illustrated embodiment, the first switch circuit 111 can also be referred to as the first switch circuit, the first switch circuit 112 can also be referred to as the second switch circuit, the first protection circuit 113 can also be referred to as the first protection circuit, and the first protection circuit 114 can also be referred to as the second protection circuit. The first protection circuit 113 is electrically connected to the first switch circuit 111. The first protection circuit 114 is electrically connected to the first switch circuit 112 and the first protection circuit 113. The first terminal of the first resistor 115 is electrically connected to the first protection circuit 113 and the first protection circuit 114. The second terminal of the first resistor 115 is electrically connected to the first input / output terminal 101 of the first general-purpose input / output circuit 100. The first drive circuit 116 is electrically connected to the first switch circuit 111 and the first switch circuit 112.

[0099] In this embodiment, the first receiving circuit 120 includes a first inverter circuit 121 and a second inverter circuit 122. In this embodiment, the first inverter circuit 121 can also be referred to as the first inverter circuit, and the second inverter circuit 122 can also be referred to as the second inverter circuit. The input terminal of the first inverter circuit 121 is electrically connected to the first input / output terminal 101 of the first general-purpose input / output circuit 100. The input terminal of the second inverter circuit 122 is electrically connected to the output terminal of the first inverter circuit 121 and the first data output terminal 102.

[0100] In this embodiment, the first driving circuit 116 receives input data Din and a drive intensity control signal DSC. The first driving circuit 116 is used to control the first_1 switching circuit 111 and the first_2 switching circuit 112 according to the drive intensity control signal DSC and the input data Din. The first_1 switching circuit 111 and the first_2 switching circuit 112 can be operated to alternately output high-level signals and low-level signals to the first_1 protection circuit 113 and the first_2 protection circuit 114, so that the first_1 protection circuit 113 and the first_2 protection circuit 114 alternately output voltage signals of high-level signals and low-level signals to the first resistor 115, and form a data signal corresponding to the input data Din to the first input / output terminal 101 of the first general-purpose input / output circuit 100. Specifically, the first switching circuit 111 outputs a high-level signal to the first protection circuit 113, so that the voltage signal of the high-level signal is output by the first protection circuit 113 to the first resistor 115; the first switching circuit 112 outputs a low-level signal to the first protection circuit 114, so that the voltage signal of the low-level signal is output by the first protection circuit 114 to the first resistor 115.

[0101] In this embodiment, the first switching circuit 111, the first switching circuit 112, the first protection circuit 113, the first protection circuit 114, and the first resistor 115 operate in the high-voltage domain, while the first driving circuit 116 operates in the low-voltage domain. The first transmitting circuit 110 converts the low-voltage input data Din into a high-voltage data signal and outputs the data signal via the first input / output terminal 101. The first protection circuit 113 and the first protection circuit 114 provide a voltage divider effect to reduce the voltage across the first switching circuit 111 and the first switching circuit 112, and effectively protect the first driving circuit 116 so that it operates in the low-voltage domain (or in a safe region).

[0102] It is important to note that the high voltage domain and low voltage domain described in this invention are relative. The high voltage domain described in this invention refers to the operating voltage of electronic components at a higher voltage than that of the low voltage domain. For example, the high voltage domain described in this invention may represent electronic components operating at approximately 1.2 volts or approximately 1.8 volts, and the low voltage domain may represent electronic components operating at approximately 0.75 volts or approximately 0.8 volts, and this invention is not limited thereto. The specific values ​​of the high voltage domain and low voltage domain may vary depending on the application of different circuit nodes, and may also be selected, for example, based on the device operating voltage of the Process Design Kit (PDK).

[0103] In this embodiment, the first inverter circuit 121 operates in the high-voltage domain, and the first inverter circuit 122 operates in the low-voltage domain. The first inverter circuit 121 and the first inverter circuit 122 can form a non-inverter circuit, and are used to convert the high-voltage domain data signal received at the first input / output terminal 101 into low-voltage domain output data Dout, and output the output data Dout from the first data output terminal 102 to the back-end circuit.

[0104] Figure 2 This is a schematic diagram of a general-purpose input / output circuit according to another embodiment of the present invention. (See reference) Figure 2 The second general-purpose input / output circuit 200 includes a second transmitting circuit 210 and a second receiving circuit 220. In this embodiment, the second transmitting circuit 210 includes a second-first switching circuit 211, a second-second switching circuit 212, a second-first protection circuit 213, a second-second protection circuit 214, a second resistor 215, and a second driving circuit 216. Figure 2 In the embodiment shown, the second_1 switch circuit 211 can also be called the first switch circuit, the second_2 switch circuit 212 can also be called the second switch circuit, the second_1 protection circuit 213 can also be called the first protection circuit, and the second_2 protection circuit 214 can also be called the second protection circuit.

[0105] In this embodiment, the second-level switching circuit 211 includes M switching transistors, from the first-level switching transistor Ts1_1 to the first-level switching transistor Ts1_M, where M is a positive integer. The number of the first-level switching transistors Ts1_1 to the first-level switching transistor Ts1_M can be one or more. If the number of the first-level switching transistors Ts1_1 to the first-level switching transistor Ts1_M is multiple, then the first-level switching transistors Ts1_1 to the first-level switching transistor Ts1_M are electrically connected in parallel. In this embodiment, the first terminals of the first-level switching transistors Ts1_1 to the first-level switching transistor Ts1_M are electrically connected to the first operating voltage V1. The second terminals of the first-level switching transistors Ts1_1 to the first-level switching transistor Ts1_M are electrically connected to the second-level protection circuit 213. The control terminals of the first-1 switching transistor Ts1_1 to the first-M switching transistor Ts1_M are electrically connected to the second drive circuit 216.

[0106] In this embodiment, the second-second switching circuit 212 includes M switching transistors, from the second-first switching transistor Ts2_1 to the second-m switching transistor Ts2_M. The number of the second-first switching transistors Ts2_1 to the second-m switching transistor Ts2_M can be one or more. If the number of the second-first switching transistors Ts2_1 to the second-m switching transistor Ts2_M is multiple, then the second-first switching transistors Ts2_1 to the second-m switching transistor Ts2_M are electrically connected in parallel. In this embodiment, the first terminals of the second-first switching transistors Ts2_1 to the second-m switching transistor Ts2_M are electrically connected to the second-second protection circuit 214. The second terminals of the second-first switching transistors Ts2_1 to the second-m switching transistor Ts2_M are electrically connected to ground. The control terminals of the second-first switching transistors Ts2_1 to the second-m switching transistor Ts2_M are electrically connected to the second driving circuit 216.

[0107] In this embodiment, the first 1st switching transistor Ts1_1 to the first 1st 1st switching transistor Ts1_M are P-type transistors, and the second 1st switching transistor Ts2_1 to the second 2nd 1st switching transistor Ts2_M are N-type transistors. The first terminal of the first 1st switching transistor Ts1_1 to the first 1st ... The control terminals of the first-to-last switching transistors Ts1_1 to Ts1_M and the second-to-last switching transistors Ts2_1 to Ts2_M can be the gate terminals of the transistors.

[0108] In this embodiment, the second protection circuit 213 includes a first protection transistor Tp1. The first terminal of the first protection transistor Tp1 is electrically connected to the second terminals of the first-in-1 switching transistors Ts1_1 to Ts1_M switching transistors Ts1_M of the second-in-1 switching circuit 211. The second terminal of the first protection transistor Tp1 is electrically connected to the first terminal of the second resistor 215. The second protection circuit 214 includes a second protection transistor Tp2. The first terminal of the second protection transistor Tp2 is electrically connected to the first terminal of the second resistor 215. The second terminal of the second protection transistor Tp2 is electrically connected to the first terminals of the second-in-1 switching transistors Ts2_1 to Ts2_M switching transistors Ts2_M of the second-in-2 switching circuit 212.

[0109] In this embodiment, the control terminal of the first protection transistor Tp1 receives the first protection signal C1, and the control terminal of the second protection transistor Tp2 receives the second protection signal C2. The first protection signal C1 and the second protection signal C2 can be constant voltages, and are used to clamp the first protection transistor Tp1 and the second protection transistor Tp2, so that the first protection transistor Tp1 and the second protection transistor Tp2 operate in the linear region mode respectively. The first protection transistor Tp1 and the second protection transistor Tp2 can be operated via the first protection signal C1 and the second protection signal C2 respectively, thus forming equivalent resistances, thereby allowing the first_1 switching transistors Ts1_1 to the first_M switching transistors Ts1_M and the second_1 switching transistors Ts2_1 to the second_M switching transistors Ts2_M to withstand lower voltages and have smaller parasitic capacitances during operation (or switching).

[0110] In this embodiment, the first protection transistor Tp1 is a P-type transistor, and the second protection transistor Tp2 is an N-type transistor, but the present invention is not limited thereto. Furthermore, the present invention does not limit the number of the first protection transistor Tp1 and the second protection transistor Tp2. In one embodiment, the second_1 protection circuit 213 and the second_2 protection circuit 214 may also be composed of multiple transistors connected in series or parallel, or one or more circuit elements that can form an equivalent resistance.

[0111] In this embodiment, the second driving circuit 216 includes a first driving unit 2161_1 to an Mth driving unit 2161_M. The number of the first driving units 2161_1 to the Mth driving units 2161_M is one or more, and their number corresponds to the number of the first_1 switching transistors Ts1_1 to the first_M switching transistors Ts1_M connected in parallel (and also corresponds to the number of the second_1 switching transistors Ts2_1 to the second_M switching transistors Ts2_M). Each of the first driving units 2161_1 to the Mth driving units 2161_M is electrically connected to the control terminal of a corresponding switching transistor of the first_1 switching transistors Ts1_1 to the first_M switching transistors Ts1_M and the control terminal of a corresponding switching transistor of the second_1 switching transistors Ts2_1 to the second_M switching transistors Ts2_M. The second driving circuit 216 receives input data Din and a drive strength control signal DSC. The second drive circuit 216 can control the second-first switch circuit 211 and the second-second switch circuit 212 through the first drive unit 2161_1 to the Mth drive unit 2161_M according to the drive intensity control signal DSC and the input data Din.

[0112] In this embodiment, the second_1 switching circuit 211, the second_2 switching circuit 212, the second_1 protection circuit 213, the second_2 protection circuit 214, and the second resistor 215 operate in the high-voltage domain, while the second driving circuit 216 operates in the low-voltage domain. The second transmitting circuit 210 converts the low-voltage domain input data Din into a high-voltage domain data signal and outputs the data signal via the second input / output terminal 201 of the second general-purpose input / output circuit 200. To this end, the first protection transistor Tp1 and the second protection transistor Tp2 can respectively provide a voltage divider effect to reduce the voltage experienced by the first_1 switching transistors Ts1_1 to the first_M switching transistors Ts1_M and the second_1 switching transistors Ts2_1 to the second_M switching transistors Ts2_M, and can effectively protect the second driving circuit 216 to operate in the low-voltage domain (or in a safe region).

[0113] In this embodiment, the second receiving circuit 220 includes a second-first inverter circuit 221 and a second-second inverter circuit 222. In this embodiment, the second-first inverter circuit 221 can also be referred to as the first inverter circuit, and the second-second inverter circuit 222 can also be referred to as the second inverter circuit. The input terminal of the second-first inverter circuit 221 is electrically connected to the second input / output terminal 201 of the second general-purpose input / output circuit 200. The input terminal of the second-second inverter circuit 222 is electrically connected to the output terminal of the second-first inverter circuit 221 and the second data output terminal 202.

[0114] In this embodiment, the second-first inverter circuit 221 includes a third switching transistor Ts3, a third protection circuit 2211, a fourth protection circuit 2212, and a fourth switching transistor Ts4. The first terminal of the third switching transistor Ts3 is electrically connected to a first operating voltage V1. The control terminal of the third switching transistor Ts3 is electrically connected to the second input / output terminal 201 of the second general-purpose input / output circuit 200. The third protection circuit 2211 is electrically connected to the third switching transistor Ts3 and the input terminal of the second-second inverter circuit 222. The fourth protection circuit 2212 is electrically connected to the third protection circuit 2211 and the input terminal of the second-second inverter circuit 222. The first terminal of the fourth switching transistor Ts4 is electrically connected to the fourth protection circuit 2212. The second terminal of the fourth switching transistor Ts4 is electrically connected to ground voltage. The control terminal of the fourth switching transistor Ts4 is electrically connected to the second input / output terminal 201 of the second general-purpose input / output circuit 200. In this embodiment, the third switching transistor Ts3 is a P-type transistor, and the fourth switching transistor Ts4 is an N-type transistor.

[0115] In this embodiment, the third protection circuit 2211 includes a third protection transistor Tp3. The first terminal of the third protection transistor Tp3 is electrically connected to the second terminal of the third switching transistor Ts3. The second terminal of the third protection transistor Tp3 is electrically connected to the input terminal of the second-second inverter circuit 222. The fourth protection circuit 2212 includes a fourth protection transistor Tp4. The first terminal of the fourth protection transistor Tp4 is electrically connected to the input terminal of the second-second inverter circuit 222. The second terminal of the fourth protection transistor Tp4 is electrically connected to the first terminal of the fourth switching transistor Ts4.

[0116] In this embodiment, the control terminal of the third protection transistor Tp3 receives the third protection signal C3. The control terminal of the fourth protection transistor Tp4 receives the fourth protection signal C4. The third protection signal C3 and the fourth protection signal C4 can be constant voltages, and are used to clamp the third protection transistor Tp3 and the fourth protection transistor Tp4, so that the third protection transistor Tp3 and the fourth protection transistor Tp4 operate in the linear region mode respectively. The third protection transistor Tp3 and the fourth protection transistor Tp4 are operated via the third protection signal C3 and the fourth protection signal C4 respectively, and thus form equivalent resistances, thereby allowing the third switching transistor Ts3 and the fourth switching transistor Ts4 to withstand lower voltages and have smaller parasitic capacitances during operation (or switching process). In one embodiment, the first protection signal C1 can be equal to the third protection signal C3, and the second protection signal C2 can be equal to the fourth protection signal C4.

[0117] In this embodiment, the third protection transistor Tp3 is a P-type transistor, and the fourth protection transistor Tp4 is an N-type transistor, but the present invention is not limited thereto. Furthermore, the present invention does not limit the number of the third protection transistor Tp3 and the fourth protection transistor Tp4. In one embodiment, the third protection circuit 2211 and the fourth protection circuit 2212 may also be composed of multiple transistors connected in series or parallel, or one or more circuit elements that can form an equivalent resistance. In this embodiment, the third protection transistor Tp3 and the fourth protection transistor Tp4 can respectively provide a voltage divider effect to reduce the voltage experienced by the third switching transistor Ts3 and the fourth switching transistor Ts4, and can effectively protect the second inverter circuit 222 operating in the low voltage domain.

[0118] In this embodiment, the second inverter circuit 222 includes a fifth switching transistor Ts5, a fifth protection circuit 2221, a sixth protection circuit 2222, and a sixth switching transistor Ts6. The first terminal of the fifth switching transistor Ts5 is electrically connected to the second operating voltage V2. The control terminal of the fifth switching transistor Ts5 is electrically connected to the second terminal of the third protection transistor Tp3 and the first terminal of the fourth protection transistor Tp4 of the second inverter circuit 221. The fifth protection circuit 2221 is electrically connected to the fifth switching transistor Ts5 and the second data output terminal 202 of the second general-purpose input / output circuit 200. The sixth protection circuit 2222 is electrically connected to the fifth protection circuit 2221 and the second data output terminal 202 of the second general-purpose input / output circuit 200. The first terminal of the sixth switching transistor Ts6 is electrically connected to the sixth protection circuit 2222. The second terminal of the sixth switching transistor Ts6 is electrically connected to ground voltage. The control terminal of the sixth switching transistor Ts6 is electrically connected to the second terminal of the third protection transistor Tp3 and the first terminal of the fourth protection transistor Tp4 of the second-inverter circuit 221. In this embodiment, the fifth switching transistor Ts5 is a P-type transistor, and the sixth switching transistor Ts6 is an N-type transistor.

[0119] In this embodiment, the fifth protection circuit 2221 includes a fifth protection transistor Tp5. The first terminal of the fifth protection transistor Tp5 is electrically connected to the second terminal of the fifth switching transistor Ts5. The second terminal of the fifth protection transistor Tp5 is electrically connected to the second data output terminal 202 of the second general-purpose input / output circuit 200. The sixth protection circuit 2222 includes a sixth protection transistor Tp6. The first terminal of the sixth protection transistor Tp6 is electrically connected to the second data output terminal 202 of the second general-purpose input / output circuit 200. The second terminal of the sixth protection transistor Tp6 is electrically connected to the first terminal of the sixth switching transistor Ts6.

[0120] In this embodiment, the control terminal of the fifth protection transistor Tp5 receives the fifth protection signal C5. The control terminal of the sixth protection transistor Tp6 receives the sixth protection signal C6. The fifth protection signal C5 and the sixth protection signal C6 can be constant voltages, used to clamp the fifth protection transistor Tp5 and the sixth protection transistor Tp6, so that the fifth protection transistor Tp5 and the sixth protection transistor Tp6 operate in the linear region mode respectively. The fifth protection transistor Tp5 and the sixth protection transistor Tp6 operate via the fifth protection signal C5 and the sixth protection signal C6 respectively, thus forming equivalent resistances, thereby allowing the fifth switching transistor Ts5 and the sixth switching transistor Ts6 to withstand lower voltages and have smaller parasitic capacitances during operation (or switching process). In one embodiment, the first protection signal C1 can be equal to the fifth protection signal C5, and the second protection signal C2 can be equal to the sixth protection signal C6. Alternatively, the third protection signal C3 can be equal to the fifth protection signal C5, and the fourth protection signal C4 can be equal to the sixth protection signal C6.

[0121] In this embodiment, the fifth protection transistor Tp5 is a P-type transistor, and the sixth protection transistor Tp6 is an N-type transistor, but the present invention is not limited thereto. Furthermore, the present invention does not limit the number of the fifth protection transistor Tp5 and the sixth protection transistor Tp6. In one embodiment, the fifth protection transistor Tp5 and the sixth protection transistor Tp6 may also be composed of multiple transistors connected in series or parallel, or one or more circuit elements that can form an equivalent resistance. In this embodiment, the fifth protection transistor Tp5 and the sixth protection transistor Tp6 can respectively provide a voltage divider effect to reduce the voltage experienced by the fifth switching transistor Ts5 and the sixth switching transistor Ts6, and can effectively protect the back-end chip core logic electrically connected to the second data output terminal 202 and operating in the low-voltage domain.

[0122] In this embodiment, the second-first inverter circuit 221 operates in the high-voltage domain, and the second-second inverter circuit 222 operates in the low-voltage domain. The second-first inverter circuit 221 and the second-second inverter circuit 222 can form a non-inverter circuit and are used to convert the data signal received at the second input / output terminal 201 from a high-voltage logic signal to a low-voltage logic signal, and output it from the second data output terminal 202.

[0123] In this embodiment, the first operating voltage V1 is higher than the second operating voltage V2. The first operating voltage V1 is used to cause the third switching transistor Ts3 and the third protection transistor Tp3 to convert the data signal provided by the second input / output terminal 201 of the second general-purpose input / output circuit 200 into a high-voltage logic signal. The second operating voltage V2 is used to cause the fifth switching transistor Ts5 and the fifth protection transistor Tp5 to convert the high-voltage logic signal provided by the second-first inverter circuit 221 into a low-voltage logic signal. In one embodiment, the first operating voltage V1 may correspond to the operating voltage of the communication interface of an external device electrically connected to the second input / output terminal 201. The second operating voltage V2 may be the operating voltage (or working voltage) of the back-end chip core logic electrically connected to the second data output terminal 202.

[0124] Therefore, the second general-purpose input / output circuit 200 of this embodiment can provide effective voltage protection for both the second transmitting circuit 210 and the second receiving circuit 220. Furthermore, since the second general-purpose input / output circuit 200 of this embodiment does not require a level shifter to change the voltage signal level, it can be implemented with a smaller circuit layout area.

[0125] Figure 3 This is a schematic diagram of a driving unit according to an embodiment of the present invention. (See reference) Figure 3 The following description uses a set of drive units 2161 as an example, and can be compared with the above. Figure 2 The first driving unit 2161_1 to the Mth driving unit 2161_M, the driving unit 2161 can be Figure 2 The first driving unit 2161_1 to the Mth driving unit 2161_M is used. In this embodiment, the driving unit 2161 includes a NAND gate 301 and an AND gate 302. The first input terminal of the NAND gate 301 receives input data Din. The second input terminal of the NAND gate 301 receives an enable signal EN. The output terminal of the NAND gate 301 is electrically connected to a first switching transistor Ts1, wherein the first switching transistor Ts1 is... Figure 2 The first switching transistor Ts1_1 to the first M switching transistor Ts1_M are electrically connected to the driving unit 2161. For example, if the driving unit 2161 is the first driving unit 2161_1, then the first switching transistor Ts1 is the first switching transistor Ts1_1. The first input terminal of AND gate 302 receives the input data Din. The second input terminal of AND gate 302 receives the enable signal En. The output terminal of AND gate 302 is electrically connected to the second switching transistor Ts2, wherein the second switching transistor Ts2 is... Figure 2The second switching transistor Ts2_1 to the second-M switching transistor Ts2_M are electrically connected to the driving unit 2161. For example, if the driving unit 2161 is the first driving unit 2161_1, then the second switching transistor Ts2 is the second-1 switching transistor Ts2_1. The first terminal of the first switching transistor Ts1 is electrically connected to the first operating voltage V1. The second terminal of the first switching transistor Ts1 is electrically connected to the first protection transistor Tp1. The first terminal of the second switching transistor Ts2 is electrically connected to the second protection transistor Tp2. The second terminal of the second switching transistor Ts2 is electrically connected to the ground voltage. The second terminal of the first protection transistor Tp1 is electrically connected to the second resistor 215 and the first terminal of the second protection transistor Tp2. The control terminal of the first protection transistor Tp1 receives the first protection signal C1. The control terminal of the second protection transistor Tp2 receives the second protection signal C2.

[0126] In this embodiment, the enable signal En is based on the above... Figure 2 The drive strength control signal DSC is determined by the drive strength control signal. The drive strength control signal DSC is a digital signal with a multi-bit width (e.g., using...). <x:0>wherein the number of bits thereof corresponds to the number of driving units. In this regard, one of the bits of the driving strength control signal DSC can serve as an enable signal En. More specifically, when the input data Din is written into the sending end circuit of the general-purpose input / output circuit, the sending end circuit of the general-purpose input / output circuit can determine the number of driving units to be used (i.e., determine the corresponding enable signal to be corresponding to a bit value of "0" or "1") through the driving strength control signal DSC according to the required driving strength.

[0127] Figure 4 is a schematic diagram of an artificial intelligence chip according to an embodiment of the present application. Referring to Figure 4 , the artificial intelligence chip 400 includes a core circuit 410, a third general-purpose input / output circuit 420, and an input / output pad 430. The third general-purpose input / output circuit 420 can have a circuit architecture as the first general-purpose input / output circuit 100 and the second general-purpose input / output circuit 200 of the above-described Figure 1 or Figure 2 embodiments. The relevant implementation and technical details of the third general-purpose input / output circuit 420 can be referred to the above-described descriptions of the first general-purpose input / output circuit 100 and the second general-purpose input / output circuit 200 of each of the above-described embodiments for sufficient teaching, suggestion, and implementation guidance.

[0128] In the present embodiment, the third general-purpose input / output circuit 420 has an input / output terminal. The third general-purpose input / output circuit 420 is electrically connected to the input / output pad 430 through the input / output terminal. The core circuit 410 can provide input data and a driving strength control signal to the third general-purpose input / output circuit 420, and can receive output data from the data output terminal of the third general-purpose input / output circuit 420. The third general-purpose input / output circuit 420 can receive a data signal (for the core circuit 410) received from an external device by the input / output pad 430 through the input / output terminal, and can also send a data signal (corresponding to the input data provided by the core circuit 410) to the input / output pad 430 through the input / output terminal, and thus to the external device.

[0129] The artificial intelligence chip 400 can be any one of a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU).

[0130] In summary, the universal input and output circuit and the artificial intelligence chip with the universal input and output circuit can provide a voltage division effect by designing a protection circuit in the receiving end circuit and the sending end circuit, so as to reduce the voltage borne by the switch transistor in the universal input and output circuit during operation, and effectively protect the core circuit operating in the low voltage domain. Moreover, the universal input and output circuit and the artificial intelligence chip with the universal input and output circuit can realize the above-mentioned circuit protection function in the form of a smaller circuit layout. In addition, the universal input and output circuit and the artificial intelligence chip with the universal input and output circuit also have the advantage of smaller parasitic capacitance.

[0131] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A general-purpose input / output circuit, characterized in that, include: The transmitting circuit includes: First switching circuit; Second switching circuit; The first protection circuit is electrically connected to the first switching circuit; The second protection circuit is electrically connected to the second switching circuit and the first protection circuit; and, A resistor, wherein a first end of the resistor is electrically connected to the first protection circuit and the second protection circuit, and a second end of the resistor is electrically connected to the input / output terminal of the general-purpose input / output circuit.

2. The general-purpose input / output circuit according to claim 1, characterized in that, The first protection circuit includes: A first protection transistor, wherein a first terminal of the first protection transistor is electrically connected to the first switching circuit, and a second terminal of the first protection transistor is electrically connected to the first terminal of the resistor. The second protection circuit includes: A second protection transistor, wherein the first terminal of the second protection transistor is electrically connected to the first terminal of the resistor, and the second terminal of the second protection transistor is electrically connected to a second switching circuit.

3. The general-purpose input / output circuit according to claim 2, characterized in that, The control terminal of the first protection transistor receives a first protection signal, and the control terminal of the second protection transistor receives a second protection signal. The first protection transistor and the second protection transistor operate in linear region mode according to the first protection signal and the second protection signal, respectively.

4. The general-purpose input / output circuit according to claim 2, characterized in that, The first protection transistor is a P-type transistor, and the second protection transistor is an N-type transistor.

5. The general-purpose input / output circuit according to claim 1, characterized in that, The transmitting circuit also includes: The driving circuit is electrically connected to the first switching circuit and the second switching circuit, and is used to receive input data and driving intensity control signals. The driving circuit controls the first switching circuit and the second switching circuit according to the driving intensity control signal and the input data.

6. The general-purpose input / output circuit according to claim 5, characterized in that, The first switching circuit, the second switching circuit, the first protection circuit, the second protection circuit, and the resistor operate in the high voltage domain, while the drive circuit operates in the low voltage domain.

7. The general-purpose input / output circuit according to claim 5, characterized in that, The first switching circuit includes at least one first switching transistor, a first terminal of the at least one first switching transistor is electrically connected to a first operating voltage, a second terminal of the at least one first switching transistor is electrically connected to the first protection circuit, and a control terminal of the at least one first switching transistor is electrically connected to the driving circuit. The second switching circuit includes at least one second switching transistor, the first terminal of the at least one second switching transistor is electrically connected to the second protection circuit, the second terminal of the at least one second switching transistor is electrically connected to the ground voltage, and the control terminal of the at least one second switching transistor is electrically connected to the driving circuit.

8. The general-purpose input / output circuit according to claim 7, characterized in that, The at least one first switching transistor is a P-type transistor, and the at least one second switching transistor is an N-type transistor.

9. The general-purpose input / output circuit according to claim 7, characterized in that, The driving circuit includes at least one driving unit, and each of the at least one driving unit is electrically connected to the control terminals of a corresponding one of the at least one first switching transistor and a corresponding one of the at least one second switching transistor.

10. The general-purpose input / output circuit according to claim 9, characterized in that, Each of the at least one driving unit includes: A NAND gate, wherein the first input of the NAND gate receives the input data, the second input of the NAND gate receives an enable signal, and the output of the NAND gate is electrically connected to the corresponding first switching transistor; and, An AND gate, wherein the first input of the AND gate receives the input data, the second input of the AND gate receives the enable signal, and the output of the AND gate is electrically connected to the corresponding second switching transistor. The enable signal is determined based on the drive intensity control signal.

11. The general-purpose input / output circuit according to claim 1, characterized in that, Also includes: The receiving circuit includes: A first inverter circuit, wherein the input terminal of the first inverter circuit is electrically connected to the input and output terminals of the general-purpose input and output circuit; as well as, A second inverter circuit, wherein the input terminal of the second inverter circuit is electrically connected to the output terminal of the first inverter circuit.

12. The general-purpose input / output circuit according to claim 11, characterized in that, The first inverter circuit operates in the high voltage domain, and the second inverter circuit operates in the low voltage domain.

13. The general-purpose input / output circuit according to claim 11, characterized in that, The first inverter circuit includes: A third switching transistor, wherein the first terminal of the third switching transistor is electrically connected to a first operating voltage, and the control terminal of the third switching transistor is electrically connected to the input / output terminal of the general-purpose input / output circuit; The third protection circuit is electrically connected to the third switching transistor and the second inverter circuit; The fourth protection circuit is electrically connected to the third protection circuit and the second inverter circuit; and, A fourth switching transistor, wherein the first terminal of the fourth switching transistor is electrically connected to the fourth protection circuit, the second terminal of the fourth switching transistor is electrically connected to the ground voltage, and the control terminal of the fourth switching transistor is electrically connected to the input / output terminal of the general-purpose input / output circuit.

14. The general-purpose input / output circuit according to claim 13, characterized in that, The third switching transistor is a P-type transistor, and the fourth switching transistor is an N-type transistor.

15. The general-purpose input / output circuit according to claim 13, characterized in that, The third protection circuit includes: A third protection transistor, wherein the first terminal of the third protection transistor is electrically connected to the second terminal of the third switching transistor, and the second terminal of the third protection transistor is electrically connected to the second inverter circuit. The fourth protection circuit includes: A fourth protection transistor, wherein the first terminal of the fourth protection transistor is electrically connected to the second inverter circuit, and the second terminal of the fourth protection transistor is electrically connected to the first terminal of the fourth switching transistor.

16. The general-purpose input / output circuit according to claim 15, characterized in that, The control terminal of the third protection transistor receives a third protection signal, and the control terminal of the fourth protection transistor receives a fourth protection signal. The third protection transistor is a P-type transistor, and the fourth protection transistor is an N-type transistor. The third protection transistor and the fourth protection transistor operate in linear region mode respectively according to the third protection signal and the fourth protection signal.

17. The general-purpose input / output circuit according to claim 11, characterized in that, The second inverter circuit includes: A fifth switching transistor, wherein the first terminal of the fifth switching transistor is electrically connected to a second operating voltage, and the control terminal of the fifth switching transistor is electrically connected to the first inverter circuit; The fifth protection circuit is electrically connected to the fifth switching transistor and the data output terminal of the general-purpose input / output circuit; The sixth protection circuit is electrically connected to the data output terminal of the fifth protection circuit and the general-purpose input / output circuit; and, A sixth switching transistor, wherein the first terminal of the sixth switching transistor is electrically connected to the sixth protection circuit, the second terminal of the sixth switching transistor is electrically connected to the ground voltage, and the control terminal of the sixth switching transistor is electrically connected to the first inverter circuit.

18. The general-purpose input / output circuit according to claim 17, characterized in that, The fifth switching transistor is a P-type transistor, and the sixth switching transistor is an N-type transistor.

19. The general-purpose input / output circuit according to claim 17, characterized in that, The fifth protection circuit includes: A fifth protection transistor, wherein the first terminal of the fifth protection transistor is electrically connected to the second terminal of the fifth switching transistor, and the second terminal of the fifth protection transistor is electrically connected to the data output terminal of the general-purpose input / output circuit. The sixth protection circuit includes: A sixth protection transistor, wherein the first terminal of the sixth protection transistor is electrically connected to the data output terminal of the general-purpose input / output circuit, and the second terminal of the sixth protection transistor is electrically connected to the first terminal of the sixth switching transistor.

20. The general-purpose input / output circuit according to claim 19, characterized in that, The control terminal of the fifth protection transistor receives the fifth protection signal, and the control terminal of the sixth protection transistor receives the sixth protection signal. The fifth protection transistor is a P-type transistor, and the sixth protection transistor is an N-type transistor. The fifth protection transistor and the sixth protection transistor operate in linear region mode respectively according to the fifth protection signal and the sixth protection signal.

21. An artificial intelligence chip, characterized in that, include: Core circuit; A general-purpose input / output circuit is electrically connected to the core circuit and has input / output terminals; as well as, Input / output pads are electrically connected to the input / output terminals. The general-purpose input / output circuit includes: A transmitting circuit, coupled to the core circuit, and the transmitting circuit includes: First switching circuit; Second switching circuit; The first protection circuit is electrically connected to the first switching circuit; The second protection circuit is electrically connected to the second switching circuit and the first protection circuit; and, A resistor, wherein a first end of the resistor is electrically connected to the first protection circuit and the second protection circuit, and a second end of the resistor is electrically connected to the input / output terminal.

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