Sub-block interleaving for polarity coding systems, processes, and signaling

Abstract

A sub-block interleaving for polarity coding systems, processes, and signaling is disclosed. A wireless transmit / receive unit (WTRU) may generate a plurality of polarity coded bits using polarity coding. The WTRU may divide the plurality of polarity coded bits into sub-blocks of the same size in a sequential manner. The WTRU may apply sub-block type interleaving to the sub-block by using an interleaver mode. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block interleaving may include interleaving on the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may cascade bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a ring buffer. The WTRU may select a plurality of bits from the interleaved bits for transmission.

Description

This application is a divisional application of patent application No. 202210960706.7, filed on August 11, 2022, entitled "Sub-block Interleaving for Polar Coding Systems, Processes, and Signaling". Patent application No. 202210960706.7 is a divisional application of patent application No. 201880020225.X, filed on March 21, 2018, entitled "Sub-block Interleaving for Polar Coding Systems, Processes, and Signaling". Cross-reference to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 474,875, filed March 22, 2017; U.S. Provisional Patent Application No. 62 / 500,887, filed May 3, 2017; U.S. Provisional Patent Application No. 62 / 519,700, filed June 14, 2017; U.S. Provisional Patent Application No. 62 / 545,615, filed August 15, 2017; and U.S. Provisional Patent Application No. 62 / 556,104, filed September 8, 2017, the contents of which are incorporated herein by reference. Background Technology

[0002] Mobile communications are constantly evolving. The fifth generation of mobile communication technology can be referred to as 5G. 5G mobile wireless communication systems can implement various radio access technologies (RATs), including New Radio (NR). Use cases for NR can include, for example, ultra-wideband mobile broadband (eMBB), ultra-reliable low-latency communication (URLLC), and massive machine-type communication (mMTC). Existing encoding schemes and processing methods for coded bits used to transmit control information and / or data can be supplemented by new encoding schemes and processing mechanisms for coded bits. Summary of the Invention

[0003] A system, method, and tool are disclosed for interleaving polarity-coded bits as part of rate matching. A wireless transmit / receive unit (WTRU) can generate multiple polarity-coded bits using polarity coding. These multiple polarity-coded bits can be generated using a master code length. The WTRU can divide the multiple polarity-coded bits into equal-sized sub-blocks. The polarity-coded bits can be divided into sub-blocks sequentially. The length of each sub-block can be the ratio of the master code length to the number of sub-blocks. The WTRU can apply sub-block interleaving to the sub-blocks using an interleaver pattern. The interleaver pattern can be given by d1() in the following equation:

[0004] Subblocks associated with a subset of the said subblocks are interleaved, while subblocks associated with another subset of the said subblocks are not interleaved. The subblock interleaving involves interleaving over the subblocks without interleaving the bits associated with each said subblock. For example, bit groups or subblocks may be interleaved, while bits within a subblock may not be interleaved. The interleaved subsets of said subblocks are contiguous and do not overlap with the uninterleaved subsets of said subblocks.

[0005] The WTRU can concatenate bits from each interleaved sub-block to generate interleaved bits. For example, the concatenated bits can be formed according to the interleaved sub-blocks, with bits within each sub-block not interleaved. Bits associated with each interleaved sub-block can be concatenated sequentially. The WTRU can store the interleaved bits associated with the interleaved sub-blocks in a ring buffer. The WTRU can select multiple bits (e.g., multiple consecutive bits) from the interleaved bits for transmission. The multiple bits can be stored consecutively in the ring buffer. The multiple bits can be selected based on a rate matching scheme. The rate matching scheme can be determined based on the mother code length, the rate matching output size, and the code rate. The rate matching scheme can be one of the following: a repetition scheme, a puncturing scheme, or a shortening scheme. For example, when the rate matching output size is greater than the mother code length, the rate matching scheme can be a repetition scheme. When the rate matching output size is less than the mother code length, the rate matching scheme can be a shortening scheme or a puncturing scheme. The selection between the shortening scheme and the puncturing scheme can be based on the code rate.

[0006] The first subset of interwoven sub-blocks may include the middle sub-blocks of the plurality of sub-blocks, while the second subset of non-interwoven sub-blocks may contain an even number of sub-blocks. The second subset of a sub-block includes an equal number of sub-blocks on each side of the first subset of the sub-block. The third subset of interwoven sub-blocks may be adjacent to the second subset of the sub-block. The fourth subset of non-interwoven sub-blocks may include the first subset of the sub-block, the second subset of the sub-block, and sub-blocks other than the third subset of the sub-block. The fourth subset of the sub-block may be adjacent to the third subset of the sub-block. Attached Figure Description

[0007] Figure 1A This is a system diagram illustrating an exemplary communication system that can implement one or more of the disclosed embodiments.

[0008] Figure 1B It is shown that, according to the embodiment, it is possible to Figure 1A The diagram shows an exemplary wireless transmit / receive unit (WTRU) used within the communication system.

[0009] Figure 1C It is shown that, according to the embodiment, it is possible to Figure 1AThe diagram shows an exemplary radio access network (RAN) and an exemplary core network (CN) used within the communication system.

[0010] Figure 1D It is shown that, according to the embodiment, it is possible to Figure 1A The system diagram shown is of another exemplary RAN and another exemplary CN used within the communication system.

[0011] Figure 2 An exemplary polarity encoder is shown.

[0012] Figure 3 An example polarity encoding is shown.

[0013] Figure 4 An example of parity check (PC) polarity coding is shown.

[0014] Figure 5 An example of using polarity encoding to process control information is shown.

[0015] Figure 6 An exemplary implementation of rate matching control is shown.

[0016] Figure 7 An exemplary rate matching is shown.

[0017] Figure 8 An example bit selection is shown.

[0018] Figure 9 An example bit selection is shown.

[0019] Figure 10 An example bit selection is shown.

[0020] Figure 11 An example bit selection is shown.

[0021] Figure 12 An example bit selection is shown.

[0022] Figure 13 An exemplary encoding of a Cyclic Redundancy Check (CRC)-Auxiliary (CA) polar code with a long CRC is shown.

[0023] Figure 14 An exemplary distribution for decoding a CA polar code with a long CRC is shown.

[0024] Figure 15 An exemplary encoding of a CA polar code with two separate CRCs is shown.

[0025] Figure 16 An exemplary decoding of a CA polar code with two separate CRCs is shown.

[0026] Figure 17 An exemplary encoding of the PC polar code is shown.

[0027] Figure 18 An exemplary decoding of the PC polar code is shown.

[0028] Figure 19 An exemplary decoding of a PC polarity code with a CA list selection is shown.

[0029] Figure 20 An exemplary block error rate (BLER) comparison between sub-block-based punching and existing shortening schemes.

[0030] Figure 21 An exemplary sub-block interleaver with 8 sub-blocks for polar code rate matching is shown.

[0031] Figure 22 An exemplary sub-block interleaver with 16 sub-blocks for polar code rate matching is shown.

[0032] Figures 23A-23C An exemplary sub-block interleaver with 32 sub-blocks for polar code rate matching is shown.

[0033] Figure 24 An exemplary 16-quadrature amplitude modulation (QAM) modulation is shown.

[0034] Figure 25 An exemplary 16QAM modulation is shown.

[0035] Figure 26 An exemplary 16QAM modulation with four segments is shown.

[0036] Figure 27 An exemplary quadrature phase shift keying (QPSK) modulation with two segmented parts is shown.

[0037] Figure 28 An exemplary QPSK modulation with two segmented parts is shown.

[0038] Figure 29 An exemplary QPSK modulation with 5 segments is shown.

[0039] Figure 30 An exemplary channel interleaver is shown.

[0040] Figure 31 An example of interlacing is shown.

[0041] Figure 32 An exemplary block interleaver with a depth of 5 is shown.

[0042] Figure 33Exemplary performance comparisons of different interleavers are shown at a tapped delay line (TDL)-A channel model with a delay spread of 100 ns, 1 / 2 code rate, and QPSK modulation.

[0043] Figure 34 Exemplary performance comparisons of different interleavers are shown at a TDL-A channel model with a delay spread of 100 ns, a 1 / 2 code rate, and 16QAM modulation.

[0044] Figure 35 Exemplary performance comparisons of different interleavers are shown at a TDL-A channel model with a delay spread of 100 ns, a 1 / 2 code rate, and 16QAM modulation.

[0045] Figure 36 An example of performance improvement that can be observed using a matrix interleaver is shown.

[0046] Figures 37-48 Exemplary performance comparisons of various exemplary methods and schemes disclosed herein are shown.

[0047] Figure 49 An exemplary triangular interlacer is shown.

[0048] Figure 50 An exemplary triangular interlacer is shown.

[0049] Figure 51 An exemplary polarity encoding system is shown. Detailed Implementation

[0050] Specific embodiments of the illustrative examples will now be described with reference to the accompanying drawings. While this description provides detailed examples of possible embodiments, it should be noted that these details are for illustrative purposes and in no way constitute a limitation on the scope of this application.

[0051] Figure 1AThis is an illustration of an exemplary communication system 100 that can implement one or more of the disclosed embodiments. The communication system 100 can be a multiple access system providing voice, data, video, messaging, broadcasting, and other content to multiple wireless users. The communication system 100 enables multiple wireless users to access such content by sharing system resources, including wireless bandwidth. For example, the communication system 100 can use one or more channel access methods, such as Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal FDMA (OFDMA), Single Carrier FDMA (SC-FDMA), Zero-Tail Unique Word DFT Extended OFDM (ZT UW DTS-s OFDM), Unique Word OFDM (UW-OFDM), Resource Block Filtering OFDM, and Filter Bank Multicarrier (FBMC), etc.

[0052] like Figure 1A As shown, the communication system 100 may include wireless transmit / receive units (WTRUs) 102a, 102b, 102c, 102d, RAN 104 / 113, CN 106 / 115, public switched telephone network (PSTN) 108, Internet 110, and other networks 112. However, it should be understood that the disclosed embodiments contemplate any number of WTRUs, base stations, networks, and / or network components. Each WTRU 102a, 102b, 102c, 102d may be any type of device configured to operate and / or communicate in a wireless environment. For example, any WTRU 102a, 102b, 102c, or 102d may be referred to as a “station” and / or “STA”, and may be configured to transmit and / or receive wireless signals. It may include user equipment (UE), mobile stations, fixed or mobile subscriber units, subscription-based units, pagers, cellular phones, personal digital assistants (PDAs), smartphones, laptops, netbooks, personal computers, wireless sensors, hotspots or Mi-Fi devices, Internet of Things (IoT) devices, watches or other wearable devices, head-mounted displays (HMDs), vehicles, drones, medical devices and applications (e.g., remote surgery), industrial devices and applications (e.g., robots and / or other wireless devices operating in industrial and / or automated processing chain environments), consumer electronics devices, and devices operating on commercial and / or industrial wireless networks, etc. Any WTRU 102a, 102b, 102c, or 102d may be interchangeably referred to as a UE.

[0053] The communication system 100 may also include base stations 114a and / or 114b. Each base station 114a, 114b may be any type of device configured to enable access to one or more communication networks (e.g., CN 106 / 115, Internet 110, and / or other networks 112) by wirelessly interfacing with at least one of WTRUs 102a, 102b, 102c, 102d. For example, base stations 114a, 114b may be base transceiver stations (BTS), node B, e-node B, home node B, home e-node B, gNB, NR node B, site controller, access point (AP), and wireless routers, etc. Although each base station 114a, 114b is described as a single component, it should be understood that base stations 114a, 114b may include any number of interconnected base stations and / or network components.

[0054] Base station 114a may be part of RAN 104 / 113, and the RAN may also include other base stations and / or network components (not shown), such as base station controllers (BSCs), radio network controllers (RNCs), relay nodes, etc. Base station 114a and / or base station 114b may be configured to transmit and / or receive radio signals on one or more carrier frequencies called cells (not shown). These frequencies may be in licensed spectrum, unlicensed spectrum, or a combination of licensed and unlicensed spectrum. A cell may provide radio service coverage for a specific geographic area that is relatively fixed or may change over time. A cell may be further divided into cell sectors. For example, a cell associated with base station 114a may be divided into three sectors. Thus, in one embodiment, base station 114a may include three transceivers, that is, each transceiver corresponds to one sector of the cell. In one embodiment, base station 114a may use multiple-input multiple-output (MIMO) technology and may use multiple transceivers for each sector of the cell. For example, by using beamforming, signals can be transmitted and / or received in a desired spatial direction.

[0055] Base stations 114a and 114b can communicate with one or more of WTRUs 102a, 102b, 102c, and 102d via air interface 116, wherein the air interface can be any suitable wireless communication link (e.g., radio frequency (RF), microwave, centimeter wave, millimeter wave, infrared (IR), ultraviolet (UV), visible light, etc.). Air interface 116 can be established using any suitable radio access technology (RAT).

[0056] More specifically, as described above, the communication system 100 can be a multiple access system and can use one or more channel access schemes, such as CDMA, TDMA, FDMA, OFDMA, and SC-FDMA, etc. For example, base station 114a in RAN 104 / 113 and WTRUs 102a, 102b, and 102c can implement a certain radio technology, such as Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access (UTRA), wherein the technology can use Wideband CDMA (WCDMA) to establish air interfaces 115 / 116 / 117. WCDMA may include communication protocols such as High-Speed ​​Packet Access (HSPA) and / or Evolved HSPA (HSPA+). HSPA may include High-Speed ​​Downlink (DL) Packet Access (HSDPA) and / or High-Speed ​​UL Packet Access (HSUPA).

[0057] In one embodiment, base station 114a and WTRUs 102a, 102b, 102c may implement a certain radio technology, such as Evolved UMTS Terrestrial Radio Access (E-UTRA), wherein the technology may use Long Term Evolution (LTE) and / or Advanced LTE (LTE-A) and / or Advanced LTA Pro (LTE-A Pro) to establish air interface 116.

[0058] In one embodiment, base station 114a and WTRUs 102a, 102b, 102c may implement a certain radio technology, such as NR radio access, wherein the radio technology may use a novel radio (NR) to establish air interface 116.

[0059] In one embodiment, base station 114a and WTRUs 102a, 102b, and 102c can implement multiple radio access technologies. For example, base station 114a and WTRUs 102a, 102b, and 102c can jointly implement LTE radio access and NR radio access (e.g., using the dual connectivity (DC) principle). Thus, the air interface used by WTRUs 102a, 102b, and 102c can be characterized by multiple types of radio access technologies and / or transmissions sent to / from multiple types of base stations (e.g., eNBs and gNBs).

[0060] In other embodiments, base station 114a and WTRUs 102a, 102b, 102c may implement the following radio technologies, such as IEEE 802.11 (i.e., WiFi), IEEE 802.16 (i.e., WiMAX), CDMA2000, CDMA2000 1X, CDMA2000 EV-DO, Provisional Standard 2000 (IS-2000), Provisional Standard 95 (IS-95), Provisional Standard 856 (IS-856), Global System for Mobile Communications (GSM), Enhanced Data Rate for GSM Evolution (EDGE), and GSM EDGE (GERAN), etc.

[0061] Figure 1A Base station 114b can be a wireless router, home node B, home e node B, or access point, and can use any suitable RAT to facilitate wireless connectivity in a local area, such as a business premises, residence, vehicle, campus, industrial facility, air corridor (e.g., for use by drones), and road, etc. In one embodiment, base station 114b and WTRUs 102c, 102d can establish a wireless local area network (WLAN) by implementing a radio technology such as IEEE 802.11. In one embodiment, base station 114b and WTRUs 102c, 102d can establish a wireless personal area network (WPAN) by implementing a radio technology such as IEEE 802.15. In yet another embodiment, base station 114b and WTRUs 102c, 102d can establish a picocell or femtocell by using a cellular-based RAT (e.g., WCDMA, CDMA2000, GSM, LTE, LTE-A, LTE-A Pro, NR, etc.). Figure 1A As shown, base station 114b can be directly connected to the Internet 110. Therefore, base station 114b does not necessarily need to access the Internet 110 via CN 106 / 115.

[0062] RAN 104 / 113 can communicate with CN 106 / 115, where CN can be any type of network configured to provide voice, data, application, and / or VoIP services to one or more WTRUs 102a, 102b, 102c, 102d. This data can have different Quality of Service (QoS) requirements, such as different throughput requirements, latency requirements, fault tolerance requirements, reliability requirements, data throughput requirements, and mobility requirements, etc. CN 106 / 115 can provide call control, billing services, location-based services, prepaid calling, internet connectivity, video distribution, etc., and / or can perform advanced security functions such as user authentication. Although in Figure 1AWhile not shown, it should be understood that RAN 104 / 113 and / or CN 106 / 115 can communicate directly or indirectly with other RANs that use the same RAT or a different RAT as RAN 104 / 113. For example, in addition to connecting to RAN 104 / 113 which uses NR radio technology, CN 106 / 115 can also communicate with other RANs (not shown) that use GSM, UMTS, CDMA2000, WiMAX, E-UTRA, or WiFi radio technologies.

[0063] CN 106 / 115 may also act as a gateway for WTRU 102a, 102b, 102c, 102d to access PSTN 108, the Internet 110, and / or other networks 112. PSTN 108 may include a circuit-switched telephone network providing Simple Old-Style Telephone Service (POTS). The Internet 110 may include a globally interconnected computer network and equipment system using common communication protocols such as Transmission Control Protocol (TCP), User Datagram Protocol (UDP), and / or Internet Protocol (IP) from the TCP / IP Internet Protocol suite. Network 112 may include wired and / or wireless communication networks owned and / or operated by other service providers. For example, network 112 may include another CN connected to one or more RANs, which may use the same RAT or a different RAT as RAN 104 / 113.

[0064] Some or all of the WTRUs 102a, 102b, 102c, and 102d in the communication system 100 may include multi-mode capability (e.g., WTRUs 102a, 102b, 102c, and 102d may include multiple transceivers communicating with different wireless networks on different wireless links). For example... Figure 1A The WTRU 102c shown can be configured to communicate with base station 114a using cellular-based radio technology, and with base station 114b using IEEE 802 radio technology.

[0065] Figure 1B This is a system diagram illustrating an example of WTRU 102. (See diagram below.) Figure 1B As shown, WTRU 102 may include a processor 118, a transceiver 120, a transmit / receive unit 122, a speaker / microphone 124, a numeric keypad 126, a display / touchpad 128, non-removable memory 130, removable memory 132, a power supply 134, a Global Positioning System (GPS) chipset 136, and / or other peripheral devices 138. It should be understood that, while remaining consistent with the embodiments, WTRU 102 may also include any sub-combination of the foregoing components.

[0066] Processor 118 can be a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor (DSP), multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and a state machine, etc. Processor 118 can perform signal encoding, data processing, power control, input / output processing, and / or any other function that enables WTRU 102 to operate in a wireless environment. Processor 118 can be coupled to transceiver 120, and transceiver 120 can be coupled to transmitting / receiving unit 122. Although Figure 1B While the processor 118 and transceiver 120 are described as separate components, it should be understood that the processor 118 and transceiver 120 can also be integrated into a single electronic component or chip.

[0067] Transmit / receive component 122 may be configured to transmit or receive signals to or from a base station (e.g., base station 114a) via air interface 116. For example, in one embodiment, transmit / receive component 122 may be an antenna configured to transmit and / or receive RF signals. As an example, in another embodiment, transmit / receive component 122 may be an emitter / detector configured to transmit and / or receive IR, UV, or visible light signals. In yet another embodiment, transmit / receive component 122 may be configured to transmit and receive both RF and optical signals. It should be understood that transmit / receive component 122 may be configured to transmit and / or receive any combination of wireless signals.

[0068] Although Figure 1B While the transmit / receive component 122 is described as a single component, the WTRU 102 may include any number of transmit / receive components 122. More specifically, the WTRU 102 may use MIMO technology. Thus, in one embodiment, the WTRU 102 may include two or more transmit / receive components 122 (e.g., multiple antennas) that transmit and receive radio signals via the air interface 116.

[0069] Transceiver 120 can be configured to modulate signals to be transmitted by transmitter / receiver 122 and demodulate signals received by transmitter / receiver 122. As described above, WTRU 102 can have multimode capability. Therefore, transceiver 120 can include multiple transceivers that allow WTRU 102 to communicate using various RATs such as NR and IEEE 802.11.

[0070] The processor 118 of WTRU 102 can be coupled to a speaker / microphone 124, a numeric keypad 126, and / or a display / touchpad 128 (e.g., a liquid crystal display (LCD) unit or an organic light-emitting diode (OLED) display unit), and can receive user input data from these components. The processor 118 can also output user data to the speaker / microphone 124, the numeric keypad 126, and / or the display / touchpad 128. Furthermore, the processor 118 can access information from and store data in any suitable memory, such as non-removable memory 130 and / or removable memory 132. Non-removable memory 130 can include random access memory (RAM), read-only memory (ROM), a hard disk, or any other type of memory storage device. Removable memory 132 can include a subscriber identity module (SIM) card, a memory stick, and a secure digital storage (SD) card, etc. In other embodiments, processor 118 may access information from and store data in memories that are not actually located in WTRU 102, such as those memories located in a server or home computer (not shown).

[0071] The processor 118 can receive power from the power supply 134 and can be configured to distribute and / or control power for other components in the WTRU 102. The power supply 134 can be any suitable device that powers the WTRU 102. For example, the power supply 134 may include one or more dry cell battery packs (such as nickel-cadmium (Ni-Cd), nickel-zinc (Ni-Zn), nickel-metal hydride (NiMH), lithium-ion (Li-ion), etc.), solar cells, and fuel cells, etc.

[0072] The processor 118 may also be coupled to a GPS chipset 136, which may be configured to provide location information (e.g., longitude and latitude) related to the current location of the WTRU 102. As a supplement or replacement to the information from the GPS chipset 136, the WTRU 102 may receive location information from base stations (e.g., base stations 114a, 114b) via the air interface 116, and / or determine its location based on signal timing received from two or more nearby base stations. It should be understood that, while remaining consistent with the embodiments, the WTRU 102 may acquire location information using any suitable positioning method.

[0073] The processor 118 can also be coupled to other peripheral devices 138, which may include one or more software and / or hardware modules providing additional features, functions, and / or wired or wireless connectivity. For example, peripheral devices 138 may include accelerometers, electronic compasses, satellite transceivers, digital cameras (for photos and / or video), Universal Serial Bus (USB) ports, vibration devices, television transceivers, hands-free headsets, etc. Modules, FM radio units, digital music players, media players, video game console modules, internet browsers, virtual reality and / or augmented reality (VR / AR) devices, and activity trackers, etc. Peripheral device 138 may include one or more sensors, which may be one or more of the following: gyroscopes, accelerometers, Hall effect sensors, magnetometers, orientation sensors, proximity sensors, temperature sensors, time sensors, geolocation sensors, altimeters, light sensors, touch sensors, magnetometers, barometers, gesture sensors, biometric sensors, and / or humidity sensors.

[0074] WTRU 102 may include a full-duplex wireless device, wherein the reception and transmission of some or all signals (e.g., associated with subframes for UL (e.g., for transmission) and downlink (e.g., for reception)) may be concurrent and / or simultaneous for the wireless device. The full-duplex wireless device may include an interference management unit that reduces and / or substantially eliminates self-interference by means of hardware (e.g., choke coils) or by means of a processor (e.g., a separate processor (not shown) or by means of processor 118) for signal processing. In one embodiment, WTRU 102 may include a half-duplex wireless device, wherein the transmission and reception of some or all signals (e.g., associated with specific subframes for UL (e.g., relative to transmission) and downlink (e.g., relative to reception) for the device.

[0075] Figure 1C This is a system diagram illustrating RAN 104 and CN 106 according to one embodiment. As described above, RAN 104 can communicate with WTRUs 102a, 102b, and 102c using E-UTRA radio technology on air interface 116. Furthermore, RAN 104 can also communicate with CN 106.

[0076] RAN 104 may include eNodeBs 160a, 160b, and 160c; however, it should be understood that RAN 104 may include any number of eNodeBs while remaining consistent with the embodiments. Each eNodeB 160a, 160b, and 160c may include one or more transceivers communicating with WTRUs 102a, 102b, and 102c on air interface 116. In one embodiment, eNodeBs 160a, 160b, and 160c may implement MIMO technology. Thus, for example, eNodeB 160a may use multiple antennas to transmit radio signals to and / or receive radio signals from WTRU 102a.

[0077] Each eNodeB 160a, 160b, and 160c can be associated with a specific cell (not shown) and can be configured to handle radio resource management decisions, handover decisions, user scheduling in UL and / or DL, etc. For example... Figure 1C As shown, nodes B160a, 160b, and 160c can communicate with each other via the X2 interface.

[0078] Figure 1C The CN 106 shown may include a Mobility Management Entity (MME) 162, a Serving Gateway (SGW) 164, and a Packet Data Network (PDN) Gateway (or PGW) 166. While each of the foregoing components is described as part of the CN 106, it should be understood that any of these components may be owned and / or operated by an entity other than the CN operator.

[0079] The MME 162 can connect to each eNode-B 160a, 160b, and 160c in RAN 104 via the S1 interface and can act as a control node. For example, the MME 162 can be responsible for authenticating users of WTRUs 102a, 102b, and 102c, bearer activation / deactivation, and selecting a specific serving gateway during the initial attach process of WTRUs 102a, 102b, and 102c, etc. The MME 162 can also provide control plane functionality for handover between RAN 104 and other RANs (not shown) using other radio technologies (such as GSM and / or WCDMA).

[0080] The SGW 164 can connect to each eNode-B 160a, 160b, and 160c in RAN 104 via the S1 interface. The SGW 164 typically routes and forwards user data packets to / from WTRUs 102a, 102b, and 102c. Furthermore, the SGW 164 can perform other functions, such as anchoring the user plane during handover between eNBs, triggering paging processing when DL data is available to WTRUs 102a, 102b, and 102c, and managing and storing the context of WTRUs 102a, 102b, and 102c, etc.

[0081] SGW 164 can be connected to PGW 166, which can provide packet-switched network (e.g., Internet 110) access for WTRU 102a, 102b, 102c to facilitate communication between WTRU 102a, 102b, 102c and IP-enabled devices.

[0082] CN 106 can facilitate communication with other networks. For example, CN 106 can provide circuit-switched network (e.g., PSTN 108) access for WTRUs 102a, 102b, and 102c to facilitate communication between WTRUs 102a, 102b, and 102c and conventional landline communication equipment. For example, CN 106 may include or communicate with an IP gateway (e.g., an IP Multimedia Subsystem (IMS) server), and the IP gateway may act as an interface between CN 106 and PSTN 108. Furthermore, CN 106 can provide WTRUs 102a, 102b, and 102c with access to other networks 112, which may include other wired and / or wireless networks owned and / or operated by other service providers.

[0083] Although Figure 1A-1D The WTRU is described as a wireless terminal; however, it should be understood that in some typical embodiments, such a terminal may use a wired communication interface (e.g., temporary or permanent) with the communication network.

[0084] In a typical embodiment, the other network 112 may be a WLAN.

[0085] A WLAN employing an Infrastructure Basic Services Set (BSS) model may have an Access Point (AP) for the BSS and one or more Stations (STAs) associated with the AP. The AP may access or interface with a Distributed System (DS) or other types of wired / wireless networks that send traffic into and / or out of the BSS. Traffic originating outside the BSS and destined for a STA can be delivered to the STA via the AP. Traffic originating from a STA and destined for a destination outside the BSS can be sent to the AP for delivery to the appropriate destination. Traffic between STAs within the BSS can be sent via the AP, for example, a source STA can send traffic to the AP and the AP can deliver the traffic to the destination STA. Traffic between STAs within the BSS may be considered and / or referred to as point-to-point traffic. Point-to-point traffic can be sent between the source and destination STAs (e.g., directly therebetween) using Direct Link Establishment (DLS). In some typical embodiments, the DLS may use 802.11e DLS or 802.11z Tunneled DLS (TDLS). A WLAN using the Independent BSS (IBSS) mode does not have an access point (AP) and is located within the IBSS or the STAs using the IBSS (e.g., all STAs) can communicate directly with each other. Here, the IBSS communication mode is sometimes referred to as a "self-organizing" communication mode.

[0086] When operating in 802.11ac infrastructure mode or a similar mode, the AP can transmit beacons on a fixed channel (e.g., the primary channel). The primary channel can have a fixed width (e.g., a 20 MHz bandwidth) or a width dynamically set via signaling. The primary channel can be the operating channel of the BSS and can be used by STAs to establish connections with the AP. In some typical embodiments, carrier-sense multiple access with collision avoidance (CSMA / CA) can be implemented (e.g., in an 802.11 system). For CSMA / CA, STAs, including the AP (e.g., each STA), can sense the primary channel. If a particular STA senses / detects and / or determines that the primary channel is busy, that particular STA can fall back. Within a given BSS, at any given time, only one STA (e.g., only one station) can be transmitting.

[0087] High-throughput (HT) STAs can communicate using a 40MHz wide channel (e.g., by combining a 20MHz wide main channel with adjacent or non-adjacent 20MHz wide channels to form a 40MHz wide channel).

[0088] Very High Throughput (VHT) STAs can support channels with widths of 20MHz, 40MHz, 80MHz, and / or 160MHz. 40MHz and / or 80MHz channels can be formed by combining consecutive 20MHz channels. A 160MHz channel can be formed by combining eight consecutive 20MHz channels or by combining two non-consecutive 80MHz channels (this combination is referred to as an 80+80 configuration). For the 80+80 configuration, after channel coding, data is transmitted and passed through a segmented parser that splits the data into two streams. Inverse Fast Fourier Transform (IFFT) processing and time-domain processing can be performed independently on each stream. The streams can be mapped onto two 80MHz channels, and the data can be transmitted by the STA performing the transmission. On the receiver of the STA performing the reception, the above operations for the 80+80 configuration can be reversed, and the combined data can be sent to the Media Access Control (MAC).

[0089] 802.11af and 802.11ah support sub-1 GHz operating modes. Compared to 802.11n and 802.11ac, the channel operating bandwidth and carrier used in 802.11af and 802.11ah are reduced. 802.11af supports 5 MHz, 10 MHz, and 20 MHz bandwidths in the TV white space (TVWS) spectrum, while 802.11ah supports 1 MHz, 2 MHz, 4 MHz, 8 MHz, and 16 MHz bandwidths using non-TVWS spectrum. According to typical embodiments, 802.11ah can support instrument-type control / machine-type communication (e.g., MTC devices in macro coverage areas). MTCs may have certain capabilities, such as limited capabilities including support (e.g., only support) certain and / or limited bandwidths. MTC devices may include a battery with a battery life exceeding a threshold (e.g., maintaining a very long battery life).

[0090] For a WLAN system that can support multiple channels and channel bandwidths (e.g., 802.11n, 802.11ac, 802.11af, and 802.11ah), the WLAN system includes a channel that can be designated as the primary channel. The bandwidth of the primary channel can be equal to the maximum common operating bandwidth supported by all STAs in the BSS. The bandwidth of the primary channel can be set and / or limited by a particular STA, which is derived from all STAs operating in the BSS that support the minimum bandwidth operating mode. In the example regarding 802.11ah, even if the AP and other STAs in the BSS support 2MHz, 4MHz, 8MHz, 16MHz, and / or other channel bandwidth operating modes, the width of the primary channel can be 1MHz for STAs that support (e.g., only support) the 1MHz mode (e.g., MTC type devices). Carrier sensing and / or Network Allocation Vector (NAV) settings can depend on the status of the primary channel. If the primary channel is busy (e.g., because an STA (which only supports the 1MHz operating mode) is transmitting to the AP), then the entire available band can be considered busy even if most of the frequency band remains idle and available.

[0091] In the United States, the available frequency band for 802.11ah is 902MHz to 928MHz. In South Korea, the available frequency band is 917.5MHz to 923.5MHz. In Japan, the available frequency band is 916.5MHz to 927.5MHz. Depending on the country code, the total bandwidth available for 802.11ah is 6MHz to 26MHz.

[0092] Figure 1D This is a system diagram illustrating RAN 113 and CN 115 according to one embodiment. As described above, RAN 113 can communicate with WTRUs 102a, 102b, and 102c using NR radio technology on air interface 116. Furthermore, RAN 113 can also communicate with CN 115.

[0093] RAN 113 may include gNBs 180a, 180b, and 180c; however, it should be understood that RAN 113 may include any number of gNBs while remaining consistent with the embodiments. Each gNB 180a, 180b, and 180c may include one or more transceivers for communicating with WTRUs 102a, 102b, and 102c via air interface 116. In one embodiment, gNBs 180a, 180b, and 180c may implement MIMO technology. For example, gNBs 180a and 180b may use beamforming to transmit and / or receive signals to and / or from gNBs 180a, 180b, and 180c. Thus, for example, gNB 180a may use multiple antennas to transmit radio signals to and / or receive radio signals from WTRU 102a. In one embodiment, gNBs 180a, 180b, and 180c may implement carrier aggregation technology. For example, gNB 180a can transmit multiple component carriers to WTR 102a (not shown). A subset of these component carriers may be in unlicensed spectrum, while the remaining component carriers may be in licensed spectrum. In one embodiment, gNBs 180a, 180b, and 180c may implement Cooperative Multipoint (CoMP) technology. For example, WTRU 102a can receive cooperative transmissions from gNB 180a and gNB 180b (and / or gNB 180c).

[0094] WTRUs 102a, 102b, and 102c can communicate with gNBs 180a, 180b, and 180c using transmissions associated with scalable parameter configurations. For example, the OFDM symbol spacing and / or OFDM subcarrier spacing can be different for different transmissions, different cells, and / or different portions of the radio transmission spectrum. WTRUs 102a, 102b, and 102c can communicate with gNBs 180a, 180b, and 180c using subframes or transmission time intervals (TTIs) of different or scalable lengths (e.g., containing different numbers of OFDM symbols and / or varying absolute durations).

[0095] gNBs 180a, 180b, and 180c can be configured to communicate with WTRUs 102a, 102b, and 102c in standalone and / or non-standalone configurations. In standalone configuration, WTRUs 102a, 102b, and 102c can communicate with gNBs 180a, 180b, and 180c without accessing other RANs (e.g., eNodeBs 160a, 160b, and 160c). In standalone configuration, WTRUs 102a, 102b, and 102c can use one or more of gNBs 180a, 180b, and 180c as mobile anchors. In standalone configuration, WTRUs 102a, 102b, and 102c can use signals in unlicensed frequency bands to communicate with gNBs 180a, 180b, and 180c. In a non-standalone configuration, WTRUs 102a, 102b, and 102c communicate / connect with gNBs 180a, 180b, and 180c simultaneously with other RANs (e.g., eNodeBs 160a, 160b, and 160c). For example, WTRUs 102a, 102b, and 102c can communicate substantially simultaneously with one or more gNBs 180a, 180b, and 180c, as well as one or more eNodeBs 160a, 160b, and 160c, by implementing DC principles. In a non-standalone configuration, eNodeBs 160a, 160b, and 160c can act as mobile anchors for WTRUs 102a, 102b, and 102c, and gNBs 180a, 180b, and 180c can provide additional coverage and / or throughput to service WTRUs 102a, 102b, and 102c.

[0096] Each gNB 180a, 180b, and 180c can be associated with a specific cell (not shown) and can be configured to handle radio resource management decisions, handover decisions, user scheduling in UL and / or DL, support network slicing, implement dual connectivity, implement interoperability processing between NR and E-UTRA, route user plane data to User Plane Functions (UPF) 184a and 184b, and route control plane information to Access and Mobility Management Functions (AMF) 182a and 182b, etc. Figure 1D As shown, gNB 180a, 180b, and 180c can communicate with each other via the Xn interface.

[0097] Figure 1DThe CN 115 shown may include at least one AMF 182a, 182b, at least one UPF 184a, 184b, at least one Session Management Function (SMF) 183a, 183b, and may include data network (DN) 185a, 185b. While each of the foregoing components is described as part of the CN 115, it should be understood that any of these components may be owned and / or operated by an entity other than the CN operator.

[0098] AMF 182a and 182b can connect to one or more gNBs 180a, 180b, and 180c in RAN 113 via the N2 interface and can act as control nodes. For example, AMF 182a and 182b can be responsible for authenticating users of WTRU 102a, 102b, and 102c, supporting network slicing (e.g., handling different PDU sessions with different needs), selecting specific SMF 183a and 183b, managing registration areas, terminating NAS signaling, and mobility management, etc. AMF 182a and 1823b can use network slicing to customize the CN support provided to WTRU 102a, 102b, and 102c based on the service types used by WTRU 102a, 102b, and 102c. As an example, different network slices can be established for different use cases, such as services relying on Ultra Reliable Low Latency (URLLC) access, services relying on Enhanced Massive Mobile Broadband (eMBB) access, and / or services for Machine Type Communication (MTC) access, etc. AMF 162 can provide control plane functionality for switching between RAN 113 and other RANs (not shown) using other radio technologies such as LTE, LTE-A, LTE-A Pro, and / or non-3GPP access technologies like WiFi.

[0099] SMFs 183a and 183b can connect to AMFs 182a and 182b in CN 115 via the N11 interface. SMFs 183a and 183b can also connect to UPFs 184a and 184b in CN 115 via the N4 interface. SMFs 183a and 183b can select and control UPFs 184a and 184b, and can configure traffic routing through UPFs 184a and 184b. SMFs 183a and 183b can perform other functions, such as managing and allocating UE IP addresses, managing PDU sessions, controlling policy enforcement and QoS, and providing downlink data notifications. PDU session types can be IP-based, non-IP-based, Ethernet-based, etc.

[0100] UPF 184a and 184b can be connected via the N3 interface to one or more gNBs 180a, 180b, and 180c in RAN 113, thus providing packet-switched network (e.g., Internet 110) access for WTRU 102a, 102b, and 102c to facilitate communication between WTRU 102a, 102b, and 102c and IP-enabled devices. UPF 184 and 184b can perform other functions such as routing and forwarding packets, enforcing user plane policies, supporting multihomed PDU sessions, handling user plane QoS, buffering downlink packets, and providing mobility anchoring processing, etc.

[0101] CN 115 can facilitate communication with other networks. For example, CN 115 may include or can communicate with an IP gateway (e.g., an IP Multimedia Subsystem (IMS) server) that acts as an interface between CN 115 and PSTN 108. Furthermore, CN 115 can provide WTRUs 102a, 102b, and 102c with access to other networks 112, which may include other wired and / or wireless networks owned and / or operated by other service providers. In one embodiment, WTRUs 102a, 102b, and 102c can be connected to local data networks (DNs) 185a and 185b via the N3 interface connected to UPFs 184a and 184b and the N6 interface between UPFs 184a and 184b and DNs 185a and 185b.

[0102] In view of Figure 1A-1D And about Figure 1A-1D The corresponding descriptions herein refer to one or more of the functions described below, which can be performed by one or more emulation devices (not shown): WTRU 102a-d, Base Station 114a-b, eNodeB 160a-c, MME 162, SGW 164, PGW 166, gNB 180a-c, AMF 182a-b, UPF 184a-b, SMF 183a-b, DN 185a-b, and / or any other one or more devices described herein. These emulation devices can be one or more devices configured to simulate one or more of the functions described herein. For example, these emulation devices can be used to test other devices and / or simulate network and / or WTRU functions.

[0103] The simulation equipment may be designed to perform one or more tests on other devices in a laboratory environment and / or a carrier network environment. For example, the one or more simulation devices may perform one or more functions while being implemented and / or deployed, wholly or partially, as part of a wired and / or wireless communication network, to test other devices within the communication network. The one or more simulation devices may perform one or more functions while being temporarily implemented / deployed as part of a wired and / or wireless communication network. The simulation equipment may be directly coupled to other devices to perform tests, and / or may use over-the-air wireless communication to perform tests.

[0104] One or more simulation devices can perform one or more functions, including all functionalities, without being implemented / deployed as part of a wired and / or wireless communication network. For example, the simulation devices can be used in test scenarios, such as test laboratories and / or undeployed (e.g., under test) wired and / or wireless communication networks, to perform tests on one or more components. The one or more simulation devices can be test equipment. The simulation devices can transmit and / or receive data using direct RF coupling and / or wireless communication via RF circuitry (which, for example, may include one or more antennas).

[0105] One or more of the features disclosed herein can be used Figure 1A-1D It may be implemented by one or more of the devices, methods and / or systems described herein.

[0106] Capacity-achieving codes, in addition to Turbo codes and / or low-density parity-check (LDPC) codes, may include polar codes. Polar codes may be linear block codes with one or more of the following characteristics: low encoding and / or decoding complexity, low error flatness (e.g., very low error flatness), or explicit construction scheme.

[0107] The polarity code (N,K) can be based on the information block length K and the code block length N. The value N can be set to a power of 2, for example, N=2. n , where n is an integer. The polar code generator matrix can be represented as Among them B N This is a bit-reversed permutation matrix. Represents the nth Kronecker power, and In an exemplary implementation of polar codes, for simplification purposes, the bit-reversal permutation matrix B is... N It can be ignored on the encoder side and bit reversal can be performed on the decoder side. Figure 2 This is an example of a polarity encoder with N=8. Figure 2 It shows An exemplary implementation. The codeword of the polarity code can be derived from... Provided.

[0108] For decoding polarity-coded bits, sequential elimination (SC) decoding can be used. Advanced decoding schemes, such as sequential elimination list (SCL) decoding or CRC-assisted SCL (CA-SCL) decoding, can also be used based on SC decoding.

[0109] CRC-assisted (CA) polarity codes can be polarity codes using a CRC-assisted successive elimination list (SCL) decoder. In CRC-assisted decoding, CRC bits are used to select the final codeword from a list of candidate codewords. This final codeword can be selected at the decoding end. The CRC bits are designed and used for error correction purposes, rather than, for example, error detection. The CRC bits can be used for local error detection.

[0110] Multiple code constructions of the polarity code can be provided. The polarity code can be constructed according to encoding and decoding. The design of the polarity code can rely on K information bits to a polarity encoder. The mapping of N input bits at each location. The K information bits can be placed on K bit channels, for example, K optimal bit channels. The remaining NK input bits not mapped to the information bits can be called frozen bits. The frozen bits can have fixed values, for example, the frozen bits can be set to the value 0. The set of positions of the frozen bits can be called the frozen set. The determination of the optimal bit channel can vary and depend on channel conditions. In determining the frozen channel set, the bit channels can be ranked based on their reliability. Reliable bit channels can be classified as good bit channels, while less reliable bit channels can be classified as bad bit channels.

[0111] The reliability of a bit channel can be calculated. For example, one or more of the following can be used to calculate the reliability of a bit channel: Bhattacharyya hopping, Monte Carlo estimation, full transition probability matrix estimation, or Gaussian approximation. These schemes can have different computational complexities and can be applied to different channel conditions. Signal-to-noise ratio (SNR) parameters can be selected. For example, the SNR can be selected before performing reliability calculations.

[0112] The ranking of a bit channel can be calculated. This ranking can be calculated without using the designed SNR parameters. For example, the ranking sequence can be generated from a formula or extended from a smaller sequence. Once the ranking of the bit channel is determined, information bits can be mapped to bit channels with high reliability. The frozen bits can be mapped to bit channels with lower reliability, such as... Figure 3As shown.

[0113] Figure 4 An exemplary parity check (PC) polarity coding is illustrated. The difference between PC polarity codes and non-PC polarity codes can be that a subset of frozen subchannels is selected as PC-frozen subchannels. PC functions can be established for error correction in the subchannels. In one example (e.g., at each parity subchannel location), each decoded bit involved in the PC function on the PC-frozen subchannel can help prune the list of decoder trees. In one example, paths satisfying the PC function may exist; the rest are eliminated on the fly. For example, only positive PC functions can be established to be consistent with a decoder based on successive elimination. Figure 4 An example of mapping information bits to PC polar code input is shown.

[0114] The introduction of PC polarity codes allows for the removal of CRC bits from CA polarity codes. During CRC-assisted successive elimination list (SCL) decoding, the PC polarity codes can be used for error correction. This reduces the overhead of polarity codes and can lead to higher coding gain.

[0115] Polar codes can be used as channel codes for uplink (UL) and / or downlink (DL) control information. The CRC bits can be used for control messages to reduce the false alarm rate. The polar code for the physical channel can support one of the following: CRC + basic polar code, or J-bit error detection CRC + concatenated polar code. The CRC + basic polar code (e.g., CA polarity) can be combined with a longer CRC (e.g., (J+J') bit CRC) and / or a distributed CRC (e.g., J-bit CRC). The concatenated polar code can be one or more of the following: J'-bit CRC + basic polarity, J'-bit distributed CRC + basic polarity, PC polarity, or hash sequence PC polarity. Encoding schemes that achieve the advantages of both mechanisms(s) can be implemented.

[0116] Polar coding designs for control and / or data information can be provided. Unlike truncated convolutional codes (TBCC), polar codes (which can be block codes) can have different block lengths. Rate matching for polar codes can be designed to improve performance. Rate matching selection can be performed using one or more of the following: repetition mechanism, puncturing mechanism, and / or shortening mechanism. The selection of the rate matching mechanism can be performed based on one or more parameters described herein.

[0117] Polar code design may include code construction selection (e.g., CRC-assisted (CA) polar coding or parity check (PC) polar coding) and / or code sequence selection. Flexible polar coding schemes capable of supporting multiple polar codes can be provided.

[0118] Polarity coding for the control channel can be provided. Figure 5 An exemplary processing of control information (e.g., downlink control information (DCI) or uplink control information (UCI)) using polarity codes is illustrated. Control boxes within the polarity coding subsystem may include code selection control boxes and rate matching control boxes.

[0119] The code selection control box determines the type of polarity code to be used. The code selection control box determines the associated CRC length. Exemplary polarity code types may include the polarity code types described herein and / or other variations, such as advanced PC polarity codes with CA list selection. The determination of the polarity code type may be based on one or more of the following: WTRU category, WTRU capability, or configuration. In an example, the WTRU category may correspond to a polarity code. In an example, the polarity code type may be configured via a Radio Resource Control (RRC) connection establishment message or an RRC connection reconfiguration message. In an example, the polarity code type may be predefined. The corresponding CRC length may be determined. For example, the CRC length may be determined based on the determined polarity code type. For example, when the list length is equal to 8, a 16-bit CRC may be used for PC polarity codes; for CA polarity codes with a long CRC, for example, a 19-bit CRC may be used. The code selection control box may send CRC length information to the CRC attachment box. The CRC attachment box may pass the polarity code type to the channel coding box.

[0120] Figure 5 The rate matching control box can perform one or more of the following: calculate the desired codeword length (e.g., the length of the coded bits used for transmission), i.e. Bits; calculate the mother code length N (e.g., after calculating the desired codeword length); determine the rate matching scheme(s) to be used; or determine a detailed rate matching scheme(s). The rate matching control block may perform the calculation or make the determination based on one or more of the following: uplink control information (UCI) or downlink control information (DCI) block size K, CRC length J, or code rate R.

[0121] In one example, to calculate the mother code length N, this mother code length N can be assumed to be a power of 2 due to the polarity code characteristics. The mother code length N can be greater than or less than the desired codeword length. For example, if the expected codeword length is slightly greater than 2 n If n is a certain integer, then the length of the mother code can be 2^n bits. n Instead of 2 n+1 The choice of mother code length can be based on one or more formulas. In one example, if if For a given constant fraction τ, it can be:

[0122] In one example, if if For a given constant integer τ, it can be, for example, 10. Other exemplary formulas can be similar to the ones above, where the value τ can be a function of n. For example, if n ≤ 5, then τ = 0; otherwise... And if n≤6, then τ=0; otherwise The formula for the mother code length may or may not depend on the code rate. The formula and its parameter τ may differ for different code rates or code rate ranges.

[0123] The selection of the mother code length can be based on one or more lookup tables. Table 1 shows an example of a lookup table (LUT) for selecting the desired codeword length for a corresponding mother code length N. The first row of Table 1 represents the range of desired codeword lengths, and the second row represents the corresponding mother code length. For example, if the desired codeword length is 50 bits, which is in the range [33, 70], then the mother code length can be selected as 64 bits. If the desired codeword length is 275 bits, which is in the range [141, 280], then the selected mother code length can be 256 bits. In the exemplary Table 1, the maximum mother code length can be fixed at 1024 bits. Table 1

[0124] Table 2 shows another example of a LUT, where the maximum mother code length can be 512 bits. Table 2

[0125] The determination of the mother code length can depend on the code rate. In one example, when the coding rate is high (e.g., >1 / 2), it is desirable that the codeword length be small (or slightly larger than) the length of the information bits. The mother code length can be chosen to be relatively large, so that the use of this mother code length can contain more information than can be contained within it (e.g., in the case of rate = 1 / 2).

[0126] For example, when the mother code length depends on the code rate, the exemplary Tables 1 and 2 can be applied to certain code rates. For example, if the code rate is greater than a threshold (e.g., 1 / 2), the mother code length N can be a power of 2. This mother code length can be greater than the desired codeword length. If the code rate is less than the threshold, the mother code length N can be determined based on one or more lookup tables (e.g., Table 1 and / or Table 2). The selection of the mother code length can depend on the modulation order. For example, Tables 1 and 2 can be used for lower-order modulation (e.g., QPSK). Different sets of tables can be defined for higher-order modulation (e.g., 64QAM).

[0127] Figure 37 , Figure 38 , Figure 39 as well as Figure 40 The implementations of 10 are shown for bit rates of 1 / 5, 1 / 3, 2 / 5, and 1 / 2 respectively. -3 The minimum SNR required to achieve the target BLER level. These exemplary simulation results show that the code rate may be less than or equal to 2 / 5 and the code block length may be between 2 and 1. n Up to 2 n In cases where the result is between (1 + 1 / 8), a repetition scheme can be chosen. For example, if... At 2 n Up to 2 n If the length of the mother code is between (1+1 / 8) and the code rate is less than 2 / 5, then the mother code length N can be selected as, for example, 2. n Instead of 2 n+1 .

[0128] Further performance simulations of split-natural puncturing, split-natural shortening, and bit-inversion shortening examples are available here. In these simulations, QPSK modulation and an AWGN channel are assumed. Polar codes with PW sequences and a CA-SCL (L=8) decoding algorithm can be used in these simulations. A 19-bit CRC can be appended to the source data. This CRC bit can be considered part of the information bits.

[0129] The rate matching control box determines the rate matching schemes that can be used. Rate matching schemes may include one or more of the following: repetition, shortening, or puncturing. The selection of a repetition rate matching scheme may depend on the relationship between the mother code length and the desired codeword length. For example, if the mother code length is less than the desired codeword length, a repetition scheme may be selected. Otherwise, a shortening scheme or a puncturing scheme may be selected. The selection between a shortening scheme and a puncturing scheme may depend on at least one of the following: code rate R, or mother code rate. At low bitrates or low mother bitrates, puncturing schemes work well and are therefore usable. At high bitrates or high mother bitrates, shortening schemes work well and are therefore usable. The function f(R) can be used. m, R). If f(R m , R) < Thr, a puncturing scheme can be selected; otherwise, a shortening scheme can be selected.

[0130] Figure 41 and Figure 42 show the minimum SNR required to achieve the target BLER levels of 10 -2 and 10 -3 respectively for a code rate of 1 / 5. Figure 43 and Figure 44 show the minimum SNR required to achieve the target BLER levels of 10 -2 and 10 -3 respectively for a code rate of 1 / 3. Figure 45 and Figure 46 show the minimum SNR required to achieve the target BLER levels of 10 -2 and 10 -3 respectively for a code rate of 2 / 5. Figure 47 and Figure 48 show the minimum SNR required to achieve the target BLER levels of 10 -2 and 10 -3 respectively for a code rate of 1 / 2.

[0131] Based on these simulation results, the following scheme can be established: When the code rate is greater than 2 / 5, the shortening scheme can be selected. When the code rate is less than or equal to 2 / 5, the puncturing scheme can be selected. In one example, the code rate threshold for selecting the puncturing scheme or the shortening scheme can be 2 / 5.

[0132] Rate matching can be implemented by using concatenated polar codes (e.g., in addition to the repetition, shortening, and / or puncturing schemes). For example, for a desired codeword length of 288 bits, 224 bits can be punctured or shortened from a mother code length of 512 bits. One way can be to repeat 32 bits from a mother code length of 256 bits. Another way can be to split the 288 bits into 256 bits and 32 bits. One polar code can be used with the mother code length of 256 bits, and another polar code can be used with the mother code length of 32 bits. If the desired codeword length is close to the sum of some numbers that are powers of 2, this scheme can be used. The repetition, shortening, or puncturing scheme can be applied to each component of the concatenated polar codes.

[0133] Figure 6 shows an exemplary rate matching control process. In the process of determining the (multiple) detailed rate matching schemes, one or more of the following can be applied.

[0134] If the repetition scheme is selected as the rate matching scheme, then Figure 5The rate matching control box allows selection of a detailed repetition scheme. This repetition scheme can include one or more of the following: repetition from the top of the ring buffer (e.g., natural repetition), repetition from the bottom of the ring buffer, repetition from the top of the ring buffer with bit reversal, repetition from the bottom of the ring buffer with bit reversal, random picking, uniform / distributed repetition, repetition in a continuous manner from a configured starting point, or repetition in an interleaved manner from a configured starting point. Assume e0,…,e N-1 Let N be the polarity-coded bits, and N+L be the number of bits transmitted. For repetition from the top of the ring buffer, the transmitted bits can be represented as: e0,…,e N-1 ,e0,…,e L-1 For bits repeated from the bottom of the ring buffer, the transmitted bits can be represented as: e N-1 ,…,e0,e N-1 ,…,e N-L For bits repeated from the top of the ring buffer with bit reversal, the transmitted bits can be represented as: e BR(0) ,…,e BR(N-1) ,e BR(0) ,…,e BR(L-1) For bits that repeat from the bottom of the ring buffer with bit reversal, the transmitted bits can be represented as: e BR(N-1) ,…,e BR(0) ,e BR(N-1) ,…,e BR(N-L) The choice of repetition scheme can depend on one or more of the following: the number of repeated bits, the mother code length, or the code rate. Based on the determined repetition scheme, a repetition vector can be calculated. The length of the repetition vector can be equal to the desired codeword length. Subtracting the mother code length N, each value of the repetition vector can be an index with a value between 1 and N (or between 0 and N-1). Based on the expected codeword length and the mother code length, the rate matching box can determine the N repeatable output bits of the polarity encoder. For example, for N = 256, In this case, the repetition vector can be (1,2,3,4), which implies that the first 4 bits of the polarity encoder output can be repeated. For example... Figure 6 As shown, the repeating vector can be sent to Figure 5 The rate matching box.

[0135] If a puncturing scheme is selected, the rate matching box can select a detailed puncturing scheme. This puncturing scheme can include one or more of the following: puncturing from the top of the ring buffer, puncturing from the bottom of the ring buffer, puncturing from the top of the ring buffer with bit reversal, puncturing from the bottom of the ring buffer with bit reversal, distributed puncturing (e.g., natural decomposition puncturing), puncturing continuously from a configured starting point, or puncturing interleaved from a configured starting point. Assume e0,…,eN-1 Let L be the number of punctured bits, where L is the polarity-coded bit. For puncturing from the top of a ring buffer, the punctured bits can be represented as: e0,…,e0. L-1 For a hole punched at the bottom of a ring buffer, the punched bit can be represented as: e N-L ,…,e N-1 For a ring buffer with a hole punched at the top and bit inversion, the punched bit can be represented as: e BR(0) ,…,e BR(L-1) For a ring buffer with a hole punched at the bottom and bit inversion, the punched bit can be represented as: e BR(N-L) ,…,e BR(N-1) The distributed puncturing can start from 0, N / 4, and / or N / 2. Punching can be performed sequentially. The choice of puncturing scheme can depend on one or more of the following: the number of punctured bits, the master code length, the code rate, etc. Based on the selected puncturing scheme and the number of bits to be punctured, a puncturing vector can be calculated. Figure 6 As shown, the punch vector can be sent to the rate matching box.

[0136] When a shortening scheme is selected, the rate matching frame can select a detailed shortening scheme. This shortening scheme can include one or more of the following: shortening from the bottom of the ring buffer, shortening from the bottom of the ring buffer with bit inversion (e.g., referred to as bit inversion shortening), or natural decomposition shortening. The selection of the shortening scheme can depend on one or more of the following: the number of punctured bits, the master code length, the code rate, etc. Based on the selected shortening scheme and the number of bits to be shortened, a punctured vector can be calculated, which can be sent to the rate matching frame. A shortening vector corresponding to the punctured vector can be calculated. For a polar encoder without bit inversion, the shortening vector can be equal to the punctured vector. For a polar encoder with bit inversion, the shortening vector can be equal to the bit inversion of the punctured vector. The shortening vector can be sent to the zero-insertion subframe within the channel coding frame.

[0137] In one example, the K-bit source information of downlink control information (DCI) or uplink control information (UCI) can be transmitted via a CRC attachment frame. The length J of the CRC bits can be determined by... Figure 5 The code selection control box determines the CRC. This box supports possible CRC scenarios, including single-length CRC, two separate CRCs, and standard CRC. It utilizes the CA polarity encoding process of a single CRC (such as...). Figure 13 (as shown) and the PC polarity encoding process (as shown) Figure 17 The difference between (as shown) can be the CRC length. For CA polar codes, the CRC can be set to J+J'; for PC polar codes, the CRC can be set to J.

[0138] The source bit (e.g., after the CRC is appended to the source bit) can be sent to Figure 5 The channel coding frame. This channel coding frame can perform (multiple) polarity coding operations. For example... Figure 5 As shown, the channel coding frame may include one or more of the following sub-frames: a zero-insertion sub-frame, a bit-channel mapping sub-frame, a sequence generation or selection sub-frame, or a polarity coding sub-frame. The zero-insertion sub-frame inserts zeros into a sequence (K+J) (combined source bits and CRC bits). The position of the inserted zeros may depend on the shortening vector input from the rate matching control frame. The sequence generation or selection sub-frame generates a ranked sequence (or selects from a pre-generated ranked sequence) based on one or more of the following: a given mother code length N input from the rate matching control frame, a code type input from the code selection control frame, and / or other factors such as channel conditions (e.g., SNR). For example, for a CA polarity code with a mother code length of 64 and an SNR of 5dB, we can select or generate a ranked sequence, or select a ranked sequence from a pre-generated sequence list. The bit-mapping sub-frame maps information and / or CRC bits to an appropriate bit channel for the polarity code. This operation may depend on the code type and the input ranked sequence. For example, for PC polar codes, the bit mapping subframe may determine, for example, an information set, a PC freeze set, and / or a freeze set based on a given ranked sequence. For CA polar codes, the bit mapping subframe may determine, for example, the information set and the freeze set based on a given ranked sequence. The bit mapping subframe may embed WTRU ID and CRC bits using operations such as XOR. The WTRU ID may be embedded by XORing the WTRU ID with the PC freeze bits for the PC polar code. For example, the WTRU ID may be included in the freeze set. During polar encoding, the freeze set may correspond to the number of constant bits (e.g., 0). In this case, the constant bits may be replaced with the WTRU ID. Inserting the WTRU ID into the freeze set may cause undesirable decoding errors in the UE. The polar encoding subframe may perform polar encoding operations (e.g., regular polar encoding operations), such as a generator matrix: or

[0139] like Figure 5 As shown, polarity-coded bits can be sent to a rate matching box. This rate matching box can perform puncturing or repetition operations. The selection of the puncturing vector or repetition vector can be received from the rate matching box. Figure 7 An example of rate matching for polarity-coded bits is shown. For example... Figure 7 As shown, N=2 from the polarity coding frame (not shown in the figure). nBits can be sent to an interleaver subframe within a rate-matching frame. In this example, the interleaver subframe can reorder subblocks and the N-polarity coded bits contained within them. The operation of the interleaver subframe can be associated with the rate-matching scheme used. In one example, if perforation from the top and / or bottom of the ring buffer is used, the interleaver subframe can be transparent, i.e., no specific operation is required. In one example, if a top-perforation scheme with bit inversion and / or a bottom-perforation scheme with bit inversion is used, the interleaver subframe can perform bit inversion operations on N coded bits. In one example, if a distributed perforation scheme is used, the interleaver subframe can perform interleaving operations in the middle of the N coded bits. Similar operations can be used for one or more shortening and / or repetition schemes.

[0140] Interleaved bits can be stored in a ring buffer or a virtual ring buffer. For example... Figure 7 As shown, the operation of saving bits to a ring buffer can be performed by the bit collection subframe. Further as... Figure 7 As shown, depending on the punch vector or repeat vector that can be generated by the rate matching control box, the bit selection subbox can select bits from the ring buffer. The punch vector or repeat vector can be interpreted to determine a pair of parameters (e.g., start point, duration) associated with the ring buffer.

[0141] In one example, where a punching scheme from the top of the ring buffer can be applied, the punching vector can be (0,…,0,1,1,…,1), and the first L bits are 0' and the next NL bits are 1', a pair of parameters can be determined (e.g., L+1,NL). Figure 8 An example bit selection is shown. For example... Figure 8 As shown, the bits to be used can begin at position L+1 of the ring buffer, and the bit sequence length can be NL. A similar operation can be applied to a scheme that punches holes from the top of the ring buffer with bit reversal. In this scheme, the bits can be saved to the ring buffer after the bit reversal operation. A similar operation can be applied to a distributed puncturing scheme. In this scheme, the bits can be saved to the ring buffer after performing an interleaving or interleaving operation on N encoded bits.

[0142] In one example, where a scheme of punching holes from the bottom of the ring buffer can be applied, where the punch vector can be (1,…,1,0,…,0), and where the first L bits are 1' and the last NL bits are 0', a pair of parameters (e.g., 1, L) can be determined. Figure 9 An example bit selection is shown. For example... Figure 9 As shown, the bits to be used can start at the first position of the ring buffer, and the bit sequence length is L.

[0143] A similar operation can be applied to the scheme of "punching a hole at the bottom of the ring buffer and performing a bit reversal". In this scheme, the bits can be retained in the ring buffer after the bit reversal operation.

[0144] In one example, where a scheme of repeating from the top of the ring buffer can be applied, where the repeat vector can be (1,…,1,0,…,0), and where the first L bits are 1' and the last NL bits are 0', a pair of parameters (e.g., 1, N+L) can be determined. Figure 10 An example bit selection is shown. For example... Figure 10 As shown, the bits to be used can start at the first position of the ring buffer, and the bit sequence length is N+L.

[0145] In one example, where a scheme of repeating from the bottom of the ring buffer can be applied, where the repeat vector can be (0,…,0,1,…,1), and where the first NL bits are 0' and the last L bits are 1', a pair of parameters (e.g., NL,N+L) can be determined. Figure 11 An example bit selection is shown. For example... Figure 11 As shown, the bits to be used can start at the first position of the ring buffer, and the bit sequence length is N+L.

[0146] The start and / or end points can be located on the first or last encoded bit. In some examples, neither the start nor the end point may be located on the first or last encoded bit. In the case of a hybrid scheme using top-punch and bottom-punch methods, the start and end points can be intermediate bits of the encoded bits. In one example, 1-bit shortening and top-punch can be used, with a punch vector of (0,…,0,1,…,1,0), where the first L bits are 0', the subsequent N–L-1 bits are 1', and the last bit is 0. A pair of parameters (e.g., L+1, N-1) can be determined. Figure 12 An example bit selection is shown.

[0147] Advanced PC polarity codes with CA list selection can be provided. For example, polarity codes that are a hybrid of PC polarity codes and CRC auxiliary list selection capabilities can be provided. Figure 13 and 14 Exemplary encoding and decoding of CA polar codes are shown in long CRC scenarios (e.g., as described herein). Figure 13 An exemplary encoding of a CA polar code with a long CRC is shown. Figure 14 An exemplary decoding of a CA polar code with a long CRC is shown.

[0148] like Figure 13As shown, on the encoding side, a long CRC bit (J+J') can be appended to the information bits. A CRC length of 16 bits can be used, for example, this value can be specified for LTE control channels. Other values ​​of J can also be used, for example, this value can be specified for other communication systems. The value J' can depend on the list size L within the Cyclic Redundancy Check (CRC) Assisted Successive Elimination List (CA-SCL) decoder. In one example, J' = log₂L. The K+(J+J') bits can be encoded using basic polar codes, and rate matching can be applied.

[0149] like Figure 14 As shown, on the decoder side, demodulated symbols can be sent to the CA-SCL decoder. The SCL decoder block can output a list containing L candidate sequences to the CRC-assisted (CA) list selection box. The CA list selection box can provide feedback on sequences selected based on CRC check results and / or the priority of the candidate sequences. If any of the L candidate sequences fail the CRC check (e.g., all L candidate sequences fail the CRC check), a detection error can be declared.

[0150] The (J+J') bits can be used in the CRC auxiliary list selection process (e.g., error correction process). Error detection checks can be performed after the error correction, since the selected sequence may have already passed the CRC check.

[0151] Figure 15 and 16 Exemplary scenarios for encoding and decoding CA polar codes with two separate CRCs (e.g., as described herein) are shown respectively. Figure 15 An exemplary encoding of a CA polar code with two separate CRCs is shown. Figure 16 An exemplary decoding of a CA polar code with two separate CRCs is shown.

[0152] like Figure 15 As shown, on the encoding side, JCRC bits can be appended to the K information bits. These CRC bits can be used for error detection. Additional J'CRC bits can be appended to the information bits with error detection CRC. These J'CRC bits can be used for error correction. Figure 15 As shown, the resulting (K+J+J′) bits can be encoded by a PC polarity encoder. Rate matching can be applied to the polarity encoded bits.

[0153] like Figure 16As shown, on the decoder side, demodulated symbols can be sent to the CA-SCL decoder, where the SCL decoder box can provide a list of L candidate sequences to the CA list selection box. The CA list selection box can feed back the selected sequence to the SCL decoder. The CA list selection box can select a sequence based on the J'-bit CRC check result and / or the priority of the candidate sequences. If any of the L candidate sequences fail the CRC check (e.g., all L candidate sequences fail the CRC check), a detection error can be declared, such as... Figure 16 As indicated by the down arrow inside. The decoded sequence or error declaration can be passed to the CRC check box. This CRC check box can use a J-bit CRC for error detection. If the CRC check passes, the sequence can be sent to the output; otherwise, an error can be detected and / or decoding failure can be declared.

[0154] Figure 17 and 18 Exemplary encoding and decoding for PC polar codes with CRC (e.g., as described herein) are shown respectively. Figure 17 An exemplary encoding using a PC polar encoder is shown. Figure 18 An exemplary decoding for PC polar codes is shown.

[0155] like Figure 17 As shown, on the encoding side, JCRC bits can be appended to the K information bits. These CRC bits can be used for error detection. The (K+J) bits can be encoded using PC polarity codes. The PC polarity encoded bits can be rate-matched. Multiple frozen bits can be selected as PC frozen bits within the PC polarity codes. These PC frozen bits can be used for error correction, for example, during candidate sequence selection.

[0156] like Figure 18 As shown, on the decoder side, demodulated symbols can be sent to a PC-SCL decoder, which can output a single sequence. This sequence can be passed to a CRC check. If the CRC check passes, the sequence can be sent to the output; otherwise, an error can be detected and / or decoding failure can be declared.

[0157] This document discloses a PC polarity code that is a combination of PC polarity code and CRC auxiliary list selection capability. Such encoding is similar to, for example, reference [reference name missing]. Figure 17 The example shown is a PC polarity encoding case.

[0158] Figure 19 An exemplary decoder for PC polarity codes with CRC auxiliary list selection is shown. Figure 19As shown, on the decoder side, demodulated symbols can be sent to a cascaded PC-SCL decoder. This cascaded PC-SCL decoder block may include a modified PC-SCL decoder sub-block and a CRC auxiliary list selection sub-block. The modified PC-SCL decoder can generate a list with L candidate sequences (e.g., instead of a single sequence) by selecting from the CA list. Figure 18 (As shown). Each of the L candidate sequences can be passed to an internal PC check within the decoder. The modified PC-SCL decoder outputs L candidate sequences, acting as an SCL decoder, which differs from, for example, a PC SCL decoder that outputs a single codeword. The L candidate sequences can be associated with one or more rankings. The candidate sequences can be checked using CRC, for example, based on the JCRC bits. If a high-ranking sequence passes the CRC check, that sequence can be identified as the decoded sequence. If no sequence passes the CRC check, detection / decoding failure can be declared.

[0159] The selection of the polarity code type may depend on one or more of the following: WTRU capability, WTRU category, or WTRU configuration. For example, for a WTRU with high capability, an advanced PC polarity code may be used. For a WTRU with low capability, a basic polarity code may be used. The selection of the polarity code may be determined based on the WTRU category. For example, WTRU categories 1, 2, and 3 may correspond to basic polarity codes, while WTRU categories 4, 5, and 6 may correspond to advanced PC polarity codes. The performance of the CA polarity code and the PC polarity code may depend on the list size used within the SCL decoding. With a larger list size, the PC polarity code may outperform the CA polarity code, while with a smaller list size, the CA polarity code may outperform the PC polarity code. The selection of the polarity code to be used may depend on the list size that the WTRU can support. This list size may be a part of the WTRU capability.

[0160] Puncture vector generation for shortening and / or puncturing can be provided. Puncture and / or shortening schemes can be used to exclude some bits from the output encoded bits. This may not affect code construction. Shortening schemes can puncture the output encoded bits and set the corresponding input bits to zero. These input bits can be included in the frozen bit set. These input bits can be different from other frozen bits that are set to predefined values ​​(e.g., non-zero values). Because some input bits are pre-set as frozen bits due to shortening, the frozen bit set may need to be adjusted accordingly.

[0161] The corresponding input bits can depend on the bit reversal (BR) operation included in the polarity encoding process. When the polarity encoding process includes a BR operation... When, the input bit index corresponding to the output bit can be the BR of the output bit index. When the BR operation is not included in the polar coding process When, if the input bit and the output bit have the same index, the input bit can correspond to the output bit.

[0162] The difference between puncturing and shortening lies in the way of performing decoding. When calculating the log-likelihood ratio (LLR) value or probability of each output bit based on the received signal, the LLR value or probability of each punctured (shortened) output bit can be defined. For the puncturing scheme, the LLR value can be set to log(1)=0. For example, it can indicate that the possibility of the punctured bit being 0 or 1 is the same. For the shortening scheme, the LLR value can be set to log(0)=-∞, which can imply that the punctured bit is equal to 0 (for example, it is always equal to 0)

[0163] The puncturing scheme and the shortening scheme can generate a puncturing vector to be used within the rate matching box as shown in Figure 5 The puncturing scheme and / or the shortening scheme can be provided so that a common puncturing vector can be generated for puncturing and / or shortening.

[0164] In one example, a mother code with length N = 2 n has M bits to be punctured or shortened. Let P(i) be the position of the i-th punctured bit, 0 ≤ i < M. Let I s (i) be the input bit position corresponding to the punctured bit P(i). In the case of shortening, the I s (i) bit can be shortened and set to a frozen bit.

[0165] In one example, I s (i) can be selected as: I s (i)=N - 1 - i, if i < N / 4, if i ≥ N / 4 and if i ≥ N / 4 and where [x] can be the largest integer less than x. mod(a,b) can be the remainder of a / b.

[0166] This puncturing / shortening can be extended to: I s (i)=N - 1 - i, if i < N / 2 G , if i ≥ N / 2 G and

[0167] In one example, I s (i) can be selected as: If mod(i,G)=0 If mod(i,G)=g≠0

[0168] In one example, sub-block-based puncturing can be used. For a master code length N, the N bits (e.g., N polarity-coded bits) can be divided (e.g., equally divided) into b sub-blocks. These b sub-blocks can be divided sequentially. The number of sub-blocks b can be assumed to be a power of 2. Each sub-block can have One bit. The I s (i) can be selected as follows: Functions d1 and d2 can be predefined individually, or d1 can be a function of d2. Function d1() can be a mapping function that determines the position of the sub-block within the set of sub-blocks. Function d2() can be a mapping function that determines the position of a bit within the sub-block.

[0169] In one example, d2() can be defined in such a way that d2[i] = i. d1 can depend on the reliability distribution of the bit channel of the polar code. d1[0] can correspond to the lowest reliable block of the bit channel. d1[1] can correspond to the second lowest reliable block of the bit channel, and so on. For example, for the case of b=2, we can make d1[0]=0, d1[1]=1; for the case of b=4, we can make d1[0]=0, d1[1]=1; d1[2]=2, d1[1]=3; for the case of b=8, we can make d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=4, d1[4]=3, d1[5]=5, d1[6]=6, d1[7]=7; (pattern 1) or d1[0]=0, d1[1]=1, d1[2]=4, d1[3]=2, d1[4]=3, d1[5]=5, d1[6]=6, d1[7]=7. When b=8, pattern 1 can be considered as starting from the end index. Interleaver pattern Interleaved mode Symmetric interleaver pattern. For... The interleaver mode is d1[0] = 0, d1[1] = 1, and it can generate mode 1. Pattern 1 can be represented in a tabular format as shown in Table 3. Other patterns can be represented in tabular form. i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> 0 0 4 3 1 1 5 5 2 2 6 6 3 4 7 7 Table 3 For the case where b = 16, we can make: d1[0]=0,d1[1]=1,d1[2]=2,d1[3]=4,d1[4]=8,d1[5]=3,d1[6]=5,d1[7]=6,d1[8]=9,d1[9]=10,d1

[10] =12,d1

[11] =7,d1

[12] =11,d1

[13] =13,d1

[14] =14,d1

[15] =15; (Mode 2) or d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=3, d1[4]=4, d1[5]=8, d1[6]=5, d1[7]=6, d1[8]= 9, d1[9]=10, d1

[10] =12, d1

[11] =7, d1

[12] =11, d1

[13] =13, d1

[14] =14, d1

[15] =15; or d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=4, d1[4]=3, d1[5]=8, d1[6]=5, d1[7]=6, d1[8]= 9, d1[9]=10, d1

[10] =12, d1

[11] =7, d1

[12] =11, d1

[13] =13, d1

[14] =14, d1

[15] =15; Pattern 2 can be represented in tabular format, as shown in Table 4. i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> 0 0 4 8 8 9 12 11 1 1 5 3 9 10 13 13 2 2 6 5 10 12 14 14 3 4 7 6 11 7 15 15 Table 4 For the case where b = 32, we can make: d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=4, d1[4]=8, d1[5]=16, d1[6]=3, d1[7]=5, d1[8]=6, d1 [9]=9,d1

[10] =10, d1

[11] =17, d1

[12] =12, d1

[13] =18, d1

[14] =20, d1

[15] =7, d1

[16] =24, d1

[17] =11, d1

[18] =13, d1

[19] =19, d1

[20] =14, d1

[21] =21, d1

[22] =22, d1

[23] =25, d1[24 ]=26, d1

[25] =28, d1

[26] =15, d1

[27] =23, d1

[28] =27, d1

[29] =29, d1

[30] =30, d1

[31] =31.

[0170] Expression (1) can also be represented as: where d′1[i] = b - 1 - d1[i], d′2[i] = B - 1 - d2[i], and / or where d′1[i] = d1[i], d′2[i] = d2[i]. In one example, d1() can be represented as in pattern (1) or pattern (2) or other patterns described herein. In one example, d2() can be represented as d2(i) = i.

[0171] The value of d1[i] can be derived by classifying the value representing each block i. If i indicates a block with an input bit index from B×(i - 1) to B×(i - 1) + B - 1, the representative value can be the average reliability value, or the minimum reliability value, or the maximum reliability value of the range. d1[i] can be the index of the sub - block with the i - th representative value.

[0172] Some d1[i′] and d1[i″] (i′≠i″) within the derived d1[i] can be swapped, for example, to improve the properties of the Hamming distance and the error performance of shortening and puncturing. A common total puncturing vector for puncturing and / or shortening can be used, and the determination of shortening or puncturing can be based on a specific criterion. This criterion can be the code rate described herein.

[0173] The common total puncturing vector can be divided into a puncturing part and a shortening part, where this common puncturing vector can be shared between puncturing and shortening. In one example, shortening can be used for P(i), i < p0, while puncturing can be used for P(i), i ≥ p0. p0 can be fixed or can depend on the code rate (or mother code rate) or p. p can be the total number of puncturing and shortening, and p0 ≤ p. When shortening can be used, the corresponding input bit position I s (i) can be set to 0, where in the case that the BR operation is applied to the polar encoder, P(i) = BR(I s (i), n), or in the case that the BR operation is not applied to the polar encoder, P(i) = I s (i). Here, in n bits, BR(x, n) can be the bit - reversal of the integer x; according to the indices of these zero - valued input bits, the unfrozen bits in the polar encoder can be rearranged; these zero - valued input bits can be excluded during the process of unfrozen bit selection.

[0174] Figure 20 Shows an exemplary BLER comparison between the proposed sub - block - based puncturing and shortening schemes. In a shortening example with N = 512, K = 126, P = 182, CA - SCL decoding is applied with a list size of 8 and a CRC length of 16. This example is for the second mode or the case of b = 16. As can be seen from the results, the exemplary scheme at 10 -3The BLER can have a coding gain of ~0.35dB.

[0175] When R(i) is the position of the i-th repeating bit, R(i) = P(N–1 - (i%N)). i can be greater than N-1 for repeating. i can be less than N-1 for puncturing and / or shortening. The repeating pattern can be configured based on a common puncturing vector that can be used for puncturing and shortening. An interleaver (such as the interleaver described herein) can be configured based on R(i) or P(i), and the i-th bit position (index) after interleaving can be the R(i)-th bit position (index) before interleaving (e.g., where the index starts from zero).

[0176] The interleaver pattern d1() or d′1() can be determined as indicated by expression 1 or 2, and can be used for sub-block level interleaving. See expression 1 or 2. This can be the index of the bit before applying sub-block-based interleaving, corresponding to the i-th bit after applying sub-block interleaving. In this expression, i can be the index of the bit after interleaving. The number of bits in a sub-block or the sub-block size B can be determined as: Where N is the number of polarity coded bits (e.g., mother code length) and b is the number of sub-blocks. It can be the index of the interleaved sub-block containing the i-th bit after interleaving. `d2()` can be the index of the sub-block before interleaving. `mod(i,B)` can be the index of the i-th bit in the sub-block after interleaving. `d2()` can be the interleaver mode in the sub-block. In one example, the expression `d2(x) = x` can indicate that interleaving is not applied in the sub-block. `d2(mod(i,B))` can be the index of a bit in the sub-block before interleaving, which can correspond to the i-th bit in the sub-block after applying sub-block-level interleaving.

[0177] Figure 21 It shows the use of An example of a sub-block interleaver for 8 sub-blocks indexed. In this example, polarity-coded bits can be divided (e.g., equally and sequentially) into 8 sub-blocks (e.g., sub-blocks 0 to 7). These 8 sub-blocks can be interleaved based on interleaver mode 1. Based on mode 1, these sub-blocks can be rearranged in the order [0,1,2,4,3,5,6,7]. This rearranged sub-block can be stored as a ring buffer.

[0178] Figure 22 It shows the use of An example of a sub-block interleaver for 16 sub-blocks indexed. Polarity-coded bits can be divided into (e.g., equally divided) 16 sub-blocks. These 16 sub-blocks can be interleaved based on an interleaver mode (Mode 2 as described herein). Based on Mode 2, these sub-blocks can be rearranged in the order [0,1,2,4,8,3,5,6,9,10,12,7,11,13,14,15].

[0179] By doubling each sub-block to 2 sub-blocks, interleaver pattern 1 can be expanded to 16 sub-blocks. For example, the middle 8 sub-blocks can be interleaved or staggered, while the top 4 and bottom 4 sub-blocks can remain unchanged. The interleaver pattern is as follows: d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=3, d1[4]=4, d1[5]=8, d1[6]=5, d1[7]=9, d1[8]= 6, d1[9]=10, d1

[10] =7, d1

[11] =11, d1

[12] =12, d1

[13] =13, d1

[14] =14, d1

[15] =15.

[0180] By quadrupling each sub-block, interleaver pattern 1, as described here, can be expanded to 32 sub-blocks. For example, the middle 16 sub-blocks can be interleaved, while the top 8 and bottom 8 sub-blocks can remain unchanged. The interleaver pattern is as follows: d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=3, d1[4]=4, d1[5]=5, d1[6]=6, d1[7]=7, d1[8]=8, d1[ 9]=16, d1

[10] =9, d1

[11] =17, d1

[12] =10, d1

[13] =18, d1

[14] =11, d1

[15] =19, d1

[16] =12, d1

[17] =20, d1

[18] =13, d1

[19] =21, d1

[20] =14, d1

[21] =22, d1

[22] =15, d1

[23] =23, d1[24 ]=24, d1

[25] =25, d1

[26] =26, d1

[27] =27, d1

[28] =28, d1

[29] =29, d1

[30] =30, d1

[31] =31.

[0181] Figures 23A-23C It shows the use of An example of a sub-block interleaver with 32 sub-blocks indexed. In this example, the middle 16 sub-blocks can be interleaved, while the top 8 and bottom 8 sub-blocks can be directly copied from interleaver pattern mode 1 (e.g., described herein). This provides interleaver pattern mode 3 as shown below: d1[0]=0, d1[1]=1, d1[2]=2, d1[3]=4, d1[4]=3, d1[5]=5, d1[6]=6, d1[7]=7, d1[8]=8, d1[ 9]=16, d1

[10] =9, d1

[11] =17, d1

[12] =10, d1

[13] =18, d1

[14] =11, d1

[15] =19, d1

[16] =12, d1

[17] =20,d1

[18] =13,d1

[19] =21,d1

[20] =14,d1

[21] =22,d1

[22] =15,d1

[23] =23,d1

[24] =24,d1

[25] =25,d1

[26] =26,d1

[27] =28,d1

[28] =27,d1

[29] =29,d1

[30] =30,d1

[31] =31. (Pattern 3) This pattern 3 can be expressed in the tabular format shown in Table 5. i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> i <![CDATA[d1(i)]]> 0 0 4 3 8 8 12 10 16 12 20 14 24 24 28 27 1 1 5 5 9 16 13 18 17 20 21 22 25 25 29 29 2 2 6 6 10 9 14 11 18 13 22 15 26 26 30 30 3 4 7 7 11 17 15 19 19 21 23 23 27 28 31 31 Table 5

[0182] An interleaver can be used after rate matching. A group-based channel interleaver can be provided. The output coded bits generated by the polarity encoder can be interleaved. For example, coded bits can be interleaved after applying the rate matching function and / or before modulation. Exemplary interleaving operations can provide improved block error rate (BLER) performance, such as when using higher-order modulation or in the presence of attenuation channels.

[0183] Input information bits may correspond to output coded bits. Input information bits may have an associated reliability ordering. Rate-matched output coded bits may be ordered based on the reliability ordering associated with their respective corresponding input information bits.

[0184] c(i) can be the value of the i-th encoded and rate-matched bit, where i = 0, 1, ..., N. M can indicate the bit index of the output encoded bit (e.g., natural order, sequence index from the start point). M can be the rate-matching parameter, which can be the number of bits punctured or shortened. In one example, rate matching can be performed by repetition. In this example, M can be negative. When an output bit is repeated, the index order of that output bit can be associated with the same index order associated with the original repeated bit.

[0185] cr(j) can be the value of the (N–M–1–j)th reliable output coded bit, where j = 0, 1, …, NM indicates the reliability index of the output coded bit. The reliability ordering of this output coded bit can follow the reliability ordering of the corresponding input bits. When the corresponding input bit can be a frozen bit and / or a parity bit, the associated reliability ordering can be a fairly low and / or the lowest reliability ordering. When the output bit is repeated, the associated reliability ordering can be the same as the reliability ordering associated with the original repeated bit.

[0186] In one example, Q=2 can be used. q -ary modulation. The number of input bits provided for this modulation can be q. These bits can be used to generate modulation symbols. The reliability of these q bits may vary. For example, if q = 4, the first two bits can be classified as having higher reliability than the last two bits of LTE 16QAM. Two levels of reliability can be provided for bits modulated using 16QAM.

[0187] In an example using 64QAM (e.g., where q = 6), the bits can be classified into three reliability levels. The first two bits can be classified as the most reliable, the next two or more bits can be classified as having a lower reliability than the first two bits, and the last two bits can be classified as having the lowest reliability. q -ary modulation can have q / 2 reliability levels. Multiple or a certain number of reliability levels can be utilized.

[0188] In one example, c(i), i = 0, ..., NM bits can be divided into q / 2 blocks. These M bits are divided equally. BL(k) indicates the k-th block. After division, each block can be interleaved. The interleaver can be a random interleaver, a block interleaver, a bit-reversing interleaver, a natural decomposition interleaver, etc. The effect of the selected interleaver used within rate matching can be counted (see, for example...). Figure 7 (and related descriptions provided herein). In the example using a random interleaver, an interleaving pattern can be generated based on a pseudo-random sequence, which may include, for example, the gold sequence used in LTE technology. In the case of a block interleaver, the same or different interleaving depths can be applied to the block interleaver.

[0189] In one example, cr(j), j = 0, ..., NM bits can be divided into q / 2 blocks. For example, the bits can be divided equally. Each sub-block can be represented by BL(k). Each sub-block (e.g., after division) can be interleaved using one or more interleavers. Each BL(k) block (e.g., after interleaving) can be mapped to input bits that will be provided for modulation and associated with a specific reliability level.

[0190] For example, interleaved bits from the q / 2 block described herein can be mapped to modulation symbols. In one example, bits provided for modulation with high reliability can be associated with rate-matched coded bits with high reliability (e.g., which may correspond to input bits with high reliability). In another example, bits provided for modulation with low reliability can be associated with rate-matched coded bits with low reliability (e.g., which may correspond to input bits with low reliability). The k-th component bit of the modulation symbol can be associated with BL(k). Figure 24 An exemplary implementation of this example using 16AQM is shown, where shaded boxes indicate more reliable bits, while unshaded boxes indicate less reliable bits.

[0191] In one example, a relatively unreliable bit provided for modulation may be associated with a relatively more reliable rate-matched coded bit (e.g., a bit that may correspond to a more reliable input bit). The k-th component bit of the modulation symbol may be associated with BL(q / 2–k / 2). Figure 25 An exemplary implementation of this example using 16AQM is shown, where shaded boxes indicate more reliable bits, while unshaded boxes indicate less reliable bits. These representations can be applied to one or more of the coded bits and component bits of the modulation symbol example. In other examples, 64QAM modulation and / or 256QAM modulation may be used.

[0192] In one example, the encoding and rate-matching bits can be divided into q / 2 blocks. Figure 26 An implementation of this example using 16QAM modulation and 4 divisions is shown. Figure 26 As shown, shaded boxes indicate more reliable bits, while unshaded boxes indicate less reliable bits. Figure 27 An exemplary QPSK modulation with two segments is shown. Figure 28 An example of exemplary QPSK modulation with two segments is shown. (For 2) q The number of segments in -ary modulation can include, for example, (q-1) segments or the number of basic segments. Figure 29 An exemplary QPSK modulation with 5 blocks is shown. The coding and rate-matching bits may be equally divided or not. For example, the blocks may have different numbers of bits.

[0193] Figure 30An exemplary channel interleaver for a physical channel is shown. Operation can be applied to the uplink and / or downlink using a parallel block interleaver. The output, assuming rate matching, may include M bits u1,…,u M These bits can be divided into several groups. The number of groups can be represented as p. For simplification, M is divisible by p. If M is not divisible by p, empty bits or dummy bits can be inserted into the rate-matched output so that the total number of bits is divisible by p.

[0194] The bits can be grouped according to their order. The first group may include u1, u2, ..., u M / p The second group may include And the p-th group may include The bits can be grouped based on an interleaved order. The first group may include u1, u2, u3, u4, u5, u6, u7, u8, u9, u1, u9, u1, u9, u1, u9, u1, u9, u1, u1, u9, u1, u1, u1, u2 ... p+1 ,…,u M-p+1 The second group may include u2,u p+2 ,…,u M-p+2 And the p-th group may include u p ,u 2p ,…,u M The bits can be grouped based on subgroup operations. Subgroups v1,…,v can be generated. q Subgroups may include those from u1,…,u M Several bits. Subgroups v1,..,v q Bits u1,…,u can be considered as bits within the operations described herein. M

[0195] The grouped bits can be passed to their respective interleavers. These interleavers can be block interleavers with the same depth, block interleavers with different depths, or arbitrary interleavers. In the example of block interleavers, assume d1, d2, ..., d p Let d be the depth of these p block interleavers. i Some or all of them can have different values. Depth value d i It can be a prime number. d i Other values ​​are possible.

[0196] Interleaved bits from p groups can be combined into a joint output. The interleaved bits can be combined in group order. For example, the first group of interleaved bits can be generated first, followed by the second group, and so on. The interleaved bits can be combined in a group order with a specific pattern. For example, the second group of interleaved bits can be generated first, followed by the fifth group, and so on. The interleaved bits can be combined in an interleaved order. For example, this order could be: first bit from the first group, first bit from the second group, ..., first bit from the last group, second bit from the first group, second bit from the second group, ..., second bit from the last group, third bit from the first group, ... The interleaved bits can be combined in an interleaved order (e.g., by using group order).

[0197] Figure 31 An example interleaving that can be performed between rate matching and modulation is shown. In one example, interleaving can be performed first within a rate matching frame. Interleaving performed after a rate matching frame can be considered as interleaving performed as part of a rate matching frame or function.

[0198] Exemplary interleaver designs may depend on the modulation order. Deterministic or block interleavers that perform interleaving after a rate matching box or function to obtain higher-order modulation and performance within the attenuation channel may allow the number of rows to be equal to or equal to the modulation order minus one.

[0199] The block interleaver following the rate matching box can be described by the depth of the rate matching box. Figure 32 An example of a block interleaver with a depth of 5 (e.g., the number of rows in the block interleaver) is shown. The depth of the block interleaver can depend on the modulation order. For example, a block interleaver with a depth of 7 may not be sufficient for 64QAM modulation (e.g., it may not achieve the desired performance). For 16QAM modulation, a block interleaver with a depth of 7 may be sufficient (e.g., it can achieve the desired performance).

[0200] like Figure 33 , Figure 34 and Figure 35 As shown, a block interleaver with a depth of 11 is sufficient for QPSK, 16QAM and / or 64QAM modulation orders, as well as AWGN channels and / or attenuation channels. Figure 32This can be followed by a block interleaver of depth 11, having 11 rows. A uniform block interleaver of fixed depth can be used for each supported modulation order. For example, for simplicity, a uniform block interleaver of fixed depth can be used for each supported modulation order. Each supported modulation and / or modulation order can include modulation and / or modulation orders that can achieve gain by using a block interleaver. The block interleaver used can include a block interleaver of depth 11 as a bit-channel interleaver after the rate matching frame for modulation such as QPSK, 16QAM, 64QAM, and / or 64QAM. An example could use a block interleaver of depth 11 as a bit-channel interleaver after the rate matching frame for each supported modulation order, for example, for modulations that may be higher than 64QAM. A triangular interleaver can be used after the rate matching frame, for example, to achieve performance similar to that achieved by a block interleaver. A random interleaver can be used after the rate matching frame to achieve performance similar to that achieved by a block interleaver and / or a triangular interleaver.

[0201] Block interleavers with varying depths can be used. For example, different depths based on the modulation order can be used. For instance, block interleavers with depths of 5, 7, and / or 11 can be applied to QPSK modulation, and / or block interleavers with depths of 7 and / or 11 can be applied to 16QAM modulation. Block interleavers with depths of 5 and / or 11 can be applied to 64QAM modulation. Block interleavers with a depth of 11 can be applied to 16QAM modulation, and / or block interleavers with a depth of 5 can be applied to 64QAM modulation.

[0202] The depth of the block interleaver can be selected and / or specified based on the code rate. For example, a smaller depth can be used at high code rates. A larger depth can be used at low code rates. In the 1 / 2 code rate example, one or more depths can be used to achieve similar block error rate performance. In one example, a depth of 3 can be used for the modulation order (e.g., all modulation orders). In one example, at a code rate of 1 / 6, a larger depth (e.g., 11) can be used to achieve better block error rate performance than a shorter depth (e.g., 3 or 5). In one example, as described herein, the depth of the block interleaver can be selected and / or specified based on the modulation order and / or code rate.

[0203] If natural decomposition shortening or puncturing schemes are used as rate matching schemes, an interleaver within the rate matching frame or function can be designed so that the encoded bits can be equally divided into four groups. The second and third groups of these four groups can be interleaved.

[0204] Figure 36An exemplary performance gain for using a determinate interleaver for 16QAM modulation after a rate-matched frame is shown. Performance simulations of natural decomposition puncturing, natural decomposition shortening, bit inversion shortening, and natural repetition examples provide the results described herein. In this simulation, QPSK modulation and a QWGN channel are assumed. In this simulation, polar codes with PW sequences and a CA-SCL (L=8) decoding algorithm can be used. A 19-bit CRC can be appended to the source data. This CRC bit can be considered as part of the information bits.

[0205] Triangular channel interleavers can be used in uplink (UL) transmissions. Parallel rectangular interleavers can be used in downlink (DL) transmissions. Triangular channel interleavers are available.

[0206] In one example, it is possible to make u1,…,u M Let M be the output bits of a rate-matched converter that can be transmitted. A minimum integer P can be determined such that... Assumption And y1,…,y Q For y i =u i ,1≤i≤M, and y i =NULL, M+1≤i≤Q, such as Figure 49 As shown, the bit sequence y1,…,y can be represented as... Q An isosceles right triangle is written row by row from the top left corner of the array. The output of the triangle interleaver can be a bit sequence read column by column starting from the first column, for example, y1, y2, y3, y4, y5, y6, y7, y8, y9, y1 ... P+1 ,y 2P During this process, empty bits can be skipped.

[0207] Various variations of the triangular interleaver are available. In one example, a null bit can be inserted at the beginning of the bit sequence from the rate-matching box. A minimum integer P can be determined such that... Assumption And y1,…,y Q For y i =NULL, 1≤i≤QM and y i =u i-(Q-M) Q-M+1≤i≤Q, the bit sequence y1,…,y Q Write isosceles right triangles row by row, starting from the top left corner of the array. For example, columnar permutations can be applied. The output of the triangular interleaver can be a bit sequence read column by column, starting from the first column, for example, y1, y2. P+1 ,y 2P During this process, empty bits can be skipped. This avoids errors in the bit sequence u1,…,u M Insert an empty bit at the beginning so that the first output bit is u1.

[0208] In one example, such as Figure 50 As shown, the bottom right corner of the array can be applied. This can be done in the bit sequence u1,…,u M Insert a null bit at the end. The smallest integer P can be determined such that... Assumption And y1,…,y Q For y i =u i , 1≤i≤M, and such that y i =NULL, M+1≤i≤Q, then as Figure 50 As shown, the bit sequence y1,…,y can be sequentially arranged row by row starting from the bottom right corner of the array. Q Write an isosceles right triangle. For example, columnar permutations can be applied. The output of the triangular interleaver can be a bit sequence read column by column, starting from the first column, for example, y Q-P+1 ,y Q-P+2 ,y Q-2P+2 …In this process, empty bits can be skipped.

[0209] In one instance, the bit sequence u1,…,u M Insert the bottom right corner of the array and an empty bit at the beginning of the array. The smallest integer P can be determined such that... Assumption And y1,…,y Q For y i =NULL, 1≤i≤QM, and make y i =u i-(Q-M) If Q-M+1≤i≤Q, then as follows Figure 50 As shown, the bit sequence y1,…,y can be sequentially arranged row by row starting from the bottom right corner of the array. Q Write an isosceles right triangle. For example, columnar permutations can be applied. The output of the triangular interleaver can be a bit sequence read column by column, starting from the first column, for example, y Q-P+1 ,y Q-P+2 ,y Q-2P+2 During this process, empty bits can be skipped. Columnar permutations can be applied to, for example, further randomize the output of the triangular interleaver.

[0210] Parallel triangular interleavers can be applied as described herein. For example, M output bits from a rate matcher can be divided into B groups. Each group can have the same number of bits or a different number of bits. One or more virtual / empty bits can be added to ensure that each group has the same number of bits. The number of groups can depend on the modulation order. The M output bits of the rate matcher can be divided in different ways. Triangular interleavers can be applied to the groups. The outputs of the triangular interleavers for each group can be combined, for example, via cascading or interleaving operations. For example, v can be made i,1 ,…,v i,Q Let v be the output bit from the i-th group. Assuming there are 4 groups, if interleaving is applied, the final output of the channel interleaver can be given as v. 1,1 ,v 2,1 ,v 3,1 ,v 4,1 ,v 1,2 ,v 2,2 ,v 3,2 ,v 4,2, v 1,3 ,…,v 1,Q ,v 2,Q ,v 3,Q ,v 4,Q . Figure 30 The example shown can be applied to a triangular interweaver.

[0211] Figure 51 An example of a polarity coding system is shown. For example... Figure 51 As shown, an exemplary polarity coding system may include one or more of the following: a CRC attachment and coding construction frame, a rate matching control frame, a polarity coding frame, a rate matching frame, a channel interleaving frame, or a modulation frame. The channel interleaving frame may be referred to as a channel interleaver or a bit interleaver. In one example, the channel interleaving frame may be part of the rate matching frame. Figure 51 The polar coded bits N from the polar coding frame can be rate matched based on the rate matching scheme generated by the rate matching control frame described herein. The rate-matched bits M can be passed through the channel interleaving frame to interleave the M bits as described herein. The bits after the channel interleaving frame can be sent to the modulation frame to generate modulation symbols as described herein.

[0212] While features and elements have been described above in specific combinations, those skilled in the art will understand that each feature or element can be used alone without the other features and elements described, or in any combination with other features and elements. Although the foregoing features take into account New Radio (NR), 3G, 4G, 5G, LTE, LTE-A, and / or other examples, it should be understood that the features described herein are not limited to these technologies and may also be applicable to other wireless systems.

[0213] The processes described herein can be implemented using computer programs, software, or firmware, and can be contained in a computer-readable medium executed by a computer and / or processor. Examples of computer-readable media include, but are not limited to, electronic signals (transmitted via wired and / or wireless connections) and / or computer-readable storage media. Examples of computer-readable storage media include, but are not limited to, read-only memory (ROM), random access memory (RAM), registers, buffer memory, semiconductor memory devices, magnetic media (e.g., but not limited to internal hard disks and removable disks), magneto-optical media, and / or optical media (e.g., CD-ROM discs and / or digital universal discs (DVDs)). The processor associated with the software is used to implement an radio frequency transceiver for use in WTRUs, terminals, base stations, RNCs, and / or any host computer.

Claims

1. A wireless transmit / receive unit (WTRU), comprising: The processor is configured as follows: Generate multiple uplink control information (UCI) bits to be transmitted in the codeword; Apply the polar code to the UCI bit; Generate polarity-encoded UCI bits based on the applied polarity code; as well as Transmit the polarity-encoded UCI bits.

2. The WTRU according to claim 1, wherein the processor is configured to: Determine the codeword length associated with the transmission of the polarity-encoded UCI bits; and The mother code length is determined based on the codeword length, wherein the mother code length is associated with the polarity code.

3. The WTRU according to claim 2, wherein the processor is configured to: Rate matching is performed on the polarity-encoded UCI bits, wherein the rate matching is performed using one of the following: If the codeword's code rate is less than a threshold and the mother code length is greater than the codeword length, then the puncturing scheme, and If the code rate of the codeword is greater than the threshold and the length of the mother code is greater than the length of the codeword, then a shortening scheme is adopted.

4. The WTRU according to claim 2, wherein the mother code length is determined based on the code rate.

5. The WTRU of claim 1, wherein the codeword further comprises a plurality of cyclic redundancy check (CRC) bits.

6. The WTRU of claim 3, wherein the code rate corresponds to the number of UCI bits and cyclic redundancy check (CRC) bits in the codeword divided by the number of encoded bits in the codeword.

7. The WTRU according to claim 1, wherein the polar code includes a concatenated polar code.

8. A wireless transmit / receive unit (WTRU), comprising: The processor is configured as follows: The first plurality of polar-encoded bits are generated using the mother code length and polarity encoding. Determine a second set of polarity-encoded bits from the first set of polarity-encoded bits; as well as Transmit the second plurality of polarity-encoded bits.

9. The WTRU of claim 8, wherein the processor is configured to: Determine a first group subset of the first plurality of polarity-encoded bits; and Determine a second subset of the first plurality of polarity-encoded bits.

10. The WTRU of claim 9, wherein the size of each group in the first group subset and each group in the second group subset of the first plurality of polarity-coded bits is based on the ratio of the mother code length to the number of groups in the first group subset and the second group subset.

11. The WTRU of claim 9, wherein a sub-block interleaver pattern is further used to determine the second plurality of polar-coded bits such that the position of the first group subset remains unchanged and the position of the second group subset changes.

12. The WTRU of claim 9, wherein the second group subset comprises a first group portion and a second group portion, wherein adjacent groups in the first group portion exchange positions and wherein groups in the second group portion are moved to predetermined positions.

13. The WTRU of claim 10, wherein the order of the polar-coded bits in the second plurality of polar-coded bits associated with each group in the first group subset or with each group in the second group subset remains unchanged.

14. The WTRU of claim 8, wherein the WTRU is further configured to apply a rate matching scheme to a second plurality of polarity-coded bits stored in a ring buffer, wherein the rate matching scheme is determined based on the mother code length, the rate matching output size, and the code rate.

15. The WTRU of claim 14, wherein the rate matching scheme is one of a repeating scheme, a punching scheme, or a shortening scheme.

16. The WTRU of claim 15, wherein the rate matching scheme is a repetition scheme when the rate matching output size is greater than the mother code length, and wherein the rate matching scheme is a shortening scheme or a puncturing scheme when the rate matching output size is less than the mother code length, wherein the selection between the shortening scheme and the puncturing scheme is based on the code rate.

17. The WTRU of claim 14, wherein the processor is configured to: The sub-block interleaver is executed after the rate matching scheme is applied to the second or more polarity-encoded bits stored.

18. The WTRU of claim 11, wherein the sub-block interleaver mode is based on a mapping function, wherein the mapping function determines the position of the bits within the sub-block.

19. The WTRU of claim 18, wherein the processor is configured to: Perform a sub-block interleaver on the first and second group subsets of 8, 16, or 32 sub-blocks.

20. The WTRU of claim 18, wherein the position of each group in the first group subset and the second group subset is based on the following group-based sub-block interleaver pattern: d1[0] = 0, d1[1] = 1, d1[2] = 2, d1[3] = 4, d1[4] = 3, d1[5] = 5, d1[6] = 6, d1[7] = 7, d1[8] = 8, d1[9] = 16, d1[10] = 9, d1[11] = 17, d1[12] = 10, d1[13] = 18, d1[14] = 11, d1[15] = 19, d1[16] = 12, d1[17] = 20, d1[18] = 13, d1[19] = 21, d1[20] = 14, d1[21] = 22, d1[22] = 15, d1[23]=23, d1[24]=24, d1[25]=25, d1[26]=26, d1[27]= 28,d1[28]=27,d1[29]=29,d1[30]=30,d1[31]=31, wherein the first group subset of the first plurality of polar-encoded bits includes d1[0] to d1[2], d1[5] to d1[8], d1[23] to d1[26], and d1[29] to d1[31], and the second group subset of the first plurality of polar-encoded bits includes d1[3] to d1[4], d1[9] to d1[22], and d1[27] to d1[28].

21. The WTRU of claim 18, wherein the interleaved sub-blocks are stored in a ring buffer.

22. A wireless transmit / receive unit (WTRU), the WTRU comprising: The processor is configured as follows: Generate multiple uplink control information (UCI) bits to be transmitted in the codeword; Apply the polar code to the UCI bit; Generate polarity-encoded UCI bits based on the applied polarity code; as well as Transmit the polarity-encoded UCI bits.

23. The WTRU of claim 22, wherein the processor is configured to: Determine the codeword length associated with the transmission of the polarity-encoded UCI bits; and The mother code length is determined based on the codeword length, wherein the mother code length is associated with the polarity code.

24. The WTRU of claim 22, wherein the processor is configured to: Rate matching is performed on the polarity-encoded UCI bits, wherein the rate matching is performed using one of the following: If the codeword's code rate is less than a threshold and the mother code length is greater than the codeword length, then the puncturing scheme, and If the code rate of the codeword is greater than the threshold and the length of the mother code is greater than the length of the codeword, then a shortening scheme is adopted.

25. The WTRU of claim 23, wherein the mother code length is determined based on the code rate.

26. The WTRU of claim 22, wherein the codeword further comprises a plurality of cyclic redundancy check (CRC) bits.

27. The WTRU of claim 24, wherein the code rate corresponds to the number of UCI bits and cyclic redundancy check (CRC) bits in the codeword divided by the number of encoded bits in the codeword.

28. The WTRU of claim 22, wherein the polar code comprises a concatenated polar code.

29. A wireless transmit / receive unit (WTRU), comprising: The processor is configured as follows: The first plurality of polar-encoded bits are generated using the mother code length and polarity encoding. Determine a second set of polarity-encoded bits from the first set of polarity-encoded bits; as well as Transmit the second plurality of polarity-encoded bits.

30. The WTRU of claim 29, wherein the processor is configured to: Determine a first group subset of the first plurality of polarity-encoded bits; and Determine a second subset of the first plurality of polarity-encoded bits.

31. The WTRU of claim 30, wherein the size of each group in the first group subset and each group in the second group subset of the first plurality of polarity-coded bits is based on the ratio of the mother code length to the number of groups in the first group subset and the second group subset.

32. The WTRU of claim 31, wherein a sub-block interleaver pattern is further used to determine the second plurality of polar-coded bits such that the position of the first group subset remains unchanged and the position of the second group subset changes.

33. The WTRU of claim 31, wherein the second group subset comprises a first group portion and a second group portion, wherein adjacent groups in the first group portion exchange positions and wherein groups in the second group portion are moved to predetermined positions.

34. The WTRU of claim 33, wherein the order of the polar-coded bits in the second plurality of polar-coded bits associated with each group in the first group subset or with each group in the second group subset remains unchanged.

35. The WTRU of claim 29, wherein the WTRU is further configured to apply a rate matching scheme to a second plurality of polarity-coded bits stored in a ring buffer, wherein the rate matching scheme is determined based on the mother code length, the rate matching output size, and the code rate.

36. The WTRU of claim 35, wherein the rate matching scheme is one of a repeating scheme, a punching scheme, or a shortening scheme.

37. The WTRU of claim 36, wherein the rate matching scheme is a repetition scheme when the rate matching output size is greater than the mother code length, and wherein the rate matching scheme is a shortening scheme or a puncturing scheme when the rate matching output size is less than the mother code length, wherein the selection between the shortening scheme and the puncturing scheme is based on the code rate.

38. The WTRU of claim 35, wherein the processor is configured to: The sub-block interleaver is executed after the rate matching scheme is applied to the second or more polarity-encoded bits stored.

39. The WTRU of claim 32, wherein the sub-block interleaver mode is based on a mapping function, wherein the mapping function determines the position of the bits within the sub-block.

40. The WTRU of claim 39, wherein the processor is configured to: Perform a sub-block interleaver on the first and second group subsets of 8, 16, or 32 sub-blocks.

41. The WTRU of claim 39, wherein the position of each group in the first group subset and the second group subset is based on the following group-based sub-block interleaver pattern: d1[0] = 0, d1[1] = 1, d1[2] = 2, d1[3] = 4, d1[4] = 3, d1[5] = 5, d1[6] = 6, d1[7] = 7, d1[8] = 8, d1[9] = 16, d1[10] = 9, d1[11] = 17, d1[12] = 10, d1[13] = 18, d1[14] = 11, d1[15] = 19, d1[16] = 12, d1[17] = 20, d1[18] = 13, d1[19] = 21, d1[20] = 14, d1[21] = 22, d1[22] = 15, d1[23]=23, d1[24]=24, d1[25]=25, d1[26]=26, d1[27]= 28,d1[28]=27,d1[29]=29,d1[30]=30,d1[31]=31, wherein the first group subset of the first plurality of polar-encoded bits includes d1[0] to d1[2], d1[5] to d1[8], d1[23] to d1[26], and d1[29] to d1[31], and the second group subset of the first plurality of polar-encoded bits includes d1[3] to d1[4], d1[9] to d1[22], and d1[27] to d1[28].

42. The WTRU of claim 39, wherein the interleaved sub-blocks are stored in a ring buffer.

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