Equipment baud rate configuration method and device, electronic equipment and storage medium

Abstract

The invention provides an equipment baud rate configuration method and device, electronic equipment and a storage medium, and the method comprises the steps: firstly obtaining a baud rate configuration signal, the baud rate configuration signal at least comprises an interrupt number of a system-to-system management interrupt (SMI), then obtaining a first baud rate and a second baud rate according to the interrupt number, and storing the first baud rate and the second baud rate. The method comprises the following steps: firstly, acquiring a first Baud rate and a second Baud rate in a memory, then acquiring BIOS (Basic Input Output System) information, and finally, respectively configuring the first Baud rate and the second Baud rate in the memory into a register of main equipment and a register of standby equipment on the basis of an SMI (Serial Management Interface) interrupt number in the BIOS information so as to complete the configuration operation of the Baud rates of the equipment. According to the technical scheme, the Baud rate parameters are bound with the registers of the main device and the standby device through the same SMI interrupt number, the problems that the parameters of the main device and the standby device are confused, and the configured target device is misplaced are solved, and the accuracy of Baud rate configuration is greatly improved.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a method, apparatus, electronic device, and storage medium for configuring device baud rate. Background Technology

[0002] In current computer systems, there are usually master devices and backup devices. The stability of serial communication depends on the precise configuration of the baud rate of the master device and the baud rate of the backup device.

[0003] In related technologies, manually configuring the baud rates of the primary and backup devices separately lacks unified signal triggering and process control, resulting in asynchronous baud rate configurations between the primary and backup devices.

[0004] Therefore, ensuring the synchronous configuration and effectiveness of device baud rates has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides a method, apparatus, electronic device, and storage medium for configuring the baud rate of a device, in order to solve problems such as asynchronous baud rate configuration and failure to take effect between the main device and the backup device in related technologies.

[0006] In a first aspect, embodiments of this application provide a method for configuring the baud rate of a device, including:

[0007] Obtain the baud rate configuration signal, which must include at least the interrupt number of the System Management Interrupt (SMI).

[0008] Based on the interrupt number, obtain and store the first baud rate and the second baud rate; wherein, the first baud rate is used by the master device to configure the baud rate, and the second baud rate is used by the standby device to configure the baud rate;

[0009] Obtain Basic Input Output System (BIOS) information; based on the SMI interrupt number in the BIOS information, configure the first baud rate in memory to the master device's register, and configure the second baud rate information in memory to the standby device's register to complete the device baud rate configuration operation.

[0010] In one possible implementation, storing the first baud rate and the second baud rate in the memory includes:

[0011] Based on the first preset mapping relationship, the offset address corresponding to the interrupt number is determined; wherein, the first preset mapping relationship represents the mapping relationship between the SMI interrupt number and the memory offset address;

[0012] The first and second baud rates are obtained and stored in the memory in the area corresponding to the offset address.

[0013] In one possible implementation, in response to a baud rate storage completion signal, the System Management Interrupt (SMI) mechanism is triggered to invoke Basic Input / Output System BIOS information, including:

[0014] When the storage of the first baud rate and the second baud rate is completed, a baud rate storage completion signal is generated;

[0015] Send the baud rate storage complete signal to the Baseboard Management Controller (BMC).

[0016] The SMI mechanism is triggered by the BMC, and BIOS information is invoked.

[0017] In one possible implementation, based on the SMI interrupt number in the BIOS information, a first baud rate in memory is configured into the master device's register, and a second baud rate information in memory is configured into the standby device's register, including:

[0018] According to the second preset mapping relationship, the first register offset address in the register of the master device corresponding to the SMI interrupt number and the second register offset address in the register of the standby device corresponding to the SMI interrupt number are determined respectively; wherein, the second preset mapping relationship represents the mapping relationship between the SMI interrupt number and the first register offset address and the second register offset address respectively.

[0019] The first baud rate is stored in the area corresponding to the offset address of the first register, and the second baud rate is stored in the area corresponding to the offset address of the second register.

[0020] In one possible implementation, the method for configuring the device baud rate further includes:

[0021] In response to a device restart signal, the target device is retrieved from the registers of a Complex Programmable Logic Device (CPLD); the CPLD registers are the registers in the system used to store the startup information of the target device; the target device is either a primary device or a backup device that is starting up.

[0022] Retrieve the configuration information corresponding to the target device from the memory;

[0023] Based on the configuration information of the target device, determine the target baud rate used by the target device when performing serial port initialization;

[0024] The target device's serial port is initialized based on the target baud rate.

[0025] In one possible implementation, the target baud rate includes a default baud rate or a configured baud rate; after initializing the serial port of the target device based on the target baud rate, the method for configuring the device baud rate further includes:

[0026] Clear the baud rate configuration of the target device.

[0027] Secondly, embodiments of this application provide a device baud rate configuration apparatus, including:

[0028] The acquisition module is used to acquire the baud rate configuration signal, which includes at least the interrupt number of the system to the system management interrupt (SMI).

[0029] The acquisition module is also used to acquire and store the first baud rate and the second baud rate according to the interrupt number; wherein, the first baud rate is used for the master device to configure the baud rate, and the second baud rate is used for the standby device to configure the baud rate;

[0030] The processing module obtains the BIOS information of the Basic Input / Output System; based on the SMI interrupt number in the BIOS information, it configures the first baud rate in the memory into the register of the master device, and configures the second baud rate information in the memory into the register of the standby device to complete the device baud rate configuration operation.

[0031] In one possible implementation, the acquisition module is specifically used for:

[0032] Based on the first preset mapping relationship, the offset address corresponding to the interrupt number is determined; wherein, the first preset mapping relationship represents the mapping relationship between the SMI interrupt number and the memory offset address;

[0033] The first and second baud rates are obtained and stored in the memory in the area corresponding to the offset address.

[0034] In one possible implementation, the processing module is specifically used for:

[0035] When the storage of the first baud rate and the second baud rate is completed, a baud rate storage completion signal is generated;

[0036] Send the baud rate storage completion signal to the baseboard management controller (BMC);

[0037] The SMI mechanism is triggered by the BMC, and BIOS information is invoked.

[0038] In one possible implementation, the processing module is specifically used for:

[0039] According to the second preset mapping relationship, the first register offset address in the register of the master device corresponding to the SMI interrupt number and the second register offset address in the register of the standby device corresponding to the SMI interrupt number are determined respectively; wherein, the second preset mapping relationship represents the mapping relationship between the SMI interrupt number and the first register offset address and the second register offset address respectively.

[0040] The first baud rate is stored in the area corresponding to the offset address of the first register, and the second baud rate is stored in the area corresponding to the offset address of the second register.

[0041] In one possible implementation, the method for configuring the device baud rate further includes:

[0042] In response to a device restart signal, the target device is retrieved from the CPLD register of the complex programmable logic device; the CPLD register is a register in the system used to store the startup information of the target device; the target device is a primary device or a backup device that is starting up.

[0043] Retrieve the configuration information corresponding to the target device from the memory;

[0044] Based on the configuration information of the target device, determine the target baud rate used by the target device when performing serial port initialization;

[0045] The target device's serial port is initialized based on the target baud rate.

[0046] In one possible implementation, the target baud rate includes a default baud rate or a configured baud rate; after initializing the serial port of the target device based on the target baud rate, the method for configuring the device baud rate further includes:

[0047] Clear the baud rate configuration of the target device.

[0048] Thirdly, embodiments of this application provide an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0049] The memory stores the instructions that the computer executes;

[0050] The processor executes computer-executable instructions stored in memory to implement the method as described in the first aspect or any of the above.

[0051] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method described in the first aspect or any of the above-mentioned methods.

[0052] Fifthly, embodiments of this application provide a computer program. The computer program product includes a computer program stored in a computer-readable storage medium. At least one processor can read the computer program from the computer-readable storage medium. When the at least one processor executes the computer program, it can implement the methods described in the first aspect or any of the above-mentioned methods.

[0053] The device baud rate configuration method, apparatus, electronic device, and storage medium provided in this application embodiment first acquire a baud rate configuration signal, which includes at least the interrupt number of the System Management Interrupt (SMI) provided by the system. Then, based on the interrupt number, a first baud rate and a second baud rate are acquired and stored. The first baud rate is used for baud rate configuration of the master device, and the second baud rate is used for baud rate configuration of the standby device. Basic Input / Output System (BIOS) information is acquired. Finally, based on the SMI interrupt number in the BIOS information, the first baud rate in the memory is configured into the register of the master device, and the second baud rate information in the memory is configured into the register of the standby device to complete the device baud rate configuration operation. This technical solution, from acquiring the configuration signal, matching the baud rates of the master device and the standby device, to the subsequent location of the register address, uses the same SMI interrupt number to bind the baud rate parameter to the hardware register throughout the entire process. This avoids the problem of parameter confusion between the master device and the standby device and misalignment of the configuration target device, and significantly improves the accuracy of baud rate configuration. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0055] Figure 1 A flowchart illustrating the device baud rate configuration method provided in this application embodiment. Figure 1 ;

[0056] Figure 2 A flowchart illustrating the device baud rate configuration method provided in this application embodiment. Figure 2 ;

[0057] Figure 3 A flowchart illustrating the device baud rate configuration method provided in this application embodiment. Figure 3 ;

[0058] Figure 4 A schematic diagram of the device baud rate configuration apparatus provided in the embodiments of this application;

[0059] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0060] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0062] Before introducing the embodiments of this application, the application background of the embodiments of this application will be explained first:

[0063] In computer systems such as servers that have primary and backup devices, the stability of serial communication depends on the precise configuration of the baud rates of the primary and backup devices. Currently, server systems often face two core challenges in configuring the baud rates of the primary and backup devices:

[0064] On the one hand, the triggering mechanism for baud rate configuration is scattered, relying mostly on manual operation or independent commands, lacking unified signal triggering and process control, which can easily lead to asynchronous configuration of the main equipment and the backup equipment.

[0065] On the other hand, the linkage mechanism between baud rate configuration and BIOS information is imperfect. The server system has difficulty confirming the storage status of the baud rate in the memory through standardized signals. Furthermore, during the BIOS call process, the BIOS cannot accurately write the baud rate parameter into the register of the corresponding master or backup device, resulting in baud rate configuration target confusion and baud rate parameter writing failure. This seriously affects the reliability of the system's serial communication. Especially in scenarios such as remote server operation and maintenance and critical equipment debugging, the above problems will directly reduce the server system management efficiency and operational stability.

[0066] Therefore, ensuring the synchronous configuration and effectiveness of device baud rates has become an urgent technical problem to be solved.

[0067] To address the technical problems existing in related technologies, the inventors of this application propose the following solution: For the issue of asynchronous baud rate configuration and failure to take effect, a complete association of the baud rate configuration process is established based on the SMI interrupt number, achieving unified configuration, accurate storage, and reliable activation of the baud rates for the primary and backup devices. First, a baud rate configuration signal containing the SMI interrupt number is obtained. The interrupt number is used as an identifier to associate the first and second baud rates corresponding to the primary and backup devices, avoiding confusion in baud rate configuration parameter transmission. Then, based on a preset mapping relationship, the first and second baud rates are stored in the server system's memory. Next, based on the baud rate storage completion signal, the SMI mechanism is activated through the BMC, and BIOS information is called. According to the SMI interrupt number information in the BIOS information, the first and second baud rates are written into the registers of the corresponding primary and backup devices, solving the problem of baud rate configuration target confusion and achieving synchronous baud rate configuration. When the device restarts, the server system determines the target device from the CPLD register, retrieves the corresponding configuration information from memory to determine the target baud rate, and completes serial port initialization, achieving accurate activation of the baud rate configuration information for the primary and backup devices.

[0068] The parts not described in detail are disclosed in the following embodiments.

[0069] The technical solution of this application will now be described in detail through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0070] Figure 1 A flowchart illustrating the device baud rate configuration method provided in this application embodiment. Figure 1 ,like Figure 1 As shown, the method may include the following steps:

[0071] Step 11: Obtain the baud rate configuration signal. The baud rate configuration signal must include at least the interrupt number of the system to the System Management Interrupt (SMI).

[0072] In this step, the user sets the SMI interrupt number in the one-click baud rate configuration script. The SMI interrupt number includes the BIOS baud rate information of the primary and backup devices. Then, a baud rate configuration signal is sent, and the server system receives the baud rate configuration signal through a preset signal transmission mechanism.

[0073] Step 12: Obtain and store the first and second baud rates based on the interrupt number.

[0074] The first baud rate is used by the master device to configure the baud rate, and the second baud rate is used by the standby device to configure the baud rate.

[0075] In this step, the server system queries a pre-defined parameter mapping table based on the acquired SMI interrupt number. This table stores the association between different interrupt numbers and the corresponding baud rates of the primary and backup devices. By matching the interrupt numbers, the first baud rate of the primary device and the second baud rate of the backup device can be accurately extracted. Using the method of associating SMI interrupt numbers with dual baud rates (i.e., the baud rate of the primary device and the baud rate of the backup device) avoids confusion between the parameters of the primary and backup devices.

[0076] Then, the server system determines the memory offset address corresponding to the current SMI interrupt number based on the first preset mapping relationship, and writes the obtained first baud rate and second baud rate into the storage area corresponding to the offset address according to the preset format, so as to realize the centralized and orderly storage of dual baud rates.

[0077] In one example, the memory could be a complementary metal-oxide-semiconductor (CMOS).

[0078] For example, the SMI interrupt number is 0x3c (corresponding to a baud rate of 9600). Querying the preset parameter mapping table, the memory offset addresses corresponding to SMI interrupt number 0x3c are 0x6C (used to store the master device baud rate information) and 0x6E (used to store the standby device baud rate information). The corresponding baud rate configuration information is written as 0x11 at offset address 0x6C and 0x11 at offset address 0x6E respectively. The third bit (1) from left to right in 0x11 written at offset address 0x6C represents the baud rate set for the master device upon next restart. The third bit (1) from left to right in 0x11 written at offset address 0x6E represents the baud rate set for the standby device upon next restart. The fourth bit (1) from left to right in 0x11 represents the master device's configured baud rate as 9600.

[0079] For example, if the SMI interrupt number is 0x3d and the baud rate is 115200, the preset parameter mapping table will show the memory offset addresses corresponding to the SMI interrupt number 0x3d as 0x6C (used to store the master device baud rate information) and 0x6E (used to store the standby device baud rate information). The corresponding baud rate configuration information is written as 0x12 at offset address 0x6C and offset address 0x6E respectively. In the 0x12 written at offset address 0x6C, the third bit from left to right is 1, which means that the master device will be configured with a baud rate for the next restart. In the 0x12 written at offset address 0x6E, the third bit from left to right is 1, which means that the standby device will be configured with a baud rate for the next restart. The fourth bit from left to right in the 0x12 represents that the master device is configured with a baud rate of 115200.

[0080] Step 13: Obtain the Basic Input / Output System (BIOS) information.

[0081] In this step, after the memory successfully stores the first and second baud rates, the server system automatically generates a baud rate storage completion signal and sends it to the BMC. Upon receiving this signal, the BMC triggers the SMI mechanism according to preset logic, and calls the baud rate configuration information bound to the current SMI interrupt number in the BIOS through a hardware-level interrupt response. This achieves a seamless connection from baud rate data storage to baud rate configuration execution, ensuring that the baud rate configuration can be synchronized and configured promptly after data storage is ready.

[0082] Specifically, step 13 may include the following implementation methods:

[0083] Step 1: When the first baud rate and the second baud rate are stored, generate a baud rate storage completion signal.

[0084] In this implementation, the server system monitors the write status of the first baud rate and the second baud rate in real time through the memory controller. When it is confirmed that the data has been completely stored in the corresponding offset address of the memory, a baud rate storage completion signal containing a storage success identifier and the current SMI interrupt number is automatically generated.

[0085] Step 2: Send the baud rate storage completion signal to the board management controller (BMC).

[0086] In this implementation, the baud rate storage completion signal is transmitted to the BMC through a preset hardware interface. The SMI interrupt number carried in the baud rate storage completion signal can help the BMC identify the current baud rate configuration information.

[0087] Step 3: Trigger the SMI mechanism through the BMC and call the BIOS information.

[0088] In this implementation, after the BMC receives the baud rate storage completion signal, it triggers the SMI mechanism and then calls the BIOS information. Through the linkage between the BMC and the SMI mechanism, hardware-level triggering from baud rate data storage to baud rate configuration execution is achieved, ensuring the timeliness and authority of baud rate configuration.

[0089] Step 14: Based on the SMI interrupt number in the BIOS information, configure the first baud rate in the memory to the register of the master device, and configure the second baud rate information in the memory to the register of the standby device to complete the device baud rate configuration operation.

[0090] In this step, the BIOS identifies the current SMI interrupt number, reads the first and second baud rates from the corresponding offset addresses in memory, and then determines the primary device's first register offset address and the standby device's second register offset address corresponding to the interrupt number based on a second preset mapping relationship. Subsequently, the first baud rate is precisely written to the corresponding offset address in the primary device register, and the second baud rate is written to the corresponding offset address in the standby device register. This achieves precise matching from baud rate data reading to writing in the primary and standby device registers, ultimately completing the synchronized configuration of the primary and standby device baud rates.

[0091] Specifically, step 13 includes the following implementation methods:

[0092] Step 1: Based on the second preset mapping relationship, determine the first register offset address in the register of the master device corresponding to the SMI interrupt number, and the second register offset address in the register of the standby device corresponding to the SMI interrupt number.

[0093] The second preset mapping relationship represents the mapping relationship between the SMI interrupt number and the first register offset address and the second register offset address, respectively.

[0094] In this implementation, the SMI interrupt number is first extracted from the BIOS information. Then, the first register offset address in the master device's register and the second register offset address in the standby device's register are accurately matched through the second preset mapping relationship. The second preset mapping relationship ensures the correspondence between the SMI interrupt number and the offset addresses of the master and standby device registers, avoiding the risk of register address confusion under different baud rate configuration scenarios. This provides hardware-level address guidance for accurately writing baud rate parameters to the master and standby devices.

[0095] Step 2: Store the first baud rate in the area corresponding to the offset address of the first register, and store the second baud rate in the area corresponding to the offset address of the second register.

[0096] In this implementation, the first baud rate read from memory is written to the memory cell corresponding to the first register offset address in the master device register according to the master device's register data format. Simultaneously, the second baud rate is written to the memory cell corresponding to the second register offset address in the standby device register according to the standby device's register data format. During the writing process, BIOS information is verified through register readback to ensure the baud rate configuration information is transmitted correctly. Ultimately, this achieves synchronized baud rate parameters for the master and standby devices at the hardware register level, fundamentally guaranteeing the consistency of serial communication rates between the two devices.

[0097] For example, the first register offset address is 0x6H, which is used to store the configuration baud rate of the master device; the first register offset address is 0x6G, which is used to store the default baud rate of the master device; the second register offset address is 0x6K, which is used to store the configuration baud rate of the standby device; and the second register offset address is 0x6L, which is used to store the default baud rate of the standby device.

[0098] The device baud rate configuration method provided in this application first obtains a baud rate configuration signal, which includes at least the interrupt number of the System Management Interrupt (SMI). Then, based on the interrupt number, a first baud rate and a second baud rate are obtained and stored. The first baud rate is used for baud rate configuration of the master device, and the second baud rate is used for baud rate configuration of the standby device. Basic Input / Output System (BIOS) information is obtained. Finally, based on the SMI interrupt number in the BIOS information, the first baud rate in the memory is configured into the register of the master device, and the second baud rate information in the memory is configured into the register of the standby device to complete the device baud rate configuration operation. This technical solution, from obtaining the configuration signal, matching the baud rates of the master device and the standby device, to the subsequent location of the register address, uses the same SMI interrupt number to bind the baud rate parameter to the hardware register throughout the entire process. This avoids the problem of parameter confusion between the master device and the standby device and the misalignment of the configuration target device, and greatly improves the accuracy of baud rate configuration.

[0099] Based on the above embodiments, Figure 2 A flowchart illustrating the device baud rate configuration method provided in this application embodiment. Figure 2 ,like Figure 2 As shown, step 12 may include the following steps:

[0100] Step 21: Based on the first preset mapping relationship, determine the offset address corresponding to the interrupt number.

[0101] The first preset mapping relationship represents the mapping relationship between the SMI interrupt number and the memory offset address.

[0102] The aforementioned first preset mapping relationship allocates different storage areas in the memory for the baud rate information in different SMI interrupt numbers.

[0103] In this step, based on the first preset mapping relationship, the offset address of the memory corresponding to the interrupt number is determined. By binding the interrupt number with the offset address, the data storage areas of different baud rate configuration tasks are avoided from overlapping, providing a clear address guide for the subsequent rapid reading of baud rate parameters by BIOS information, while ensuring the orderly storage of baud rate data in multiple scenarios.

[0104] Step 22: Store the acquired first baud rate and second baud rate into the area of ​​memory corresponding to the offset address.

[0105] In this step, the first baud rate and the second baud rate are sequentially written to the memory area corresponding to the memory offset address according to a preset data format. During the writing process, the server system performs data verification through the memory controller to ensure that the baud rate data is stored in memory completely and without error.

[0106] The device baud rate configuration method provided in this application first determines the offset address corresponding to the interrupt number based on a first preset mapping relationship. The first preset mapping relationship represents the mapping relationship between the SMI interrupt number and the memory offset address. Then, the obtained first baud rate and second baud rate are stored in the area of ​​the memory corresponding to the offset address. This avoids conflicts and confusion in the storage of baud rate information under different configuration scenarios, and enables the baud rates of the main device and the backup device to be stored in an orderly manner, thereby improving the accuracy of baud rate configuration.

[0107] Based on the above embodiments, Figure 3 A flowchart illustrating the device baud rate configuration method provided in this application embodiment. Figure 3 ,like Figure 3 As shown, the method may also include the following steps:

[0108] Step 31: In response to the device restart signal, obtain the target device from the CPLD register of the complex programmable logic device.

[0109] The CPLD register is a register in the system used to store the startup information of the target device; the target device is the master device or the backup device that is starting up.

[0110] In this step, when the server system detects a device restart signal (such as a cold start or warm restart command), it triggers the serial port initialization phase of the BIOS full-stage boot process. The server system accesses the CPLD and obtains the current device's boot information, thereby determining whether the device being restarted is the primary or backup device, providing a clear target for subsequent targeted baud rate configuration.

[0111] The BIOS consists of three phases: the Security Phase (SEC), the Preposition Extensible Firmware Interface Initialization (PEI), and the Driver Execution Environment (DXE).

[0112] Step 32: Obtain the configuration information corresponding to the target device from the memory.

[0113] In this step, the corresponding offset address region in the memory is located by querying the first preset mapping relationship, the configuration information matching the target device is extracted from the memory, and the baud rate configuration is determined based on the SMI interrupt number in the configuration information.

[0114] The configuration information indicates whether the target device has configured the baud rate before restarting.

[0115] For example, the interrupt number in the configuration information of the master device during the restart is 0x3c. Its corresponding baud rate configuration information is 0x11 written at the offset address 0x6C in the memory (used to store the master device baud rate information). The high 4 bits (that is, the third bit from the left) of 0x11 are 1, and the low 4 bits (that is, the fourth bit from the left) are 1, which means that the master device is configured with a baud rate of 9600. In summary, this shows that the master device has performed baud rate configuration, and the configured baud rate is 9600. The serial port initialization during restart is performed using a baud rate of 9600.

[0116] For example, the interrupt number in the configuration information of the master device during the restart is 0x3c, and the corresponding baud rate configuration information is 0x01 written at the offset address 0x6C in the memory (used to store the master device baud rate information). The high 4 bits of 0x11 (that is, the third bit from the left to the right) are 0, indicating that the master device has not performed baud rate configuration and uses the master device's default baud rate for serial port initialization during restart.

[0117] Step 33: Determine the target baud rate used by the target device when performing serial port initialization based on the configuration information corresponding to the target device.

[0118] In this step, if the interrupt number in the configuration information of the target device indicates that a baud rate is configured, then the configured baud rate is used as the target baud rate; if the interrupt number in the configuration information of the target device indicates that no baud rate is configured, then the default baud rate of the target device is used as the target baud rate.

[0119] Step 34: Initialize the serial port of the target device based on the target baud rate.

[0120] In this step, the server system configures the serial port controller registers of the target device according to the determined target baud rate, including setting key communication parameters such as data transmission rate, parity bit, and stop bits to initialize the serial port. After the parameter configuration is complete, the success of the serial port initialization is confirmed by sending test data and verifying the returned results.

[0121] Specifically, after step 34, the method for configuring the device baud rate also includes:

[0122] Clear the baud rate configuration of the target device.

[0123] In this implementation, after the serial port initialization is complete, the server system automatically clears the configuration baud rate corresponding to the target device from the memory to avoid interference during the subsequent startup process of the target device system.

[0124] For example, the target device's configured baud rate information is 0x11 stored in the memory at offset address 0x6C (used to store the master device's baud rate information), and the server system modifies 0x11 to 0x00 at offset address 0x6C in the memory.

[0125] The device baud rate configuration method provided in this application first responds to a device restart signal by retrieving the target device from the CPLD register of a complex programmable logic device. The CPLD register is a register in the system used to store the startup information of the target device. The target device is either a primary device or a backup device during startup. This ensures that the baud rate configuration strictly matches the actual startup device, guaranteeing the effectiveness of the device baud rate synchronization configuration. Then, the configuration information corresponding to the target device is retrieved from the memory. Based on the configuration information corresponding to the target device, the target baud rate used by the target device during serial port initialization is determined. Finally, the serial port is initialized based on the target baud rate, ensuring that the target device communicates at the correct rate in the early stages of BIOS startup, further guaranteeing the accurate effectiveness of the device baud rate synchronization configuration.

[0126] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0127] Figure 4 This is a schematic diagram of the device baud rate configuration apparatus provided in an embodiment of this application. Figure 4 As shown, the device includes:

[0128] The acquisition module 41 is used to acquire the baud rate configuration signal, which includes at least the interrupt number of the system to the system management interrupt (SMI).

[0129] The acquisition module 41 is also used to acquire and store the first baud rate and the second baud rate according to the interrupt number; wherein the first baud rate is used for the master device to configure the baud rate, and the second baud rate is used for the standby device to configure the baud rate;

[0130] Processing module 43 acquires the Basic Input / Output System (BIOS) information; based on the SMI interrupt number in the BIOS information, it configures the first baud rate in the memory into the register of the master device, and configures the second baud rate information in the memory into the register of the standby device to complete the device baud rate configuration operation.

[0131] In one possible implementation, the acquisition module 42 is specifically used for:

[0132] Based on the first preset mapping relationship, the offset address corresponding to the interrupt number is determined; wherein, the first preset mapping relationship represents the mapping relationship between the SMI interrupt number and the memory offset address;

[0133] The first and second baud rates are obtained and stored in the memory in the area corresponding to the offset address.

[0134] In one possible implementation, the processing module 42 is specifically used for:

[0135] When the storage of the first baud rate and the second baud rate is completed, a baud rate storage completion signal is generated;

[0136] Send the baud rate storage completion signal to the baseboard management controller (BMC);

[0137] The SMI mechanism is triggered by the BMC, and BIOS information is invoked.

[0138] In one possible implementation, the processing module 42 is specifically used for:

[0139] According to the second preset mapping relationship, the first register offset address in the register of the master device corresponding to the SMI interrupt number and the second register offset address in the register of the standby device corresponding to the SMI interrupt number are determined respectively; wherein, the second preset mapping relationship represents the mapping relationship between the SMI interrupt number and the first register offset address and the second register offset address respectively.

[0140] The first baud rate is stored in the area corresponding to the offset address of the first register, and the second baud rate is stored in the area corresponding to the offset address of the second register.

[0141] In one possible implementation, the method for configuring the device baud rate further includes:

[0142] Processing module 42 is also used to obtain the target device from the CPLD register of the complex programmable logic device in response to the device restart signal; the CPLD register is a register in the system used to store the startup information of the target device; the target device is a master device or a standby device that is starting up;

[0143] The acquisition module 41 is also used to acquire configuration information corresponding to the target device from the memory;

[0144] The processing module 42 is also used to determine the target baud rate used by the target device when performing serial port initialization based on the configuration information corresponding to the target device;

[0145] The processing module 42 is also used to initialize the serial port of the target device based on the target baud rate.

[0146] In one possible implementation, the target baud rate includes a default baud rate or a configured baud rate; after initializing the serial port of the target device based on the target baud rate, the method for configuring the device baud rate further includes:

[0147] Processing module 42 is also used to clear the configuration baud rate of the target device.

[0148] The apparatus provided in this application embodiment can be used to execute the determination method in any of the above embodiments. Its implementation principle and technical effect are similar, and will not be described again here.

[0149] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented in software via processing element calls, while others are implemented in hardware. Additionally, these modules can be fully or partially integrated together, or implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. During implementation, each step of the above method or each of the above modules can be completed through the integrated logic circuits in the hardware of the processor element or through software instructions.

[0150] Figure 5 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application, such as... Figure 5 As shown, the electronic device may include: a processor 51, a memory 52, and computer program instructions stored in the memory 52 and executable on the processor 51. When the processor 51 executes the computer program instructions, it implements the method provided in any of the foregoing embodiments.

[0151] Optionally, the various components of the electronic device can be connected via a system bus.

[0152] The memory 52 can be a separate storage unit or a storage unit integrated into the processor 51. The number of processors 51 can be one or more.

[0153] It should be understood that the processor 51 can be a Central Processing Unit (CPU), or other general-purpose processors 51, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor 51 can be a microprocessor 51, or any conventional processor 51. The steps of the method disclosed in this application can be directly manifested as being executed by the hardware processor 51, or being executed by a combination of hardware and software modules within the processor 51.

[0154] The system bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The system bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus. Memory 52 may include random access memory (RAM) 52, and may also include non-volatile memory (NVM) 52, such as at least one disk storage device 52.

[0155] All or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a readable memory 52. ​​When the program is executed, it performs the steps of the above method embodiments; and the aforementioned memory 52 (storage medium) includes: read-only memory 52 (ROM), RAM, flash memory 52, hard disk, solid-state hard disk, magnetic tape, floppy disk, optical disk, and any combination thereof.

[0156] The electronic device provided in this application embodiment can be used to execute the method provided in any of the above method embodiments. Its implementation principle and technical effect are similar, and will not be repeated here.

[0157] This application provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the computer to perform the above-described method.

[0158] The aforementioned computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory, electrically erasable programmable read-only memory, erasable programmable read-only memory, programmable read-only memory, read-only memory, magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0159] Optionally, a readable storage medium can be coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Alternatively, the readable storage medium can be an integral part of the processor. Both the processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components within the device.

[0160] This application also provides a computer program product, which includes a computer program stored in a computer-readable storage medium. At least one processor can read the computer program from the computer-readable storage medium, and the at least one processor can implement the above-described method when executing the computer program.

[0161] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for configuring the baud rate of a device, characterized in that, include: Obtain the baud rate configuration signal, which includes at least the interrupt number of the system to the system management interrupt (SMI); Based on the interrupt number, obtain and store the first baud rate and the second baud rate; wherein, the first baud rate is used by the master device to configure the baud rate, and the second baud rate is used by the standby device to configure the baud rate; Obtain Basic Input / Output System (BIOS) information; Based on the SMI interrupt number in the BIOS information, the first baud rate in the memory is configured into the register of the master device, and the second baud rate information in the memory is configured into the register of the standby device to complete the device baud rate configuration operation.

2. The method according to claim 1, characterized in that, The step of obtaining and storing the first baud rate and the second baud rate based on the interrupt number includes: Based on the first preset mapping relationship, the offset address corresponding to the interrupt number is determined; wherein, the first preset mapping relationship represents the mapping relationship between the SMI interrupt number and the memory offset address; The first baud rate and the second baud rate are obtained and stored in the memory in the region corresponding to the offset address.

3. The method according to claim 2, characterized in that, The acquisition of Basic Input / Output System (BIOS) information includes: When the first baud rate and the second baud rate are stored, the baud rate storage completion signal is generated; The baud rate storage completion signal is sent to the substrate management controller (BMC). The SMI mechanism is triggered by the BMC, and the BIOS information is invoked.

4. The method according to claim 1, characterized in that, The step of configuring the first baud rate in the memory to the register of the master device based on the interrupt number of the SMI in the BIOS information, and configuring the second baud rate information in the memory to the register of the standby device, includes: According to the second preset mapping relationship, the first register offset address in the register of the master device corresponding to the SMI interrupt number and the second register offset address in the register of the standby device corresponding to the SMI interrupt number are determined respectively; wherein, the second preset mapping relationship represents the mapping relationship between the SMI interrupt number and the first register offset address and the second register offset address respectively; The first baud rate is stored in the region corresponding to the offset address of the first register, and the second baud rate is stored in the region corresponding to the offset address of the second register.

5. The method according to claim 1, characterized in that, The method further includes: In response to a device restart signal, the target device is retrieved from the CPLD register of a complex programmable logic device; the CPLD register is a register in the system used to store startup information of the target device; the target device is either the primary device or the backup device that is starting up. Retrieve the configuration information corresponding to the target device from the memory; Based on the configuration information corresponding to the target device, determine the target baud rate used by the target device when performing serial port initialization; The target device is initialized with a serial port based on the target baud rate.

6. The method according to claim 5, characterized in that, The target baud rate includes a default baud rate or a configured baud rate; after initializing the serial port of the target device based on the target baud rate, the method further includes: Clear the configured baud rate of the target device.

7. A device for configuring baud rate, characterized in that, include: The acquisition module is used to acquire the baud rate configuration signal, wherein the baud rate configuration signal includes at least the interrupt number of the system to the system management interrupt (SMI); The acquisition module is further configured to acquire and store a first baud rate and a second baud rate based on the interrupt number; wherein the first baud rate is used by the master device to configure the baud rate, and the second baud rate is used by the standby device to configure the baud rate. The processing module acquires the Basic Input / Output System (BIOS) information; based on the interrupt number of the SMI in the BIOS information, it configures the first baud rate in the memory into the register of the master device, and configures the second baud rate information in the memory into the register of the standby device, so as to complete the device baud rate configuration operation.

8. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 6.

10. A computer program, characterized in that, The computer program includes a computer program stored in a computer-readable storage medium, which at least one processor can read from the computer-readable storage medium, and which, when executing the computer program, can implement the method described in any one of claims 1 to 6.

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