Separation gate IGBT structure and gate drive circuit thereof
By designing a separate gate IGBT structure and gate drive circuit, independent adjustment of current and voltage change rate during IGBT switching is achieved, optimizing switching losses and EMI noise, reducing on-state voltage drop and turn-off losses, and improving the optimization effect of switching waveform.
Patent Information
- Application Number
- CN202511478844.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-16
- Publication Date
- 2026-01-13
AI Technical Summary
In existing IGBT structures, the depth of the trench gate affects the on-state voltage drop and the capacitance size, which cannot be adjusted independently. This makes it difficult to optimize the rate of change of current and voltage during switching. Furthermore, the adjustment of the capacitor and resistor in the gate drive circuit cannot be controlled independently, resulting in increased EMI noise and switching losses.
The IGBT adopts a split-gate structure, which includes a control gate and a modulation gate. The capacitance and current change rates are adjusted by different driving chips and loop resistors. The capacitor connection is optimized through structural design and electric field shielding effect to achieve independent adjustment of current and voltage change rates.
Independent adjustment of current and voltage change rate during IGBT switching is achieved, optimizing switching losses and EMI noise, reducing on-state voltage drop and turn-off losses, and improving the optimization effect of switching waveform.
Smart Images
Figure CN121335120A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the technical field, specifically relating to a split-gate IGBT structure and its gate driving circuit. Background Technology
[0002] As a composite power semiconductor device, the Insulated Gate Bipolar Transistor (IGBT) combines the advantages of high input impedance of the Metal-Oxide-Semiconductor Field-Effect Transistor (MOFET) and low on-state voltage drop of the Bipolar Transistor. Since its invention in the 1980s, it has been widely used in variable frequency home appliances, new energy, electric vehicles, smart grids, and other fields.
[0003] IGBTs are bipolar devices that inject electrons and holes into the N-type drift region from the front and back sides, respectively, when turned on. Higher front-side electron injection efficiency results in a higher carrier concentration (electrons and holes) near the front side during conduction, leading to a lower on-state voltage drop. Employing a trench gate and introducing an N-type layer (carrier storage layer) with a higher doping concentration than the N-type drift region beneath the P-type base of the IGBT can increase the carrier concentration on the front side, further reducing the on-state voltage drop. Figure 1 A cross-sectional view of a prior art IGBT employing this scheme is presented. However, the carrier concentration is proportional to the depth of the trench below the P-base region, and the decrease in on-state voltage drop leads to an increase in gate and collector capacitance, thereby resulting in a decrease in the rate of change of Vce voltage during switching.
[0004] Using a smaller gate resistor Rg in the IGBT gate drive circuit can accelerate the turn-on speed and reduce turn-on losses Eon. On the other hand, increased switching speed generates significant electromagnetic interference (EMI) noise. EMI is mainly caused by oscillations due to parasitic inductance, capacitance, and resistance (LCR) parameters in the circuit. Wire bonding of the IGBT chip electrodes and copper traces on the circuit board generate parasitic inductance and resistance, and parasitic capacitance exists between the IGBT chip electrodes. Excessively high dVce / dt and dIc / dt during IGBT turn-on and turn-off will cause overcharging of voltage and current in the LCR circuit. In addition to adjusting the turn-on and turn-off gate resistors Rgon and Rgoff, the switching speed can be adjusted at the same gate resistance by adjusting the size and ratio of the capacitances of different electrodes of the IGBT chip. Figure 1A schematic diagram of an IGBT employing a trench gate structure in the prior art is shown. The diagram shows N+ regions on both sides of the active gate trench, the emitter trench connected to the emitter potential, and no N+ regions on either side of the redundant gate trench. By adjusting the ratio of the active gate trench, emitter trench, and redundant gate trench, the magnitude and ratio of the IGBT chip's input capacitance, output capacitance, and reverse capacitance can be adjusted, thereby regulating dVce / dt and dIc / dt during the turn-on and turn-off processes.
[0005] Figure 2 A schematic diagram of the existing gate electrode driving circuit is given. The driving chip U1 is connected to the gate electrode through Rgon and Rgoff. Since the IGBT has parasitic capacitances Cge, Cgc and Cce between the Gate and Emitter, the Gate and Collector, and the Collector and Emitter, the driving chip U1 will charge and discharge Cge and Cgc during the turn-on and turn-off processes.
[0006] While existing technologies have enabled the adjustment of IGBT capacitors Cge and Cgc, they still have the following drawbacks: 1. The depth of the trench gate affects both the on-state voltage drop and capacitance of the IGBT. Increasing the trench depth can reduce the front-side carrier concentration, but it leads to an increase in Cgc capacitance, which in turn increases the turn-on and turn-off losses.
[0007] 2. The values of capacitors Cge and Cgc are both affected by the IGBT structural parameters, and their values cannot be adjusted independently.
[0008] 3. In the gate drive circuit, the gate resistor Rg (Rgon or Rgoff) charges both Cge and Cgc simultaneously, and these two resistors affect dIc / dt and dVce / dt during the turn-on and turn-off processes, respectively. Therefore, it is impossible to independently control the charging and discharging of Cge and Cgc. Summary of the Invention
[0009] The purpose of this invention is to provide a discrete gate IGBT structure and its gate driving circuit.
[0010] This application provides a split-gate IGBT structure, including: The layers arranged from top to bottom are: Emitter electrode, N+ region, P base layer, N layer, N-drift layer, Nbuffer layer, P collector layer, and Collector electrode. The aG control gate trench is connected to the control gate electrode aG; the aG control gate trench extends from the upper surface of the P base layer to the N layer; the aG control gate trench has a sidewall oxide layer, a top oxide layer, and a bottom oxide layer on its two sides, top surface, and bottom surface, respectively; the N+ region is located on one or both sides of the upper end of the aG control gate trench. Two mG modulation gate trenches are connected to the modulation gate electrode mG; the two mG modulation gate trenches are located on both sides of the aG control gate trench and are spaced apart from the aG control gate trench; the mG modulation gate trenches are partially located within the N layer; mG sidewall oxide layer, mG top oxide layer and mG bottom oxide layer are respectively provided on the sides, top surface and bottom surface of the mG modulation gate trenches.
[0011] In one embodiment of this application, the depth of the aG control gate trench is not less than 1.1 times the depth of the PN junction formed by the P base layer and the N layer.
[0012] In one embodiment of this application, the thickness of the top oxide layer of aG is greater than the thickness of the sidewall oxide layer and the bottom oxide layer of aG; The thickness of the oxide layer on the bottom surface of aG is not less than 60% of the thickness of the oxide layer on the sidewall of aG; The thickness of the oxide layer on the aG sidewall is 500 angstroms to 1500 angstroms.
[0013] In one embodiment of this application, the thickness of the aG sidewall oxide layer is 1000 angstroms.
[0014] In one embodiment of this application, the thickness of the oxide layer on the bottom surface of aG is not less than 150% of the thickness of the oxide layer on the sidewall of aG.
[0015] In one embodiment of this application, the width of the mG modulation gate trench is not less than the width of the aG control gate trench; The thickness of the mG sidewall oxide layer is less than the thickness of the mG top oxide layer and the mG bottom oxide layer; The thickness of the oxide layer on the top surface of the mG is greater than 150% of the thickness of the oxide layer on the sidewall of the mG.
[0016] In one embodiment of this application, the overlap thickness between the upper end of the mG modulation gate trench and the P base layer is less than 10% of the thickness of the P base layer; the overlap thickness between the lower end of the mG modulation gate trench and the N-drift layer is 0% - 30% of the thickness of the N-drift layer.
[0017] In one embodiment of this application, the upper end of the mG modulation gate trench extends into the P base layer, and the depth of the extension into the P base layer is less than 10% of the thickness of the P base layer; The lower end of the mG modulation gate trench extends into the N-drift layer, and the depth of the extension into the N-drift layer is 30% to 100% of the thickness of the N-drift layer; The thickness of the oxide layer on the sidewall of the mG is less than the thickness of the oxide layer on the bottom surface of the mG and the oxide layer on the top surface of the mG.
[0018] In one embodiment of this application, the upper end of the mG modulation gate trench extends to the upper surface of the P base layer, and the lower end extends into the N-drift layer.
[0019] In one embodiment of this application, the mG modulation gate trench includes an upper trench and a lower trench, and each trench has an upper electrode and a lower electrode inside; wherein the upper electrode 104 is connected to the Emitter electrode, and the lower electrode is connected to the modulation gate electrode mG; The upper end of the upper trench extends to the upper surface of the P base layer; The lower trench extends through the N layer to the N-drift layer; An mG intermediate oxide layer is provided between the lower end of the upper trench and the upper end of the lower trench; The thickness of the intermediate oxide layer of mG is greater than the thickness of the sidewall oxide layer of mG.
[0020] Accordingly, this application provides a gate driving circuit applied to a split-gate IGBT structure having a control gate electrode aG and a modulation gate electrode mG, comprising: a driver chip U1 and a driver chip U2; wherein The driver chip U1 includes: The first input side IN1, the first power supply terminal VDD1, and the first common reference terminal COM1; and On the first output side, the gate electrode aG is connected to the control gate electrode through parallel gate resistors Rgon1 and Rgoff1. The driver chip U2 includes: The second input side IN2, the second power supply terminal VDD2, and the second common reference terminal COM2; and On the second output side, the gate electrode mG is connected to the modulation gate electrode mG through parallel gate resistors Rgon2 and Rgoff2.
[0021] In one embodiment of this application, the first output side includes: an output terminal OUTH1 and an output terminal OUTL1, which output high level and low level respectively; the output terminal OUTH1 is connected to the control gate electrode aG through a gate resistor Rgon1, and the output terminal OUTL1 is connected to the control gate electrode aG through a gate resistor Rgoff1. The second output side includes: an output terminal OUTH2 and an output terminal OUTL2, which output high level and low level respectively; the output terminal OUTH2 is connected to the control gate electrode aG through the gate resistor Rgon2, and the output terminal OUTL2 is connected to the control gate electrode aG through the gate resistor Rgoff2.
[0022] In one embodiment of this application, the first output side is connected to the gate resistor Rgon1 and the gate resistor Rgoff1 respectively through diodes DA1 and DB1 with opposite directions; The second output side is connected to the gate resistor Rgon2 and the gate resistor Rgoff2 respectively through diodes DA2 and DB2 with opposite directions.
[0023] In one embodiment of this application, the second input side IN2 of the driver chip U2 is connected to the second power supply terminal VDD2.
[0024] In one embodiment of this application, the second input side IN2 of the driver chip U2 is connected to the second common reference terminal COM2.
[0025] The beneficial effects of this invention are: Unlike existing technologies, this application provides a split-gate IGBT structure and its gate drive circuit, which enables independent adjustment of the current change rate dIc / dt and voltage change rate dVce / dt during IGBT turn-on and turn-off. Through structural design and electric field shielding effect, the main parts of capacitors Cge and Cgc are connected to the control gate aG and modulation gate mG, respectively, thereby enabling separate driving of Cge and Cgc, thus optimizing the device's switching losses and EMI noise. By controlling the depth of the modulation gate mG in the N-drift layer, a thinner drift region with a higher doping concentration can be used to achieve the same breakdown voltage, thereby simultaneously reducing its on-state voltage drop and turn-off losses. The adjustment of the current change rate dIc / dt and voltage change rate dVce / dt is achieved through different drive chips and the gate resistance of the circuit, thus optimizing the IGBT's switching waveform. Regarding the trade-off between turn-on losses and EMI noise, given a clear EMI noise source (dVce / dt or dIc / dt), the turn-on loss can be further optimized by adjusting another change rate parameter.
[0026] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.
[0027] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0028] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0029] Figure 1 This is a cross-sectional view of an IGBT using a trench gate and an N-layer carrier storage layer in existing technology; Figure 2 This is a schematic diagram of an existing IGBT gate drive circuit; Figure 3 This is a schematic diagram of the planar layout of a split-gate IGBT structure according to a preferred embodiment of the present invention; Figure 4 This is a cross-sectional schematic diagram of a split-gate IGBT structure according to a preferred embodiment of the present invention; Figure 5 This is a cross-sectional schematic diagram of a split-gate IGBT structure according to another preferred embodiment of the present invention; Figure 6 This is a cross-sectional schematic diagram of a split-gate IGBT structure according to another preferred embodiment of the present invention; Figure 7 This is a cross-sectional schematic diagram of a split-gate IGBT structure according to another preferred embodiment of the present invention; Figure 8 This is a schematic diagram of a gate driving circuit according to a preferred embodiment of the present invention; Figure 9 This is a timing diagram of the gate drive signals IN2 / mG and IN1 / aG according to a preferred embodiment of the present invention; Figure 10 This is a schematic diagram of a gate driving circuit according to another preferred embodiment of the present invention; Figure 11 This is a schematic diagram of a gate driving circuit according to another preferred embodiment of the present invention; Figure 12 This is a schematic diagram of a gate drive circuit according to another preferred embodiment of the present invention.
[0030] In the picture: Emitter electrode 1, P base layer 2, N layer 3, N-drift layer 4, N buffer layer 5, P collector layer 6, Collector electrode 7, aG control gate trench 8, aG sidewall oxide layer 81, aG top oxide layer 82, aG bottom oxide layer 83, N+ region 9, mG modulation gate trench 10, mG sidewall oxide layer 101, mG top oxide layer 102, mG bottom oxide layer 103, upper trench 104, lower trench 105, mG intermediate oxide layer 106. Detailed Implementation
[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] Taking the IGBT turn-on process as an example, this paper analyzes the influencing factors of the current change rate dIc / dt and voltage change rate dVce / dt during the turn-on process. An IGBT can be equivalently represented as a front-side MOSFET driving a vertical PNP transistor, where the channel electron current when the MOSFET is turned on serves as the base current of the PNP transistor. Ignoring stray inductance in the circuit, the expressions for dIc / dt and dVce / dt during IGBT turn-on are as follows: Among them, the gate drive voltage source outputs a high level of V. g_in The gate drive resistance is R. g The voltage between the Gate and Emitter during IGBT turn-on is V. ge g m V represents the transconductance of the MOS channel electron current corresponding to the IGBT. th C is the threshold voltage of the IGBT. ge and C gc These represent the capacitances between the Gate and Emitter, and between the Gate and Collector of the IGBT, respectively, α. PNP This represents the common-base current gain of the vertical PNP transistor. From the expression above, it can be seen that dI... c / dt and R g C ge The product of is inversely proportional, while dV ce / dt and R g C gc The product is inversely proportional.
[0033] Figure 2 In the existing IGBT driver circuit, the driver chip U1 includes a power supply terminal VDD and a common reference terminal COM. The input terminal IN is connected to the main controller to receive control signals from the main controller. The common reference terminal COM and the IGBT Emitter are shorted together as a common potential. The output terminals OTH and OUTL are high-level and low-level output terminals, respectively, connected to the gate resistors Rgon and Rgoff. In some driver chips, OTH and OUTL are connected together and marked as the OUT terminal. Based on the analysis of the turn-on process dIc / dt and dVce / dt above, both dIc / dt and dVce / dt are controlled by the same turn-on resistor Rgon, and the current flowing through capacitors Cge and Cgc is inversely proportional to their capacitance values. Since the values of capacitors Cge and Cgc are closely related to the IGBT structure and change with the applied voltage Vce, it is impossible to independently optimize dIc / dt and dVce / dt in this driver circuit.
[0034] This application provides a split-gate IGBT structure and its gate driving circuit, which are described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, in the following embodiments, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.
[0035] See Figure 8 One embodiment of this application provides a gate driving circuit. In this embodiment, the gate of the IGBT is divided into a control gate electrode aG and a modulation gate electrode mG. For ease of understanding, Figure 3 A schematic planar layout of a split-gate IGBT structure according to one embodiment is provided. The collector electrode is located on the back side of the chip, while the emitter electrode (Pad), control gate aG, and modulation gate mG electrode (Pad) are all located on the front side of the chip. aG, mG, and the emitter are all connected to external circuitry via wire bonding. Figure 8In the gate structure, the Cge capacitor, corresponding to the existing structure, is connected between aG and the Emitter and is labeled Cage in the figure; the Cgc capacitor, corresponding to the existing structure, is connected between mG and the Emitter and is labeled Cmgc in the figure. Through chip structure optimization and planar layout optimization, the embodiments of the present invention propose a split-gate IGBT structure, corresponding to the existing structure where the gate electrode is divided into a control gate electrode aG and a modulation gate electrode mG, which separately control Cage and Cmgc. The control gate electrode aG and the modulation gate electrode mG are driven by driver chips U1 and U2, respectively, and their corresponding turn-on / turn-off gate resistors are Rgon1 / Rgoff1 and Rgon2 / Rgoff2, respectively. It should be noted that the values of Rgon1 / Rgoff1 and Rgon2 / Rgoff2 can be the same or different.
[0036] In some embodiments, U1 and U2 can be controlled by control signals IN1 and IN2, respectively.
[0037] In the circuit of this invention, the turn-on dIc / dt and dVce / dt of the IGBT are adjusted by the product of Rgon1*Cage and Rgon2*Cmgc, respectively, achieving independent control of turn-on dIc / dt and dVce / dt. A similar analysis can be performed on dIc / dt and dVce / dt during the IGBT turn-off process of this invention, except that the control resistors are replaced by Rgoff1 and Rgoff2, respectively.
[0038] It should be noted that in the device of this invention, there are also corresponding distributed capacitances between the control gate electrode aG and the Collector electrode, between the modulation gate electrode mG and the Emitter electrode, and between the control gate electrode aG and the modulation gate electrode mG. As long as their influence on the device's turn-on and turn-off processes can be ensured to be negligible, the device can still be used. Figure 8 We will analyze its characteristics using the driving circuit.
[0039] See Figure 9 During the turn-on process, IN1 turns on before IN2, with a delay difference of Tm(on); during the turn-off process, IN1 turns off after IN2, with a delay difference of Tm(off). Generally, the IGBT's turn-on voltage is 15V, and the turn-off voltage is 0V or a negative gate voltage (minimum -15V). The minimum values of Tm(on) and Tm(off) are both 0, in which case the timing of IN1 and IN2 is synchronized. The maximum values of Tm(on) and Tm(off) are generally less than 10µs, typically less than 1µs. By setting Tm(on) and Tm(off) to different values, the modulation gate mG can be charged and discharged after the IGBT turns on or before it turns off, thereby optimizing its switching losses.
[0040] See Figure 8 In one embodiment, the driver chip U1 includes: a first input side IN1, a first power supply terminal VDD1, and a first common reference terminal COM1; and a first output side, which is connected to the control gate electrode aG through parallel gate resistors Rgon1 and Rgoff1; the driver chip U2 includes: a second input side IN2, a second power supply terminal VDD2, and a second common reference terminal COM2; and a second output side, which is connected to the modulation gate electrode mG through parallel gate resistors Rgon2 and Rgoff2.
[0041] In this embodiment, the first output side includes: an output terminal OUTH1 and an output terminal OUTL1, which output high level and low level respectively; the output terminal OUTH1 is connected to the control gate electrode aG through a gate resistor Rgon1, and the output terminal OUTL1 is connected to the control gate electrode aG through a gate resistor Rgoff1; the second output side includes: an output terminal OUTH2 and an output terminal OUTL2, which output high level and low level respectively; the output terminal OUTH2 is connected to the control gate electrode aG through a gate resistor Rgon2, and the output terminal OUTL2 is connected to the control gate electrode aG through a gate resistor Rgoff2.
[0042] See Figure 10 In one embodiment, the first output side is connected to the gate resistor Rgon1 and the gate resistor Rgoff1 via diodes DA1 and DB1 with opposite directions, respectively; the second output side is connected to the gate resistor Rgon2 and the gate resistor Rgoff2 via diodes DA2 and DB2 with opposite directions, respectively.
[0043] In this embodiment, the first output side is OUT1, and the second output side is OUT2. For U1, the turn-on and turn-off resistors can be individually adjusted by connecting diodes DA1 and DB1 in series with the turn-on resistor Rgon1 and turn-off resistor Rgoff1, respectively. Optionally, the anode of DA1 and the cathode of DB1 are connected to OUT1, ensuring unidirectional current flow in their respective branches. Optionally, DA1 and DB1 can be Schottky diodes, typically surface-mount silicon Schottky diodes with a voltage of 30V or higher and a current of 1A or higher. A similar analysis applies to U2.
[0044] See Figure 11 In one embodiment, the second input side IN2 of the driver chip U2 is connected to the second power supply terminal VDD2 to ensure that its output OUTH2 is high level and OUTL2 is in a high impedance state.
[0045] In this embodiment, the modulation gate electrode mG is always at a high potential (e.g., 15V) in steady state. During the turn-on and turn-off transients, the influence of the Collector voltage change on mG can be quickly responded to by Cmgc and Rgon2, avoiding any impact on the IGBT switching waveform.
[0046] See Figure 12 In one embodiment, the second input side IN2 of the driver chip U2 is connected to the second common reference terminal COM2, ensuring that its output OTH2 is in a high-impedance state and OUTL2 is at a low level. In this circuit, the modulation gate electrode mG is always at a low potential (e.g., 0V) in the steady state. During the turn-on and turn-off transients, the influence of the Collector voltage change on mG can be quickly responded to by Cmgc and Rgoff2, avoiding any impact on the IGBT switching waveform.
[0047] Further, see Figure 3 In one embodiment of the split-gate IGBT structure of this application, the Collector electrode is located on the back side of the chip, while the Emitter electrode Pad, the Control Gate electrode aG Pad, and the Modulation Gate electrode mG Pad are all located on the front side of the chip. The IGBT chip includes a cell region and a terminal region surrounding the cell region. Since the terminal region does not participate in conduction when it is in the on state, this application mainly discusses the structure of the cell region.
[0048] See Figure 4 In one embodiment of this application, the split-gate IGBT structure includes: The following layers are arranged from top to bottom: Emitter electrode 1, N+ region 9, P base layer 2, N layer layer 3, N- drift layer 4, N buffer layer 5, P collector layer 6, and Collector electrode 7. The aG control gate trench 8 is connected to the control gate electrode aG; the aG control gate trench 8 extends from the upper surface of the P base layer 2 to the N layer 3; the aG control gate trench 8 has an aG sidewall oxide layer 81, an aG top oxide layer 82, and an aG bottom oxide layer 83 respectively on its two sides, top surface, and bottom surface; the N+ region 9 is located on one or both sides of the upper end of the aG control gate trench 8; Two mG modulation gate trenches 10 are connected to the modulation gate electrode mG; the two mG modulation gate trenches 10 are located on both sides of the aG control gate trench 8 and are spaced apart from the aG control gate trench 8; the mG modulation gate trenches 10 are partially located within the N layer 3; the mG modulation gate trenches 10 are provided with mG sidewall oxide layer 101, mG top surface oxide layer 102 and mG bottom surface oxide layer 103 on both sides, top surface and bottom surface respectively.
[0049] In this embodiment, on the silicon substrate region, the P collector, N buffer / N-drift / N-layer, and P base on the back side form a PNP transistor, where the P collector is the emitter of the PNP transistor, the N buffer / N-drift / N-layer is the base of the PNP transistor, and the P base is the collector of the PNP transistor. On the front side, the N+, P base, N-layer, and aG trench gate form a MOSFET, corresponding to the source, substrate, drain, and gate of the MOSFET, respectively.
[0050] In this embodiment, the function of the aG control gate trench 8 is to control the gate and control the conduction and turn-off of the MOSFET channel electronic current.
[0051] Optionally, the depth of the aG control gate trench 8 is not less than 1.1 times the depth of the PN junction formed by the P base layer 2 and the N layer 3.
[0052] Optionally, the thicknesses of the aG sidewall oxide layer 81, the aG top oxide layer 82, and the aG bottom oxide layer 83 can be the same or different.
[0053] In one embodiment, optionally, the thickness of the top oxide layer 82 of aG is greater than the thickness of the sidewall oxide layer 81 of aG and the bottom oxide layer 83 of aG.
[0054] Optionally, the top oxide layer 82 of aG can be formed by deposition, while the bottom oxide layer 83 of aG and the sidewall oxide layer 81 of aG can be formed by oxidation. In one embodiment, oxide layers are grown simultaneously on the sidewalls and bottom by thermal oxidation, and the thickness of the bottom oxide layer 83 of aG is less than that of the sidewall oxide layer 81 of aG, but not less than 60% of the thickness of the sidewall oxide layer 81 of aG. In another embodiment, the thickness of the bottom oxide layer 83 of aG can be increased by sidewall masking and local oxidation, and is greater than that of the sidewall oxide layer 81 of aG; optionally, the thickness of the bottom oxide layer 83 of aG is not less than 150% of the thickness of the sidewall oxide layer 81 of aG. The aG control gate trench 8, the aG sidewall oxide layer 81, the aG top oxide layer 82, and the emitter electrode form a capacitor Cage. The aG control gate trench 8, the aG bottom oxide layer 83, the semiconductor region below them, and the collector electrode have a parasitic capacitance Cagc. As explained above, the value of Cagc should be as small as possible (achieved by increasing the thickness of the aG bottom oxide layer 83).
[0055] In one embodiment, the thickness of the aG sidewall oxide layer 81 is related to the threshold voltage. Optionally, the thickness of the aG sidewall oxide layer 81 is 500 angstroms to 1500 angstroms, preferably around 1000 angstroms.
[0056] In this embodiment, an mG modulation gate trench 10 is used to shield the aG control gate trench 8, thereby reducing Cagc. The width of the mG modulation gate trench 10 is greater than or equal to the width of the aG control gate trench 8, and the spacing is determined by electrical characteristics. In some embodiments, by controlling the width and spacing of the mG modulation gate trench 10, it can be ensured that when the Collector applies a reverse bias voltage relative to the mG modulation gate to reach the critical pinch-off voltage, the N-layer depletion regions caused by adjacent mG modulation gates connect together, thereby shielding the influence of the Collector electrode on the aG control gate. The critical pinch-off voltage is generally less than 20V, typically less than 2V. Preferably, the pinch-off voltage is between 0.5V and 1.5V.
[0057] Optionally, the thickness of the mG sidewall oxide layer 101 is less than the thickness of the mG top oxide layer 102 and the mG bottom oxide layer 103. By thickening the mG top oxide layer 102 in the overlapping region between the top of the mG modulation gate trench 10 and the P base, the parasitic capacitance Cmge between the mG modulation gate trench 10 and the emitter electrode can be reduced. Preferably, the thickness of the mG top oxide layer 102 is greater than 150% of the thickness of the mG sidewall oxide layer 101.
[0058] See Figure 4 The overlap thickness between the upper end of the mG modulation gate trench 10 and the P base layer 2 is less than 10% of the thickness of the P base layer 2; the overlap thickness between the lower end of the mG modulation gate trench 10 and the N-drift layer 4 is 0%-30% of the thickness of the N-drift layer 4.
[0059] See Figure 5 In one embodiment, compared to Figure 4 The main structural difference lies in the location and depth of the mG modulation gate trench 10. The N-drift layer, as the main breakdown voltage layer during blocking, has the lowest doping concentration. The doping concentration of the N-drift layer is primarily limited by the breakdown voltage; the higher the breakdown voltage, the lower the doping concentration, and the thicker the layer. On the other hand, to maintain a constant on-state voltage drop during conduction, a large number of excess carriers need to be injected into the N-drift layer. These excess carriers need to be removed during turn-off, thus increasing turn-off losses. For a 1200V IGBT, a typical N-drift layer is between 80µm and 120µm, with a doping concentration of 1E14cm⁻¹. -3 The following is an example of the excess carrier concentration during conduction at 1E16 cm⁻¹. -3The use of mG modulation gate trenches that penetrate both the N-layer and the N-drift layer can increase the breakdown voltage of IGBT devices under the same N-drift layer thickness and doping concentration, thereby optimizing their conduction or turn-off characteristics.
[0060] Specifically, the upper end of the mG modulation gate trench 10 extends into the P base layer 2, and the depth of the extension into the P base layer 2 is less than 10% of the thickness of the P base layer 2; the lower end of the mG modulation gate trench 10 extends into the N-drift layer 4, and the depth of the extension into the N-drift layer 4 is 30% to 100% of the thickness of the N-drift layer 4.
[0061] In the blocking state, the potential of the mG modulation gate trench 10 is 0, therefore the bottom oxide layer 103 of the mG must withstand part or even all of the breakdown voltage. Optionally, the thickness of the mG sidewall oxide layer 101 is less than the thickness of the bottom oxide layer 103 and the top oxide layer 102 of the mG.
[0062] See Figure 6 In one embodiment, compared to Figure 4 The upper end of the mG modulation gate trench 10 extends to the upper surface of the P base layer 2, that is, the mG modulation gate trench 10 extends to the front side of the chip. This structure has a simple process, but its disadvantage is that the parasitic capacitance Cmge is relatively large.
[0063] See Figure 7 In one embodiment, compared to Figure 4 The upper end of the mG modulation gate trench 10 extends to the upper surface of the P base layer 2, that is, the mG modulation gate trench 10 extends to the front side of the chip. Compared to Figure 6The mG modulation gate trench 10 comprises an upper trench 104 and a lower trench 105, each containing an upper electrode and a lower electrode. The upper electrode is connected to the emitter electrode 1, and the lower electrode is connected to the modulation gate electrode mG. The upper end of the upper trench 104 extends to the upper surface of the P base layer 2, and the lower trench 105 extends through the N layer 3 to the N-drift layer 4. The lower trench 105 is connected to the modulation gate electrode, and the upper trench 104 is connected to the emitter electrode. An mG intermediate oxide layer 106 is disposed between the lower end of the upper trench 104 and the upper end of the lower trench 105. By connecting the electrode of the upper trench 104 to the emitter, the corresponding Cmge capacitance can be canceled out. In the lower trench 105, the intermediate mG oxide layer 106 and the upper emitter electrode also form a Cmge capacitor. To avoid the influence of this capacitor, the thickness of the intermediate mG oxide layer 106 at the top of the lower trench 105 is greater than the thickness of the mG sidewall oxide layer 101. Optionally, the thickness of the intermediate mG oxide layer 106 is more than 150% of the thickness of the mG sidewall oxide layer 101.
[0064] In summary, this invention proposes a split-gate IGBT device structure and driving circuit, enabling independent adjustment of the current change rate dIc / dt and voltage change rate dVce / dt during IGBT turn-on and turn-off. In existing driving circuits, the adjustment of the current change rate dIc / dt and voltage change rate dVce / dt can only be achieved through a common gate resistor in the driving circuit; however, in this invention, the adjustment of the current change rate dIc / dt and voltage change rate dVce / dt is achieved through different driving chips and the Rg of the circuit, thus optimizing the IGBT switching waveform. Regarding the trade-off between turn-on loss and EMI noise, given a clear EMI noise source (dVce / dt or dIc / dt), the turn-on loss can be further optimized by adjusting the other change rate parameter. This invention proposes a split-gate IGBT device structure. Through structural design and electric field shielding effects, the main parts of capacitors Cge and Cgc are connected to the control gate aG and modulation gate mG, respectively, thereby enabling separate driving of Cge and Cgc and optimizing the device's switching losses and EMI noise. In this invention, by controlling the depth of the modulation gate mG in the N-drift layer, a thinner drift region with a higher doping concentration can be used to achieve the same breakdown voltage, thereby simultaneously reducing its on-state voltage drop and turn-off losses.
[0065] It should be noted that all the devices (parts whose specific structures are not specified) selected in this application are general standard parts or parts known to those skilled in the art, and their structures and principles can be known to those skilled in the art through technical manuals or conventional experimental methods.
[0066] In the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.
[0067] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0068] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification.
Claims
1. A split-gate IGBT structure, characterized in that, include: The following layers are arranged from top to bottom: Emitter electrode (1), N+ region (9), P base layer (2), N layer layer (3), N-drift layer (4), N buffer layer (5), P collector layer (6) and Collector electrode (7). The aG control gate trench (8) is connected to the control gate electrode aG; the aG control gate trench (8) extends from the upper surface of the P base layer (2) to the N layer (3); the aG control gate trench (8) is provided with aG sidewall oxide layer (81), aG top surface oxide layer (82) and aG bottom surface oxide layer (83) on its two sides, top surface and bottom surface respectively; the N+ region (9) is located on one or both sides of the upper end of the aG control gate trench (8); Two mG modulation gate trenches (10) are connected to the modulation gate electrode mG; the two mG modulation gate trenches (10) are located on both sides of the aG control gate trench (8) and are spaced apart from the aG control gate trench (8); the mG modulation gate trenches (10) are partially located in the Nlayer layer (3); the mG modulation gate trenches (10) are provided with mG sidewall oxide layer (101), mG top surface oxide layer (102) and mG bottom surface oxide layer (103) on both sides, top surface and bottom surface respectively.
2. The split-gate IGBT structure according to claim 1, characterized in that, The depth of the aG control gate trench (8) is not less than 1.1 times the depth of the PN junction formed by the P base layer (2) and the N layer layer (3).
3. The split-gate IGBT structure according to claim 1, characterized in that, The thickness of the top oxide layer (82) of aG is greater than the thickness of the sidewall oxide layer (81) and the bottom oxide layer (83) of aG; The thickness of the bottom oxide layer (83) of aG is not less than 60% of the thickness of the sidewall oxide layer (81) of aG; The thickness of the aG sidewall oxide layer (81) is 500 angstroms to 1500 angstroms.
4. The split-gate IGBT structure according to claim 3, characterized in that, The thickness of the bottom oxide layer (83) of aG is not less than 150% of the thickness of the sidewall oxide layer (81) of aG.
5. The split-gate IGBT structure according to claim 1, characterized in that, The width of the mG modulation gate trench (10) is not less than the width of the aG control gate trench (8); The thickness of the mG sidewall oxide layer (101) is less than the thickness of the mG top oxide layer (102) and the mG bottom oxide layer (103); The thickness of the top oxide layer (102) of the mG is greater than 150% of the thickness of the sidewall oxide layer (101) of the mG.
6. The split-gate IGBT structure according to claim 1, characterized in that, The overlap thickness between the upper end of the mG modulation gate trench (10) and the P base layer (2) is less than 10% of the thickness of the P base layer (2); The overlap thickness between the lower end of the mG modulation gate trench (10) and the N-drift layer (4) is 0% - 30% of the thickness of the N-drift layer (4).
7. The split-gate IGBT structure according to claim 1, characterized in that, The upper end of the mG modulation gate trench (10) extends into the P base layer (2), and the depth of the extension into the P base layer (2) is less than 10% of the thickness of the P base layer (2); The lower end of the mG modulation gate trench (10) extends into the N-drift layer (4), and the depth of the extension into the N-drift layer (4) is 30% to 100% of the thickness of the N-drift layer (4); The thickness of the mG sidewall oxide layer (101) is less than the thickness of the mG bottom oxide layer (103) and the mG top oxide layer (102).
8. The split-gate IGBT structure according to claim 1, characterized in that, The upper end of the mG modulation gate trench (10) extends to the upper surface of the P base layer (2), and the lower end extends into the N-drift layer (4).
9. The split-gate IGBT structure according to claim 1, characterized in that, The mG modulation gate trench (10) includes an upper trench (104) and a lower trench (105), and each trench has an upper electrode and a lower electrode inside; wherein the upper electrode is connected to the Emitter electrode (1); and the lower electrode is connected to the modulation gate electrode mG. The upper end of the upper trench (104) extends to the upper surface of the P base layer (2); The lower trench (105) extends through the N layer (3) to the N-drift layer (4); An mG intermediate oxide layer (106) is provided between the lower end of the upper trench (104) and the upper end of the lower trench (105). The thickness of the mG intermediate oxide layer (106) is greater than the thickness of the mG sidewall oxide layer (101).
10. A gate driving circuit applied to a split-gate IGBT structure having a control gate electrode aG and a modulation gate electrode mG, characterized in that, include: Driver chip U1 and driver chip U2; in The driver chip U1 includes: The first input side IN1, the first power supply terminal VDD1, and the first common reference terminal COM1; and On the first output side, the gate electrode aG is connected to the control gate electrode through parallel gate resistors Rgon1 and Rgoff1. The driver chip U2 includes: The second input side IN2, the second power supply terminal VDD2, and the second common reference terminal COM2; and On the second output side, the gate electrode mG is connected to the modulation gate electrode mG through parallel gate resistors Rgon2 and Rgoff2.
11. The gate driving circuit according to claim 10, characterized in that, The first output side includes: an output terminal OUTH1 and an output terminal OUTL1, which output high level and low level respectively; the output terminal OUTH1 is connected to the control gate electrode aG through the gate resistor Rgon1, and the output terminal OUTL1 is connected to the control gate electrode aG through the gate resistor Rgoff1. The second output side includes: an output terminal OUTH2 and an output terminal OUTL2, which output high level and low level respectively; the output terminal OUTH2 is connected to the control gate electrode aG through the gate resistor Rgon2, and the output terminal OUTL2 is connected to the control gate electrode aG through the gate resistor Rgoff2.
12. The gate driving circuit according to claim 10, characterized in that, The first output side is connected to the gate resistor Rgon1 and the gate resistor Rgoff1 respectively through diodes DA1 and DB1 with opposite directions; The second output side is connected to the gate resistor Rgon2 and the gate resistor Rgoff2 respectively through diodes DA2 and DB2 with opposite directions.
13. The gate driving circuit according to claim 11, characterized in that, The second input side IN2 of the driver chip U2 is connected to the second power supply terminal VDD2.
14. The gate driving circuit according to claim 11, characterized in that, The second input side IN2 of the driver chip U2 is connected to the second common reference terminal COM2.