Integrated circuit device and method of manufacturing integrated circuit

Abstract

An integrated circuit device with a CFET device includes high cells in a first row and low cells in a second row. The integrated circuit device also includes one or more self-aligned vertical interconnects in the first row of high cells. Each self-aligned vertical interconnect is at least partially embedded in the side recess. The side recess has a boundary surface conformally coated with an insulating material that terminates the at least one gate conductor that intersects the active region structure in the high cell. In the integrated circuit device, at least three short cells arranged in succession in the second row are free of any self-aligned vertical interconnects. The embodiment of the invention also relates to an integrated circuit device and a method for manufacturing the integrated circuit.

Description

Technical Field

[0001] Embodiments of this disclosure relate to integrated circuit devices and methods for manufacturing integrated circuits. Background Technology

[0002] Integrated circuits (ICs) typically comprise multiple IC devices fabricated according to one or more IC layouts. IC devices sometimes include complementary field-effect transistor (CFET) devices. CFET devices typically have an upper FET located on top of a lower FET in a stacked configuration. Both the upper and lower FETs in a CFET device are located above the conductors in the lower conductor layer, but below the conductors in the upper conductor layer. Summary of the Invention

[0003] Embodiments of this disclosure provide an integrated circuit device comprising: a tall cell having wide complementary field-effect transistor (CFET) devices and arranged in a first row along a first direction; a short cell having narrow complementary field-effect transistor devices and arranged in a second row along the first direction, the second row being adjacent to the first row, wherein, when measured along a second direction perpendicular to the first direction, the height of the second row having the short cells is less than the height of the first row having the tall cells, and wherein at least three short cells consecutively arranged in the second row of the short cells have no self-aligned vertical interconnects; and one or more self-aligned vertical interconnects located in the first row of the tall cells, wherein each of the one or more self-aligned vertical interconnects extending upward in a third direction is at least partially embedded in a side recess adjacent to an active region structure in the tall cell of the tall cell, the third direction being perpendicular to the first direction and the second direction, and wherein the side recess has a boundary surface conformally coated with an insulating material terminating at least one gate conductor intersecting the active region structure.

[0004] Another embodiment of this disclosure provides an integrated circuit device, comprising: a substrate; a first type wide active region structure and a second type wide active region structure stacked on top of each other at a front side of the substrate, wherein each of the first type wide active region structure and the second type wide active region structure extends in a first direction; a first vertical interconnect at least partially embedded in a first side recess and a second vertical interconnect at least partially embedded in a second side recess, both extending in a direction perpendicular to a surface of the substrate, the second vertical interconnect at least partially embedded in a second side recess, both extending in a direction perpendicular to a surface of the substrate, wherein each side recess has a boundary surface conformally coated with an insulating material terminating one or more gate conductors intersecting the first type wide active region structure or the second type wide active region structure, wherein the first vertical interconnect and the second vertical interconnect are spaced apart from each other by a first distance along the first direction; and a first type narrow active region structure and a second type narrow active region structure stacked on top of each other at the front side of the substrate, wherein each of the first type narrow active region structure and the second type narrow active region structure extends in the first direction with a uniform width for a length greater than the first distance.

[0005] Another embodiment of this disclosure provides a method for manufacturing an integrated circuit, comprising: manufacturing a first type wide active region structure and a first type narrow active region structure extending in a first direction; manufacturing lower gate conductors, each lower gate conductor intersecting one of the first type wide active region structure and the first type narrow active region structure; manufacturing a second type wide active region structure on top of the first type wide active region structure and manufacturing a second type narrow active region structure on top of the first type narrow active region structure; manufacturing upper gate conductors, each upper gate conductor intersecting one of the second type wide active region structure and the second type narrow active region structure; etching the first type wide active region structure and the second type wide active region structure to form a first side groove and a second side groove, the first side groove and the second side groove being along... The first direction is separated from each other by a first distance, while each of the first type of narrow active region structure and the second type of narrow active region structure is kept in a range of uniform width longer than the first distance; each of the lower gate conductor and the upper gate conductor adjacent to the first side groove or the second side groove is trimmed and terminated at the boundary surface of the first side groove or the second side groove; a conformally coated insulating material is deposited on the boundary surface of the first side groove and the second side groove; and a metal material is deposited in the empty space defined by the insulating material on the boundary surface of the first side groove and the second side groove, and the empty space is filled with the metal material, thereby forming a first vertical interconnect at least partially embedded in the first side groove and a second vertical interconnect at least partially embedded in the second side groove. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a layout diagram of an integrated circuit having self-aligned vertical interconnects implemented in a circuit cell (with an inverter circuit) according to some embodiments.

[0008] Figures 2A to 2C This is a cross-sectional view of an integrated circuit according to some embodiments.

[0009] Figures 3A to 3C This is a schematic diagram of a process flow for manufacturing a self-aligned vertical interconnect according to some embodiments, wherein the self-aligned vertical interconnect is partially embedded in a side groove adjacent to an active region structure.

[0010] Figure 4This is a schematic diagram of a simplified layout of circuit units according to some embodiments.

[0011] Figure 5A This is a schematic diagram of a simplified layout of a portion of an integrated circuit according to some embodiments.

[0012] Figures 5B to 5C According to some embodiments Figure 5A A cross-sectional view of an integrated circuit.

[0013] Figure 6 This is a schematic diagram of a simplified layout of a portion of an integrated circuit according to some embodiments.

[0014] Figures 7A to 7C This is a schematic diagram of a simplified layout of a portion of an integrated circuit according to some embodiments.

[0015] Figure 8 This is a flowchart of a method for manufacturing an integrated circuit (IC) having a CFET device according to some embodiments.

[0016] Figure 9 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0017] Figure 10 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the discussed embodiments and / or configurations.

[0019] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] In some embodiments, the integrated circuit device having a CFET device includes tall cells in a first row and short cells in a second row. The integrated circuit device also includes one or more vertical interconnects in the tall cells of the first row. Each vertical interconnect, extending in a direction perpendicular to the surface of the substrate, is at least partially embedded in a side recess. The side recess has a boundary surface conformally coated with an insulating material that terminates at least one gate conductor intersecting with an active region structure in the tall cell. In some embodiments, none of the short cells in the second row include vertical interconnects.

[0021] In some implementations, each vertical interconnect in the first row of high cells directly connects the upper and lower layer conductors. The upper conductor is located in the upper conductor layer above all transistors in the CFET device, and the lower conductor is located in the lower conductor layer below all transistors in the CFET device. The vertical interconnects in the high cells reduce IR drop and improve the performance of the integrated circuit device, while the speed and current drive capability of the transistors in the low cells are not reduced.

[0022] Figure 1 This is a layout diagram of an integrated circuit having self-aligned vertical interconnects implemented in a circuit cell (with an inverter circuit) according to some embodiments. Figures 2A to 2C This is a cross-sectional view of an integrated circuit according to some embodiments. Specifically, Figure 2A , Figure 2B and Figure 2C Correspondingly, it is described in Figure 1 A cross-sectional view of the integrated circuit in the cutting planes specified by lines A-A', B-B', and C-C'.

[0023] Figure 1The layout diagram includes an upper portion and a lower portion. The upper portion of the layout diagram includes a layout pattern for specifying the first type of active region structure 80F, gate conductors (such as 152F, 155F and 158F), terminal conductors (such as 134F and 136F), upper layer conductors (such as 122F, 124F, 126F and 128F), upper layer power rail 120F, inter-terminal connector MDLI, dummy gate conductors g151F and g159F at cell boundaries, and various via connectors. The lower portion of the layout diagram includes layout patterns for specifying the second type of active region structure 80B, gate conductors (such as 152B, 155B and 158B), terminal conductors (such as 134B and 136B), lower layer conductors (such as 122B, 124B, 126B and 128B), lower layer power rail 120B, inter-terminal connector MDLI, dummy gate conductors g151B and g159B at cell boundaries, and various through-hole connectors.

[0024] exist Figure 1 In the layout diagram, each of the first type active region structure 80F and the second type active region structure 80B extends in the X direction. Various gate conductors and various terminal conductors extend in the Y direction. The first type active region structure 80F is stacked with the second type active region structure 80B on the front side of the substrate and offset from the second type active region structure along the Z direction. Figures 2A to 2C The cross-sectional view also depicts the stacking of the first type of active region structure 80F and the second type of active region structure 80B along the Z direction. Figure 1 and Figures 2A to 2C In this system, the X, Y, and Z directions are orthogonal to each other and form an orthogonal coordinate system.

[0025] exist Figure 1 In the layout diagram, the gate conductor 155F extending in the Y direction intersects with the first type active region structure 80F in the channel region of the first type transistor, and the gate conductor 155B extending in the Y direction intersects with the second type active region structure 80B in the channel region of the second type transistor. Each terminal conductor 134F and 136F extending in the Y direction intersects with the first type active region structure 80F at one of the terminal regions of the first type transistor. Each terminal conductor 134B and 136B extending in the Y direction intersects with the second type active region structure 80B at one of the terminal regions of the second type transistor. The terminal regions of the transistor are either the source region or the drain region of the transistor.

[0026] In some embodiments, the first type transistor formed in the first type active region structure 80F is a PMOS transistor, and the second type transistor formed in the second type active region structure 80B is an NMOS transistor. In some alternative embodiments, the first type transistor formed in the first type active region structure 80F is an NMOS transistor, and the second type transistor formed in the second type active region structure 80B is a PMOS transistor. The CFET device is formed having a first type transistor stacked with the second type transistor.

[0027] In some embodiments, each of the first type active region structure 80F and the second type active region structure 80B includes one or more nanosheets, therefore Figure 1 Each of the PMOS and NMOS transistors in the configuration is a nanosheet transistor. In some embodiments, each of the first type active region structure 80F and the second type active region structure 80B includes one or more nanowires, therefore, Figure 1 Each of the PMOS and NMOS transistors in the structure is a nanowire transistor.

[0028] exist Figure 1 In the layout diagram, the upper power rail 120F extending in the X direction is located in the upper conductor layer, and the lower power rail 120B extending in the X direction is located in the lower conductor layer. For example... Figures 2A to 2C As shown, the upper conductor layer is located above the first type active region structure 80F and the second type active region structure 80B, while the lower conductor layer is located below the first type active region structure 80F and the second type active region structure 80B. Furthermore, multiple upper-layer conductors (such as 122F, 124F, 126F, and 128F) extending in the X direction are implemented in the upper conductor layer, and multiple lower-layer conductors (such as 122B, 124B, 126B, and 128B) extending in the X direction are implemented in the lower conductor layer.

[0029] In addition, such as Figure 1 and Figures 2A to 2C As shown, a first type of transistor and a second type of transistor are coupled to each other to form an inverter circuit, which is configured to receive voltage supplies from the upper power rail 120F and the lower power rail 120B.

[0030] exist Figure 1 and Figure 2AIn this circuit, terminal conductor 136F (serving as the drain terminal of a first-type transistor) and terminal conductor 136B (serving as the drain terminal of a second-type transistor) are electrically connected together via an inter-terminal connector MDLI. Terminal conductors 136F and 136B form the output node of the inverter circuit. Terminal conductor 136B is connected to the lower conductor 124B via a through-hole connector VB, thereby configuring the lower conductor 124B to receive the output signal of the inverter circuit from terminal conductor 136B.

[0031] exist Figure 1 and Figure 2B In this circuit, gate conductors 155F and 155B are connected together to form the input node of the inverter circuit. Gate conductor 155F is connected to the upper conductor 122F via a via connector VG, thereby configuring gate conductor 155F (as the input node of the inverter circuit) to receive input signals from the upper conductor 122F. In some embodiments, gate conductor 155B is connected to the lower conductor 122B via a via connector VGB (not shown), thereby configuring gate conductor 155B (as the input node of the inverter circuit) to receive input signals from the lower conductor 122B.

[0032] exist Figure 1 and Figure 2C In this configuration, terminal conductor 134F, serving as the source terminal of a first-type transistor, is electrically connected to the upper power rail 120F via a through-hole connector VD. Terminal conductor 134B, serving as the source terminal of a second-type transistor, is electrically connected to the lower power rail 120B via a through-hole connector VDB. In some embodiments, since the first-type transistor is a PMOS transistor and the second-type transistor is an NMOS transistor, the upper power rail 120F is configured to receive an upper power supply voltage VDD, while the lower power rail 120B is configured to receive a lower power supply voltage VSS. In some embodiments, since the first-type transistor is an NMOS transistor and the second-type transistor is a PMOS transistor, the upper power rail 120F is configured to receive a lower power supply voltage VSS, while the lower power rail 120B is configured to receive an upper power supply voltage VDD.

[0033] exist Figure 1 In this circuit, a first type transistor having a gate conductor 155F and a second type transistor having a gate conductor 155B are stacked as a CFET device. The inverter circuit in circuit unit 90 is implemented by the first CFET device having gate conductors 155F and 155B. Additional circuitry in circuit unit 90 is implemented by other CFET devices, such as a second CFET device having gate conductors 152F and 152B and a third CFET device having gate conductors 158F and 158B. Figure 1The layout pattern for the terminal conductors used to designate the second and third CFET devices, as well as the layout pattern for designating additional components (such as through-hole connectors and inter-terminal connectors) in the additional circuit, is not explicitly shown.

[0034] Circuit cell 90 is defined on one side by dummy gate conductors g151F and g151B, and on the other side by dummy gate conductors g159F and g159B. The vertical cell boundary 101 of circuit cell 90 is aligned with dummy gate conductors g151F and g151B, and the vertical cell boundary 109 of circuit cell 90 is aligned with dummy gate conductors g159F and g159B. The width of circuit cell 90, measured along the X direction, is determined by the pitch between dummy gate conductors g151F and g159F or the pitch between dummy gate conductors g151B and g159B.

[0035] Each of the dummy gate conductors 151F and 159F defines a boundary isolation region in the first type active region structure 80F at the intersection between the respective dummy gate conductor and the first type active region structure 80F. The boundary isolation region in the first type active region structure 80F isolates the active regions (i.e., channel region, source region, and drain region) of the first type transistors in circuit cell 90 from the active regions of other first type transistors in adjacent circuit cells (in the first type active region structure 80F). Each of the dummy gate conductors 151B and 159B defines a boundary isolation region in the second type active region structure 80B at the intersection between the respective dummy gate conductor and the second type active region structure 80B. The boundary isolation region in the second type active region structure 80B isolates the active regions of the second type transistors in circuit cell 90 from the active regions of other second type transistors in adjacent circuit cells (in the second type active region structure 80B).

[0036] When viewed from a direction perpendicular to the substrate, the horizontal boundary 102 of the circuit cell 90 extending in the X direction overlaps with the upper power rail 120F and the lower power rail 120B. In some embodiments, the horizontal boundary 102 extends in the X direction at the centerline of the upper power rail 120F and / or the lower power rail 120B. When viewed from a direction perpendicular to the substrate, the horizontal boundary 108 of the circuit cell 90 extending in the X direction overlaps with the upper conductor 128F and the lower conductor 128B. In some embodiments, each of the upper conductor 128F and the lower conductor 128B is a power rail, and the horizontal boundary 108 extends in the X direction at the centerline of the upper conductor 128F and / or the lower conductor 128B. In some embodiments, the height of the circuit cell 90, measured along the Y direction, is determined by the pitch distance between the upper power rail 120F and the upper conductor 128F or by the pitch distance between the lower power rail 120B and the lower conductor 128B. In some alternative embodiments, the height of the circuit unit 90 is determined by other elements in the circuit unit.

[0037] exist Figure 1 In the layout diagram, each of the upper and lower portions further includes a layout pattern for specifying the side recess 180 and the self-aligned vertical interconnect 100, which is at least partially embedded in the side recess 180. The side recess 180 has a boundary surface 188 facing the negative Y direction, a boundary surface 181 facing the positive X direction, and a boundary surface 183 facing the negative X direction. Each of the boundary surfaces 188, 181, and 183 is conformally coated with an insulating material. The conformally coated insulating material on the boundary surface 188 terminates the gate conductors 152F, 155F, 158F (as shown in the upper portion of the layout diagram) and the gate conductors 152B, 155B, 158B (as shown in the lower portion of the layout diagram). Figure 2B The cross-sectional view also shows the gate conductors 155F and 155B terminated by insulating material conformally coated on the boundary surface 188.

[0038] The self-aligned vertical interconnect 100 occupies space in the side recess 180 while being at least partially embedded in the side recess 180. For example... Figure 2B As shown, the self-aligned vertical interconnect 100 extends long enough in the Z direction (perpendicular to the substrate surface) to pass through the horizontal surfaces PP' and QQ'. Here, the horizontal surface PP' is located at the upper edge of the first type active region structure 80F, and the horizontal surface QQ' is located at the lower edge of the second type active region structure 80B, with each of the horizontal surfaces PP' and QQ' being parallel to the substrate surface.

[0039] In some embodiments, the self-aligned vertical interconnect 100 electrically connects the upper conductor 126F to the lower conductor 126B (wherein this connection is not explicitly shown in the figures). In some embodiments, the self-aligned vertical interconnect 100 is long enough to directly connect the upper conductor 126F to the lower conductor 126B. In some embodiments, the self-aligned vertical interconnect 100 connects the upper conductor 126F to the lower conductor 126B through one or more through-hole connectors. In some embodiments, one or both of the upper conductor 126F and the lower conductor 126B are configured to receive a power supply voltage. Similarly, in some embodiments, the self-aligned vertical interconnect 100 electrically connects the upper conductor 128F to the lower conductor 128B (wherein this connection is not explicitly shown in the figures), with each of the upper conductor 128F and the lower conductor 128B implemented as a power rail.

[0040] Figures 3A to 3C This is a schematic diagram of a process flow for manufacturing self-aligned vertical interconnects according to some embodiments, wherein the self-aligned vertical interconnects are partially embedded in side recesses adjacent to active region structures. This process is carried out after the fabrication of some components in an integrated circuit. Figures 3A to 3C The side groove is 180. (For example...) Figure 3A As shown, before fabricating the side recess 180, a first type of active region structure 80F and a second type of active region structure 80B stacked on top of each other are fabricated. Gate conductors 152F, 155F, and 158F, as well as gate conductors 152B, 155B, and 158B, are also fabricated before fabricating the side recess. Furthermore, various terminal conductors are fabricated before fabricating the side recess 180. Figure 3A (Not explicitly shown in the text).

[0041] like Figure 3AAs shown, in the process of manufacturing the side recess 180, the exposed area defined by a mask (defined as a CMG pattern) undergoes a dry etching process. In some embodiments, in a layout design process, the CMG pattern is a layout pattern used to specify the cuts of the metal gate. After the dry etching process, an empty space including the side recess 180 is created in the exposed area defined by the mask. The boundary surface 188 of the side recess 180 terminates each gate conductor 152F, 155F, and 158F, and each gate conductor 152, 155B, and 158B. That is, during the dry etching process, portions of the gate conductors 152F / 152B, 155F / 155B, and 158F / 158B extending into the exposed area defined by the mask (shown as a CMG pattern) are removed. The depth of the side recess 180 along the Y direction relates to the amount or length of material removed from the gate conductors terminated by the mask (shown as a CMG pattern). The length of the side groove 180 along the X direction is determined by the distance between boundary surface 181 and boundary surface 183, which are also terminated by a mask (shown as a CMG pattern).

[0042] In the process of manufacturing the side groove 180, such as Figure 3A As shown, some material is also removed from the dummy gate conductors g151 and g159 at the vertical cell boundaries of the circuit cells, and thus the dummy gate conductors g151 and g159 terminate accordingly at some boundary surfaces 384 and 386 of the empty spaces created in the exposed area defined by the mask. In some alternative embodiments, each of the dummy gate conductors g151 and g159 does not terminate at the boundary surface 384 or 386 of the empty spaces created in the exposed area defined by the mask.

[0043] After manufacturing the side groove 180, in the next step, such as Figure 3B As shown, dielectric material 310 is conformally coated on the boundary surfaces of the side grooves 80 (i.e., 188, 181 and 183) and various other boundary surfaces (e.g., 382, ​​384 and 386) of the empty spaces created by the dry etching process in the previous steps.

[0044] Following the conformal deposition step, in the next step, such as Figure 3C As shown, the remaining empty spaces defined by the dielectric material on the boundary surfaces (i.e., 188, 181, 183 and 386) are filled with metallic material, thereby forming a self-aligned vertical interconnect 100 in the circuit unit.

[0045] In such Figure 1In the illustrated embodiment, the first type of active region structure 80F has a uniform width between the dummy gate conductors g151F and g159F, and the second type of active region structure 80B has a uniform width between the dummy gate conductors g151B and g159B. That is, the stacked active region structures 80F / 80B have a uniform width between the vertical cell boundary 101 and the vertical cell boundary 109 of the circuit cell. Figure 4 In some of the embodiments shown, the stacked active region structures 80F / 80B do not have a uniform width between the vertical cell boundaries 101 and 109 of the circuit cells.

[0046] Figure 4 This is a simplified layout diagram of circuit units according to some embodiments. Figure 4 In the circuit, the circuit cell is defined in the X direction by a dummy gate conductor g151 at the vertical cell boundary 101 and a dummy gate conductor g159 at the vertical cell boundary 109. Gate conductors 152F / 152B, 155F / 155B, and 158F / 158B intersect with the first type wide active region structure and the second type wide active region structure of the stacked active region structure 80F / 80B, respectively. Although Figure 1 Each of the gate conductors 152F / 152B, 155F / 155B, and 158F / 158B is terminated by the boundary surface 188 of the side recess 180. Figure 4 Only gate conductors 155F / 155A are terminated by the boundary surface 188 of the side recess 180, but gate conductors 152F / 152B and 158F / 158B are correspondingly terminated by conformally coated insulating material on boundary surfaces 384 and 386 (which are not in the rectangular side recesses accommodating the self-aligned vertical interconnect 100). Therefore, the transistor in a CFET device having gate conductors 155F / 155B has a gate width equal to the reduced width W2 of the stacked active region structure 80F / 80B, and the transistor in a CFET device having gate conductors 152F / 152B or 158F / 158B has a gate width equal to the width W1 of the stacked active region structure 80F / 80B. Here, the gate width W1 is greater than the gate reduction width W2. Even though the gate conductors 155F / 155B are shortened to provide space for accommodating the self-aligned vertical interconnect 100, the gate conductors in other regions of the circuit cell still maintain a longer length. Therefore, transistors formed with gate conductors in other regions of the circuit cell maintain greater drive strength and greater current carrying capacity than transistors formed with gate conductors 155F / 155B.

[0047] In some embodiments, the integrated circuit includes a plurality of tall cells arranged in a first row and a plurality of short cells arranged in a second row. Self-aligned vertical interconnects are implemented in one or more tall cells in the first row, but not in the short cells in the second row, at least within a portion of the integrated circuit. CFET devices in the tall cells are implemented with a wide active region structure. CFET devices in the short cells are implemented with a narrow active region structure. The height of the tall cells in the first row is greater than the height of the short cells in the second row.

[0048] Figure 5A This is a simplified layout diagram of a portion of an integrated circuit according to some embodiments. Figure 5A In this embodiment, this portion of the integrated circuit includes tall cells arranged in cell rows 502 and 504, and short cells arranged in cell rows 512 and 514. Several tall cells are depicted in cell rows 502 and 504 as examples, and several short cells are also depicted in cell rows 512 and 514 as examples. Although they may exist, additional tall and short cells are not explicitly shown in cell rows 502 and 504 or cell rows 512 and 514.

[0049] The height of each of the taller cell rows 502 and 504 is greater than the height of the shorter cell rows 512 or 514. The height of the taller cell is greater than the height of the shorter cell. Figure 5A In the middle row, high cells TCell1, TCell2, and TCell3 are arranged in cell row 502 (cell row 502 is located between row boundaries 531 and 532). The CFET devices in high cells TCell1, TCell2, and TCell3 are implemented as a stacked wide active region structure 580F / 580B. Low cells SCell1, SCell2, SCell3, SCell4, SCell5, and SCell6 are arranged in cell row 512 (cell row 512 is located between row boundaries 532 and 533). The CFET devices in low cells SCell1-SCell6 are implemented as a stacked narrow active region structure 582F / 582B. High cells TCell4 and TCell5 are arranged in cell row 504 (cell row 504 is located between row boundaries 533 and 534). The CFET devices in high cells TCell4 and TCell5 are implemented as a stacked wide active region structure 584F / 584B. The low-profile cells SCell7, SCell8, and SCell9 are arranged in cell row 514 (cell row 514 is located between row boundaries 534 and 535). The CFET devices in the low-profile cells SCell7-SCell9 are implemented as a 586F / 586B structure with stacked narrow active regions.

[0050] Each of the high cells TCell1, TCell3, and TCell5 has a self-aligned vertical interconnect 100, 100C, or 100E. Each of the high cells TCell1, TCell3, and TCell5 also has a corresponding side recess (i.e., 180, 180C, or 180E) for accommodating the self-aligned vertical interconnect. The self-aligned vertical interconnects 100 and 100C, extending in the Z direction (perpendicular to the X and Y directions), are partially embedded in the corresponding side recess (i.e., 180 or 180C) adjacent to the stacked active region structures 580F / 580B. The self-aligned vertical interconnect 100E, extending in the Z direction, is partially embedded in the corresponding side recess 180E adjacent to the stacked active region structures 584F / 584B. Another self-aligned vertical interconnect 100D, not in the high cell, is partially embedded in the corresponding side recess (i.e., 180D) adjacent to the stacked active region structures 584F / 584B.

[0051] Each of the side grooves 180, 180C, 180D, and 180E has a corresponding boundary surface (i.e., 188, 188C, 188D, or 188E) which is conformally coated with an insulating material. Figure 5A (Not shown in the image). Each self-aligned vertical interconnect 100, 100C, 100D and 100E is separated from the corresponding stacked active region structure (580F / 580B or 584F / 584B) by insulating material on the corresponding boundary surface (i.e. 188, 188C, 188D or 188E).

[0052] Figures 5B to 5C According to some embodiments Figure 5A A cross-sectional view of an integrated circuit. Specifically, Figure 5B and Figure 5C Correspondingly, it describes the composition of Figure 5A A cross-sectional view of the integrated circuit in the cutting plane specified by lines M-M' and N-N'.

[0053] like Figures 5A to 5CAs shown, in cell row 502 between row boundaries 531 and 532, the stacked wide active region structures 580F / 580B include a first type of wide active region structure 580F and a second type of wide active region structure 580B stacked on top of each other. In cell row 512 between row boundaries 532 and 533, the stacked narrow active region structures 582F / 582B include a first type of narrow active region structure 582F and a second type of narrow active region structure 582B stacked on top of each other. In cell row 504 between row boundaries 533 and 534, the stacked wide active region structures 584F / 584B include a first type of wide active region structure 584F and a second type of wide active region structure 584B stacked on top of each other. In cell row 514 between row boundaries 534 and 535, the stacked narrow active region structures 586F / 586B include a first type of narrow active region structure 586F and a second type of narrow active region structure 586B stacked on top of each other.

[0054] exist Figure 5A In the stacked wide active region structures (e.g., 580F / 580B or 584F / 584B) where the width is not narrowed by the side grooves, the width is a wide width W1. However, in the regions where the width is narrowed by the side grooves, the width of the stacked wide active region structures (e.g., 580F / 580B or 584F / 584B) is a reduced width W2. The width of the stacked narrow active region structures (e.g., 582F / 582B or 586F / 586B) is a narrow width W3.

[0055] In such Figure 5B In the example shown, in the cutting plane M-M', the width of at least one of the first type wide active region structure 580F and the second type wide active region structure 580B is a reduced width W2, and the width of at least one of the first type wide active region structure 584F and the second type wide active region structure 584B is a wide width W1 (the wide width W1 is greater than the reduced width W1). In the example shown... Figure 5C In the example shown, in the cutting plane N-N', the width of at least one of the first type wide active region structure 580F and the second type wide active region structure 580B is a reduced width W2, and similarly, the width of at least one of the first type wide active region structure 584F and the second type wide active region structure 584B is also a reduced width W2.

[0056] In such Figures 5B to 5CIn the example shown, in each of the cutting planes M-M' and N-N', the width of at least one of the first type narrow active region structure 582F and the second type narrow active region structure 582B is a narrow width W3 (narrow width W3 is less than wide width W1), and similarly, the width of at least one of the first type narrow active region structure 586F and the second type narrow active region structure 586B is also a narrow width W3 (narrow width W3 is less than wide width W1).

[0057] exist Figures 5B to 5C In some embodiments, each of the first type of active region structure (i.e., 580F, 582F, 584F, and 586F) and the second type of active region structure (i.e., 580B, 582B, 584B, and 586B) includes multiple nanostructures (such as nanosheets or nanowires). In some example embodiments, the multiple nanostructures in the first or second type of active region structure include multiple stacked nanosheets (such as two, three, or four stacked nanosheets). In some embodiments, a metal gate surrounding the multiple nanostructures in the first type of active region structure forms the gate terminal of a first type transistor, and a conductive segment on either side of the metal gate that is in conductive contact with the multiple nanostructures forms the source or drain terminal of the first type transistor. Similarly, a metal gate surrounding the multiple nanostructures in the second type of active region structure forms the gate terminal of a second type transistor, and a conductive segment on either side of the metal gate that is in conductive contact with the multiple nanostructures forms the source or drain terminal of the second type transistor. In some embodiments, the first type transistor is a PMOS transistor, and the second type transistor is an NMOS transistor. In some embodiments, the first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor.

[0058] exist Figure 5A In the diagram, the height of each cell row containing the tall cells (i.e., 502 and 504) is height H. A And the height of each high unit is equal to or less than the height H. A In some implementations, the height of each high cell is equal to the height H. A Measure the height of each high-cell row along the Y-direction. Figure 5A In the diagram, the height of each cell row (i.e., 512 or 514) containing short cells is height H. B And the height of each dwarf unit is equal to or less than the height H. B In some implementations, the height of each dwarf unit is equal to the height H. B Measure the height of each row of short cells along the Y direction.

[0059] In some embodiments, the width of the stacked wide active region structure, the width of the stacked narrow active region structure, and the depth of each side recess are all related to the height H of the cell row containing the tall cells. A Proportional. In some example implementations, the width W1 of the wide active region structure of the stack, which is not narrowed by side grooves, is from 0.5H. A up to 0.7H A Within the range, the width W2 of the stacked wide active region structure, which is narrowed by side grooves, is reduced from 0.3H. A up to 0.4H A Within the range, the narrow width W3 of the stacked narrow active region structure is from 0.3H A up to 0.4H A Within that range. Furthermore, in Figure 5A In this context, the spacing (measured along the Y direction) between the self-aligned vertical interconnect (e.g., 100D) and the adjacent stacked wide active region structure (e.g., 584F / 584B) is distance S. In some example embodiments, distance S ranges from 0.1H. A up to 0.2H A Within the range. In some embodiments, the depth B of the side groove is 0.2H. A up to 0.3H A between.

[0060] exist Figure 5A In this context, while some tall cells are implemented with self-aligned vertical interconnects, no short cells are implemented with self-aligned vertical interconnects. Figure 5A In the portion of the integrated circuit, there are no side recesses in the cell rows 512 and 514 containing low-profile cells, and each of the stacked narrow active region structures 582F / 582B and 586F / 586B has a uniform width at least in the portion of the integrated circuit shown. Each of the first type of narrow active region structure and the second type of narrow active region structure (in cell rows 512 or 514) extends in the X direction with a uniform width for a distance longer than a distance L, which is the distance between the self-aligned vertical interconnects 100 and 100C. In fact, the width of the stacked narrow active region structures (e.g., 582F / 582B or 586F / 586B) is uniform for a range at least as long as the total length TL of the portion of the integrated circuit shown.

[0061] exist Figure 5A In the stacked wide active region structure 580F / 580B adjacent to the side recesses 180 and 180C, the segments have reduced widths, such as W2, while the segments of the stacked wide active region structure 580F / 580B located between the side recesses 180 and 180C have wide widths, such as W1.

[0062] In such Figure 5A In the example embodiments shown, none of the shown low-profile cells contain self-aligned vertical interconnects. In some embodiments, at least three low-profile cells arranged consecutively in a row of low-profile cells lack any self-aligned vertical interconnects. For example, low-profile cells SCell2, SCell3, and SCell4 (arranged consecutively in cell row 512) lack any self-aligned vertical interconnects. Low-profile cells SCell3, SCell4, and SCell5 (also arranged consecutively in cell row 512) also lack any self-aligned vertical interconnects. In some embodiments, at least four low-profile cells arranged consecutively in a row of low-profile cells lack any self-aligned vertical interconnects. For example, low-profile cells SCell2, SCell3, SCell4, and SCell5 lack any self-aligned vertical interconnects. Low-profile cells SCell2, SCell3, SCell4, and SCell5 are arranged consecutively in cell row 512 within a distance L, which measures the distance between self-aligned vertical interconnects 100 and 100C.

[0063] exist Figure 5A In the integrated circuit, a power grid is also included at each row boundary 531-535, and horizontal conductive tracks are included between the power grids. Although each of the power grids and horizontal conductive tracks extends in the X direction, in... Figure 5A The Y-coordinates of the power grid and the horizontal conductive track are schematically depicted on the upper right side. Also... Figure 5A The upper right side schematically depicts the width of each of the power grid and horizontal conductive tracks.

[0064] exist Figure 5A In the middle, power grid rail 120 (which represents upper power rail 120F and lower power rail 120B) is implemented at each of the row boundaries 531, 533 and 535. Figures 2A to 2C An example of an upper power rail 120F and a lower power rail 120B in a power grid track 120 is shown. A power grid track 140 (representing the upper and lower power rails) is implemented at each of row boundaries 532 and 534. In one embodiment, as... Figures 2A to 2C As shown in the example, the power grid track 140 is implemented at the horizontal boundary 108 of the circuit unit 90 as having an upper conductor 128F and a lower conductor 128B.

[0065] exist Figure 5A In each cell row 502 and 504, a set of three horizontal conductive tracks 122, 124, and 126 are implemented. Here, the horizontal conductive tracks 122, 124, and 126 respectively represent upper conductors 122F, 124F, and 126F and lower conductors 122B, 124B, and 126B, such as in... Figures 2A to 2CIn the example shown, a set of two horizontal conductive tracks 142 and 144 (each horizontal conductive track represents an upper conductor and a lower conductor) are implemented within each cell row 512 and 514.

[0066] In such Figures 5A to 5C In the example shown, the width of the stacked wide active region structure narrows in some areas via side grooves. In some alternative embodiments, the width of the stacked wide active region structure remains uniform in cell rows 502 and 504.

[0067] In some embodiments, such as in Figure 6 In this context, the integrated circuit includes one or more dual-height circuit units, which are implemented with self-aligned vertical interconnects. Figure 6 This is a simplified layout diagram of a portion of an integrated circuit according to some embodiments. Figure 6 In the figure, several selected tall cells and several selected short cells are depicted. Figure 6 The high cells depicted include high cell TCell10 in cell row 506 and high cell TCell11 in cell row 508. Figure 6 The dwarf units depicted include dwarf units SCell7, SCell8 and SCell9 in unit row 514 and dwarf unit SCell10 in unit row 516.

[0068] Figure 6 This is a simplified layout diagram of a portion of an integrated circuit according to some embodiments. Figure 6 The figure also depicts a dual-height cell DCell0. The dual-height cell DCell0 occupies cell rows 506 and 516. The dual-height cell DCell0 is defined along the X-direction by vertical cell boundaries 601 and 609. The dual-height cell DCell0 is defined along the Y-direction by horizontal cell boundaries 602 and 608. When viewed from a direction perpendicular to the substrate, each of the horizontal cell boundaries 602 and 608 of the dual-height cell DCell0 overlaps with a power grid track 120. Each power grid track 120 includes an upper power rail 120F and a lower power rail 120B stacked on top of each other. The upper power rails at horizontal cell boundaries 602 and 608 are configured to receive the same first power supply voltage (such as an upper power supply voltage VDD). The lower power rails at horizontal cell boundaries 602 and 608 are configured to receive the same second power supply voltage (such as a lower power supply voltage VSS).

[0069] exist Figure 6The diagram schematically shows other power grid tracks “PG” extending in the X direction. It also schematically shows horizontal conductive tracks “cLn” extending in the X direction. Each power grid track “MG” corresponds to an upper-level power supply track and a lower-level power supply track. Each horizontal conductive track “cLn” corresponds to an upper-level conductor and a lower-level conductor.

[0070] Since the dual-height cell DCell0 occupies cell row 506 containing tall cells and cell row 516 containing short cells, the height H of the dual-height cell DCell0 is... C =H A +H B In other words, the height H of the dual-height unit DCell0 C It is the height H of the cell row containing the tall cells. A and the height H of the cell row containing the short cells B The sum of .

[0071] The dual-height cell DCell0 includes a wide CFET device implemented in a stacked wide active region structure 588F / 588B and a narrow CFET device implemented in a stacked narrow active region structure 589F / 589B. Each wide CFET device in the dual-height cell DCell0 includes a first-type wide transistor located in the first-type wide active region structure 588F and a second-type wide transistor located in the second-type wide active region structure 588B. Each narrow CFET device in the dual-height cell DCell0 includes a first-type narrow transistor located in the first-type narrow active region structure 589F and a second-type narrow transistor located in the second-type narrow active region structure 589B.

[0072] Each of the first type wide active region structure 588F and the second type wide active region structure 588B has boundary isolation regions at vertical cell boundaries 601 and 609. The boundary isolation regions in the stacked wide active region structures 588F / 588B isolate the active regions of the wide CFET devices in the dual-height cell DCell0 from the active regions of other wide transistors in adjacent circuit cells. Each of the first type narrow active region structure 589F and the second type narrow active region structure 589B also has boundary isolation regions at vertical cell boundaries 601 and 609. The boundary isolation regions in the stacked narrow active region structures 589F / 589B isolate the active regions of the narrow CFET devices in the dual-height cell DCell0 from the active regions of other narrow transistors in adjacent circuit cells.

[0073] The dual-height cell DCell0 also includes a self-aligned vertical interconnect 100DC partially embedded in a side recess 180DC adjacent to the stacked wide active region structures 588F / 588B. The boundary surface 188DC of the side recess 180DC is conformally coated with an insulating material. The conformally coated insulating material on the boundary surface 188DC terminates one or more gate conductors intersecting with the first type wide active region structure 588F and / or the second type wide active region structure 588B in the dual-height cell DCell0. The stacked narrow active region structures 589F / 589B have a uniform width between vertical cell boundaries 601 and 609. No self-aligned vertical interconnect for the dual-height cell DCell0 is implemented in the region 670 between the stacked narrow active region structures 589F / 589B and the horizontal cell boundary 608. In some embodiments, no self-aligned vertical interconnects of the dual-height cell DCell0 are implemented in the region separating the power rails 120F / 120B from the first type narrow active region structure 589F and the second type narrow active region structure 589B.

[0074] As an example, in Figure 6 In the dual-height cell DCell0, a self-aligned vertical interconnect 100DC is provided, which is partially embedded in a side recess 180DC adjacent to the stacked wide active region structures 588F / 588B. In some embodiments, the dual-height cell includes two or more self-aligned vertical interconnects, and each self-aligned vertical interconnect in the dual-height cell is received by a side recess adjacent to the stacked wide active region structures 588F / 588B.

[0075] exist Figure 5A and Figure 6 In the example layout design, a row of short cells is located between two rows of tall cells, and a row of tall cells is located between two rows of short cells. Figure 5A and Figure 6 The layout can be characterized as an "ABABAB" design. Figures 7A to 7C The text describes the optional layout arrangement between tall and short cell rows. Figures 7A to 7C This is a schematic diagram of a simplified layout of a portion of an integrated circuit according to some embodiments.

[0076] exist Figure 7A In the integrated circuit, the portion includes cell rows 701 and 702 with tall cells and cell rows 711-714 with short cells. Utilizing... Figure 7A The “ABBABB” layout involves inserting a pair of adjacent rows of short cells between two rows of tall cells. For example, a pair of cell rows 711 and 712 with short cells are inserted between cell rows 701 and 702 with tall cells.

[0077] exist Figure 7BIn the integrated circuit, the cell rows 701-704 have tall cells and the cell rows 711 and 712 have short cells. Utilizing... Figure 7B The “AABAAB” layout involves inserting a pair of adjacent rows of tall cells between two rows of short cells. For example, a pair of adjacent cell rows 703 and 704 with tall cells are inserted between cell rows 711 and 712 with short cells.

[0078] exist Figure 7C In the integrated circuit, the cell rows 701-704 have tall cells and the cell rows 711 and 712 have short cells. Utilizing... Figure 7C The "AABBAA" layout involves inserting a pair of adjacent rows of short cells between a first pair of adjacent rows of tall cells and a second pair of adjacent rows of tall cells. Additionally, a pair of adjacent rows of tall cells (not explicitly shown in the figure) is inserted between the first pair of adjacent rows of short cells and the second pair of adjacent rows of short cells. For example, a pair of adjacent cell rows with short cells (i.e., 711 and 712) is inserted between a first pair of adjacent cell rows with tall cells (i.e., 701 and 702) and a second pair of adjacent cell rows with tall cells (i.e., 703 and 704). A pair of adjacent cell rows with tall cells (i.e., 703 and 704) is inserted between a first pair of adjacent cell rows with short cells (i.e., 711 and 712) and a second pair of adjacent cell rows with short cells (not explicitly shown in the figure).

[0079] exist Figures 7A to 7C The diagram schematically illustrates the power grid track "PG" extending in the X direction and the horizontal conductive track "cLn" extending in the X direction. Each power grid track "MG" corresponds to an upper power supply track and a lower power supply track. Each horizontal conductive track "cLn" corresponds to an upper conductor and a lower conductor.

[0080] Figure 8 This is a flowchart of a method 800 for manufacturing an integrated circuit (IC) having a CFET device according to some embodiments. It should be understood that... Figure 8 Additional operations are performed before, during, and / or after the method described in this document 800, and some other processes may be described only briefly in this document.

[0081] In operation 810, a first type of wide active region structure and a first type of narrow active region structure extending in a first direction are manufactured. In such a way... Figures 5A to 5C In the example shown, a wide active region structure (i.e., 580B) and a narrow active region structure (i.e., 582B) are fabricated at the bottom of the stacked active region structure.

[0082] In operation 815, a lower gate conductor is fabricated that intersects with one of the first type wide active region structure and the first type narrow active region structure. In such a way... Figures 5A to 5C The example shown and Figure 1 In the lower part, gate conductors 152B, 155B and 158B are manufactured.

[0083] In operation 820, a second type wide active region structure is fabricated on top of the first type wide active region structure, and a second type narrow active region structure is fabricated on top of the first type narrow active region structure. Figures 5A to 5C In the example shown, a wide active region structure (i.e., 580F) and a narrow active region structure (i.e., 582F) are fabricated at the top of the stacked active region structures.

[0084] In operation 825, an upper gate conductor is fabricated that intersects with one of the second type wide active region structures and the second type narrow active region structures. In such a way... Figures 5A to 5C The example shown and Figure 1 In the upper part, gate conductors 152F, 155F and 158F are manufactured.

[0085] In operation 830, each of the first type wide active region structure and the second type wide active region structure is etched to form a first side recess and a second side recess. In operation 830, the first type narrow active region structure and the second type narrow active region structure are not etched. Figures 5A to 5C and Figure 3A In the example shown, the first type of wide active region structure and the second type of wide active region structure in the wide active region structure 580F / 580B are etched to form side recesses 180 and 180C. The first type of narrow active region structure and the second type of narrow active region structure in the narrow active region structure 582F / 582B are not etched to form any side recesses.

[0086] In operation 832, the boundary surface of the first-side recess or the second-side recess is trimmed and terminated for each of the lower gate conductor and the upper gate conductor adjacent to the first-side recess or the second-side recess. In such a way... Figure 3A In the example shown, gate conductors 152F / 152B, 155F / 155B, and 158F / 158B are trimmed and terminate at boundary surface 188.

[0087] In operation 840, insulating material is deposited on the boundary surface of the first side groove and the second side groove, thereby conformally coating the boundary surface with insulating material. In such a way... Figure 3B In the example shown, dielectric material 310 is conformally coated on the boundary surfaces (i.e., 188, 181, and 183) of the side grooves 180. In such... Figures 5A to 5CIn the example shown, insulating material is conformally coated on the boundary surfaces of side groove 180 and side groove 180C.

[0088] In operation 850, metallic material is deposited into an empty space defined by insulating material on the boundary surfaces of the first and second side grooves, and a first vertical interconnect in the first side groove and a second vertical interconnect in the second side groove are formed by filling the empty space with metallic material. Figure 3C In the example shown, the empty space defined by the dielectric material on the boundary surface of the side groove 180 is filled with a metallic material, forming a self-aligned vertical interconnect 100. In such a case... Figures 5A to 5C In the example shown, the empty space defined by the insulating material on the boundary surfaces of the side grooves 180 and 180C is filled with a metallic material, thereby forming the self-aligned vertical interconnect 100 and the self-aligned vertical interconnect 100C.

[0089] In operation 860, upper and lower layer conductors are formed, and each vertical interconnect is electrically connected between the upper and lower layer conductors. Figures 5A to 5C and Figures 2A to 2C In the example shown, the upper conductor 126F is electrically connected to the lower conductor 126B through some implementation of the self-aligned vertical interconnect 100.

[0090] Figure 9 This is a block diagram of an electronic design automation (EDA) system 900 according to some embodiments.

[0091] In some embodiments, the EDA system 900 includes an Automatic Placement and Routing (APR) system. According to one or more embodiments, the method of designing layout diagrams described herein represents wiring arrangements, which, for example, can be implemented using the EDA system 900 according to some embodiments.

[0092] In some embodiments, the EDA system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable storage medium 904. Among other things, the storage medium 904 also encodes (i.e. stores) computer program code 906, which is a set of executable instructions. Execution of the instructions 906 by the hardware processor 902 indicates (at least partially) an EDA tool that, according to one or more embodiments, implements some or all of the methods described herein (hereinafter referred to as the process and / or method).

[0093] Processor 902 is electrically coupled to computer-readable storage medium 904 via bus 908. Processor 902 is also electrically coupled to I / O interface 910 via bus 908. Network interface 912 is also electrically connected to processor 902 via bus 908. Network interface 912 is connected to network 914, enabling processor 902 and computer-readable storage medium 904 to be connected to external components via network 914. Processor 902 is configured to execute computer program code 906 encoded in computer-readable storage medium 904 so that system 900 can be used to perform some or all of the process and / or method. In one or more embodiments, processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0094] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 904 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0095] In one or more embodiments, storage medium 904 stores computer program code 906 configured to enable system 900 (where such execution representation (at least partially) EDA tools) to perform part or all of the process and / or method. In one or more embodiments, storage medium 904 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 904 stores a standard cell library 907 including such standard cells disclosed herein. In one or more embodiments, storage medium 904 stores one or more layout diagrams 909 corresponding to one or more layouts disclosed herein.

[0096] EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuitry. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 902.

[0097] EDA system 900 also includes a network interface 912 coupled to processor 902. Network interface 912 allows system 900 to communicate with a network 914 to which one or more other computer systems are connected. Network interface 912 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the process and / or method are implemented in two or more systems 900.

[0098] System 900 is configured to receive information via I / O interface 910. The information received via I / O interface 910 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 902. This information is transmitted to processor 902 via bus 908. EDA system 900 is configured to receive information related to the user interface (UI) via I / O interface 910. This information is stored as UI 942 on computer-readable medium 904.

[0099] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 900. In some embodiments, a layout diagram including standard cells is generated using a suitable layout generation tool.

[0100] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), etc.

[0101] Figure 10 This is a block diagram of an integrated circuit (IC) manufacturing system 1000 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1000 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0102] exist Figure 10In this IC manufacturing system 1000, entities such as design room 1020, mask room 1030, and IC manufacturer / fab 1050 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC device 1060. The entities in system 1000 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1020, mask room 1030, and IC manufacturer 1050 are owned by a single, larger company. In some embodiments, two or more of design room 1020, mask room 1030, and IC manufacturer 1050 coexist in a shared facility and use shared resources.

[0103] Design studio (or design team) 1020 generates IC design layout 1022. IC design layout 1022 includes various geometric patterns designed for IC device 1060. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1060 to be manufactured. The layers are combined to form various IC components. For example, portions of IC design layout 1022 include various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1020 performs appropriate design steps to form IC design layout 1022. These design steps include one or more of logic design, physical design, or placement and routing. IC design layout 1022 is presented in the form of one or more data files containing information about the geometric patterns. For example, IC design layout 1022 may be represented in GDSII or DFII file format.

[0104] Mask chamber 1030 includes data preparation 1032 and mask fabrication 1044. Mask chamber 1030 uses an IC design layout 1022 to fabricate one or more masks 1045 for fabricating various layers of an IC device 1060 according to the IC design layout 1022. Mask chamber 1030 performs mask data preparation 1032, in which the IC design layout 1022 is converted into a representative data file (RDF). Mask data preparation 1032 provides the RDF to mask fabrication 1044. Mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1045 or a semiconductor wafer 1053. The design layout 1022 is manipulated by mask data preparation 1032 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer 1050. Figure 10 In this diagram, mask data preparation 1032 and mask manufacturing 1044 are shown as separate elements. In some embodiments, mask data preparation 1032 and mask manufacturing 1044 may be collectively referred to as mask data preparation.

[0105] In some embodiments, mask data preparation 1032 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 1022. In some embodiments, mask data preparation 1032 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution aids, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, treating OPC as an inverse imaging problem.

[0106] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 1022, which has already undergone process processing in the OPC. This set of mask creation rules includes geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for the effects of photolithography implementation during mask fabrication 1044, which can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0107] In some embodiments, mask data preparation 1032 includes a lithography process inspection (LPC), an LPC simulation performed by an IC manufacturer 1050 to manufacture an IC device 1060. The LPC simulates this process based on an IC design layout 1022 to create a simulated manufactured device, such as IC device 1060. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after the LPC has created a simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1022.

[0108] It should be understood that, for clarity, the above description of mask data preparation 1032 has been simplified. In some embodiments, data preparation 1032 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 1022 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1022 during data preparation 1032 can be performed in various different sequences.

[0109] After mask data preparation 1032 and during mask fabrication 1044, a mask 1045 or a set of masks 1045 is fabricated based on a modified IC design layout 1022. In some embodiments, mask fabrication 1044 includes performing one or more photolithographic exposures based on the IC design layout 1022. In some embodiments, a pattern is formed on the mask (photomask or intermediate mask) 1045 using a mechanism of electron beams (e-beams) or multiple electron beams based on the modified IC design layout 1022. The mask 1045 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1045. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (such as ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 1045. In the phase-shifting mask (PSM) version of mask 1045, various components in the pattern formed on the phase-shifting mask are configured with appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 1044 is used in various processes. For example, this mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1053, in etching processes to form various etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0110] IC manufacturer 1050 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturer 1050 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end process (BEOL) manufacturing) for the interconnection and packaging of IC products, and a third manufacturing facility for providing other services for foundry operations.

[0111] IC manufacturer 1050 includes manufacturing tool 1052 configured to perform various manufacturing operations on semiconductor wafer 1053, such that IC device 1060 is manufactured according to a mask (e.g., mask 1045). In various embodiments, manufacturing tool 1052 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes discussed herein.

[0112] IC manufacturer 1050 uses mask 1045, manufactured by mask chamber 1030, to manufacture IC device 1060. Therefore, IC manufacturer 1050 uses IC design layout 1022 at least indirectly to manufacture IC device 1060. In some embodiments, semiconductor wafer 1053 is manufactured by IC manufacturer 1050 using mask 1045 to form IC device 1060. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1053 also includes one or more of various doped regions, dielectric components, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0113] This disclosure relates to an integrated circuit device. The integrated circuit device includes tall cells having wide CFET devices arranged in a first row along a first direction; short cells having narrow CFET devices arranged in a second row along the first direction, the second row adjacent to the first row, wherein the height of the second row with short cells is less than the height of the first row with tall cells when measured along a second direction perpendicular to the first direction, and wherein at least three short cells consecutively arranged in the second row of short cells have no self-aligned vertical interconnects; and one or more self-aligned vertical interconnects located in the first row of tall cells, wherein each self-aligned vertical interconnect extending upward in a third direction perpendicular to the first and second directions is at least partially embedded in a side recess, and wherein the side recess has a boundary surface conformally coated with an insulating material terminating at least one gate conductor intersecting with an active region structure in the tall cell.

[0114] In some embodiments, the integrated circuit device includes: a first type wide active region structure and a second type wide active region structure, stacked on top of each other and extending in the first direction, wherein each of the wide complementary field-effect transistor devices includes a first type wide transistor located in the first type wide active region structure and a second type wide transistor located in the second type wide active region structure; and a first type narrow active region structure and a second type narrow active region structure, stacked on top of each other and extending in the first direction, wherein each of the narrow complementary field-effect transistor devices includes a first type narrow transistor located in the first type narrow active region structure and a second type narrow transistor located in the second type narrow active region structure.

[0115] In some embodiments, none of the dwarf cells in the second row of the dwarf cells have any self-aligned vertical interconnects.

[0116] In some embodiments, each self-aligned vertical interconnect connects an upper layer conductor to a lower layer conductor, wherein the upper layer conductor is located in an upper conductor layer above all active region structures, and the lower layer conductor is located in a lower conductor layer below all active region structures.

[0117] In some embodiments, each self-aligned vertical interconnect connects an upper layer conductor to a lower layer conductor, wherein the upper layer conductor is located in an upper conductor layer above all active region structures, and the lower layer conductor is located in a lower conductor layer below all active region structures, wherein each self-aligned vertical interconnect is configured to receive a power supply voltage via the upper layer conductor or via the lower layer conductor.

[0118] In some embodiments, the integrated circuit device includes: a first set of wires extending in the first direction and overlapping the first row of the tall cells; and a second set of wires extending in the first direction and overlapping the second row of the short cells, wherein the first set has more wires than the second set.

[0119] Another aspect of this disclosure relates to an integrated circuit device. The integrated circuit device includes: a substrate; a first type of wide active region structure and a second type of wide active region structure stacked on top of each other at the front side of the substrate, wherein each of the first type of wide active region structure and the second type of wide active region structure extends in a first direction; a first vertical interconnect at least partially embedded in a first side recess and a second vertical interconnect at least partially embedded in a second side recess while extending in a direction perpendicular to the surface of the substrate, wherein each side recess has a boundary surface conformally coated with an insulating material terminating one or more gate conductors intersecting the first type of wide active region structure or the second type of wide active region structure, wherein the first vertical interconnect and the second vertical interconnect are spaced apart from each other by a first distance along the first direction; and a first type of narrow active region structure and a second type of narrow active region structure stacked on top of each other at the front side of the substrate, wherein each of the first type of narrow active region structure and the second type of narrow active region structure extends in the first direction with a uniform width for a distance longer than the first distance.

[0120] In some embodiments, the boundary surface of each side recess terminates with one or more gate conductors that intersect with the first type wide active region structure or the second type wide active region structure.

[0121] In some embodiments, each of the first side groove and the second side groove is at least partially embedded in the first type wide active region structure and the second type wide active region structure.

[0122] In some embodiments, each of the first type wide active region structure and the second type wide active region structure has a uniform width.

[0123] In some embodiments, each of the first type wide active region structure and the second type wide active region structure has a first reduced width in a first segment adjacent to the first side groove, each of the first type wide active region structure and the second type wide active region structure has a second reduced width in a second segment adjacent to the second side groove, and each of the first type wide active region structure and the second type wide active region structure has a wide width in a third segment between the first segment and the second segment.

[0124] In some embodiments, the integrated circuit device further includes: an upper conductor in an upper conductor layer above all active region structures; and a lower conductor in a lower conductor layer below all active region structures, wherein each of the first vertical interconnect and the second vertical interconnect connects one of the upper conductors to one of the lower conductors.

[0125] In some embodiments, each of the first vertical interconnect and the second vertical interconnect is configured to receive a power supply voltage via the upper layer conductor or via the lower layer conductor.

[0126] In some embodiments, the integrated circuit device further includes: a power rail extending in the first direction, wherein, within a range longer than the first distance measured along the first direction, there are no vertical interconnects separating the power rail from the first type of narrow active region structure and the second type of narrow active region structure.

[0127] In some embodiments, the width of the first type wide active region structure is greater than the width of the first type narrow active region structure, and the width of the second type wide active region structure is greater than the width of the second type narrow active region structure.

[0128] In some embodiments, each vertical interconnect is a self-aligned vertical interconnect.

[0129] In some embodiments, the integrated circuit device includes: a row of tall cells having a first type of transistor located in a first type of wide active region structure and a second type of transistor located in a second type of wide active region structure; and a row of short cells having a first type of transistor located in a first type of narrow active region structure and a second type of transistor located in a second type of narrow active region structure, wherein each short cell has no self-aligned vertical interconnect.

[0130] In some embodiments, the integrated circuit device includes: a first set of wires extending in the first direction and overlapping rows of the tall cells; and a second set of wires extending in the first direction and overlapping rows of the short cells, wherein the first set has more wires than the second set.

[0131] Another aspect of this disclosure relates to a method. The method includes fabricating a first-type wide active region structure and a first-type narrow active region structure extending in a first direction. The method also includes fabricating lower gate conductors, each intersecting one of the first-type wide active region structure and the first-type narrow active region structure. The method further includes fabricating a second-type wide active region structure on top of the first-type wide active region structure and a second-type narrow active region structure on top of the first-type narrow active region structure. The method also includes fabricating upper gate conductors, each intersecting one of the second-type wide active region structure and the second-type narrow active region structure. The method further includes etching the first-type wide active region structure and the second-type wide active region structure to form a first side recess and a second side recess spaced apart from each other by a first distance along the first direction, while maintaining each of the first-type narrow active region structure and the second-type narrow active region structure to a uniform width range longer than the first distance. The method further includes trimming and terminating each of the lower gate conductor and the upper gate conductor adjacent to the first side recess or the second side recess at the boundary surface of the first side recess or the second side recess. The method further includes depositing a conformally coated insulating material on the boundary surface of the first side groove and the second side groove. The method also includes depositing a metallic material in the empty space defined by the insulating material on the boundary surface of the first side groove and the second side groove, and filling the empty space with the metallic material, wherein a first vertical interconnect at least partially embedded in the first side groove and a second vertical interconnect at least partially embedded in the second side groove are formed.

[0132] In some embodiments, the method further includes: fabricating a lower conductor in a lower conductor layer below all active region structures; fabricating an upper conductor in an upper conductor layer above all active region structures; and conductively connecting the first vertical interconnect between the first upper conductor and the first lower conductor, and conductively connecting the second vertical interconnect between the second upper conductor and the second lower conductor.

[0133] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. Having read the foregoing specification, those skilled in the art will be able to influence various variations, equivalent substitutions, and various other embodiments widely disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

Claims

1. An integrated circuit device, comprising: A high cell, wherein wide complementary field-effect transistor (CFET) devices are arranged in a first row along a first direction; A low-profile cell, comprising narrow complementary field-effect transistor devices and arranged in a second row along the first direction, the second row being adjacent to the first row, wherein, when measured along a second direction perpendicular to the first direction, the height of the second row having the low-profile cells is less than the height of the first row having the high-profile cells, and wherein at least three low-profile cells consecutively arranged in the second row of the low-profile cells have no self-aligned vertical interconnects; and One or more self-aligned vertical interconnects are located in the first row of the high cells, wherein each of the one or more self-aligned vertical interconnects extending upward in a third direction is at least partially embedded in a side recess adjacent to an active region structure in the high cell of the high cell, the third direction being perpendicular to the first direction and the second direction, and wherein the side recess has a boundary surface conformally coated with an insulating material terminating at least one gate conductor intersecting the active region structure.

2. The integrated circuit device according to claim 1, comprising: A first type of wide active region structure and a second type of wide active region structure are stacked on top of each other and extend in the first direction, wherein each of the wide complementary field-effect transistor devices includes a first type of wide transistor located in the first type of wide active region structure and a second type of wide transistor located in the second type of wide active region structure; and A first type of narrow active region structure and a second type of narrow active region structure are stacked on top of each other and extend in the first direction, wherein each of the narrow complementary field-effect transistor devices includes a first type of narrow transistor located in the first type of narrow active region structure and a second type of narrow transistor located in the second type of narrow active region structure.

3. The integrated circuit device according to claim 1, wherein, None of the dwarf cells in the second row of the dwarf cells have any self-aligned vertical interconnects.

4. The integrated circuit device according to claim 1, wherein, Each self-aligned vertical interconnect connects an upper layer conductor to a lower layer conductor, wherein the upper layer conductor is located in an upper conductor layer above all active region structures, and the lower layer conductor is located in a lower conductor layer below all active region structures.

5. The integrated circuit device according to claim 4, wherein, Each self-aligned vertical interconnect is configured to receive a power supply voltage via the upper layer conductor or via the lower layer conductor.

6. The integrated circuit device according to claim 1, comprising: The first set of wires extends in the first direction and overlaps with the first row of the high cell; as well as The second group of wires extends in the first direction and overlaps with the second row of the short unit, wherein the first group has more wires than the second group.

7. An integrated circuit device, comprising: Substrate; A first type of wide active region structure and a second type of wide active region structure are stacked on top of each other at the front side of the substrate, wherein each of the first type of wide active region structure and the second type of wide active region structure extends in a first direction. A first vertical interconnect, at least partially embedded in a first side recess, and a second vertical interconnect, at least partially embedded in a second side recess, both extend in a direction perpendicular to the surface of the substrate. The second vertical interconnect is at least partially embedded in a second side recess and also extends in a direction perpendicular to the surface of the substrate. Each side recess has a boundary surface conformally coated with an insulating material terminating at one or more gate conductors intersecting the first type of wide active region structure or the second type of wide active region structure. The first vertical interconnect and the second vertical interconnect are separated from each other by a first distance along the first direction. A first type of narrow active region structure and a second type of narrow active region structure are stacked on top of each other at the front side of the substrate, wherein each of the first type of narrow active region structure and the second type of narrow active region structure extends in the first direction with a uniform width for a distance longer than the first distance.

8. The integrated circuit device according to claim 7, wherein, The boundary surface of each side recess terminates at one or more gate conductors that intersect with either the first type of wide active region structure or the second type of wide active region structure.

9. The integrated circuit device according to claim 7, wherein, Each of the first side groove and the second side groove is at least partially embedded in the first type wide active region structure and the second type wide active region structure.

10. A method for manufacturing an integrated circuit, comprising: Manufacturing a first type of wide active region structure and a first type of narrow active region structure extending in a first direction; Fabricate a lower gate conductor, each lower gate conductor intersecting with one of the first type wide active region structure and the first type narrow active region structure; A second type of wide active region structure is fabricated on top of the first type of wide active region structure, and a second type of narrow active region structure is fabricated on top of the first type of narrow active region structure. Fabricate upper gate conductors, each upper gate conductor intersecting with one of the second type wide active region structure and the second type narrow active region structure; The first type of wide active region structure and the second type of wide active region structure are etched to form a first side groove and a second side groove, the first side groove and the second side groove being separated from each other by a first distance along the first direction, while each of the first type of narrow active region structure and the second type of narrow active region structure is kept in a range of uniform width longer than the first distance. At the boundary surface of the first side groove or the second side groove, each of the lower gate conductor and the upper gate conductor adjacent to the first side groove or the second side groove is trimmed and terminated; Conformally coated insulating material is deposited on the boundary surface of the first side groove and the second side groove; as well as Metal material is deposited in an empty space defined by the insulating material on the boundary surfaces of the first side groove and the second side groove, and the empty space is filled with the metal material, thereby forming a first vertical interconnect that is at least partially embedded in the first side groove and a second vertical interconnect that is at least partially embedded in the second side groove.

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