Display device and electronic device

Abstract

A display device and an electronic device are provided. The display device includes: a base substrate having an active area and a peripheral area adjacent to the active area; a circuit element layer including a barrier layer on the base substrate, a plurality of insulating layers on the barrier layer, and a plurality of transistors each including a plurality of conductive patterns between the plurality of insulating layers; a display element layer including a plurality of light emitting elements connected to the plurality of transistors; a plurality of display pads in the peripheral area and connected to the plurality of transistors; a circuit board including a plurality of board pads coupled to the plurality of display pads; and a film layer between the plurality of display pads and the plurality of plate pads, in which a plurality of side surfaces of the plurality of insulating layers define a groove exposing a portion of the barrier layer and between adjacent display pads of the plurality of display pads, and the film layer is in contact with the portion of the barrier layer exposed by the groove.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0091072, filed with the Korean Intellectual Property Office on July 10, 2024, the entire disclosure (e.g., quantity) of each of which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to display devices, and for example, to pad areas of a display device. Additional embodiments relate to electronic devices that include display devices. Background Technology

[0004] The display device includes a display area that is activated in response to an electrical signal. The display device can sense input applied from the outside and can display one or more suitable images to provide information to the user through the display area.

[0005] In display devices, the pads on the display panel and the pads on the circuit board can be connected to each other. Bump-free structures can be applied to the pads on the circuit board to prevent or reduce the possibility of short circuits, etc.

[0006] The information disclosed in this background section is intended to enhance the understanding of the background of this disclosure and may contain information that does not constitute prior art. Summary of the Invention

[0007] One or more embodiments of this disclosure relate to a display device capable of improving the bonding force between the pads of a display panel and the pads of a circuit board in a bumpless structure.

[0008] One or more embodiments of this disclosure relate to a display device capable of improving the bonding strength between the pads of the display panel and the pads of the circuit board and the mechanical strength of the display panel by increasing the contact between the pads of the display panel and the pads of the circuit board in the area adjacent to the pads.

[0009] Additional aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0010] One or more embodiments of this disclosure provide a display device comprising: a base substrate having an active region and a peripheral region adjacent to the active region; a circuit element layer including a barrier layer on the base substrate, a plurality of insulating layers on the barrier layer, and a plurality of transistors each including a plurality of conductive patterns between the plurality of insulating layers; a display element layer including a plurality of light-emitting elements connected to the plurality of transistors; a plurality of display pads in the peripheral region and connected to the plurality of transistors; a circuit board including a plurality of board pads coupled to the plurality of display pads; and a film layer between the plurality of display pads and the plurality of board pads, wherein a plurality of side surfaces of the plurality of insulating layers define grooves that expose portions of the barrier layer and are located between adjacent display pads among the plurality of display pads, and the film layer contacts the portion of the barrier layer exposed by the grooves.

[0011] In one or more embodiments, the multiple side surfaces of the multiple insulating layers defining the groove may be set or predetermined at an angle.

[0012] In one or more embodiments, the multiple side surfaces of the multiple insulating layers defining the groove may be aligned with each other.

[0013] In one or more embodiments, the width (e.g., the width in one direction) of the space between the multiple side surfaces of the multiple insulating layers defining the groove may be increased in a direction away from the base substrate.

[0014] In one or more embodiments, a plurality of display pads may be arranged along a first direction and a second direction intersecting the first direction, each of the plurality of display pads may extend along the second direction, and the display pads arranged sequentially along the first direction may define a pad row.

[0015] In one or more embodiments, the recess includes a plurality of recesses, and each of the plurality of recesses may be arranged in the same row of display pads between adjacent display pads, and the plurality of recesses may be spaced apart and / or separated from each other along a first direction and a second direction (e.g., spaced apart or separated).

[0016] In one or more embodiments, the widths of the plurality of grooves can be measured in a first direction and can vary along a second direction.

[0017] In one or more embodiments, the display device may further include: a plurality of pad lines connecting a plurality of display pads and a plurality of transistors, and may be arranged between the plurality of display pads and a plurality of recesses adjacent to the plurality of display pads, wherein a first width of a first recess among the plurality of recesses may be greater than a second width of a second recess among the plurality of recesses, the first width and the second width are measured along a first direction, and the number of the plurality of pad lines adjacent to the first recess in the first direction may be less than the number of the plurality of pad lines adjacent to the second recess in the first direction.

[0018] In one or more embodiments, the recess may include a plurality of recesses arranged along a first direction, each of the plurality of recesses extending along a second direction, a plurality of display pads arranged sequentially in a plurality of pad rows along the first direction, the plurality of pad rows arranged along the second direction, and when viewed in the first direction, the plurality of recesses may overlap with a plurality of display pads in at least two different pad rows of the plurality of pad rows.

[0019] In one or more embodiments, the plurality of recesses may each include a plurality of sub-recesses spaced apart and / or separated (e.g., spaced apart or separated) from each other along a second direction, and the plurality of sub-recesses of each of the plurality of recesses may be arranged between adjacent display pads arranged in the same row of display pads.

[0020] In one or more embodiments, the plurality of insulating layers may include a buffer layer on the barrier layer and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, and a seventh insulating layer on the buffer layer. One of the plurality of transistors may include a first semiconductor pattern on the buffer layer, a first control electrode on the first insulating layer and overlapping the first semiconductor pattern, and an upper electrode on the second insulating layer and overlapping the first control electrode. Another of the plurality of transistors may include a second semiconductor pattern on the third insulating layer and a second control electrode on the fourth insulating layer and overlapping the second semiconductor pattern. The display device may further include: an input electrode and an output electrode on the fifth insulating layer and connected to the first semiconductor pattern and the second semiconductor pattern through contact holes; and a connection electrode on the sixth insulating layer and connected to the input electrode. At least one of the plurality of light-emitting elements may include a first electrode connected to the connection electrode through contact holes in the seventh insulating layer.

[0021] In one or more embodiments, the display device may further include: an encapsulation layer covering the display element layer, the encapsulation layer including a plurality of inorganic layers and an organic layer between the plurality of inorganic layers; and an input sensor directly on the encapsulation layer, wherein the input sensor may include a first sensing insulating layer on the encapsulation layer, a first conductive layer on the first sensing insulating layer, a second sensing insulating layer on the first sensing insulating layer, a second conductive layer on the second sensing insulating layer, and a third sensing insulating layer on the second sensing insulating layer.

[0022] In one or more embodiments, the plurality of display pads may each include a first pattern on a second insulating layer, a second pattern on the first pattern, a third pattern on the second pattern, and a fourth pattern on the third pattern. The second pattern may be in a first opening that penetrates the second, third, fourth, and fifth insulating layers (e.g., defined by the second, third, fourth, and fifth insulating layers), and the fourth pattern may be in a second opening that penetrates the first and second sensing insulating layers (e.g., defined by the first and second sensing insulating layers).

[0023] In one or more embodiments, the first pattern may include the same material as the first semiconductor pattern, the second pattern may include the same material as the input electrode, the third pattern may include the same material as the connection electrode, and the fourth pattern may include the same material as the second conductive layer.

[0024] In one or more embodiments, the film layer may be an anisotropic conductive film (ACF) comprising a resin and conductive particles within the resin.

[0025] In one or more embodiments, the plurality of display pads may each include a first conductive pattern, an insulating pattern on the first conductive pattern and including a polymer, and a second conductive pattern covering the insulating pattern and having two ends connected to the first conductive pattern, and the second conductive pattern may be in direct contact with the plurality of board pads.

[0026] In one or more embodiments, the film layer may be a non-conductive film (NCF) comprising resin (e.g., resin only).

[0027] In one or more embodiments, the display device may further include: a plurality of dam patterns arranged inside a groove and along a direction extending therefrom the groove, wherein the plurality of dam patterns may comprise the same material as at least one of a plurality of insulating layers.

[0028] In one or more embodiments, the plurality of board pads may each include a first pad layer, a second pad layer disposed below the second pad layer, and a third pad layer disposed below the second pad layer, and the first pad layer, the second pad layer, and the third pad layer may include different materials.

[0029] In one or more embodiments, the first pad layer may include aluminum (Al), the second pad layer may include under-bump metallization (UBM) material, and the third pad layer may include gold (Au).

[0030] One or more embodiments of this disclosure provide an electronic device, including a display device, the display device comprising: a base substrate having an active region and a peripheral region adjacent to the active region; a circuit element layer including a barrier layer on the base substrate, a plurality of insulating layers on the barrier layer, and a plurality of transistors, each including a plurality of conductive patterns between the plurality of insulating layers; a display element layer including a plurality of light-emitting elements connected to the plurality of transistors; a plurality of display pads in the peripheral region and connected to the plurality of transistors; a circuit board including a plurality of board pads coupled to the plurality of display pads; and a film layer between the plurality of display pads and the plurality of board pads, wherein a plurality of side surfaces of the plurality of insulating layers define grooves, the grooves exposing portions of the barrier layer and located between adjacent display pads among the plurality of display pads, and the film layer contacts the portion of the barrier layer exposed by the grooves.

[0031] In one or more embodiments, the electronic device may be a smart watch, a computer including tablet PCs and laptop computers, or a smart TV. Attached Figure Description

[0032] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0033] Figure 1 This is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0034] Figure 2 This is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0035] Figure 3 It is according to one or more embodiments of this disclosure. Figure 2 A cross-sectional view taken from line I-I';

[0036] Figure 4 This is a cross-sectional view of a display device in a bent state, according to one or more embodiments of the present disclosure;

[0037] Figure 5 This is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0038] Figure 6 This is a plan view of an input sensor according to one or more embodiments of the present disclosure;

[0039] Figure 7 This is a cross-sectional view of a portion of a display module according to one or more embodiments of the present disclosure;

[0040] Figure 8 This is a cross-sectional view of a plurality of interconnected pads according to one or more embodiments of the present disclosure;

[0041] Figure 9 This is a cross-sectional view of a plurality of interconnected pads according to one or more embodiments of the present disclosure;

[0042] Figure 10 This is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure;

[0043] Figure 11A It is according to one or more embodiments of this disclosure. Figure 10 A cross-sectional view taken from line I-I';

[0044] Figure 11B It is according to one or more embodiments of this disclosure. Figure 10 A cross-sectional view taken from line II-II';

[0045] Figure 12 It is according to one or more embodiments of this disclosure. Figure 10 A cross-sectional view of multiple pads connected and / or adjacent to each other, taken from line I-I'.

[0046] Figure 13 This is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure;

[0047] Figure 14 This is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure;

[0048] Figure 15 This is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure;

[0049] Figure 16A It is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure; and

[0050] Figure 16B It is according to one or more embodiments of this disclosure. Figure 16A The cross-sectional view taken from line III-III'. Detailed Implementation

[0051] This disclosure may be modified in many alternative forms, and therefore, specific embodiments will be illustrated and described in more detail in the accompanying drawings. However, it should be understood that the specific embodiments are not intended to limit this disclosure to the particular forms disclosed, but are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

[0052] In the following description, exemplary embodiments will be presented in more detail with reference to the accompanying drawings. However, this disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques not essential for a full understanding of the aspects and features of this disclosure by those skilled in the art may not be described.

[0053] It will be understood that when an element, such as a region, layer, membrane, area, or portion, is referred to as being "on," "connected to," or "attached to" another element, that element can be directly on, directly connected to, or directly attached to the other element, or one or more intervening elements may exist. Conversely, when an element or layer is referred to as being "directly on," "directly connected to," "directly attached to," or "adjacent to" another element or layer, no intervening element or layer exists. Furthermore, it will be understood that when an element is referred to as being "between" two elements, that element can be the only element between the two elements, or one or more intervening elements may exist.

[0054] Unless otherwise stated, similar reference numerals denote similar elements throughout the accompanying drawings and written description, and therefore their repeated description is not required. In the drawings, the relative dimensions of elements, layers, and regions may be enlarged for clarity. Additionally, in the drawings, the thickness, scale, and dimensions of elements may be enlarged for effective depiction of the technical content.

[0055] As used herein, the term “and / or” includes any and all combinations of one or more of the relevant listed items.

[0056] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or section from another. Therefore, the first element, component, area, layer, or section discussed below may be referred to as the second element, component, area, layer, or section without departing from the spirit and scope of this disclosure.

[0057] Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to also include the plural forms.

[0058] For ease of explanation, spatial relative terms such as “on,” “below,” “lower,” “under,” “above,” and “upper” may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s) or feature(s). It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the example terms “below” and “under” can encompass both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0059] It will also be understood that the terms “comprise,” “comprising,” “include,” “including,” “have,” and “having,” when used in this specification, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Additionally, the terms “comprise(s) / comprising,” “include(s) / including,” “have / has / having,” or similar terms include or support the terms “consisting of” and “consisting essentially of,” thereby indicating the presence of the stated features, integrals, steps, operations, elements, and / or components, while other features, integrals, steps, operations, elements, components, and / or groups thereof are absent or substantially absent.

[0060] Unless otherwise expressly stated in this disclosure, expressions such as “at least one of…”, “multiple…”, “one of…” and other prepositional phrases, when written as a connecting list before or after a list of elements, should be understood to include antonymous conjunctions, and vice versa. For example, expressions such as “at least one of a, b and c”, “choose one of the group consisting of a, b and c”, “selected from at least one of a, b and c”, “at least one of a, b and c”, “one of a, b and c”, “at least one of a to c” indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0061] As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0062] In the context of this disclosure and unless otherwise specified, a plan view is an orthographic projection of the object onto a three-dimensional surface from a position on a horizontal plane. That is, a plan view is a top-down view showing the layout and spatial relationships of various elements within an object or structure. A plan view based on a third direction DR3 refers to a top-down view of the display panel, as if looking directly down at the surface from above. In this context, the third direction DR3 is a direction perpendicular to or normal to the plane defined by the first direction DR1 and the second direction DR2. This means that in the plan view, subpixels, pads, and other components can be observed as if they were laid out on the substrate without any perspective distortion.

[0063] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, unless expressly defined herein, terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and shall not be interpreted in an idealized or overly formal sense.

[0064] Embodiments of this disclosure will be described below with reference to the accompanying drawings. Figure 1 This is a perspective view of a display device according to one or more embodiments of the present disclosure. Figure 2 This is an exploded perspective view of a display device according to one or more embodiments of the present disclosure. Figure 3 It is according to one or more embodiments of this disclosure. Figure 2 The cross-sectional view taken from line I-I'.

[0065] refer to Figures 1 to 3 The electronic device ED can be activated in response to an electrical signal. The electronic device ED may include one or more suitable embodiments. For example, the electronic device ED may be (e.g., may include) a display device, such as a smart watch, a computer (e.g., a tablet PC, a laptop computer), and a smart TV.

[0066] The electronic device ED can display an image IM on a third direction DR3 on a display surface IS parallel to each of the first direction DR1 and the second direction DR2. The display surface IS on which the image IM is displayed may correspond to the front surface of the electronic device ED. The image IM may include still images and moving images.

[0067] In one or more embodiments, the front (or upper) surface and rear (or lower) surface of each of the plurality of components are defined based on a third-party direction DR3 on which an image IM is displayed. The front and rear surfaces are opposite to each other on the third-party direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third-party direction DR3.

[0068] The distance between the front and rear surfaces in the third direction DR3 corresponds to the thickness of the electronic device ED in the third direction DR3. In this disclosure, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be changed to other directions.

[0069] The electronic device ED can sense external input applied from the outside. External input may include one or more suitable forms of input provided from the outside. For example, external input may include not only external input such as contact through a body part (such as a user's hand), but also external input applied close to or adjacent to the electronic device ED at a set or predetermined distance (e.g., hovering). In one or more embodiments, external input may include one or more suitable forms such as force, pressure, temperature, and light.

[0070] The display surface IS of the electronic device ED can be divided into a transmissive area TA and a border area BZA. The transmissive area TA can be the area in which the image IM is displayed. The user views the image IM through the transmissive area TA. In one or more embodiments, for example, as Figure 1 As shown, the transmission region TA may have a quadrilateral shape with rounded vertices. However, this is illustrated as an example, and the transmission region TA may have one or more suitable shapes and is not limited to any one embodiment.

[0071] The border area BZA is adjacent to the transmissive area TA. The border area BZA may have a set or predetermined color. The border area BZA may surround (e.g., encircle) the transmissive area TA. Therefore, the shape of the transmissive area TA may be substantially defined by the border area BZA. However, this is illustrated as an example, and the border area BZA may be arranged to be adjacent only to one or more sides of the transmissive area TA, or may not be provided. An electronic device ED according to one or more embodiments of this disclosure may include one or more suitable modifications and is not limited to any one embodiment.

[0072] Electronic device ED may include display device DD and housing EDC (or enclosure). Display device DD may include window WM, display module DM, drive module EM, optical film OTF, and lower module LM. Display module DM may include display panel DP and input sensor ISP disposed on display panel DP. Display panel DP generates image IM, and input sensor ISP obtains coordinate information about external input (e.g., touch event).

[0073] The window WM may include a transparent material through which an image IM can be emitted. For example, the window WM may include glass, sapphire, plastic, etc. The window WM is illustrated as a single layer, but this disclosure is not limited thereto and may include multiple layers. In one or more embodiments, the bezel area BZA of the above-described display device DD may be substantially provided as including an area in which a material of a set or predetermined color is printed in one area of ​​the window WM.

[0074] The display module DM may include a display panel DP and an input sensor ISP. The display panel DP according to one or more embodiments of this disclosure may be an emitting display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The emitting layer of an organic light-emitting display panel may include organic light-emitting materials, and the emitting layer of an inorganic light-emitting display panel may include inorganic light-emitting materials. The emitting layer of a quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0075] The input sensor ISP can be "directly disposed" on the display panel DP. According to one or more embodiments of this disclosure, the input sensor ISP can be formed on the display panel DP through a substantially continuous process. For example, in an embodiment where the input sensor ISP is directly disposed on the display panel DP, the adhesive film for connecting the input sensor ISP and the display panel DP is not disposed between the input sensor ISP and the display panel DP.

[0076] An optical film OTF reduces the reflection of external light incident from above a window WM. An optical film OTF according to one or more embodiments of this disclosure may include a retarder and a polarizer. The retarder may be a film-type retarder or a liquid crystal coating-type retarder, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film-type retarder or a liquid crystal coating-type retarder. The film-type may include a stretchable synthetic resin film, and the liquid crystal coating-type may include liquid crystals arranged in a set or predetermined arrangement. The retarder and polarizer may be implemented as a single polarizing film. The optical film OTF may also include a protective film disposed above or below the polarizing film.

[0077] An optical film (OTF) can be disposed on the input sensor (ISP). For example, the OTF can be disposed between the input sensor (ISP) and the window (WM). The input sensor (ISP), the OTF, and the window (WM) can be connected to each other via an adhesive layer.

[0078] refer to Figure 3 An optical adhesive layer AF1 is disposed between the input sensor ISP and the optical film OTF, and a window adhesive layer AF2 is disposed between the optical film OTF and the window WM. Therefore, the optical film OTF is connected to the input sensor ISP through the optical adhesive layer AF1, and the window WM is connected to the optical film OTF through the window adhesive layer AF2.

[0079] As an example of this disclosure, optical adhesive layer AF1 and window adhesive layer AF2 may each comprise an optically clear adhesive (OCA) film. However, the material of each of optical adhesive layer AF1 and window adhesive layer AF2 is not limited thereto, and may include any suitable, generally available, and / or commonly used adhesive or bonding agent. For example, optical adhesive layer AF1 and window adhesive layer AF2 may each comprise a pressure-sensitive adhesive (PSA), an optically clear adhesive (OCA), or an optically clear resin (OCR).

[0080] In addition to the optical film OTF, functional layers that perform different functions (e.g., protective layers) can also be arranged between the display module DM and the window WM.

[0081] The display module DM can display an image IM in response to an electrical signal and can send and / or receive information about external inputs. The display module DM can be defined as an active area AA and a peripheral area NAA. The active area AA can be defined as the area in which the image IM from the display module DM is provided.

[0082] The peripheral region NAA is adjacent to the active region AA. For example, the peripheral region NAA may surround (e.g., encircle) the active region AA. However, this is illustrated as an example, and the peripheral region NAA may be defined in one or more suitable shapes and is not limited to any one embodiment. According to one or more embodiments, the active region AA of the display module DM may correspond to at least a portion of the transmissive region TA.

[0083] According to embodiments of this disclosure, the display module DM may include a first region A1, a second region A2, and a third region A3 arranged along a second direction DR2. The first region A1 may include a portion of the peripheral region NAA and the active region AA, and the second region A2 and the third region A3 may include the remaining portions of the peripheral region NAA. The second region A2 may be a curved region bent relative to a bending axis, and the first region A1 and the third region A3 may each be a non-curved region.

[0084] The length of each of the second region A2 and the third region A3 in the first direction DR1 may be less than or equal to the length of the first region A1 in the first direction DR1. Since the display module DM according to the embodiment of this disclosure includes a region with a relatively small length that is bent relative to the bending axis, the second region A2 can be bent more easily. The third region A3 may be arranged below the first region A1 and housed in the housing EDC in the bent state of the second region A2.

[0085] The driving module EM controls the driving of the display module DM. The driving module EM may include a flexible circuit film (e.g., a flexible circuit board) FCB and a driving chip DIC. The flexible circuit film FCB may be electrically connected to the display panel DP. The flexible circuit film FCB may be attached to the end of the third region A3 of the display module DM via a bonding process. The flexible circuit film FCB may be electrically connected to the display module DM via an anisotropic conductive adhesive layer. The driving chip DIC may be mounted on the third region A3 of the display module DM. The driving chip DIC may include driving circuitry, such as data driving circuitry for driving the pixels of the display panel DP.

[0086] According to one or more embodiments, the flexible circuit membrane FCB may include a grounding wire for discharging static electricity introduced into the flexible circuit membrane FCB or into the input sensor ISP.

[0087] The driving module EM may also include multiple driving elements mounted on the flexible circuit film FCB. These driving elements may include circuitry units for converting externally input signals into signals for driving the DIC chip or for driving the display module DM. When the second region A2 and the third region A3 of the display module DM are bent, the flexible circuit film FCB may be positioned below the display module DM.

[0088] The lower module LM can be disposed on the rear surface of the display module DM. If the lower module LM is disposed on the rear surface of the display module DM (for example, when the lower module LM is disposed on the rear surface of the display module DM), the lower module LM can improve the impact resistance of the display device DD. The lower module LM can be fixed to the rear surface of the display module DM by an adhesive layer.

[0089] When the second region A2 and the third region A3 of the display module DM are bent, the third region A3 of the display module DM and the flexible circuit film FCB can be arranged on the rear surface of the lower module LM.

[0090] The housing EDC can be attached to the window WM to define the exterior of the electronic device ED. The housing EDC houses the display device DD. The housing EDC protects the components housed within it by absorbing impacts applied from the outside and preventing or reducing the infiltration of foreign objects / moisture into the electronic device ED (e.g., protecting the electronic device ED from the effects of foreign objects / moisture). In one or more embodiments, the housing EDC may be provided in the form of multiple housing members connected to each other.

[0091] Figure 4 This is a cross-sectional view of a display device in which the display panel is bent, according to one or more embodiments of the present disclosure. Figure 4 This is a cross-sectional view of the portion of the display device DD adjacent to the second region A2, in which the second region A2 is bent relative to the bending axis AX extending along the first direction DR1.

[0092] The display device DD may include a window WM, an optical film OTF, a display module DM, and a lower module LM. The lower module LM may include a first protective member PF1, a second protective member PF2, and a functional layer MP.

[0093] A window WM according to one or more embodiments may include a base portion WB, a hard coating HC, and a border pattern BP. The base portion WB may include an optically transparent insulating material. For example, the base portion WB may include a glass substrate or a synthetic resin film. The hard coating HC for protecting the base portion WB may be disposed on the front and / or rear surfaces of the base portion WB. The hard coating HC can prevent or reduce the possibility of damage to the base portion WB due to scratches, etc. In one or more embodiments, an anti-fingerprint layer may also be disposed on the base portion WB.

[0094] The border pattern BP defines the border area BZA of the window WM (for example, see...). Figure 1 The border pattern BP can be arranged adjacent to the edge of the back surface of the base part WB.

[0095] The border pattern BP can be a colored layer formed by a coating method. The border pattern BP can include a polymer resin and a pigment mixed with the polymer resin. The polymer resin can be, for example, an acrylic resin or a polyester, and the pigment can be a carbon-based pigment.

[0096] An optical film OTF can be placed below the window WM. The optical film OTF reduces the reflection of external light incident from the window WM. The window WM and the optical film OTF can be connected to each other via the window adhesive layer AF2. The display module DM and the optical film OTF can be connected to each other via the optical adhesive layer AF1.

[0097] The lower module LM may include a first protective member PF1, a functional layer MP, and a second protective member PF2. The lower module LM may be arranged between the first region A1 and the third region A3 with the second region A2 bent. The lower module LM and the display module DM may be connected to each other through a first adhesive layer AM1.

[0098] The functional layer MP may be disposed below the first protective member PF1. The functional layer MP and the first protective member PF1 may be connected to each other via a second adhesive layer AM2. The functional layer MP may be provided in a plate shape (e.g., it may be substantially flat). The functional layer MP may include multiple layers. For example, the functional layer MP may include a light-blocking layer, a heat-dissipating layer, a padding layer, and multiple adhesive layers.

[0099] A light-blocking layer can be used to eliminate and / or resolve the problem that components arranged in the display module DM are visible through the window WM in the active area AA. The light-blocking layer may include a binder and a plurality of pigment particles dispersed therein. The pigment particles may include carbon black, etc. Because the electronic device ED according to one or more embodiments includes a light-blocking layer, the electronic device ED may have the effect of improving light-shielding properties.

[0100] The heat dissipation layer can effectively dissipate the heat generated in the display module DM. The heat dissipation layer may include at least one of aluminum (Al), copper (Cu), and graphite, which have excellent or suitable heat dissipation properties. However, this disclosure is not limited thereto. The heat dissipation layer can not only improve heat dissipation characteristics but also have electromagnetic wave shielding or electromagnetic wave absorption properties.

[0101] The underlayment may be a synthetic resin foam. The underlayment may include a matrix and multiple pores. The underlayment may have an elastic and porous structure.

[0102] The matrix may include a flexible material. The matrix may include a synthetic resin. For example, the matrix may include at least one of acrylonitrile butadiene styrene copolymer (ABS), polyurethane (PU), polyethylene (PE), ethylene vinyl acetate (EVA), and polyvinyl chloride (PVC). Multiple pores can absorb (e.g., readily absorb) impacts applied to the padding layer. Because the padding layer has a porous structure, multiple pores can be defined.

[0103] According to one or more embodiments, at least one of the light-blocking layer, heat-dissipating layer, and padding layer included in the functional layer MP may not be provided, and / or multiple layers may be provided as a single layer. However, this disclosure is not limited to any one embodiment.

[0104] The functional layer MP and the second protective member PF2 can be connected to each other via the third adhesive layer AM3. The second protective member PF2 can be arranged on the rear surface of the display module DM, which overlaps with the third area A3 and the first area A1 in the plan view. The display module DM and the second protective member PF2 can be connected to each other via the fourth adhesive layer AM4.

[0105] An electronic device ED according to one or more embodiments may include a protective layer RM. The protective layer RM may be disposed in an internal space defined at the rear surface of the display module DM that overlaps with the second region A2 if the display module DM is bent (e.g., when the display module DM is bent), the side surface of the first protective member PF1, the side surface of the functional layer MP, the side surface of the second protective member PF2, and the side surface of each of the first adhesive layer AM1, the second adhesive layer AM2, the third adhesive layer AM3, and the fourth adhesive layer AM4.

[0106] Because the protective layer RM is disposed within the internal space, it supports the display module DM, allowing the shape of the second region A2 to be maintained when the display module DM is bent. For example, the protective layer can provide a support structure to support and provide the bent shape of the display module DM around the bending axis AX when the display module DM is bent, and to support the structural integrity of the display module DM. In one or more embodiments, the protective layer RM can prevent or reduce the possibility of foreign objects or the like being introduced into the display module DM through the second region A2 (e.g., protecting the display module DM from the influence of foreign objects or the like). The protective layer RM according to one or more embodiments may comprise resin.

[0107] The display panel DP according to one or more embodiments may further include a bending cover layer disposed on the second region A2. The bending cover layer can reduce the stress applied to the second region A2 when the second region A2 is bent, and can protect the second region A2.

[0108] The display device DD according to one or more embodiments may further include a conductive film CV disposed in the third region A3. The conductive film CV may cover the driver chip DIC to prevent or reduce damage to the driver chip DIC by externally introduced static electricity, and / or prevent or reduce the possibility of foreign objects being introduced into the driver chip DIC (e.g., protecting the driver chip DIC from the influence of foreign objects). In one or more embodiments, the conductive film CV may prevent or reduce the possibility of impacts being applied to the driver chip DIC and / or affecting the driver chip DIC.

[0109] Figure 5This is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0110] According to one or more embodiments of the present disclosure, the display panel DP can be divided into a first zone A1, a second zone A2 and a third zone A3 arranged along a second direction DR2. Figure 5 The first area A1, the second area A2, and the third area A3 of the display panel DP shown in the diagram are respectively related to the reference. Figure 2 The first zone A1, the second zone A2, and the third zone A3 of the described display module DM correspond to each other. As used herein, the term "zone / part corresponding to zone / part" means that the zones / parts overlap, and is not limited to meaning that the zones / parts have the same area.

[0111] A display panel DP according to one or more embodiments may include an active region AA in which pixels PX (e.g., a plurality of pixels PX) are arranged, and a peripheral region NAA adjacent to the active region AA. The active region AA and the peripheral region NAA are respectively connected to a reference. Figure 2 The active region AA and the peripheral region NAA are described in relation to each other. The active region AA corresponds to the area of ​​the first region A1 in which pixels PX are arranged, and the peripheral region NAA is defined as the remaining area excluding the area in which pixels PX are arranged.

[0112] The first region A1 may include a portion of the outer region NAA and the active region AA, and the second region A2 and the third region A3 may include the remaining portion of the outer region NAA.

[0113] The display panel (DP) may include a scan driver (SDV), a transmit driver (EDV), display pads (PD), and a driver chip (DIC) in the peripheral area (NAA). In one or more embodiments, the driver chip (DIC) may be a data driver.

[0114] The display panel (DP) may include multiple pixels (PX), multiple scan lines (SL1 to SLm), multiple data lines (DL1 to DLn), multiple emission lines (EL1 to ELm), a first control line (CSL1) and a second control line (CSL2), a power line (PL), and multiple display pads (PD). Here, m and n are natural numbers. Pixels (PX) may be connected to scan lines (SL1 to SLm), data lines (DL1 to DLn), and emission lines (EL1 to ELm).

[0115] Scan lines SL1 to SLm can extend along the first direction DR1 and can be connected to the scan driver SDV. For example, as in Figure 5 As shown, data lines DL1 to DLn in the first region A1 can extend in the second direction DR2 and can be connected to the driver chip DIC arranged in the second region A2. However, this disclosure is not limited thereto, and the driver chip DIC can be located in the third region A3 and can be connected via the second region A2 (e.g., see...). Figure 2Data lines DL1 to DLn are connected to the first zone A1. Transmit lines EL1 to ELm can extend in the first direction DR1 and can be connected to the transmit driver EDV.

[0116] The power line PL may include a portion extending in a first direction DR1 and a portion extending in a second direction DR2. The portions extending in the first direction DR1 and the second direction DR2 may be arranged on different layers. The portion of the power line PL extending in the second direction DR2 may extend from a first region A1 via a second region A2 to a third region A3. The power line PL can provide a reference voltage to the pixel PX.

[0117] The first control line CSL1 can be connected to the scan driver SDV and can extend from the first zone A1 via the second zone A2 to the third zone A3. The second control line CSL2 can be connected to the transmit driver EDV and can extend from the first zone A1 via the second zone A2 to the third zone A3.

[0118] Display pads (PDs) can be arranged within display pad areas (PDAs). Display pads (PDs) can be arranged adjacent to the end of the third area (A3) in the second direction (DR2). Driver chip (DIC), power line (PL), first control line (CSL1), and second control line (CSL2) can be connected to display pads (PDs). Flexible circuit film (FCB) can overlap with the end of the third area (A3) of display panel (DP) and can be arranged on display panel (DP). Board pads (FDs) can be arranged within the board pad area (FDA) of flexible circuit film (FCB). Board pads (FDs) can overlap display pads (PDs) one-to-one. Board pads (FDs) can be electrically connected to display pads (PDs) via anisotropic conductive film (ACF) or non-conductive film (NCF), which will be described in more detail later.

[0119] According to one or more embodiments, the display pad PD and board pad FD can be arranged to be spaced apart and / or separated (e.g., spaced apart or separated) along a first direction DR1 and a second direction DR2. Figure 5 The illustration shows that the display pads (PD) and board pads (FD) are each arranged in three rows, but the number of display pads (PD), the number of board pads (FD), and the arrangement of display pads (PD) and board pads (FD) are not limited to any one embodiment.

[0120] According to one or more embodiments, a pad line PD-L connecting the driver chip DIC and the display pad PD may also be included. The pad line PD-L may extend from the active area AA through the second area A2 to the display pad area PDA. The pad line PD-L connecting the driver chip DIC and the display pad PD is not limited to any one embodiment, as long as the pad line PD-L is a line connected to the pad.

[0121] The display panel DP according to one or more embodiments may include a first contact hole CN-H1 defined in a first region A1. The display panel DP may include an extension trace TL-L. The extension trace TL-L may extend via the first region A1 and the second region A2 to a third region A3. The extension trace TL-L may be connected through the first contact hole CN-H1 and in a one-to-one manner to corresponding traces among the first trace TL1, the second trace TL2, and the third trace TL3, which will be described in more detail later (e.g., see...). Figure 6 For example, one end of each of the plurality of extended traces TL-L may be exposed from the first contact hole CN-H1 and may be connected to the first trace TL1, the second trace TL2, and the third trace TL3 (see, for example, see...). Figure 6 Furthermore, the other end of each of the multiple extended traces TL-L can be connected to the display pad PD.

[0122] Figure 5 The illustration shows an extension trace TL-L arranged between data lines DL1 to DLn, but this disclosure is not limited thereto, and data lines DL1 to DLn may be arranged between multiple extension traces TL-L. In one or more embodiments, a first contact hole CN-H1 may be provided as a plurality of contact holes having data lines DL1 to DLn therebetween.

[0123] Figure 6 This is a plan view of an input sensor according to one or more embodiments of the present disclosure.

[0124] refer to Figure 6 An input sensor ISP according to one or more embodiments may include a first sensing electrode TE1 and a second sensing electrode TE2, as well as a first trace TL1, a second trace TL2, and a third trace TL3. In embodiments where the input sensor ISP is formed directly on the display panel DP through a substantially continuous process, the first sensing electrode TE1 and the second sensing electrode TE2 may be formed only in the active region AA, thereby overlapping with the first region A1 of the display panel DP.

[0125] The input sensor ISP can obtain information about external inputs by measuring the change in capacitance between the first sensing electrode TE1 and the second sensing electrode TE2. Multiple first sensing electrodes TE1 are arranged along a first direction DR1 and each extends along a second direction DR2. Each of the multiple first sensing electrodes TE1 may include a first sensing pattern SP1 and a first connection pattern CP1.

[0126] A first sensing pattern SP1 is arranged in the active region AA. The first sensing pattern SP1, included in a first sensing electrode TE1, may be arranged along a second direction DR2. The first sensing pattern SP1 may have a rhomboid shape. However, this is illustrated as an example, and the first sensing pattern SP1 may have one or more suitable shapes and is not limited to any one embodiment.

[0127] The first connection pattern CP1 is arranged in the active region AA. The first connection pattern CP1 can be arranged along the second direction DR2 between adjacent first sensing patterns SP1. The first connection pattern CP1 and the first sensing pattern SP1 can be arranged on different layers and can be connected through contact holes.

[0128] Multiple second sensing electrodes TE2 are arranged along a second direction DR2 and each extends along a first direction DR1. Each of the multiple second sensing electrodes TE2 may include a second sensing pattern SP2 and a second connection pattern CP2.

[0129] The second sensing pattern SP2 may be separated from and / or isolated from the first sensing pattern SP1 (e.g., spaced apart or separated). The first sensing pattern SP1 and the second sensing pattern SP2 may transmit and receive independent electrical signals without contacting each other.

[0130] A second sensing pattern SP2 is disposed in the active region AA. The second sensing pattern SP2, included in a second sensing electrode TE2, may be disposed along a first direction DR1. The second sensing pattern SP2 may have the same shape as the first sensing pattern SP1. For example, the second sensing pattern SP2 may have a rhomboid shape. However, this is illustrated as an example, and the second sensing pattern SP2 may have one or more suitable shapes and is not limited to any particular embodiment.

[0131] The second connection pattern CP2 may be arranged between adjacent second sensing patterns SP2. The second sensing pattern SP2 and the second connection pattern CP2, which are substantially included in a second sensing electrode TE2, may be formed as an integral shape or as an integral pattern.

[0132] According to one or more embodiments, the first sensing pattern SP1, the second sensing pattern SP2, and the second connecting pattern CP2 may be arranged on the same layer, and the first connecting pattern CP1 may be arranged on a different layer. The first sensing pattern SP1, the second sensing pattern SP2, and the second connecting pattern CP2 may be provided as a plurality of grid lines extending in the diagonal direction of each of the first direction DR1 and the second direction DR2.

[0133] The first trace TL1, the second trace TL2, and the third trace TL3 are arranged in the outer region NAA.

[0134] In one or more embodiments, each first sensing electrode TE1 may be connected at one end to a first trace TL1 and at the other opposite end along a second direction DR2 to a second trace TL2. For example, one end of each of the plurality of first traces TL1 may be connected to a corresponding one of the plurality of first sensing electrodes TE1. In one or more embodiments, each of the plurality of first traces TL1 is connected to the lower end of one of the two ends of each of the plurality of first sensing electrodes TE1. One end of each of the plurality of second traces TL2 is connected to the upper end of one of the two ends of each of the plurality of first sensing electrodes TE1. According to embodiments of the present disclosure, a first sensing electrode TE1 may be connected to both the first trace TL1 and the second trace TL2. Therefore, a first sensing electrode TE1 having a relatively large length compared to a second sensing electrode TE2 can maintain region-dependent sensitivity uniformly (e.g., substantially uniformly).

[0135] However, this is illustrated as an example, and in an input sensor ISP according to one or more embodiments of the present disclosure, either the first trace TL1 or the second trace TL2 may not be provided, and the present disclosure is not limited to any one embodiment.

[0136] In one or more embodiments, each second sensing electrode TE2 may be connected to a third trace TL3. For example, one end of each of the plurality of third traces TL3 may be connected to a corresponding one of the plurality of second sensing electrodes TE2. In one or more embodiments, the third trace TL3 is connected to the left end of one of the two ends of each of the plurality of second sensing electrodes TE2 along the first direction DR1.

[0137] A second contact hole CN-H2, defined by penetrating at least one of a plurality of insulating layers included in the input sensor ISP, may be defined in the input sensor ISP. The second contact hole CN-H2 may overlap with the first contact hole CN-H1 defined in the first area A1 of the display panel DP.

[0138] The other end of each of the first trace TL1, the second trace TL2, and the third trace TL3 may be disposed in the second contact hole CN-H2. The other end of each of the first trace TL1, the second trace TL2, and the third trace TL3 disposed in the second contact hole CN-H2 may be connected to a plurality of extended traces TL-L (e.g., see...). Figure 5 The corresponding one in ) . The first trace TL1, the second trace TL2 and the third trace TL3 can be arranged in the display panel DP (e.g., see Figure 5 The extended trace TL-L in the ) is connected to the display pad PD (for example, see Figure 5 ).

[0139] Figure 7This is a cross-sectional view of a portion of a display module according to one or more embodiments of the present disclosure.

[0140] Figure 7 The diagram illustrates the relationship between pixels PX (for example, see...). Figure 5 The cross-sections of the first transistor T1, the second transistor T2, and the light-emitting element OLED are partially configured. Although Figure 7 The diagram illustrates an OLED light-emitting element and its associated circuitry, structure, and arrangement; however, the remaining light-emitting elements of the display panel DP may have similar characteristics to those shown in the reference diagram. Figure 7 The configurations described in the embodiments are the same or similar.

[0141] The display panel DP may include a base substrate BL, a circuit element layer DP-CL disposed on the base substrate BL, a display element layer DP-OLED, and a packaging layer TFE. The display panel DP may also include functional layers such as an anti-reflective layer and a refractive index adjustment layer. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. In the following, the insulating layers may include organic layers and / or inorganic layers.

[0142] The circuit elements include signal lines, pixel driving circuits, etc. The circuit element layer DP-CL can be formed through processes such as coating and deposition to form insulating, semiconductor, and conductive layers, as well as through photolithography to pattern the insulating, semiconductor, and conductive layers. The display element layer DP-OLED may include the light-emitting element OLED and the pixel-defining film PDL.

[0143] The base substrate BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. For example, the synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one selected from acrylic resins, methacrylic resins, polyisoprene-based resins, vinyl resins, epoxy resins, urethane-based resins, cellulose-based resins, siloxane-based resins, polyamide-based resins, and perylene-based resins. In one or more embodiments, the base substrate BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc.

[0144] The base substrate BL according to one or more embodiments may include a first base layer, a first capping layer, a second base layer, and a second capping layer stacked sequentially along a third direction DR3. The first base layer and the second base layer may include organic materials, and the first capping layer and the second capping layer may include inorganic materials.

[0145] A light-blocking pattern BML may be disposed on a base substrate BL. The light-blocking pattern BML may block or reduce the potential influence of polarization phenomena on the first transistor T1. In one or more embodiments, the light-blocking pattern BML may block or reduce external light reaching the first transistor T1. In one or more embodiments of this disclosure, the light-blocking pattern BML may be a floating electrode isolated from another electrode or line. The light-blocking pattern BML may include molybdenum. According to one or more embodiments, a light-blocking pattern BML may not be provided.

[0146] A barrier layer (BRL) may be disposed on a light-blocking pattern (BML). The barrier layer (BRL) prevents or reduces the possibility of foreign matter being introduced from the outside (e.g., protecting the light-blocking pattern (BML) from foreign matter). The barrier layer (BRL) may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in multiples, and the silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0147] A buffer layer (BFL) can be disposed on a barrier layer (BRL). The buffer layer (BFL) can improve the adhesion between the base substrate (BL) and the conductive or semiconductor pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0148] A first semiconductor pattern OSP1 is disposed on a buffer layer BFL. The first semiconductor pattern OSP1 may include a silicon semiconductor. The first semiconductor pattern OSP1 may be a polycrystalline silicon semiconductor. However, this disclosure is not limited thereto, and the first semiconductor pattern OSP1 may include amorphous silicon.

[0149] The first semiconductor pattern OSP1 may include an input region (or a first portion), an output region (or a second portion), and a channel region (or a third portion) between the input and output regions. The channel region of the first semiconductor pattern OSP1 may be defined corresponding to a first control electrode GE1, which will be described in more detail later. The input and output regions are doped with dopants and have relatively high conductivity compared to the channel region. The input and output regions may be doped with n-type dopants. In one or more embodiments, an n-type first transistor T1 is described as an example, but the first transistor T1 may be a p-type transistor.

[0150] A first insulating layer 10 is disposed on a buffer layer BFL. The first insulating layer 10 is associated with a plurality of pixels PX (e.g., see...). Figure 2The first insulating layer 10 is commonly overlapped (e.g., all overlaps with a plurality of pixels PX as a common and continuous layer) and covers the first semiconductor pattern OSP1. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In one or more embodiments, the first insulating layer 10 may be a single-layer silicon oxide layer.

[0151] The first control electrode GE1 is disposed on the first insulating layer 10. The first control electrode GE1 may overlap with the channel region of the first semiconductor pattern OSP1.

[0152] A second insulating layer 20 covering the first control electrode GE1 is disposed on the first insulating layer 10. The second insulating layer 20 is disposed on the plurality of pixels PX (e.g., see...). Figure 1 The second insulating layer 20 may be an inorganic and / or organic layer, and may have a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In one or more embodiments, the second insulating layer 20 may be a single-layer silicon oxide layer.

[0153] The upper electrode UE can also be disposed on the second insulating layer 20. The upper electrode UE can overlap with the first control electrode GE1.

[0154] The lower control electrode GE2-B of the second transistor T2 can also be disposed on the second insulating layer 20. The lower control electrode GE2-B can overlap with the second semiconductor pattern OSP2. The lower control electrode GE2-B can form a dual gate with the upper control electrode GE2-U.

[0155] A third insulating layer 30 covering the upper electrode UE and the lower control electrode GE2-B may be disposed on the second insulating layer 20. The third insulating layer 30 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The third insulating layer 30 may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In one or more embodiments, the third insulating layer 30 may be a single-layer silicon oxide layer.

[0156] The second semiconductor pattern OSP2 may be disposed on the third insulating layer 30. The second semiconductor pattern OSP2 may include an oxide semiconductor. The second semiconductor pattern OSP2 may include a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the oxide semiconductor may include metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), and / or metal mixtures (e.g., any suitable) such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), and / or oxides thereof. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), etc.

[0157] The second semiconductor pattern OSP2 may include an input region (or a first portion), an output region (or a second portion), and a channel region (or a third portion) between the input and output regions. Impurities may be included (doped) in the input and output regions. The channel region of the second semiconductor pattern OSP2 may be defined corresponding to the upper control electrode GE2-U, which will be described in more detail later.

[0158] The impurities in the second semiconductor pattern OSP2 can be reduced metallic materials. The input and output regions can include metallic materials reduced from the metal oxide (or multiple metal oxides) constituting the channel region. Therefore, the second transistor T2 can reduce leakage current and thus can be used as a switching element with improved switching characteristics.

[0159] A fourth insulating layer 40 covering the second semiconductor pattern OSP2 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0160] The upper control electrode GE2-U can be disposed on the fourth insulating layer 40. The upper control electrode GE2-U overlaps with the second semiconductor pattern OSP2.

[0161] The fifth insulating layer 50 covering the control electrode GE2-U may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The fifth insulating layer 50 may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0162] A first input electrode SE1, a first output electrode DE1, a second input electrode SE2, and a second output electrode DE2 are disposed on a fifth insulating layer 50. The first input electrode SE1 and the first output electrode DE1 are connected to the first semiconductor pattern OSP1 via a first contact hole CH1 and a second contact hole CH2 that expose the input and output regions of the first semiconductor pattern OSP1, respectively. The first contact hole CH1 and the second contact hole CH2 penetrate the first insulating layer 10 to the fifth insulating layer 50.

[0163] The second input electrode SE2 and the second output electrode DE2 are connected to the second semiconductor pattern OSP2 through the third contact hole CH3 and the fourth contact hole CH4, which expose the input and output regions of the second semiconductor pattern OSP2, respectively. The third contact hole CH3 and the fourth contact hole CH4 penetrate the fourth insulating layer 40 and the fifth insulating layer 50.

[0164] The display panel DP according to one or more embodiments may further include a control bridging pattern BBP disposed on a fourth insulating layer 40. The control bridging pattern BBP may branch from a portion of the upper control electrode GE2-U. The control bridging pattern BBP may be connected to the lower control electrode GE2-B through a fifth contact hole CH5. The fifth contact hole CH5 penetrates the third insulating layer 30 and the fourth insulating layer 40.

[0165] A sixth insulating layer 60, covering the first input electrode SE1, the first output electrode DE1, the second input electrode SE2, and the second output electrode DE2, is disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer and may have a single-layer structure or a multi-layer structure.

[0166] The connection electrode CNE is disposed on the sixth insulating layer 60. The connection electrode CNE can be connected to the first output electrode DE1 through the sixth contact hole CH6 penetrating the sixth insulating layer 60.

[0167] A seventh insulating layer 70 (or passivation layer) covering the connecting electrode CNE is disposed on the sixth insulating layer 60. The seventh insulating layer 70 may be an organic layer and may have a single-layer structure or a multi-layer structure.

[0168] In one or more embodiments, the sixth insulating layer 60 and the seventh insulating layer 70 may be a single layer of polyimide-based resin. However, this disclosure is not limited thereto, and the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one selected from acrylic resin, methacrylic resin, polyisoprene-based resin, vinyl resin, epoxy resin, urethane-based resin, cellulose-based resin, siloxane-based resin, polyamide-based resin, and perylene-based resin.

[0169] The light-emitting element (OLED) is disposed on the seventh insulating layer 70. The anode (AE) of the OLED is disposed on the seventh insulating layer 70. The anode (AE) is connected to the connecting electrode (CNE) through the seventh contact hole (CH7) penetrating the seventh insulating layer 70. The pixel defining film (PDL) is disposed on the seventh insulating layer 70.

[0170] The pixel-defining film PDL has openings (OPs, e.g., multiple openings OP) that expose at least a portion of the anode AE. Each of the multiple openings OP in the pixel-defining film PDL may define a light-emitting region PXA for a pixel PX. For example, multiple pixels PX (e.g., see...) Figure 5 The pixels (PX) can be arranged on the plane of the display panel (DP) according to specific rules (e.g., in a plan view). The area containing multiple pixels (PX) can be compared with a reference. Figure 5 The active region AA is described in relation to the light-emitting region PXA and the non-light-emitting region NPXA adjacent to the light-emitting region PXA. The non-light-emitting region NPXA may be around the light-emitting region PXA (e.g., surrounding the light-emitting region PXA).

[0171] The hole control layer HCL can be commonly arranged in the emitting region PXA and the non-emitting region NPXA (e.g., it can be arranged as a common and continuous layer throughout the emitting region PXA and the non-emitting region NPXA). A common layer such as the hole control layer HCL can be commonly formed in multiple pixels PX (e.g., see...). Figure 5 The hole control layer (HCL) can include a hole transport layer and a hole injection layer.

[0172] The organic emitter layer (EML) is disposed on the hole control layer (HCL). The organic emitter layer (EML) may be disposed only in a region corresponding to each of the multiple openings (OPs). The organic emitter layer (EML) may be formed individually on multiple pixels (PXs) (e.g., see [link]). Figure 5 Each of the following is a sequence of characters.

[0173] In one or more embodiments, a patterned organic emitting layer (EML) is illustrated as an example, but the organic emitting layer EML may be commonly arranged in multiple pixels (PX) (e.g., it may be arranged as a common and continuous layer covering the emitting region PXA and the non-emitting region NPXA). In such an embodiment, the organic emitting layer EML can generate white light. In one or more embodiments, the organic emitting layer EML may have a multilayer structure.

[0174] An electronic control layer (ECL) may be disposed on an organic emitter layer (EML). The ECL may include an electron transport layer and an electron injection layer. A cathode (CE) may be disposed on the ECL. The ECL and CE may be commonly disposed across multiple pixel PXs (e.g., see [link to relevant documentation]). Figure 5 (e.g., each can be arranged as a common and continuous layer covering the luminescent region PXA and the non-luminescent region NPXA).

[0175] The encapsulation layer TFE may be disposed on the cathode CE. The encapsulation layer TFE may be commonly disposed in multiple pixel PXs (e.g., it may be disposed as a common and continuous layer covering the light-emitting region PXA and the non-light-emitting region NPXA). In one or more embodiments, the encapsulation layer TFE directly covers the cathode CE. The encapsulation layer TFE may cover the light-emitting element OLED. The encapsulation layer TFE may include a first inorganic encapsulation layer LIL and a second inorganic encapsulation layer UIL, and an organic encapsulation layer OL disposed between the first inorganic encapsulation layer LIL and the first inorganic encapsulation layer UIL. In one or more embodiments of this disclosure, the encapsulation layer TFE may include multiple inorganic layers and multiple organic layers stacked alternately.

[0176] The first inorganic encapsulation layer LIL and the second inorganic encapsulation layer UIL protect the OLED light-emitting element from moisture / oxygen, and the organic encapsulation layer OL protects the OLED light-emitting element from foreign matter such as dust particles. The first inorganic encapsulation layer LIL and the second inorganic encapsulation layer UIL may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc.; however, this disclosure is not limited thereto. The organic encapsulation layer OL may include an acrylic organic layer; however, this disclosure is not limited thereto.

[0177] According to one or more embodiments, the first transistor T1 may comprise a silicon semiconductor, such as a polycrystalline silicon semiconductor, and thus may have high electron mobility. Since the second transistor T2 comprises an oxide semiconductor, leakage current can be reduced. Therefore, the pixel PX (e.g., see...) can be reduced. Figure 5 The driving voltage of the pixel PX (see, for example, the driving voltage of the pixel PX) can be reduced or prevented from being reduced. Figure 5 The malfunction.

[0178] The input sensor ISP can be directly mounted on the display panel DP. The input sensor ISP may include a first sensing insulating layer TIL1, a second sensing insulating layer TIL2, and a third sensing insulating layer TIL3, as well as a first conductive layer TML1 and a second conductive layer TML2. The first sensing insulating layer TIL1, the second sensing insulating layer TIL2, and the third sensing insulating layer TIL3 may include inorganic materials and / or organic materials.

[0179] A first sensing insulating layer TIL1 can be directly disposed on the second inorganic encapsulation layer UIL of the encapsulation layer TFE. A first conductive layer TML1 can be disposed on the first sensing insulating layer TIL1. A second sensing insulating layer TIL2 can be disposed on the first sensing insulating layer TIL1 and can cover the first conductive layer TML1. A second conductive layer TML2 can be disposed on the second sensing insulating layer TIL2. A third sensing insulating layer TIL3 can be disposed on the second sensing insulating layer TIL2 and can cover the second conductive layer TML2. However, this disclosure is not limited thereto, and the first sensing insulating layer TIL1 may not be provided, and the first conductive layer TML1 may be directly disposed on the second inorganic encapsulation layer UIL. This disclosure is not limited to any one embodiment.

[0180] According to this disclosure, the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2 may comprise inorganic materials, and the third sensing insulating layer TIL3 may comprise organic materials.

[0181] refer to Figure 6 The first connection pattern CP1 of the described first sensing electrode TE1 may be included in the first conductive layer TML1. The first sensing pattern SP1, the second sensing pattern SP2, and the second connection pattern CP2 may be included in the second conductive layer TML2. Therefore, adjacent first sensing patterns SP1 can be connected to the first connection pattern CP1 through contact holes defined in the second sensing insulating layer TIL2.

[0182] Figure 8 This is a cross-sectional view of a plurality of interconnected pads according to one or more embodiments of the present disclosure. Figure 9 This is a cross-sectional view of a plurality of interconnected pads according to one or more embodiments of the present disclosure. Reference Figure 8 and Figure 9 The descriptions of the Display Pads PD and PD-A provided can be applied to the Display Pads, which will be described in more detail later, and may not be repeated.

[0183] refer to Figure 8 According to one or more embodiments, the display pad PD can be connected to the board pad FD via a film layer AF. The film layer AF according to one or more embodiments may include conductive balls CB (e.g., a plurality of conductive balls) and a resin layer RS. The resin layer RS ​​may include resin. In one or more embodiments, the film layer AF may be provided as an anisotropic conductive film (ACF).

[0184] The display pad PD according to one or more embodiments may include a first pattern P1, a second pattern P2, a third pattern P4, and a fourth pattern P4. The first pattern P1 may be disposed on a first insulating layer 10. The first pattern P1 can be connected to a reference... Figure 7The first semiconductor pattern OSP1 described is formed using the same process. Therefore, the first pattern P1 may include the same materials as the first semiconductor pattern OSP1.

[0185] A second pattern P2 may be disposed on a first pattern P1. The second pattern P2 may be disposed in a first opening OP1 in which the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 are penetrated. For example, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may define a first opening OP1 in which the second pattern P2 is positioned. The second pattern P2 may be formed using the same process as that used for the first input electrode SE1, the first output electrode DE1, the second input electrode SE2, and the second output electrode DE2. Therefore, the second pattern P2 may comprise the same material as the first input electrode SE1, the first output electrode DE1, the second input electrode SE2, and the second output electrode DE2.

[0186] The third pattern P3 can be disposed on the second pattern P2. The third pattern P3 can be formed by the same process as that used for the connecting electrode CNE. Therefore, the third pattern P3 can be made of the same material as the connecting electrode CNE.

[0187] A fourth pattern P4 may be arranged on the third pattern P3. The fourth pattern P4 may be arranged in a second opening OP2 in which the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2 are penetrated. For example, the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2 may define a second opening OP2 in which the fourth pattern P4 is positioned. The fourth pattern P4 can be connected to a reference... Figure 7 The second conductive layer TML2 of the described input sensor ISP is formed using the same process. Therefore, the fourth pattern P4 may comprise the same material as the second conductive layer TML2. However, this disclosure is not limited thereto, and the fourth pattern P4 may be formed using the same process as that used for the first conductive layer TML1.

[0188] According to one or more embodiments, at least one of the first pattern P1, second pattern P2, third pattern P3 and fourth pattern P4 included in the display pad PD may not be provided, and this disclosure is not limited to any one embodiment.

[0189] The flexible circuit film (FCB) according to one or more embodiments may include a base film (BS), an insulating layer (IL), and board pads (FD). The board pads (FD) may include a first pad layer (F1), a second pad layer (F2), and a third pad layer (F3). The base film (BS) may include silicon.

[0190] A first pad layer F1 may be disposed beneath the base film BS. The first pad layer F1 may include aluminum (Al). An insulating layer IL may be disposed beneath the base film BS and has an opening exposing at least a portion of the first pad layer F1. A second pad layer F2 may be disposed beneath the first pad layer F1. The second pad layer F2 may include under-bump metallization (UBM) material. A third pad layer F3 may be disposed beneath the second pad layer F2. The third pad layer F3 may include gold (Au). The third pad layer F3 may be connected to a fourth pattern P4 via a conductive ball CB.

[0191] According to one or more embodiments of this disclosure, the board pad FD may have a structure in which bumps disposed below the third pad layer F3 are omitted. Therefore, the thickness of the resin layer RS ​​can be reduced to be as much as the thickness of the bumps, and thus, a thin display device can be provided. However, since the area of ​​contact between the resin layer RS ​​and the pads is reduced due to the absence of bumps, the adhesion between the pads can be reduced, and the display pad area PDA and the board pad area FDA (e.g., see...) Figure 5 The mechanical strength of the resin layer (RS) can be reduced. Therefore, a structure in which the contact area of ​​the resin layer (RS) can be increased in a bumpless structure is desired or required.

[0192] refer to Figure 9 According to one or more embodiments, the display pad PD-A can be bonded to the board pad FD via the film layer NF. The film layer NF according to one or more embodiments may consist only of resin. Therefore, as... Figure 9 As shown, the conductive sphere CB may not be provided or may not be included in the film layer NF. In one or more embodiments, the film layer NF may be provided as a non-conductive film (NCF).

[0193] The display pad PD-A according to one or more embodiments may include a wiring pattern PE, a first conductive pattern PS, an insulating pattern PP, and a second conductive pattern PL. The wiring pattern PE may be disposed on the first insulating layer 10. The wiring pattern PE may be a portion of or reference to data lines DL1 to DLn disposed in the peripheral area NAA. Figure 5 This describes a portion of the pad line PD-L.

[0194] The first conductive pattern PS can be connected to the wiring pattern PE through an opening penetrating the second insulating layer 20. The first conductive pattern PS may include a first layer, a second layer, and a third layer stacked sequentially. The first and third layers may include titanium, and the second layer may include aluminum.

[0195] An insulating pattern PP may be disposed on a first conductive pattern PS. The insulating pattern PP may have a convex shape protruding along a third direction DR3 before the bonding pad FD. The insulating pattern PP may comprise a polymer. The insulating pattern PP according to one or more embodiments may comprise a negative photoresist (PR) or a positive photoresist (PR).

[0196] A second conductive pattern PL may cover an insulating pattern PP. The second conductive pattern PL may include a first, second, and third layer stacked sequentially. The first and third layers may include titanium, and the second layer may include aluminum. Both ends of the second conductive pattern PL may contact the first conductive pattern PS. Flexible circuit film FCB with reference. Figure 8 The description of the flexible circuit film FCB is the same, and a repeated description is not required.

[0197] According to one or more embodiments, in the process of compressing display pads PD-A and board pads FD, the second conductive pattern PL can be in direct contact with the board pads FD.

[0198] Figure 10 This is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure. Figure 11A It is according to one or more embodiments of this disclosure. Figure 10 The cross-sectional view taken from line I-I'. Figure 11B It is according to one or more embodiments of this disclosure. Figure 10 A cross-sectional view taken from line II-II'. (Compared to reference) Figures 5 to 9 Components that are identical or similar to those described may be represented by identical and / or similar reference numerals or symbols, and repeated descriptions may be omitted. Figure 10 The illustration includes, for example, references Figure 5 The description shows a portion of the display pad PD in the display pad area PDA. Figure 11A The illustration shows, for example, a reference. Figure 8 The board pads FD of the flexible circuit film FCB are described.

[0199] refer to Figures 10 to 11BAccording to one or more embodiments, display pads PD (e.g., including first pad PD1, second pad PD2, and third pad PD3) may be arranged to be spaced apart and / or separated (e.g., spaced apart or separated) along a first direction DR1 and a second direction DR2. The first pad PD1, second pad PD2, and third pad PD3 may each extend along the second direction DR2. In one or more embodiments, a plurality of first pads PD1 arranged along the first direction DR1 may be defined as a first pad row PL1, a plurality of second pads PD2 arranged along the first direction DR1 may be defined as a second pad row PL2, and a plurality of third pads PD3 arranged along the first direction DR1 may be defined as a third pad row PL3. The first pad row PL1, second pad row PL2, and third pad row PL3 may be spaced apart and / or separated (e.g., spaced apart or separated) along the second direction DR2.

[0200] The display panel DP according to embodiments of the present disclosure (e.g., see...) Figure 5 The PDA may include recessed SPs. Recessed SPs can be present in the display pad area of ​​the PDA (e.g., see [link]). Figure 5 It is provided as multiple in )

[0201] Multiple grooves SP may be arranged to be spaced apart and / or separated along a first direction DR1 and a second direction DR2 (e.g., spaced apart or separated). The grooves SP may extend along the second direction DR2.

[0202] According to one or more embodiments, a recess SP arranged along a first direction DR1 may be defined between a plurality of pads arranged in the same pad row. A recess SP may be arranged along the first direction DR1 between adjacent first pads PD1 among a plurality of first pads PD1 included in a first pad row PL1. For example, a recess SP may be positioned between each pair of adjacent first pads PD1 included in the first pad row PL1, resulting in an alternating pattern of first pads PD1 and recess SP for the first pad row PL1 in the first direction DR1.

[0203] Another groove SP, spaced apart and / or separated (e.g., spaced apart or separated) from a groove SP along the second direction DR2, may be arranged along the first direction DR1 between adjacent second pads PD2 among a plurality of second pads PD2 included in the second pad row PL2. For example, the groove SP may be positioned between each pair of adjacent second pads PD2 included in the second pad row PL2, resulting in an alternating pattern of second pads PD2 and groove SP for the second pad row PL2 on the first direction DR1.

[0204] Another groove SP, spaced apart and / or separated (e.g., spaced apart or separated) from another groove SP along the second direction DR2, may be arranged along the first direction DR1 between adjacent third pads PD3 among a plurality of third pads PD3 included in the third pad row PL3. For example, the groove SP may be positioned between each pair of adjacent third pads PD3 included in the third pad row PL3, resulting in an alternating pattern of third pads PD3 and groove SP for the third pad row PL3 on the first direction DR1.

[0205] refer to Figure 11A and Figure 11B The groove SP can be defined by penetrating an insulating layer disposed on a base substrate BL. According to one or more embodiments, the groove SP can be formed by penetrating an insulating layer disposed on a barrier layer BRL. More specifically, the groove SP can be formed by penetrating a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, as well as a first sensing insulating layer TIL1 and a second sensing insulating layer TIL2, disposed on the barrier layer BRL. For example, the sidewalls of the groove SP can be defined by the groove SP through the end surfaces of the buffer layer BFL, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, the first sensing insulating layer TIL1, and the second sensing insulating layer TIL2. The barrier layer BRL, buffer layer BFL, first insulating layer 10, second insulating layer 20, third insulating layer 30, fourth insulating layer 40, and fifth insulating layer 50, as well as the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2, can be referenced. Figure 7 The barrier layer BRL, buffer layer BFL, first insulating layer 10, second insulating layer 20, third insulating layer 30, fourth insulating layer 40 and fifth insulating layer 50, as well as the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2 are the same as those described.

[0206] Therefore, the groove SP can be defined by aligning the side surface (e.g., end surface) BE of the buffer layer BFL, the side surface (e.g., end surface) 10-E of the first insulating layer 10, the side surface (e.g., end surface) 20-E of the second insulating layer 20, the side surface (e.g., end surface) 30-E of the third insulating layer 30, the side surface (e.g., end surface) 40-E of the fourth insulating layer 40, the side surface (e.g., end surface) 50-E of the fifth insulating layer 50, the side surface (e.g., end surface) T1-E of the first sensing insulating layer TIL1, and the side surface (e.g., end surface) T2-E of the second sensing insulating layer TIL2.

[0207] According to one or more embodiments, the side surfaces BE, 10-E, 20-E, 30-E, 40-E, 50-E, T1-E and T2-E of the recess SP can be aligned with each other and can be tilted from the barrier layer BRL at a set or predetermined angle.

[0208] According to one or more embodiments of this disclosure, the portion of the barrier layer BRL exposed by the groove SP may be in direct contact with the resin layer RS ​​included in the film layer AF. In one or more embodiments, the resin layer RS ​​may be disposed inside the groove SP and may be in direct contact with the side surfaces BE, 10-E, 20-E, 30-E, 40-E, 50-E, T1-E, and T2-E defining the groove SP.

[0209] According to one or more embodiments, since the recess SP is included between adjacent display pads PD, the resin layer RS ​​included in the film layer AF and the display panel DP can be increased (e.g., see...). Figure 5 The contact area between them. Therefore, it is possible to provide a display pad area for the PDA and a board pad area for the FDA (e.g., see [reference]). Figure 5 The display panel DP in ) (for example, see Figure 5 The mechanical strength of the display device is improved. In one or more embodiments, this is due to the addition of a display pad area PDA and a board pad area FDA (e.g., see...). Figure 5 The amount of resin layer RS ​​filled in the ) can thus provide a display device with improved bonding strength between the display pad PD and the board pad FD.

[0210] like Figure 11B As illustrated in the diagram, the groove SP may not be limited to the space between the first pad PD1 and the second pad PD2 that are adjacent to each other along the second direction DR2. For example, see reference... Figure 5 The described pad line PD-L can be arranged between the first pad PD1 and the second pad PD2.

[0211] Figure 12 It is according to one or more embodiments of this disclosure. Figure 10 A cross-sectional view of multiple interconnected and / or adjacent pads taken from line I-I'. (Refer to reference) Figures 10 to 11B Components that are identical or similar to those described may be represented by identical and / or similar reference numerals or symbols, and repeated descriptions may be omitted. Figure 12 It is according to one or more embodiments of this disclosure. Figure 10 The cross-sectional view taken from line I-I'.

[0212] The groove SP-a can be defined by penetrating an insulating layer disposed on a base substrate BL. According to one or more embodiments, the groove SP-a can be formed by penetrating an insulating layer disposed on a barrier layer BRL. The groove SP-a can be formed by penetrating a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, as well as a first sensing insulating layer TIL1 and a second sensing insulating layer TIL2, all disposed on the barrier layer BRL. For example, the sidewalls of the groove SP can be defined by the end surfaces of the buffer layer BFL, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, the first sensing insulating layer TIL1, and the second sensing insulating layer TIL2 through which the groove SP is formed.

[0213] Therefore, the groove SP-a can be defined by the side surface (e.g., end surface) BE of the buffer layer BFL, the side surface (e.g., end surface) 10-E of the first insulating layer 10, the side surface (e.g., end surface) 20-E of the second insulating layer 20, the side surface (e.g., end surface) 30-E of the third insulating layer 30, the side surface (e.g., end surface) 40-E of the fourth insulating layer 40, the side surface (e.g., end surface) 50-E of the fifth insulating layer 50, the side surface (e.g., end surface) T1-E of the first sensing insulating layer TIL1, and the side surface (e.g., end surface) T2-E of the second sensing insulating layer TIL2.

[0214] According to one or more embodiments, the width (in the first direction DR1) of each of the plurality of spaces defining the recess SP-a among the side surfaces BE, 10-E, 20-E, 30-E, 40-E, 50-E, T1-E, and T2-E may be different from each other. For example, the width in the first direction DR1 may be increased in a direction away from the base substrate BL.

[0215] For example, the first width W1 of the space in the buffer layer BFL that defines the groove SP-a may be smaller than the second width W2 of the space in the first insulating layer 10, the second width W2 may be smaller than the third width W3 of the space in the second insulating layer 20, the third width W3 may be smaller than the fourth width W4 of the space in the third insulating layer 30, the fourth width W4 may be smaller than the fifth width W5 of the space in the fourth insulating layer 40, the fifth width W5 may be smaller than the sixth width W6 of the space in the fifth insulating layer 50, and the sixth width W6 may be smaller than the seventh width W7 of the space in the first sensing insulating layer TIL1 and the second sensing insulating layer TIL2.

[0216] According to one or more embodiments, since the side surfaces of the insulating layer defining the groove SP-a are patterned into a stepped shape, the resin layer RS ​​therein can be increased (e.g., see...). Figure 8 The area in contact with the insulating layer inside the groove SP-a.

[0217] Figure 13 This is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure. Figure 14 This is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure. Figure 15 This is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure. Figure 16A This is a plan view showing a portion of the pad area according to one or more embodiments of the present disclosure. Figure 16B It is according to one or more embodiments of this disclosure. Figure 16A The cross-sectional view taken from line III-III'.

[0218] Reference Figures 5 to 11B Components that are identical or similar to those described may be represented by identical and / or similar reference numerals or symbols, and repeated descriptions may be omitted. Figures 13 to 15 The diagram shows the arrangement of the pads and references. Figure 10 The described pad arrangements are substantially the same, and duplicate descriptions are not required. Additionally, see reference... Figures 13 to 15 The described groove cross-section can be compared with the reference. Figure 11A The cross-sections of the described grooves are corresponding or substantially similar, and repeated descriptions are not required.

[0219] refer to Figure 13 According to the display panel DP of this disclosure (for example, see...), Figure 5 The recessed area SP-A may include a display pad area PDA (see, for example, see...). Figure 5 Multiple grooves SP-A in )

[0220] The plurality of grooves SP-A may be arranged to be spaced apart and / or separated along a first direction DR1 (e.g., spaced apart or separated). In one or more embodiments, the plurality of grooves SP-A may each extend along a second direction DR2.

[0221] Therefore, when viewed in the first direction DR1, the groove SP-A can overlap with the pads included in different pad rows and can be arranged along the second direction DR2.

[0222] For example, when viewed in the first direction DR1, the groove SP-A may overlap with the first pad PD1 included in the first pad row PL1, the second pad PD2 which is spaced apart and / or separated from the first pad PD1 along the second direction DR2 and included in the second pad row PL2, and the third pad PD3 which is spaced apart and / or separated from the second pad PD2 along the second direction DR2 and included in the third pad row PL3.

[0223] refer to Figure 14 According to one or more embodiments, the plurality of grooves SP-B may each include a first sub-groove S1 and a second sub-groove S2. When viewed in the second direction DR2, the cross-sections of the first sub-groove S1 and the second sub-groove S2 taken along the first direction DR1 may be compared with... Figure 11A The cross-section corresponds to that.

[0224] The first sub-groove S1 and the second sub-groove S2 may be arranged along the second direction DR2. The first sub-groove S1 and the second sub-groove S2 may be arranged between multiple pads arranged in the same pad row and spaced apart and / or separated (e.g., spaced apart or separated) along the first direction DR1. For example, a groove SP-B may be arranged between two adjacent first pads PD1 along the first direction DR1, and a groove SP-B may include two sub-grooves (e.g., the first sub-groove S1 and the second sub-groove S2). However, this disclosure is not limited thereto, and the number of sub-grooves arranged in a groove SP-B may be two or more.

[0225] refer to Figure 15 According to one or more embodiments, the groove SP-C may include a first sub-groove S1, a second sub-groove S2, and a third sub-groove S3. The first sub-groove S1 may be disposed between a plurality of first pads PD1 in a first pad row PL1, the second sub-groove S2 may be disposed between a plurality of second pads PD2 in a second pad row PL2, and the third sub-groove S3 may be disposed between a plurality of third pads PD3 in a third pad row PL3. The widths (in the first direction DR1) of the first sub-groove S1, the second sub-groove S2, and the third sub-groove S3 disposed in different pad rows may be different from each other.

[0226] For example, a first sub-groove S1 disposed between a plurality of first pads PD1 included in a first pad row PL1 may have a first width WD1 in a first direction DR1. A second sub-groove S2 disposed between a plurality of second pads PD2 included in a second pad row PL2 may have a second width WD2 in the first direction DR1. A third sub-groove S3 disposed between a plurality of third pads PD3 included in a third pad row PL3 may have a third width WD3 in the first direction DR1.

[0227] The second width WD2 may be smaller than the first width WD1 and larger than the third width WD3. According to one or more embodiments, different numbers of pad lines PD-L may be arranged between multiple pads included in different pad rows. The pad lines PD-L may be connected to a reference. Figure 7 The first transistor T1 and the second transistor T2 are described, as well as the display pads (e.g., display pad PD and display pad PD-A).

[0228] For example, the number of pad lines PD-L arranged between multiple pads adjacent to a groove having a small width along the first direction DR1 can be greater than the number of pad lines PD-L arranged between multiple pads adjacent to a groove having a relatively large width along the first direction DR1.

[0229] For example, the number of pad lines PD-L arranged between a plurality of third pads PD3 adjacent to the third sub-groove S3 along the first direction DR1 can be greater than the number of pad lines PD-L arranged between a plurality of second pads PD2 adjacent to the second sub-groove S2 along the first direction DR1.

[0230] refer to Figure 16A and Figure 16B Display panel DP (for example, see...) Figure 5 The first dam pattern DMP1, the second dam pattern DMP2, and the third dam pattern DMP3 may be arranged inside a groove SP. The first dam pattern DMP1, the second dam pattern DMP2, and the third dam pattern DMP3 may be arranged in a groove SP to be spaced apart and / or separated along the second direction DR2 (e.g., spaced apart or separated).

[0231] like Figure 16B As shown in the diagram, the first dam pattern DMP1, the second dam pattern DMP2, and the third dam pattern DMP3 may each include first patterns D1 to eighth patterns D8 stacked sequentially. The first patterns D1 to eighth patterns D8 may be defined, for example, by referring to... Figure 11A The insulating layer of the groove SP described comprises the same material.

[0232] For example, the first pattern D1 can be formed by a process substantially the same as that of the buffer layer BFL and includes the same material as the buffer layer BFL; the second pattern D2 can be formed by a process substantially the same as that of the first insulating layer 10 and includes the same material as the first insulating layer 10; the third pattern D3 can be formed by a process substantially the same as that of the second insulating layer 20 and includes the same material as the second insulating layer 20; the fourth pattern D4 can be formed by a process substantially the same as that of the third insulating layer 30 and includes the same material as the third insulating layer 30; the fifth pattern D5 can be formed by a process substantially the same as that of the fourth insulating layer 40 and includes the same material as the fourth insulating layer 40; the sixth pattern D6 can be formed by a process substantially the same as that of the fifth insulating layer 50 and includes the same material as the fifth insulating layer 50; the seventh pattern D7 can be formed by a process substantially the same as that of the first sensing insulating layer TIL1 and includes the same material as the first sensing insulating layer TIL1; and the eighth pattern D8 can be formed by a process substantially the same as that of the second sensing insulating layer TIL2 and includes the same material as the second sensing insulating layer TIL2. At least one of the first pattern D1 to the eighth pattern D8 may not be provided.

[0233] According to one or more embodiments, since a first dam pattern DMP1, a second dam pattern DMP2, and a third dam pattern DMP3 are included arranged inside the groove SP, a reference can be added. Figure 11A The contact area of ​​the resin layer RS ​​is described.

[0234] According to one or more embodiments of the present disclosure, the area of ​​contact between the resin and the pads and the area adjacent to the pads arranged between the pads of the display panel and the pads of the circuit board can be increased, thereby improving the bonding force between the multiple pads and providing a display device with improved mechanical strength.

[0235] In this disclosure, the use of "may" in describing embodiments of this disclosure refers to "one or more embodiments of this disclosure".

[0236] As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation rather than degree and are intended to take into account the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account errors relating to the measurement and those associated with a particular number of measurements (such as limitations of the measurement system), “substantially” as used herein includes the value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, “substantially” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the value.

[0237] Furthermore, any numerical ranges disclosed and / or enumerated herein are intended to include all subranges of the same numerical precision falling within the enumerated range. For example, the range “1.0 to 10.0” is intended to include all subranges between the enumerated minimum of 1.0 and the enumerated maximum of 10.0 (and includes both the enumerated minimum of 1.0 and the enumerated maximum of 10.0), i.e., having a minimum greater than or equal to 1.0 and a maximum less than or equal to 10.0, such as 2.4 to 7.6. Any maximum numerical limit enumerated herein is intended to include all lower numerical limits falling within it, and any minimum numerical limit enumerated in this specification is intended to include all higher numerical limits falling within it. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly enumerate any subranges falling within the range expressly enumerated herein.

[0238] The display device, electronic device, means for manufacturing a display device, or any other related device or component described herein according to embodiments of the present disclosure may be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of the device may be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of the device may be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of the device may be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices without departing from the scope of embodiments of the present disclosure.

[0239] Those skilled in the art will recognize from the full scope of this disclosure that, unless otherwise stated or implied, various suitable features of the various embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked and operated in various suitable ways, and the various embodiments may be implemented independently of each other or in combination with each other in any suitable manner.

[0240] It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those skilled in the art that, unless expressly indicated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. It should be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: A base substrate having an active region and a peripheral region adjacent to the active region; A circuit element layer, the circuit element layer including a barrier layer on the base substrate, a plurality of insulating layers on the barrier layer, and a plurality of transistors, each including a plurality of conductive patterns between the plurality of insulating layers; The display element layer includes a plurality of light-emitting elements connected to the plurality of transistors; Multiple display pads are located in the peripheral region and connected to the multiple transistors; A circuit board, the circuit board including a plurality of board pads connected to the plurality of display pads; as well as A film layer, the film layer being between the plurality of display pads and the plurality of board pads, The plurality of side surfaces of the plurality of insulating layers define grooves that expose portions of the barrier layers and are located between adjacent display pads among the plurality of display pads. The membrane layer contacts the portion of the barrier layer exposed by the groove.

2. The display device according to claim 1, wherein, The plurality of side surfaces of the plurality of insulating layers defining the groove are tilted at a set or predetermined angle.

3. The display device according to claim 2, wherein, The plurality of side surfaces of the plurality of insulating layers defining the groove are aligned with each other.

4. The display device according to claim 1, wherein, The width of the space between the plurality of side surfaces of the plurality of insulating layers defining the groove increases in the direction away from the base substrate.

5. The display device according to claim 1, wherein, The plurality of display pads are arranged along a first direction and a second direction intersecting the first direction. Each of the plurality of display pads extends along the second direction, and The display pads arranged sequentially along the first direction among the plurality of display pads define a pad row.

6. The display device according to claim 5, wherein, The groove includes a plurality of grooves, and each of the plurality of grooves is arranged in the same row of display pads between adjacent display pads, and the plurality of grooves are spaced apart from each other along the first direction and the second direction.

7. The display device according to claim 6, wherein, The widths of the plurality of grooves are measured in the first direction and vary along the second direction.

8. The display device according to claim 7, further comprising: Multiple pad lines connect the multiple display pads and the multiple transistors, and are arranged between the multiple display pads and the multiple recesses adjacent to the multiple display pads. Wherein, the first width of the first groove among the plurality of grooves is greater than the second width of the second groove among the plurality of grooves, the first width and the second width are measured along the first direction, and the number of the plurality of pad lines adjacent to the first groove in the first direction is less than the number of the plurality of pad lines adjacent to the second groove in the first direction.

9. The display device according to claim 5, wherein, The groove includes a plurality of grooves arranged along the first direction, and each of the plurality of grooves extends along the second direction. The plurality of display pads are sequentially arranged in a plurality of pad rows along the first direction, and the plurality of pad rows are arranged along the second direction. When viewed in the first direction, the plurality of grooves overlap with the plurality of display pads of at least two different pad rows among the plurality of pad rows.

10. The display device according to claim 9, wherein, Each of the plurality of grooves includes a plurality of sub-grooves spaced apart from each other along the second direction, and The plurality of sub-grooves of each of the plurality of grooves are arranged in the plurality of display pads between adjacent display pads in the same row of pads.

11. The display device according to claim 1, wherein, The plurality of insulating layers includes a buffer layer on the barrier layer and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, and a seventh insulating layer on the buffer layer. One of the plurality of transistors includes a first semiconductor pattern on the buffer layer, a first control electrode on the first insulating layer and overlapping the first semiconductor pattern, and an upper electrode on the second insulating layer and overlapping the first control electrode. Another of the plurality of transistors includes a second semiconductor pattern on the third insulating layer and a second control electrode on the fourth insulating layer and overlapping the second semiconductor pattern. The display device further includes: Input and output electrodes, the input and output electrodes being located on the fifth insulating layer and connected to the first and second semiconductor patterns via contact holes; and A connecting electrode, which is located on the sixth insulating layer and connected to the input electrode, and At least one of the plurality of light-emitting elements includes a first electrode connected to the connecting electrode through a contact hole in the seventh insulating layer.

12. The display device according to claim 11, further comprising: An encapsulation layer that covers the display element layer, the encapsulation layer comprising a plurality of inorganic layers and an organic layer between the plurality of inorganic layers; as well as The input sensor is directly on the encapsulation layer. The input sensor includes a first sensing insulating layer on the encapsulation layer, a first conductive layer on the first sensing insulating layer, a second sensing insulating layer on the first sensing insulating layer, a second conductive layer on the second sensing insulating layer, and a third sensing insulating layer on the second sensing insulating layer.

13. The display device according to claim 12, wherein, Each of the plurality of display pads includes a first pattern on the second insulating layer, a second pattern on the first pattern, a third pattern on the second pattern, and a fourth pattern on the third pattern. The second pattern is in the first opening defined by the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer, and The fourth pattern is in the second opening defined by the first sensing insulating layer and the second sensing insulating layer.

14. The display device according to claim 13, wherein, The first pattern and the first semiconductor pattern comprise the same material, the second pattern and the input electrode comprise the same material, the third pattern and the connection electrode comprise the same material, and the fourth pattern and the second conductive layer comprise the same material.

15. The display device according to claim 14, wherein, The film is an anisotropic conductive film comprising resin and conductive particles inside the resin.

16. The display device according to claim 12, wherein, Each of the plurality of display pads includes a first conductive pattern, an insulating pattern comprising a polymer on the first conductive pattern, and a second conductive pattern covering the insulating pattern and having two ends connected to the first conductive pattern. The second conductive pattern is in direct contact with the plurality of board pads.

17. The display device according to claim 16, wherein, The film layer is a non-conductive film consisting only of resin.

18. The display device according to claim 1, further comprising: Multiple dam patterns are arranged inside the groove and along the direction extending from the groove. The plurality of dam patterns and at least one of the plurality of insulating layers comprise the same material.

19. An electronic device comprising: A display device, the display device comprising: A base substrate having an active region and a peripheral region adjacent to the active region; A circuit element layer, the circuit element layer including a barrier layer on the base substrate, a plurality of insulating layers on the barrier layer, and a plurality of transistors, each including a plurality of conductive patterns between the plurality of insulating layers; The display element layer includes a plurality of light-emitting elements connected to the plurality of transistors; Multiple display pads are located in the peripheral region and connected to the multiple transistors; A circuit board, the circuit board including a plurality of board pads connected to the plurality of display pads; and A film layer, the film layer being between the plurality of display pads and the plurality of board pads, The plurality of side surfaces of the plurality of insulating layers define grooves that expose portions of the barrier layers and are located between adjacent display pads among the plurality of display pads. The membrane layer contacts the portion of the barrier layer exposed by the groove.

20. The electronic device according to claim 19, wherein, The electronic device is a smart watch, a computer including tablet PCs and laptop computers, or a smart TV.

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