STI filling method
By performing nitrogen annealing during the STI filling process, followed by silicon oxide deposition and vapor annealing, and combined with SiCoNi etching, the problem of void formation during STI filling was solved, improving the density of the silicon oxide film and device performance.
Patent Information
- Application Number
- CN202511279721.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-09
- Publication Date
- 2026-01-13
AI Technical Summary
The existing STI filling process is prone to generating voids, resulting in poor density of the silicon oxide film and potential silicon loss.
After the first deposition of silicon oxide, nitrogen annealing is performed. After etching, silicon oxide is deposited again and steam annealing is performed. By combining SiCoNi etching process and chemical vapor deposition process, a dense silicon oxide film is formed.
It effectively reduces the generation of filling voids, improves the density of the silicon oxide film, reduces silicon loss, and enhances electrical insulation performance and device stability.
Smart Images
Figure CN121335518A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor design, and particularly relates to an STI filling method. Background Technology
[0002] Shallow Trench Isolation (STI) uses a silicon nitride mask to form trenches after deposition, patterning, and etching of a silicon substrate. The trenches are then filled with deposited oxides to isolate the material from the silicon substrate. It is commonly used in processes below 0.25µm.
[0003] like Figure 2 As shown, the formation of the STI structure usually involves first depositing a silicon nitride layer 3 on a semiconductor substrate 1, then patterning the silicon nitride layer 3 to form a hard mask, then etching the semiconductor substrate 1 to form trenches, filling the trenches with SiO2 to form a device isolation structure, and finally performing nitrogen annealing. After nitrogen annealing, the SiO2 film layer has low density and still has pores.
[0004] like Figure 3 As shown, steam annealing produces a more compact SiO2 film due to the crosslinking reaction (≡Si-OH+HO-Si≡→≡Si-O-Si≡+H2O), and it is less prone to pore formation, but it is easy to cause silicon loss. Summary of the Invention
[0005] This application provides an STI filling method in which nitrogen annealing is performed after the first deposition of silicon oxide, followed by etching and then silicon oxide deposition and steam annealing. This method can effectively reduce the generation of filling voids during the STI process and improve the density of the silicon oxide film.
[0006] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.
[0007] To achieve one or more of the above objectives or other objectives, the present invention provides an STI filling method.
[0008] An STI filling method, comprising:
[0009] A semiconductor substrate is provided, wherein trenches are formed in the semiconductor substrate, and a pad oxide layer and an etch barrier layer are sequentially formed on the semiconductor substrate, and the pad oxide layer is formed on the surface of the trenches;
[0010] Silicon oxide is deposited to form a first silicon oxide layer, which fills the trench and covers the etch barrier layer.
[0011] The semiconductor substrate is subjected to nitrogen annealing.
[0012] Etch the first silicon oxide layer;
[0013] Silicon oxide is deposited again to form a second silicon oxide layer, which covers the first silicon oxide layer.
[0014] The semiconductor substrate is subjected to steam annealing.
[0015] The specific process of etching the first silicon oxide layer is as follows:
[0016] The holes in the first silicon oxide layer were etched using a SiCoNi etching process.
[0017] Silicon oxide is deposited using a chemical vapor deposition process to form a second silicon oxide layer covering the first silicon oxide layer.
[0018] A pad oxide layer and an etch barrier layer are sequentially formed on the semiconductor substrate, and the trench is formed by photolithography and etching processes.
[0019] The pad oxide layer is formed on the surface of the semiconductor substrate by a thermal oxidation process;
[0020] The etching barrier layer is formed by depositing silicon nitride on the pad oxide layer using a chemical vapor deposition process.
[0021] The thermal oxidation process is a furnace tube oxidation process.
[0022] A padding oxide layer is formed on the surface of the trench by a thermal oxidation process, wherein the thermal oxidation process is an in-situ water vapor oxidation process.
[0023] Silicon oxide is deposited using a chemical vapor deposition process to form the first silicon oxide layer.
[0024] The semiconductor substrate after steam annealing is planarized to expose the etch barrier layer.
[0025] The etching barrier layer is etched to remove it.
[0026] Compared with the prior art, the beneficial effects of the present invention mainly include:
[0027] This application performs nitrogen annealing after the first deposition of silicon oxide, followed by etching and then silicon oxide deposition and steam annealing. This effectively reduces the generation of voids during STI, improves the density of the silicon oxide film, and reduces silicon loss.
[0028] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 This is a schematic diagram of an STI filling method provided in an embodiment of this application.
[0031] Figure 2 STI filling scheme 1 in the prior art.
[0032] Figure 3 STI filling scheme 2 in the prior art.
[0033] Figure 4 This is a schematic diagram of an STI filling method provided in an embodiment of this application. Detailed Implementation
[0034] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.
[0035] This application provides an STI filling method in which nitrogen annealing is performed after the first deposition of silicon oxide, followed by etching and then silicon oxide deposition and steam annealing. This method can effectively reduce the generation of filling voids during the STI process and improve the density of the silicon oxide film.
[0036] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0037] Example:
[0038] like Figure 1 As shown, an STI filling method includes:
[0039] Step S1: Provide a semiconductor substrate 1, in which trenches are formed, and a pad oxide layer 2 and an etch barrier layer 3 are sequentially formed on the semiconductor substrate 1, with the pad oxide layer 2 formed on the surface of the trench.
[0040] Step S2: Deposit silicon oxide to form a first silicon oxide layer 4. The first silicon oxide layer 4 fills the trench and covers the etch barrier layer 3.
[0041] Step S3: Perform nitrogen annealing on semiconductor substrate 1;
[0042] Step S4: Etch the holes in the first silicon oxide layer 4 to expose the holes in the first silicon oxide layer 4 and form a groove;
[0043] Step S5: Deposit silicon oxide again to form a second silicon oxide layer 5, which covers the first silicon oxide layer 4;
[0044] Step S6: Perform steam annealing on semiconductor substrate 1.
[0045] Specifically, such as Figure 4 As shown, in step S1: a pad oxide layer 2 and an etch barrier layer 3 are sequentially formed on the semiconductor substrate 1, and trenches are formed by photolithography and etching processes; specifically, a thin oxide layer (usually silicon dioxide SiO2) is first grown on the semiconductor substrate 1 by thermal oxidation process to form the pad oxide layer 2. The function of this layer is to protect the substrate surface from damage during subsequent trench etching, and it can be used as a gate oxide layer later or provide a basis for other structures after removal;
[0046] As a preferred embodiment of the present invention, the thermal oxidation process for forming the pad oxide layer 2 in this embodiment is a furnace tube oxidation process. A silicon dioxide (SiO2) film is grown by controlling the reaction of oxygen and / or water vapor with the silicon substrate surface in a high-temperature environment. It is usually carried out in a specially designed vertical or horizontal furnace tube, which can achieve large-area, uniform oxide layer growth and is easy to scale up production.
[0047] Then, silicon nitride (Si3N4) is deposited on the pad oxide layer 2 by chemical vapor deposition to form an etch barrier layer 3, which is used to prevent the oxide layer and silicon substrate from being over-etched during the subsequent etch (DRIE) process. For silicon nitride deposition, commonly used reaction gases include silane (SiH4) and ammonia (NH3), and sometimes dichlorosilane (SiH2Cl2) is also used to adjust the film properties.
[0048] Photolithography process: A layer of photoresist is uniformly coated on the etch barrier layer 3; the pattern is transferred onto the photoresist through a mask; ultraviolet light or other light sources are used to irradiate the photoresist in certain areas to cause chemical changes; the photoresist is treated with a developer to remove the exposed or unexposed parts of the photoresist, exposing the underlying etch barrier layer 3, and the desired pattern is formed on the etch barrier layer 3.
[0049] Etching process: Dry etching (e.g., plasma etching) is used to etch the etch barrier layer 3 according to the pattern defined by photolithography, penetrating to the pad oxide layer 2; the etching process continues, penetrating through the pad oxide layer 2 into the silicon substrate, forming trenches of predetermined depth and width.
[0050] Photoresist removal: After etching is complete, the remaining photoresist and any possible residues need to be thoroughly removed to ensure that subsequent processes are not affected.
[0051] A pad oxide layer 2 is then formed on the surface of the trench through a thermal oxidation process. In this embodiment, the thermal oxidation process for forming the pad oxide layer 2 on the surface of the trench is an in-situ steam oxidation process. In-situ steam oxidation (ISSG) is a special thermal oxidation process that oxidizes the silicon surface by directly generating water vapor under high temperature conditions. For complex structures, such as trenches with high aspect ratio, ISSG can provide better step coverage, reduce defects, and achieve thicker oxide layer growth at lower temperatures.
[0052] Step S2: Silicon oxide is deposited using chemical vapor deposition (CVD) to form a first silicon oxide layer 4. The first silicon oxide layer 4 fills the trench and covers the etch stop layer 3. The first silicon oxide layer 4 completely "covers the etch stop layer 3," which provides protection. More importantly, the etch stop layer 3 (usually made of silicon nitride) has a very high etch selectivity compared to silicon oxide. In the subsequent CMP step, the polishing process slows down significantly or almost stops when encountering silicon nitride (etch stop layer) with a high etch selectivity. This allows the CMP process to automatically and precisely remove the first silicon oxide layer 4 from the raised area, leaving silicon oxide only in the trench, without damaging the underlying stop layer and active area. This "self-stopping" effect greatly improves the controllability and uniformity of the process.
[0053] Step S3: Perform nitrogen annealing on the semiconductor substrate 1 to increase the density of the first silicon dioxide layer 4. Silicon dioxide films deposited by CVD processes are typically relatively "loose," potentially containing dangling bonds, microvoids, and low-density network structures. During nitrogen annealing, the high temperature provides sufficient energy to the silicon and oxygen atoms in the silicon dioxide network, enabling them to move and rearrange, thus forming a more stable and denser covalent bond network structure. A denser film means fewer pores and defect pathways, significantly reducing current leakage and improving the electrical insulation performance of the device. This is crucial for silicon dioxide as an isolation layer, directly affecting the device's power consumption and stability.
[0054] Step S4: The holes in the first silicon oxide layer 4 are etched using the SiCoNi etching process. SiCoNi can effectively expose the holes in the first silicon oxide layer 4, forming grooves. SiCoNi is an isotropic etching process, which means that its etching rate is the same in all directions (lateral and longitudinal). The isotropic nature allows the reactants to uniformly etch the inner surface of the holes, ensuring that the entire hole is completely opened and cleaned, without forming new and unpredictable morphologies.
[0055] The SiCoNi process exhibits extremely high etching selectivity and isotropy for silicon dioxide, enabling it to precisely locate and etch away microvoids or gaps that may remain after CVD deposition and annealing. These voids are typically located inside the silicon dioxide filled with trenches. The SiCoNi reactants can penetrate into these tiny voids and etch outwards from their inner walls, thereby "opening up" and expanding these hidden internal defects to form visible, clean grooves.
[0056] The SiCoNi process has an extremely high etching rate for silicon dioxide, but an extremely low etching rate for the underlying etch barrier layer 3 and semiconductor substrate 1. The selectivity ratio can reach 100:1 or even higher. Operators can perform etching with confidence without worrying too much about penetrating the underlying etch barrier layer or damaging the active silicon region. This greatly improves the controllability and safety of the process.
[0057] Step S5: Deposit silicon oxide using chemical vapor deposition to form a second silicon oxide layer 5 covering the first silicon oxide layer 4;
[0058] Finally, the semiconductor substrate 1 after steam annealing is planarized to expose the etch barrier layer 3; and the etch barrier layer 3 is etched to remove it.
[0059] This application removes the first silicon oxide layer 4 and the second silicon oxide layer 5 using a chemical mechanical polishing (CMP) process to expose the etch barrier layer 3. Once the etch barrier layer 3 is exposed, the next step is to remove it. The removal method depends on the specific material of the etch barrier layer 3. For silicon nitride etch barrier layer 3, phosphoric acid (H3PO4) can be used as an etchant for wet etching, or plasma of fluorine-based gases (such as CF4, CHF3) can be used for dry etching.
[0060] This application provides an STI filling method in which nitrogen annealing is performed after the first deposition of silicon oxide, followed by etching and then silicon oxide deposition and steam annealing. This method can effectively reduce the generation of filling voids during the STI process and improve the density of the silicon oxide film.
[0061] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.
[0062] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
Claims
1. An STI filling method, characterized in that, include: A semiconductor substrate is provided, wherein trenches are formed in the semiconductor substrate, and a pad oxide layer and an etch barrier layer are sequentially formed on the semiconductor substrate, and the pad oxide layer is formed on the surface of the trenches; Silicon oxide is deposited to form a first silicon oxide layer, which fills the trench and covers the etch barrier layer. The semiconductor substrate is subjected to nitrogen annealing. Etch the first silicon oxide layer; Silicon oxide is deposited again to form a second silicon oxide layer, which covers the first silicon oxide layer. The semiconductor substrate is subjected to steam annealing.
2. The STI filling method according to claim 1, characterized in that, The specific process of etching the first silicon oxide layer is as follows: The holes in the first silicon oxide layer were etched using a SiCoNi etching process.
3. The STI filling method according to claim 2, characterized in that, Silicon oxide is deposited using a chemical vapor deposition process to form a second silicon oxide layer covering the first silicon oxide layer.
4. The STI filling method according to claim 1, characterized in that, A pad oxide layer and an etch barrier layer are sequentially formed on the semiconductor substrate, and the trench is formed by photolithography and etching processes.
5. The STI filling method according to claim 4, characterized in that, The pad oxide layer is formed on the surface of the semiconductor substrate by a thermal oxidation process; The etching barrier layer is formed by depositing silicon nitride on the pad oxide layer using a chemical vapor deposition process.
6. The STI filling method according to claim 5, characterized in that, The thermal oxidation process is a furnace tube oxidation process.
7. The STI filling method according to claim 4, characterized in that, A padding oxide layer is formed on the surface of the trench by a thermal oxidation process, wherein the thermal oxidation process is an in-situ water vapor oxidation process.
8. The STI filling method according to claim 1, characterized in that, Silicon oxide is deposited using a chemical vapor deposition process to form the first silicon oxide layer.
9. The STI filling method according to claim 1, characterized in that, The semiconductor substrate after steam annealing is planarized to expose the etch barrier layer.
10. An STI filling method according to claim 9, characterized in that, The etching barrier layer is etched to remove it.