Multi-chip packaging structure with heat dissipation system

Abstract

The invention provides a multi-chip packaging structure with a heat dissipation system, and belongs to the technical field of packaging heat dissipation. The packaging structure comprises a substrate, a chip assembly and a heat dissipation assembly. The chip assembly comprises a first chip, a second chip and a third chip, the first chip and the second chip are arranged in a stacked mode, the first chip and the second chip are stacked in the horizontal direction, the first chip is located on the side, away from the third chip, of the second chip, the power consumption of the first chip and the second chip is smaller than that of the third chip, and the sensitive degree of the first chip to temperature is larger than that of the second chip and the third chip. The heat dissipation assembly comprises a heat dissipation cover and a heat dissipation carrier plate, the heat dissipation carrier plate is located between the chip assembly and the substrate, the coefficient of thermal expansion of the heat dissipation carrier plate is close to that of the chip assembly, the Young modulus of the heat dissipation carrier plate is larger than that of the substrate, the heat dissipation cover covers the chip assembly, the heat dissipation cover is provided with a first flow channel, and the heat dissipation carrier plate is provided with a second flow channel so as to dissipate heat of the chip assembly. The heat dissipation efficiency of the packaging structure can be improved, substrate warping is restrained, and the space utilization rate of the packaging structure is improved.

Description

Technical Field

[0001] This invention relates to the field of packaging and heat dissipation technology, and in particular to a multi-chip packaging structure with a heat dissipation system. Background Technology

[0002] With the development of the semiconductor industry, chip packaging integration is becoming increasingly higher, and chip power density is increasing. In multi-chip packaged products, multiple chips are stacked to maximize space utilization and optimize electrical performance, further exacerbating heat concentration. Therefore, in multi-chip packaged products, reducing thermal resistance and achieving efficient heat dissipation at the package end are of great significance for product performance and reliability.

[0003] In related technologies, the heat dissipation method typically involves connecting the chip to a heat sink via a thermal interface material. Heat is transferred from the chip to the heat sink through the thermal interface material, and then dissipated through system cooling measures. However, this method still suffers from problems such as low heat dissipation efficiency, easy substrate warping, and insufficient space utilization. Summary of the Invention

[0004] This invention provides a multi-chip package structure with a heat dissipation system, the purpose of which is to improve the heat dissipation efficiency of the package structure, reduce the possibility of substrate warping, and improve the space utilization of the package structure.

[0005] To achieve the above objectives, the present invention provides a multi-chip package structure with a heat dissipation system, comprising:

[0006] substrate;

[0007] A chip assembly includes a first chip, a second chip, and a third chip. The first chip and the second chip are stacked together, and the stacking direction of the first chip and the second chip is parallel to the substrate. The first chip is disposed on the side of the second chip away from the third chip. The power consumption of the first chip and the second chip is less than that of the third chip. The first chip is more sensitive to temperature than the second chip and the third chip.

[0008] A heat dissipation assembly includes a heat dissipation cap and a heat dissipation carrier plate. The heat dissipation carrier plate is disposed between the chip assembly and the substrate. The chip assembly is electrically connected to the substrate through the heat dissipation carrier plate. The difference in the coefficients of thermal expansion between the heat dissipation carrier plate and the chip assembly is less than the difference in the coefficients of thermal expansion between the substrate and the chip assembly. The Young's modulus of the heat dissipation carrier plate is greater than that of the substrate. The heat dissipation cap is disposed on the chip assembly. The heat dissipation cap has a first flow channel, and the heat dissipation carrier plate has a second flow channel. Coolant flows through both the first flow channel and the second flow channel to dissipate heat from the chip assembly.

[0009] In one embodiment, the heat dissipation carrier has a signal transmission area, the chip assembly is electrically connected to the substrate through the signal transmission area, and the second flow channel surrounds the outer periphery of the signal transmission area.

[0010] In one embodiment, the second flow channel is configured as a wave shape.

[0011] In one embodiment, the heat sink includes a top cover and a side cover connected to each other. The top cover is disposed on the side of the chip assembly away from the substrate, and the side cover is attached to the first chip along the stacking direction of the first chip and the second chip.

[0012] In one embodiment, the heat dissipation component includes thermally conductive adhesive disposed between the first chip and the side cover, between the first chip and the top cover, and between the first chip and the heat dissipation carrier plate.

[0013] In one embodiment, the heat dissipation assembly includes an on-chip heat sink disposed between the heat sink cover and the third chip. The on-chip heat sink has multiple honeycomb-shaped heat exchange cavities, all of which are connected to the first flow channel.

[0014] In one embodiment, the heat dissipation component includes thermally conductive adhesive disposed between the on-chip heat sink and the heat dissipation cap.

[0015] In one embodiment, the heat dissipation component includes a first interface and a second interface, wherein a first end of the first flow channel and a first end of the second flow channel are both connected to the first interface, and a second end of the first flow channel and a second end of the second flow channel are both connected to the second interface.

[0016] In one embodiment, the inner wall of the first flow channel has serrated protrusions.

[0017] In one embodiment, the first chip and the second chip are electrically connected via microbumps.

[0018] The above-described solution of the present invention has the following beneficial effects:

[0019] In this embodiment, the chip assembly is located between the heat sink and the heat sink carrier. The coolant in the first channel of the heat sink and the coolant in the second channel of the heat sink carrier can promptly remove the heat generated by the chip assembly under normal operating conditions from the packaging structure, thereby dissipating heat from the chip assembly and helping to maintain the temperature of the packaging structure within a suitable range. The temperature of the chip assembly can be regulated by adjusting the temperature of the coolant. Furthermore, the first and second channels located on opposite sides of the chip assembly provide an "air conditioning" environment for the chip assembly, enabling more comprehensive heat dissipation and keeping the internal temperature of the packaging structure consistently low, which helps maintain the chip assembly within a relatively low and stable temperature range. In addition, the stacking direction of the first and second chips is parallel to the substrate, which helps save internal space in the packaging structure to stack more first and second chips, facilitating communication with the third chip. The temperature-sensitive first chip is located on the side of the second chip away from the third chip, which has higher power consumption, thus keeping the first chip further away from the heat source and helping to stabilize the temperature of the first chip. The thermal expansion coefficients of the heat sink and the chip assembly are close, and the Young's modulus of the heat sink is greater than that of the substrate. This makes the heat sink less prone to warping, and at the same time, it can dissipate heat from the chip assembly and suppress warping of the substrate due to the mismatch of thermal expansion coefficients between the substrate and the chip during high-temperature reflow.

[0020] Other beneficial effects of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0021] Figure 1 This is a cross-sectional view of the packaging structure in one embodiment of the present invention;

[0022] Figure 2 This is a top view of the heat dissipation carrier plate in one embodiment of the present invention.

[0023] [Explanation of Labels in the Attached Image]

[0024] 1. Substrate; 21. First chip; 22. Second chip; 23. Third chip; 31. Heat sink; 311. First flow channel; 312. Top cover; 313. Side cover; 32. Heat sink carrier; 321. Second flow channel; 322. Signal transmission area; 33. Thermal adhesive; 34. On-chip heat sink; 35. First interface; 36. Second interface; 4. Microbump. Detailed Implementation

[0025] To make the technical problems, solutions, and advantages of this invention clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention. Furthermore, the technical features involved in the different embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0026] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] For multi-chip high-power packaged products, heat dissipation primarily focuses on reducing thermal resistance to transfer heat to the system side as much as possible. System-level measures then dissipate this heat. Effectively reducing the thermal resistance between the heat source and heat sink, and achieving rapid heat dissipation at the package side, is crucial for solving the high-temperature problem of packaged products. Furthermore, during high-temperature reflow, the mismatch in thermal expansion coefficients between the substrate and the chip can easily lead to substrate warping, reducing the yield of the packaged product. Moreover, multi-chip packaged products contain a large number of chips, and the utilization rate of their internal space needs to be improved.

[0029] In view of this, please refer to Figure 1 This application provides a multi-chip package structure with a heat dissipation system, including a substrate 1, a chip assembly, and a heat dissipation assembly.

[0030] The chip assembly includes a first chip 21, a second chip 22, and a third chip 23. The first chip 21 and the second chip 22 are stacked. The stacking direction of the first chip 21 and the second chip 22 is parallel to the substrate 1; that is, the thickness directions of both the first chip 21 and the second chip 22 are parallel to the substrate 1. The first chip 21 and the second chip 22 are relatively small in the thickness direction, saving space in the packaging structure along the extension direction of the substrate 1, allowing multiple first chips 21 and multiple second chips 22 to be arranged within the packaging structure for communication with the third chip 23. The first chip 21 is located on the side of the second chip 22 furthest from the third chip 23. The power consumption of both the first chip 21 and the second chip 22 is lower than that of the third chip 23. The first chip 21 is more sensitive to temperature than the second chip 22 and the third chip 23. The first chip 21 can be a PIC (Photonic Integrated Circuit) chip, the second chip 22 can be an EIC (Electronic Integrated Circuit) chip, and the third chip 23 can be an ASIC (Application Specific Integrated Circuit) chip.

[0031] It should be noted that the power consumption and temperature specifications of the various components in multi-chip packaged products in related technologies vary significantly. For example, the power consumption of ASIC chips can reach 150W or even higher, while the power consumption of PIC chips and EIC chips is generally in the range of a few watts. Therefore, ASIC chips, as a huge heat source, directly affect the temperature levels of PIC chips and EIC chips. The temperature specifications of ASIC chips and EIC chips are generally around 100℃, while the temperature specifications of PIC chips are generally around 70℃ because many components are very sensitive to temperature, and temperature changes can cause wavelength drift and performance degradation. In this application, the first chip 21 is disposed on the side of the second chip 22 away from the third chip 23, so that the temperature-sensitive first chip 21 is kept away from the third chip 23, which has a higher power consumption, thus helping to stabilize the temperature of the first chip 21.

[0032] The heat dissipation assembly includes a heat sink 31 and a heat sink carrier 32. The heat sink carrier 32 is disposed between the chip assembly and the substrate 1, and the chip assembly is electrically connected to the substrate 1 through the heat sink carrier 32. The difference in the coefficients of thermal expansion between the heat sink carrier 32 and the chip assembly, for example, the absolute value of the difference, is smaller than the difference in the coefficients of thermal expansion between the substrate 1 and the chip assembly, making the coefficients of thermal expansion of the heat sink carrier 32 closer to those of the chip assembly. Consequently, the thermomechanical stress between the heat sink carrier 32 and the substrate 1 is smaller during high-temperature reflow. The Young's modulus of the heat sink carrier 32 is greater than that of the substrate 1. It should be noted that Young's modulus is a mechanical property of solid materials, used to measure the stiffness of a material under tensile or compressive stress. The fact that the Young's modulus of the heat sink carrier 32 is greater than that of the substrate 1 means that, in addition to being less prone to warping itself, the heat sink carrier 32 can also suppress warping of the substrate 1 caused by the mismatch in coefficients of thermal expansion between the substrate 1 and the chip during high-temperature reflow.

[0033] It should be noted that the raw material for manufacturing the chip assembly is silicon. Due to the significant difference in the coefficients of thermal expansion between silicon and substrate 1 (the coefficient of thermal expansion of substrate 1 is much greater than that of silicon wafer), enormous thermomechanical stress is generated within the packaging structure during reflow soldering, leading to warping of substrate 1. The heat sink 32 can be made of glass. Since the coefficient of thermal expansion of glass is closer to that of silicon wafer, it reduces the thermomechanical stress between the chip assembly and the heat sink 32. Furthermore, the Young's modulus of glass is much higher than that of substrate 1, which is made of organic materials. Therefore, after reflow, the heat sink 32 can better resist the deformation of substrate 1, thus improving the warping of substrate 1.

[0034] The heat sink 31 has a first flow channel 311, and the heat sink carrier 32 has a second flow channel 321. Coolant flows through both the first flow channel 311 and the second flow channel 321 to dissipate heat from the chip assembly.

[0035] For example, the heat sink 31 can be made of copper, and can be formed by stacking two copper plates. A first flow channel 311 is formed on one of the copper plates using a wet etching process. The surfaces where the two copper plates are joined are then precision polished, and the two copper plates are bonded together using diffusion bonding to form the heat sink 31. Similar to the forming method of the first flow channel 311, a second flow channel 321 can be etched on the heat sink carrier plate 32. The heat sink carrier plate 32 can be made of glass, and can be formed by stacking two glass plates. A second flow channel 321 is etched on one of the glass plates, and the two glass plates are then bonded and sealed at high temperature. Adhesive is applied to the side of the heat sink carrier plate 32 closest to the substrate 1. The heat sink carrier plate 32 is precisely positioned to the substrate 1 using a microscope, and a certain pressure is applied combined with heating to cure the adhesive between the heat sink carrier plate 32 and the substrate 1, thereby achieving bonding between the heat sink carrier plate 32 and the substrate 1.

[0036] For example, the first flow channel 311 and the second flow channel 321 can dissipate heat from the chip assembly using water cooling or oil cooling. That is, water or oil can flow through the first flow channel 311 and the second flow channel 321 to carry away the heat generated by the chip assembly during normal operation from the packaging structure, thereby dissipating heat from the packaging structure. When the heat dissipation method is water cooling, the coolant can be ultrapure water.

[0037] In this embodiment, the chip assembly is located between the heat sink 31 and the heat sink carrier 32. The coolant in the first flow channel 311 of the heat sink 31 and the coolant in the second flow channel 321 of the heat sink carrier 32 can promptly remove the heat generated by the chip assembly under normal operating conditions from the packaging structure, thereby dissipating heat from the chip assembly and helping to maintain the temperature of the packaging structure within a suitable range. The temperature of the chip assembly can be controlled by adjusting the temperature of the coolant. Furthermore, the first flow channel 311 and the second flow channel 321 located on opposite sides of the chip assembly can provide an environment similar to "air conditioning" for the chip assembly, enabling more comprehensive heat dissipation and keeping the internal ambient temperature of the packaging structure consistently low, which helps maintain the chip assembly within a relatively low and stable temperature range. In addition, the stacking direction of the first chip 21 and the second chip 22 is parallel to the substrate 1, which helps to save internal space in the packaging structure, allowing for the stacking of more first chips 21 and second chips 22, and facilitating communication with the third chip 23. The temperature-sensitive first chip 21 is located on the side of the second chip 22 away from the third chip 23, which has a higher power consumption. This distances the first chip 21 from the heat source, which helps stabilize its temperature. The heat sink 32 has a similar coefficient of thermal expansion to the chip assembly, and its Young's modulus is greater than that of the substrate 1. This ensures that the heat sink 32 is less prone to warping, effectively dissipates heat from the chip assembly, and also suppresses warping of the substrate 1 caused by the mismatch in coefficients of thermal expansion between the substrate 1 and the chip during high-temperature reflow.

[0038] In one embodiment, please refer to Figure 2 The heat dissipation carrier 32 has a signal transmission area 322, through which the chip assembly is electrically connected to the substrate 1. A second flow channel 321 surrounds the outer periphery of the signal transmission area 322. For example, the signal transmission area 322 is etched on the heat dissipation carrier 32 at the position corresponding to the chip assembly, and the second flow channel 321 is etched in the area outside the signal transmission area 322. The second flow channel 321 surrounds the outer periphery of the signal transmission area 322 to enclose the signal transmission area 322, increasing the length of the second flow channel 321. This allows the coolant in the second flow channel 321 to remove as much heat generated by the chip assembly as possible, which is beneficial to improving the heat dissipation efficiency of the second flow channel 321 for the chip assembly.

[0039] In one embodiment, please refer to Figure 2 The second flow channel 321 is configured in a wave shape to increase the length of the second flow channel 321, so that the coolant in the second flow channel 321 can remove as much heat generated by the chip assembly as possible, which is beneficial to improving the heat dissipation efficiency of the second flow channel 321 for the chip assembly.

[0040] In one embodiment, please refer to Figure 1 The heat sink 31 includes a top cover 312 and a side cover 313 connected to each other. Both the top cover 312 and the side cover 313 have a first flow channel 311. The top cover 312 is disposed on the side of the chip assembly away from the substrate 1, and the side cover 313 is attached to the first chip 21 along the stacking direction of the first chip 21 and the second chip 22. When the side of the first chip 21 that is attached to the heat sink 32 dissipates heat through the second flow channel 321, the three sides of the temperature-sensitive first chip 21 can be dissipated through the coolant, which is beneficial to improving the heat dissipation efficiency of the first chip 21 and maintaining the temperature of the first chip 21.

[0041] In one embodiment, please refer to Figure 1 The heat dissipation component includes thermally conductive adhesive 33. Thermally conductive adhesive 33 is a single-component, thermally conductive, room-temperature curing silicone adhesive, also known as thermally conductive silicone. It is a silicone compound made primarily of silicone, with added fillers, thermally conductive materials, and other polymeric materials. It possesses good thermal conductivity and electrical insulation properties and is widely used in electronic components. The thermally conductive adhesive 33 is disposed between the first chip 21 and the side cover 313, between the first chip 21 and the top cover 312, and between the first chip 21 and the heat dissipation carrier plate 32. This ensures that the three sides of the temperature-sensitive first chip 21 are coated with thermally conductive adhesive 33. The large area of ​​thermally conductive adhesive 33 applied to the first chip 21 allows the heat generated by the first chip 21 during normal operation to be quickly transferred through the large area of ​​thermally conductive adhesive 33 to the coolant in the first flow channel 311 and the second flow channel 321, and then carried out of the packaging structure by the coolant. This improves the heat dissipation efficiency of the first chip 21, thus maintaining its temperature. For example, thermally conductive adhesive 33 is also provided between the second chip 22 and the heat sink 31, and between the second chip 22 and the heat sink carrier 32, in order to improve the heat dissipation efficiency of the second chip 22.

[0042] In one embodiment, please refer to Figure 1The heat dissipation assembly includes an on-chip heat sink 34. The on-chip heat sink 34 can be made of metal. The on-chip heat sink 34 is disposed between the heat sink 31 and the third chip 23, so that the heat generated by the third chip 23 during normal operation can be transferred through the on-chip heat sink 34 to the first flow channel 311 of the heat sink 31. The on-chip heat sink 34 has multiple honeycomb-shaped heat exchange chambers. All of the multiple heat exchange chambers are connected to the first flow channel 311. For example, coolant in the first flow channel 311 can flow into the multiple heat exchange chambers in the on-chip heat sink 34, and then flow from the multiple heat exchange chambers back into the first flow channel 311. For example, the extending direction of the multiple heat exchange chambers is parallel to the flow direction of the coolant in the first flow channel 311, so as to facilitate the flow of coolant within the heat exchange chambers. The multiple honeycomb-shaped heat exchange cavities within the on-chip heat sink 34 increase the ratio of the total area to its total volume, and also increase the contact area between the on-chip heat sink 34 and the coolant. This not only allows the heat generated by the high-power third chip 23 during normal operation to be transferred to the on-chip heat sink 34 as much as possible, but also allows the heat in the on-chip heat sink 34 to be carried away by the coolant as much as possible. On the one hand, no additional interfacial heat transfer is required, maximizing the reduction of the thermal resistance of the third chip 23, which is beneficial to improving the heat dissipation efficiency of the high-power third chip 23. On the other hand, the heat generated by the high-power third chip 23 can be carried away in time, which also reduces the impact on the first chip 21 and the second chip 22, and helps to stabilize the temperature of the first chip 21 and the second chip 22.

[0043] In one embodiment, please refer to Figure 1 The heat dissipation component includes thermally conductive adhesive 33, which is disposed between the on-chip heat sink 34 and the heat sink cover 31. This allows the heat generated by the third chip 23, which has a high power consumption, during normal operation to be quickly transferred to the on-chip heat sink 34 through the thermally conductive adhesive 33, and then carried out of the package structure by the coolant. This helps to improve the heat dissipation efficiency of the third chip 23 and maintain the temperature of the third chip 23.

[0044] In one embodiment, please refer to Figure 1The heat dissipation assembly includes a first interface 35 and a second interface 36. The first end of the first flow channel 311 and the first end of the second flow channel 321 are both connected to the first interface 35, and the second ends of the first flow channel 311 and the second flow channel 321 are both connected to the second interface 36, so that the same end of the first flow channel 311 and the second flow channel 321 shares a single interface, facilitating unified control of the flow rate and temperature of the coolant within the first flow channel 311 and the second flow channel 321. For example, the first interface 35 can be configured as an inlet, and the second interface 36 can be configured as an outlet. For example, the first interface 35 can be connected to an external cold source to provide ultrapure water at a temperature of 25℃~35℃ and a flow rate of 0.5m / s~2m / s to the first flow channel 311 and the second flow channel 321. The ultrapure water coolant is split at the first interface 35 and flows into the first flow channel 311 and the second flow channel 321 respectively. The coolant in the first flow channel 311 and the second flow channel 321 eventually merges and flows out from the second interface 36. The coolant flowing out from the second interface 36 is at a higher temperature. After heat dissipation, it flows back into the first flow channel 311 and the second flow channel 321 from the first interface 35 under the drive of the pump, forming a heat exchange cycle. In addition, the temperature and flow rate of the coolant can be adjusted based on the temperature of the chip assembly to achieve efficient temperature control of the chip assembly.

[0045] In one embodiment, the inner wall of the first flow channel 311 has serrated protrusions to increase turbulence within the first flow channel 311, which is beneficial for enhancing the turbulence effect and improving heat exchange efficiency.

[0046] Understandably, the inner wall of the second flow channel 321 may also have serrated protrusions.

[0047] In one embodiment, please refer to Figure 1 The first chip 21 and the second chip 22 are directly electrically connected via microbumps 4, which shortens the signal transmission distance between the first chip 21 and the second chip 22 and helps improve signal integrity. For example, the second chip 22 can transmit signals to the substrate 1 via gold wires.

[0048] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-chip package structure with a heat dissipation system, characterized in that, include: substrate; A chip assembly includes a first chip, a second chip, and a third chip. The first chip and the second chip are stacked together, and the stacking direction of the first chip and the second chip is parallel to the substrate. The first chip is disposed on the side of the second chip away from the third chip. The power consumption of the first chip and the second chip is less than that of the third chip. The first chip is more sensitive to temperature than the second chip and the third chip. A heat dissipation assembly includes a heat dissipation cap and a heat dissipation carrier plate. The heat dissipation carrier plate is disposed between the chip assembly and the substrate. The chip assembly is electrically connected to the substrate through the heat dissipation carrier plate. The difference in the coefficients of thermal expansion between the heat dissipation carrier plate and the chip assembly is less than the difference in the coefficients of thermal expansion between the substrate and the chip assembly. The Young's modulus of the heat dissipation carrier plate is greater than that of the substrate. The heat dissipation cap is disposed on the chip assembly. The heat dissipation cap has a first flow channel, and the heat dissipation carrier plate has a second flow channel. Coolant flows through both the first flow channel and the second flow channel to dissipate heat from the chip assembly.

2. The multi-chip package structure with a heat dissipation system according to claim 1, characterized in that, The heat dissipation carrier has a signal transmission area, and the chip assembly is electrically connected to the substrate through the signal transmission area. The second flow channel surrounds the outer periphery of the signal transmission area.

3. The multi-chip package structure with a heat dissipation system according to claim 1, characterized in that, The second flow channel is configured to be wavy.

4. The multi-chip package structure with a heat dissipation system according to claim 1, characterized in that, The heat dissipation cover includes a top cover and a side cover connected to each other. The top cover is disposed on the side of the chip assembly away from the substrate, and the side cover is attached to the first chip along the stacking direction of the first chip and the second chip.

5. The multi-chip package structure with a heat dissipation system according to claim 4, characterized in that, The heat dissipation component includes thermally conductive adhesive, which is disposed between the first chip and the side cover, between the first chip and the top cover, and between the first chip and the heat dissipation carrier plate.

6. The multi-chip package structure with a heat dissipation system according to claim 1, characterized in that, The heat dissipation assembly includes an on-chip heat sink, which is disposed between the heat sink cover and the third chip. The on-chip heat sink has multiple honeycomb-shaped heat exchange cavities, all of which are connected to the first flow channel.

7. The multi-chip package structure with a heat dissipation system according to claim 6, characterized in that, The heat dissipation component includes thermally conductive adhesive, which is disposed between the on-chip heat sink and the heat dissipation cover.

8. The multi-chip package structure with a heat dissipation system according to claim 1, characterized in that, The heat dissipation component includes a first interface and a second interface. The first end of the first flow channel and the first end of the second flow channel are both connected to the first interface, and the second end of the first flow channel and the second end of the second flow channel are both connected to the second interface.

9. The multi-chip package structure with a heat dissipation system according to claim 1, characterized in that, The inner wall of the first flow channel has serrated protrusions.

10. The multi-chip package structure with a heat dissipation system according to claim 1, characterized in that, The first chip and the second chip are electrically connected via microbumps.

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