Method for improving overlay offset of epitaxial layer, super junction device and manufacturing method of super junction device
By setting marker patterns at specific locations in the epitaxial layer of the superjunction device, the problems of large photolithography overlay misalignment and high rework rate are solved, resulting in reduced cost and cycle time as well as improved device performance.
Patent Information
- Application Number
- CN202410918474.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-09
- Publication Date
- 2026-01-13
AI Technical Summary
In the manufacturing process of superjunction devices, the large overlay value of photolithography leads to a high rework rate, which increases production costs and production cycle.
Marker patterns are set in multiple epitaxial layers. The marker pattern located below affects the top surface contour of the epitaxial layer above, while the marker pattern above is formed outside its first region, ensuring that the marker pattern of the lower layer does not interfere with the photolithography alignment of the upper layer. The photolithography overlay offset is reduced by adjusting the epitaxial layer thickness and the spacing of the marker patterns.
The photolithography overlay offset value was reduced, the photolithography rework rate was reduced, the production cost and production cycle were reduced, and the performance of superjunction devices was improved at the same time.
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Figure CN121335549A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for improving epitaxial layer overlay offset, a superjunction device and a method for fabricating the superjunction device. Background Technology
[0002] Super-junction power MOSFETs have become the industry standard in high-voltage switching converters. They offer lower on-resistance RDS(on) while having less gate and output charge, which helps maintain higher efficiency at any given frequency.
[0003] In the fabrication of superjunction devices, multiple epitaxial layers need to be stacked on the substrate. The process of multiple epitaxial layers requires an alignment layer to be etched every few epitaxial layers to ensure that the subsequent pattern does not shift. However, the actual photolithography overlapping (OL) value is often affected by a variety of factors and shifts. Large OL values require rework compensation, which greatly increases production costs and cycle time.
[0004] Therefore, it is urgent to solve the problem of how to reduce the overlay offset value of photolithography and reduce the rework rate of photolithography. Summary of the Invention
[0005] One of the objectives of this invention is to reduce the photolithographic overlay offset of multiple epitaxial layers, thereby reducing the photolithographic rework rate and thus reducing production costs and production cycle.
[0006] To achieve the above objective, the present invention provides a method for improving epitaxial layer overlay misalignment. The method includes providing a substrate and stacking a plurality of epitaxial layers on the substrate, at least two of which serve as alignment layers. The alignment layers have marking patterns for photolithographic alignment formed therein. These marking patterns are trenches located within the alignment layers. The marking pattern of the lower alignment layer influences the top surface profile of a first region of the upper alignment layer, and the marking pattern of the upper alignment layer is formed outside the first region.
[0007] Optionally, for the two alignment layers, the epitaxial layer thickness between the two alignment layers is D1, the thickness of the upper epitaxial layer of the two alignment layers is D2, and the vertical spacing of the marking patterns of the two alignment layers in the epitaxial layer thickness direction is D3, where D3>2(D1+D2).
[0008] Optionally, each of the epitaxial layers has the marking pattern formed therein; or, there are several epitaxial layers without marking patterns between two adjacent alignment layers.
[0009] Optionally, a trench-type zero-layer mark is formed in the substrate; the mark pattern in the plurality of epitaxial layers is formed outside the region of the epitaxial layer affected by the zero-layer mark.
[0010] The present invention also provides a method for fabricating a superjunction device. The method for fabricating the superjunction device includes providing a substrate and stacking multiple epitaxial layers on the substrate, wherein marking patterns are set in the multiple epitaxial layers using the method described above for improving epitaxial layer overlay misalignment.
[0011] The present invention also provides a superjunction device. The superjunction device includes a substrate and a plurality of epitaxial layers stacked on the substrate, at least two of the plurality of epitaxial layers serving as alignment layers, wherein the alignment layers are formed with marking patterns for photolithographic alignment, the marking patterns being trenches located in the alignment layers, wherein the marking pattern of the lower alignment layer affects the top surface profile of a first region of the upper alignment layer, and the marking pattern of the upper alignment layer is formed outside the first region.
[0012] Optionally, for the two alignment layers, the epitaxial layer thickness between the two alignment layers is D1, the thickness of the upper epitaxial layer of the two alignment layers is D2, and the vertical spacing of the marking patterns of the two alignment layers in the epitaxial layer thickness direction is D3, where D3>2(D1+D2).
[0013] Optionally, each of the epitaxial layers has the marking pattern formed therein; or, there are several epitaxial layers without marking patterns between two adjacent alignment layers.
[0014] Optionally, a trench-type zero-layer mark is formed in the substrate; the mark pattern in the plurality of epitaxial layers is formed outside the region of the epitaxial layer affected by the zero-layer mark.
[0015] Optionally, all of the epitaxial layers are either N-type epitaxial layers or P-type epitaxial layers.
[0016] The present invention provides a method for improving epitaxial layer overlay misalignment, a method for fabricating a superjunction device, and a superjunction device. In this method, multiple epitaxial layers are stacked on a substrate, and at least two of the epitaxial layers serve as alignment layers. The alignment layers have marking patterns for photolithographic alignment, which are trenches located within the alignment layers. The marking pattern of the lower alignment layer affects the top surface contour of a first region of the upper alignment layer. The marking pattern of the upper alignment layer is formed outside the first region. Thus, the epitaxial shape of the marking pattern of the lower alignment layer does not affect the photolithographic alignment of the marking pattern of the upper alignment layer. This reduces the photolithographic overlay misalignment value of the multiple epitaxial layers, lowers the photolithographic rework rate, and consequently reduces production costs and cycle time. It also helps improve the performance of the superjunction device. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the drift of the marker pattern in the epitaxial layer.
[0018] Figure 2 This is a schematic diagram of the distortion of the marker pattern in the epitaxial layer.
[0019] Figure 3 This is a schematic diagram showing the disappearance of the marker pattern in the epitaxial layer.
[0020] Figure 4 This is a schematic diagram of the graphic markings in the epitaxial layer when the epitaxial conformation is good.
[0021] Figure 5 This is a schematic diagram of creating a marker pattern in the area above the marker pattern in the previous layer of the epitaxial layer.
[0022] Figure 6 This is a schematic diagram of the waveform of a normal alignment signal in a photolithography process.
[0023] Figure 7 This is a waveform diagram of an abnormal alignment signal during the photolithography process.
[0024] Figure 8 This is a diagram showing the correspondence between a marker pattern created in the region above the previous layer marker pattern in the epitaxial layer and an abnormal alignment signal during the photolithography process.
[0025] Figure 9 This is a schematic diagram showing the setting of the marking pattern in the epitaxial layer of an existing superjunction device.
[0026] Figure 10 This is a partial cross-sectional schematic diagram of a superjunction device according to an embodiment of the present invention.
[0027] Explanation of reference numerals in the attached figures: 1-substrate; 2-marker pattern; 3-epitaxial layer; 4-epitaxial mark; 31-first epitaxial layer; 32-second epitaxial layer; 33-third epitaxial layer; 101-zero layer mark; 310-first marker pattern; 320-second marker pattern; 330-third marker pattern. Detailed Implementation
[0028] The inventors discovered that the main factors affecting the OL value of photolithography include the etching morphology of the mark, the epitaxial conformability of the mark, the recognition capability of the photolithography machine, and the crystal orientation deviation of the substrate.
[0029] Since multiple epitaxial layers with a total thickness of over 40 μm need to be grown during the fabrication of multilayer epitaxial superjunctions, a number of alignment layers need to be etched in these layers to ensure that the subsequent pattern does not shift relative to the previous layer. However, the OL value of photolithography is directly affected by the conformal properties of the epitaxial layer. Therefore, it is necessary to thoroughly study the influence of the conformal properties of the epitaxial layer on photolithography alignment and OL.
[0030] When an epitaxial layer 3 is grown on a substrate 1 with marking pattern 2, as the process temperature decreases and the growth rate increases, the conformability of the epitaxial layer deteriorates. For example, the epitaxial mark 4 formed by the marking pattern 2 in the epitaxial layer 3 may exhibit pattern drift (e.g., Figure 1 As shown), graphic distortion (such as) Figure 2 (as shown), or even the graphic disappears (e.g.) Figure 3 (as shown in the figure). Therefore, the actual process requires adjusting the process temperature, growth rate, etc., to ensure that the marking pattern still has a certain morphology after epitaxy, so as to ensure that the OL lithography of the next layer will not deviate too much.
[0031] However, when the epitaxy possesses good conformability, such as Figure 4 As shown, the marker pattern 2 left by the previous alignment layer etching still retains a certain morphology after several epitaxial processes; when the alignment layer with the same marker is etched again, as shown... Figure 5 As shown, the epitaxial layer on the side of the newly etched marker pattern has the shape left by the epitaxial layer of the previous marker pattern. The photolithography of the next layer will be interfered with by the shape of the marker pattern left by the previous alignment layer during the actual alignment and OL measurement process, which will lead to abnormal rework of OL, which greatly increases the manufacturing cost and production cycle.
[0032] Figure 6 This is a schematic diagram of the waveform of a normal alignment signal in a photolithography process. Figure 7 This is a waveform diagram of an abnormal alignment signal during the photolithography process. Figure 8 This diagram shows the correspondence between a marker pattern created in the region above the previous layer marker pattern in the epitaxial layer and an aberration alignment signal during the photolithography process. (Reference) Figure 5 and comparison Figure 6 and Figure 7 It can be seen that, due to the influence of the marking pattern of the preceding alignment layer on the subsequent epitaxial layers, anomalies exist in the alignment signal during the photolithographic alignment of the later alignment layer, such as... Figure 7 As shown, there are noise peaks in the alignment signal (as indicated by the dashed box). These noise peaks can easily cause abnormalities when the photolithography grasp signal is applied, resulting in a shift in the actual alignment position and thus an excessively large OL.
[0033] Based on the above research, the inventors found that: (1) when the conformability of epitaxy deteriorates, the photolithography alignment and OL of the first layer after epitaxy may exceed the standard (OOC or OOS), requiring rework, which increases product cost and production cycle; (2) when the conformability of epitaxy is good, it is beneficial to the photolithography alignment and OL of the next layer, but it is not beneficial to the photolithography alignment and OL after the subsequent alignment layer is etched.
[0034] Figure 9 This is a schematic diagram illustrating the arrangement of marking patterns within the epitaxial layer of an existing superjunction device. For example... Figure 9 As shown, in existing superjunction device fabrication, mask A is used to define the position of marker pattern a1, mask B is used to define the position of marker pattern b1 of the first epitaxial layer 31, then mask A is used to define the position of marker pattern a2 of the second epitaxial layer 32, and mask B is used to define the position of marker pattern b2 of the third epitaxial layer 33. Thus, marker pattern a2 is located directly above marker pattern a1, and marker pattern b2 is located directly above marker pattern b1. Referring to the previous analysis, it is known that because marker pattern a1 affects the top surface contour of the epitaxial layer on the side of marker pattern a2, abnormal alignment signals are prone to occur when using marker pattern a2 for photolithographic alignment, leading to a shift in the actual alignment position and resulting in a large OL (alignment error).
[0035] As the pitch of superjunction devices shrinks, the number of epitaxial layers and lithography layers required increases, leading to increasingly prominent problems such as large lithography overlay offset and high lithography rework rate.
[0036] To address the aforementioned problems, this invention provides a method for improving epitaxial layer overlay misalignment and a method for fabricating a superjunction device. The method for fabricating a superjunction device includes providing a substrate and stacking multiple epitaxial layers on the substrate, wherein a marking pattern is set in the multiple epitaxial layers using the method for improving epitaxial layer overlay misalignment provided in this application.
[0037] The method for improving epitaxial layer overlay misalignment includes providing a substrate and stacking a plurality of epitaxial layers on the substrate, at least two of the plurality of epitaxial layers serving as alignment layers, wherein the alignment layers have marking patterns for photolithographic alignment, the marking patterns being trenches located in the alignment layers, wherein the marking pattern of the lower alignment layer affects the top surface profile of a first region of the upper alignment layer, and the marking pattern of the upper alignment layer is formed outside the first region.
[0038] The method for improving epitaxial layer overlay misalignment and the fabrication method for superjunction devices proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0039] Figure 10 This is a partial cross-sectional schematic diagram of a superjunction device according to an embodiment of the present invention. (Reference) Figure 10 As shown, the material of substrate 1 can be silicon, germanium, germanium silicon, silicon carbide, gallium arsenide or indium gallium arsenide, or silicon-on-insulator, germanium-on-insulator, or other materials, such as gallium arsenide or other III-V compounds.
[0040] A zero-layer mark 101 can be formed on the top surface of the substrate 1. The zero-layer mark 101 is a trench-type mark. The method of forming the zero-layer mark 101 in the substrate 1 may include: forming a first photoresist layer on the substrate 1; defining the position of the zero-layer mark 101 with a first mask; exposing the first photoresist layer with the first mask; developing the first photoresist layer to form a patterned first photoresist layer; etching the substrate 1 with the patterned first photoresist layer as a mask to form the zero-layer mark 101 in the substrate 1; and removing the patterned first photoresist layer.
[0041] Next, a plurality of epitaxial layers are formed on substrate 1. At least two of the epitaxial layers serve as alignment layers. These alignment layers have marking patterns for photolithographic alignment. The marking patterns are trenches located within the alignment layers; that is, the marking patterns are trench-type marking points. It should be noted that, in this application, the epitaxial layer with marking patterns can be referred to as an alignment layer to distinguish it from epitaxial layers without marking patterns.
[0042] In superjunction devices, having at least two alignment layers among multiple epitaxial layers helps ensure that the photolithographic overlay offset values of the multiple epitaxial layers meet the requirements. The more epitaxial layers there are, the more alignment layers can be included. The number of alignment layers can be 2, 3, 4, or 10, etc.
[0043] In some embodiments of this application, there are several epitaxial layers without marked patterns between two adjacent alignment layers.
[0044] In other embodiments of this application, such as Figure 10 As shown, each epitaxial layer has a marking pattern to ensure that the photolithographic overlay offset value of each epitaxial layer meets the requirements.
[0045] refer to Figure 10 As shown, marking patterns in multiple epitaxial layers (including a first epitaxial layer 31, a second epitaxial layer 32, and a third epitaxial layer 33) are formed outside the region of the epitaxial layer affected by the zero-layer marking 101. The marking patterns of the lower alignment layer affect the top surface profile of the first region of the upper alignment layer, and the marking patterns of the upper alignment layer are formed outside the first region.
[0046] Specifically, after forming a zero-layer mark 101 on the substrate 1, a first epitaxial layer 31 is formed on the substrate 1. The first epitaxial layer 31 covers the top surface of the substrate 1 and the inner surface of the trench of the zero-layer mark 101. The epitaxial layer of the zero-layer mark 101 affects the top surface profile of the region A0 of the first epitaxial layer 31.
[0047] A first marker pattern 310 is fabricated in the first epitaxial layer 31. To avoid the influence of the epitaxy of the zero layer marker 101 on the first marker pattern 310, the first marker pattern 310 is formed outside the region A0 of the first epitaxial layer 31.
[0048] The method for fabricating the first marker pattern 310 in the first epitaxial layer 31 may include: forming a second photoresist layer on the first epitaxial layer 31; defining the position of the first marker pattern 310 with a second mask; exposing the second photoresist layer with the second mask; developing the second photoresist layer to form a patterned second photoresist layer; etching the first epitaxial layer 31 with the patterned second photoresist layer as a mask to form the first marker pattern 310 in the first epitaxial layer 31; and then removing the patterned second photoresist layer.
[0049] Continue to refer to Figure 10 A second epitaxial layer 32 is formed on the first epitaxial layer 31, covering the first epitaxial layer 31 and the inner surface of the first marking pattern 310. With respect to the second epitaxial layer 32, the first marking pattern 310 of the lower first epitaxial layer 31 affects the top surface profile of the first region A1 of the upper second epitaxial layer.
[0050] A second marker pattern 320 is formed in the second epitaxial layer 32, outside the first region A1 of the second epitaxial layer, to avoid the epitaxy of the first marker pattern 310 affecting the photolithographic alignment of the second marker pattern 320. Furthermore, to avoid the influence of the epitaxy of the zero-layer marker 101 on the second marker pattern 320, the second marker pattern 320 is also formed outside the region A2 of the second epitaxial layer 32 affected by the zero-layer marker 101.
[0051] refer to Figure 10 As shown, a third epitaxial layer 33 is formed on the second epitaxial layer 32. The third epitaxial layer 33 covers the second epitaxial layer 32 and the inner surface of the second marking pattern 320. The top surface contour of the first region of the third epitaxial layer 33 is affected by the marking pattern below it. The first region of the third epitaxial layer 33 may include the influence region A4 of the first marking pattern 310 on the third epitaxial layer 33 and the influence region A5 of the second marking pattern 320 on the third epitaxial layer 33. A third marking pattern 330 is formed on the third epitaxial layer 33. The third marking pattern 330 is formed outside the first region of the third epitaxial layer 33 and outside the region A3 of the third epitaxial layer.
[0052] It should be noted that this embodiment uses the creation of a marker pattern in three stacked epitaxial layers as an example. In other embodiments, the number of epitaxial layers can be greater than 3. When creating a marker pattern in an epitaxial layer above the third epitaxial layer 33, the marker pattern must be created outside the area of that epitaxial layer affected by the marker pattern below.
[0053] In this embodiment, reference Figure 10 As shown, the groove cross-section of the marking patterns (including the first marking pattern 310, the second marking pattern 320, and the third marking pattern 330) and the zero-layer marking 101 is rectangular. In other embodiments, the groove cross-section of the marking patterns can also be other shapes such as an inverted trapezoid.
[0054] refer to Figure 10 As shown, due to the issue of conformal preservation after epitaxy, the marker pattern, which is originally a right-angled groove, will grow into a trapezoid in the upper epitaxial layer. The lower base of the trapezoid is the inner frame shrinkage width, and the upper base is the outer expansion width. Experiments have verified that the lower base shrinkage width is equal to the upper base expansion width and equal to the epitaxial thickness, but there will be slight differences depending on the conformal preservation of the FAB plant. When the width of the marker pattern is less than the epitaxial growth thickness, the marker pattern will grow into an inverted triangle.
[0055] For the two alignment layers, the thickness of the epitaxial layer between the two alignment layers is D1, the thickness of the upper epitaxial layer of the two alignment layers is D2, and the vertical spacing of the marking patterns of the two alignment layers in the epitaxial layer thickness direction is D3, where D3>2(D1+D2), in order to prevent the marking patterns of the lower layer from interfering with the marking patterns of the upper layer.
[0056] For example, refer to Figure 10 As shown, the thickness of the second epitaxial layer 32 and the third epitaxial layer 33 is 5 μm. The horizontal spacing between the first marking pattern 310 and the second marking pattern 320 must be greater than 10 μm, and the horizontal spacing between the first marking pattern 310 and the third marking pattern 330 must be greater than 20 μm. The sum of the epitaxial thicknesses of the first epitaxial layer 31 and the second epitaxial layer 32 above the substrate 1 is 10 μm. Therefore, the horizontal spacing between the zero layer mark 101 and the second marking pattern 320 must be at least greater than 20 μm.
[0057] In this embodiment, any two marker patterns in the alignment layers form a set of overlay offset measurement markers. The overlay offset between the two alignment layers is determined by measuring the distance between the center lines of the marker patterns in the same set. For example, measuring the distance between the center line of the first marker pattern 310 and the center line of the second marker pattern 320 can determine the overlay offset of the second epitaxial layer 32 relative to the first epitaxial layer 31; measuring the distance between the center line of the zero layer marker 101 and the center line of the first marker pattern 310 can determine the overlay offset of the first epitaxial layer 31 relative to the substrate 1.
[0058] In this embodiment, the multiple epitaxial layers can be epitaxial layers of a first conductivity type. The first conductivity type can be N-type or P-type.
[0059] The method for fabricating a superjunction device in this embodiment further includes: etching multiple epitaxial layers to form multiple trenches; filling the multiple trenches with a semiconductor material layer of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type.
[0060] This application also provides a superjunction device, which can be fabricated using the superjunction device fabrication method provided in this application.
[0061] refer to Figure 10 As shown, the superjunction device includes a substrate 1 and a plurality of epitaxial layers stacked on the substrate 1. At least two of the plurality of epitaxial layers serve as alignment layers. The alignment layers are formed with marking patterns for photolithographic alignment. The marking patterns are trenches located in the alignment layers. The marking patterns of the lower alignment layer affect the top surface profile of a first region of the upper alignment layer. The marking patterns of the upper alignment layer are formed outside the first region.
[0062] Specifically, the material of substrate 1 can be silicon, germanium, germanium silicon, silicon carbide, gallium arsenide or indium gallium arsenide, or it can be silicon on insulator, germanium on insulator, or other materials, such as gallium arsenide or other III-V compounds.
[0063] refer to Figure 10 As shown, a trench-type zero-layer mark 101 is formed in the substrate 1; the zero-layer mark 101 is a trench-type mark point.
[0064] In some embodiments of this application, there are several epitaxial layers without marked patterns between two adjacent alignment layers.
[0065] In other embodiments of this application, such as Figure 10 As shown, each epitaxial layer has a marking pattern, meaning each epitaxial layer is an alignment layer, to ensure that the photolithographic overlay offset value of each epitaxial layer meets the requirements.
[0066] In this embodiment, the marking patterns in the plurality of epitaxial layers are formed outside the region of the epitaxial layer affected by the zero layer marking 101; the marking patterns of the lower alignment layer affect the top surface profile of the first region of the upper alignment layer, and the marking patterns of the upper alignment layer are formed outside the first region.
[0067] For example, refer to Figure 10 As shown, the multiple epitaxial layers include, but are not limited to, a first epitaxial layer 31, a second epitaxial layer 32, and a third epitaxial layer 33. A first marker pattern 310, a second marker pattern 320, and a third marker pattern 330 are respectively formed in the first epitaxial layer 31, the second epitaxial layer 32, and the third epitaxial layer 33. The extension of the zero-layer marker 101 affects the top surface contours of region A0 of the first epitaxial layer 31, region A2 of the second epitaxial layer 32, and region A3 of the third epitaxial layer 33. To avoid the zero-layer marker 101 affecting the marker patterns in the multiple epitaxial layers, the first marker pattern 310 of the first epitaxial layer 31 is located outside region A0 of the first epitaxial layer 31, the second marker pattern 320 of the second epitaxial layer 32 is located outside region A2 of the second epitaxial layer 32, and the third marker pattern 330 of the third epitaxial layer 32 is located outside region A3 of the third epitaxial layer 32.
[0068] The extension of the first marker pattern 310 affects the top surface contour of region A1 of the second epitaxial layer 32 and region A4 of the third epitaxial layer 33. The second marker pattern 320 is also disposed outside region A1 of the second epitaxial layer 32, and the third marker pattern 330 is also disposed outside region A4 of the third epitaxial layer 33.
[0069] The extension of the second marker pattern 320 affects the top surface contour of region A5 of the third epitaxial layer 33, and the third marker pattern 330 is also set outside region A5 of the third epitaxial layer 33.
[0070] For the two alignment layers, the thickness of the epitaxial layer between the two alignment layers is D1, the thickness of the upper epitaxial layer of the two alignment layers is D2, and the vertical spacing of the marking patterns of the two alignment layers in the epitaxial layer thickness direction is D3, where D3>2(D1+D2), in order to ensure that the marking pattern of the lower layer does not interfere with the marking pattern of the upper layer.
[0071] In this embodiment, all epitaxial layers are N-type epitaxial layers, and multiple trenches are formed in the multiple epitaxial layers. These trenches may be filled with a P-type semiconductor material layer. In other embodiments, all multiple epitaxial layers may be P-type epitaxial layers, and the semiconductor material layer may be N-type.
[0072] The present invention provides a method for improving epitaxial layer overlay misalignment, a method for fabricating a superjunction device, and a superjunction device. In this method, multiple epitaxial layers are stacked on a substrate 1. At least two of the multiple epitaxial layers serve as alignment layers. The alignment layers have marking patterns for photolithographic alignment. These marking patterns are trenches located within the alignment layers. The marking pattern of the lower alignment layer affects the top surface contour of a first region of the upper alignment layer. The marking pattern of the upper alignment layer is formed outside the first region. Thus, the epitaxial shape of the marking pattern of the lower alignment layer does not affect the photolithographic alignment of the marking pattern of the upper alignment layer. This reduces the photolithographic overlay misalignment value of the multiple epitaxial layers, lowers the photolithographic rework rate, and consequently reduces production costs and production cycle. It also helps improve the performance of the superjunction device.
[0073] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for improving epitaxial layer overlay misalignment, characterized in that, The method includes providing a substrate and stacking multiple epitaxial layers on the substrate, at least two of which serve as alignment layers. The alignment layers are formed with marking patterns for photolithographic alignment. The marking patterns are trenches located in the alignment layers. The marking patterns of the lower alignment layer affect the top surface profile of a first region of the upper alignment layer. The marking patterns of the upper alignment layer are formed outside the first region.
2. The method for improving epitaxial layer overlay misalignment as described in claim 1, characterized in that, For the two alignment layers, the epitaxial layer thickness between the two alignment layers is D1, the thickness of the upper epitaxial layer of the two alignment layers is D2, and the vertical spacing of the marking patterns of the two alignment layers in the epitaxial layer thickness direction is D3, where D3>2(D1+D2).
3. The method for improving epitaxial layer overlay misalignment as described in claim 1, characterized in that, Each of the epitaxial layers has the marked pattern formed therein; or, there are several epitaxial layers without marked patterns between two adjacent alignment layers.
4. The method for improving epitaxial layer overlay misalignment as described in claim 1, characterized in that, The substrate has trench-type zero-layer markers formed in it; the marker patterns in the plurality of epitaxial layers are formed outside the regions of the epitaxial layers affected by the zero-layer markers.
5. A method for fabricating a superjunction device, characterized in that, The method includes providing a substrate and stacking a plurality of epitaxial layers on the substrate, wherein a marking pattern is formed in the plurality of epitaxial layers using the method for improving epitaxial layer overlay offset as described in any one of claims 1 to 4.
6. A superjunction device, characterized in that, The device includes a substrate and a plurality of epitaxial layers stacked on the substrate, at least two of the plurality of epitaxial layers serving as alignment layers, wherein the alignment layers are provided with marking patterns for photolithographic alignment, the marking patterns being trenches located in the alignment layers, wherein the marking patterns of the lower alignment layer affect the top surface profile of a first region of the upper alignment layer, and the marking patterns of the upper alignment layer are formed outside the first region.
7. The superjunction device as described in claim 6, characterized in that, For the two alignment layers, the epitaxial layer thickness between the two alignment layers is D1, the thickness of the upper epitaxial layer of the two alignment layers is D2, and the vertical spacing of the marking patterns of the two alignment layers in the epitaxial layer thickness direction is D3, where D3>2(D1+D2).
8. The superjunction device as described in claim 6, characterized in that, Each of the epitaxial layers has the marked pattern formed therein; or, there are several epitaxial layers without marked patterns between two adjacent alignment layers.
9. The superjunction device as described in claim 6, characterized in that, The substrate has trench-type zero-layer markers formed in it; the marker patterns in the plurality of epitaxial layers are formed outside the regions of the epitaxial layers affected by the zero-layer markers.
10. The superjunction device as described in claim 6, characterized in that, All of the aforementioned epitaxial layers are either N-type epitaxial layers or P-type epitaxial layers.