Chip structure with salient points and preparation method thereof

Abstract

The invention provides a chip structure with salient points and a preparation method thereof. The chip structure comprises a substrate, and a top metal layer is arranged on the substrate; the passivation layer covers the surface of the substrate and the outer wall of the top metal layer, and a plurality of hole-shaped openings are formed in the passivation layer to expose part of the surface of the top metal layer; the bump is arranged in the hole-shaped opening and protrudes out of the surface of the passivation layer, the bump is connected with the corresponding top metal layer, and the material of the bump comprises a solder material. According to the invention, the success rate and effect of chip packaging can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a chip structure with bumps and its fabrication method. Background Technology

[0002] As device sizes continue to shrink and product integration increases, wire bonding can no longer meet the chip packaging industry's demand for small-size packages. Flip-chip packaging, achieved through ball bonding, has gradually become the mainstream due to its relative advantage in small package sizes.

[0003] In the current flip-chip packaging process, bump (ball placement) fabrication is a crucial step, all of which is completed during the packaging process. The main bump formation methods in related technologies are as follows: First, applying solder paste to the pads using a stencil, then reflowing it to form balls to create bumps; second, forming bumps of a certain height on the pad surface using electroless plating; third, plating metal with a specific diameter and height into the photoresist apertures using electroplating, which can be annealed or reflowed to form balls depending on the material; fourth, applying flux and arranging solder balls (ball placement) sequentially on the pads using a stencil, then reflowing it to form balls to create bumps.

[0004] The above four methods for making bumps have basically met the requirements of most bumps. However, with the development of technical requirements and the differences in applications, more requirements are put forward for the ball-mounting process in packaging, such as how to further miniaturize the size of the bumps and how to control the size difference between the bumps to improve the subsequent bonding success. Summary of the Invention

[0005] To address the aforementioned technical problems, the present invention provides a chip structure with bumps, comprising:

[0006] Substrate, wherein a top metal layer is provided on the substrate;

[0007] A passivation layer covers the surface of the substrate and the outer wall of the top metal layer, and the passivation layer has a plurality of hole-like openings that expose a portion of the surface of the top metal layer;

[0008] A bump is provided in the hole-shaped opening and protrudes from the surface of the passivation layer. The bump is connected to the corresponding top metal layer. The material of the bump includes solder material.

[0009] Optionally, the passivation layer includes a first dielectric layer and a second dielectric layer formed sequentially, wherein the first dielectric layer covers the surface of the substrate and the surface of the top metal layer, the second dielectric layer covers the surface of the first dielectric layer, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

[0010] Optionally, the perforated opening may also extend partially into the top metal layer.

[0011] According to another aspect of the present invention, a method for fabricating a chip structure having bumps is also provided, comprising:

[0012] A substrate is provided, wherein a top metal layer is disposed on the substrate;

[0013] A passivation layer is formed on the substrate and the top metal layer, the passivation layer extending beyond the thickness of the top metal layer by a first thickness;

[0014] The passivation layer is patterned to form a plurality of hole-like openings in the passivation layer to expose a portion of the surface of the top metal layer;

[0015] Solder material is filled into the hole-shaped opening, and the solder material is connected to the corresponding top metal layer;

[0016] Remove the passivation layer of the second thickness, so that the solder material protrudes from the hole opening, and use the solder material as a bump, wherein the second thickness is less than the first thickness.

[0017] Optionally, the step of forming the passivation layer and the bumps further includes:

[0018] A first dielectric layer and a second dielectric layer are sequentially formed to conformally cover the surface of the substrate and the outer wall of the top metal layer, and the first dielectric layer and the second dielectric layer are used as the passivation layer;

[0019] The passivation layer is patterned to form a plurality of hole-like openings in the passivation layer to expose a portion of the surface of the top metal layer;

[0020] Solder material is formed to cover the surface of the second dielectric layer and fill the pore-shaped openings;

[0021] A grinding process is performed to remove solder material outside the hole opening and to make the solder material in the hole opening flush with the surface of the surrounding second dielectric layer.

[0022] Remove the second dielectric layer of the second thickness, so that the solder material protrudes from the surface of the second dielectric layer, and use the solder material as a bump.

[0023] Optionally, the first dielectric layer comprises silicon oxide, and the second dielectric layer comprises silicon nitride.

[0024] Optionally, a first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially formed to cover the surface of the substrate and the outer wall of the top metal layer, and the first dielectric layer, the second dielectric layer, and the third dielectric layer are used as the passivation layer.

[0025] The passivation layer is patterned to form a plurality of hole-like openings in the passivation layer to expose a portion of the surface of the top metal layer;

[0026] Solder material is formed to cover the surface of the second dielectric layer and fill the pore-shaped openings;

[0027] A grinding process is performed to remove solder material outside the hole opening and to make the solder material in the hole opening flush with the surface of the surrounding third dielectric layer.

[0028] Remove the third dielectric layer and a portion of the second dielectric layer, so that the solder material protrudes from the surface of the second dielectric layer, and use the solder material as a bump.

[0029] Optionally, the first dielectric layer comprises silicon oxide, the second dielectric layer comprises silicon nitride, and the third dielectric layer comprises silicon oxide.

[0030] Optionally, after forming the passivation layer on the substrate and the top metal layer, and before forming the solder material, a polishing process is performed on the passivation layer to give it a flat surface.

[0031] Optionally, after the bumps are formed, an annealing process is performed on the substrate to reflow the bumps.

[0032] In summary, this invention provides a chip structure with bumps and its fabrication method. The chip structure includes a substrate with a top metal layer; a passivation layer covering the surface of the substrate and the outer wall of the top metal layer, the passivation layer having a plurality of apertures exposing a portion of the surface of the top metal layer; and bumps disposed in the apertures and protruding from the surface of the passivation layer, the bumps being connected to the corresponding top metal layer, the bumps being made of solder material. This application can improve the success rate and effectiveness of chip packaging. Compared to forming solder balls as bumps on the chip surface during the packaging process, this application can form bumps with smaller spacing, smaller size, and more uniform size through wafer-level processes (photolithography, deposition, and polishing) in the back-end chip manufacturing process, which is beneficial to improving the success rate and efficiency of packaging (soldering and bonding). Moreover, the process for preparing the above-mentioned bumps can be combined with the process for preparing the passivation layer and adopts common back-end process steps, thus having better practicality. Attached Figure Description

[0033] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0034] Figure 1 A flowchart illustrating a method for fabricating a chip structure with bumps, provided in an embodiment of this application;

[0035] Figures 2A-2F This is a schematic diagram of the corresponding steps in a method for fabricating a chip structure with bumps provided in this embodiment;

[0036] Figures 3A-3F This is a schematic diagram of the corresponding steps in another method for fabricating a chip structure with bumps provided in this embodiment.

[0037] In the attached figures: 10-substrate; 11-top metal layer; 11a-pad; 11b-metal interconnect; 20-passivation layer; 21-first dielectric layer; 22-second dielectric layer; 23-third dielectric layer; 24-hole opening; 25-solder material; 26-bump; H1-first thickness; H2-second thickness. Detailed Implementation

[0038] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0039] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0040] This application provides a method for fabricating a chip structure with bumps.

[0041] Figure 1 A flowchart illustrating a method for fabricating a chip structure with bumps, as provided in an embodiment of this application.

[0042] like Figure 1 As shown in the embodiments of this application, the method for fabricating a chip structure with bumps includes:

[0043] S01: A substrate is provided, wherein a top metal layer is provided on the substrate;

[0044] S02: A passivation layer is formed on the substrate and the top metal layer, wherein the passivation layer extends beyond the thickness of the top metal layer by a first thickness;

[0045] S03: The passivation layer is patterned to form a plurality of hole-like openings in the passivation layer to expose a portion of the surface of the top metal layer;

[0046] S04: Fill the hole-shaped opening with solder material, and the solder material is connected to the corresponding top metal layer;

[0047] S05: Remove the passivation layer of the second thickness, so that the solder material protrudes from the hole opening, and use the solder material as a bump, wherein the second thickness is less than the first thickness.

[0048] Figures 3A-3F This is a schematic diagram of the corresponding steps in the method for fabricating a chip structure with bumps provided in this embodiment. The following will be combined with... Figures 3A-3F This embodiment provides a detailed description of the method for fabricating a chip structure with bumps.

[0049] First, perform step S01, please refer to... Figure 2A A substrate 10 is provided, on which a top metal layer 11 is provided.

[0050] The substrate 10 may be a wafer to be processed in subsequent stages, and may include a semiconductor substrate, a semiconductor device layer, multiple metal interconnect layers, and a top metal layer 11 sequentially disposed. The top metal layer 11 is exposed on the surface of the substrate 10, and may include a first barrier metal layer, a body metal layer, and a second barrier metal layer sequentially disposed. The body metal layer may include aluminum or an aluminum alloy, and the first barrier metal layer and / or the second barrier metal layer may include titanium and / or titanium nitride. Alternatively, the top metal layer 11 may include metal interconnects 11b and metal pads 11a.

[0051] Next, proceed to step S02, please refer to... Figure 2B A passivation layer 20 is formed on the substrate 10 and the top metal layer 11, and the passivation layer 20 extends beyond the thickness of the top metal layer 11 by a first thickness H1.

[0052] The passivation layer 20 may include a first dielectric layer 21 and a second dielectric layer 22 disposed sequentially. The first dielectric layer 21 conformally covers the surface of the substrate 10 and the outer wall of the top metal layer 11. The second dielectric layer 22 covers the surface of the first dielectric layer 21. The second dielectric layer 22 can serve as the main body to protect the top metal layer 11, that is, the thickness of the second dielectric layer 22 is greater than the thickness of the first dielectric layer 21. The material of the second dielectric layer 22 may include, for example, silicon nitride. The first dielectric layer 21 can serve as a pad for the second dielectric layer 22. The material of the first dielectric layer 21 may include silicon oxide.

[0053] After forming the first dielectric layer 21 and the second dielectric layer 22, a polishing process is performed on the passivation layer 20 (i.e., the second dielectric layer 22) to give it a flat surface. At this time, the thickness of the passivation layer 20 (i.e., the polished passivation layer 20) exceeding the top metal layer 11 is the first thickness H1. This first thickness H1 can be determined based on the height of the bumps 26 on the subsequent top metal layer 11, and the first thickness H1 is greater than the height of the bumps 26. Of course, before polishing, the thickness of the first dielectric layer 21 and the second dielectric layer 22 formed is greater than the first thickness H1.

[0054] In one example, the thickness of the first dielectric layer 21 and the second dielectric layer 22 before polishing can be 4 micrometers to 6 micrometers, and the thickness of the first dielectric layer 21 and the second dielectric layer 22 after polishing can be 3 micrometers to 5 micrometers. The first thickness H1 (the thickness of the passivation layer 20 exceeding the thickness of the top metal layer 11) can be 2.5 micrometers to 4.5 micrometers.

[0055] Next, proceed to step S03, please refer to... Figure 2C The passivation layer 20 is patterned to form several hole-like openings 24 in the passivation layer 20 to expose part of the surface of the top metal layer 11.

[0056] A patterned mask layer is formed on the passivation layer 20. The patterned mask layer has multiple openings that expose the passivation layer 20 above the metal pads 11a. Then, the passivation layer 20 is etched to form a number of hole-shaped openings 24 that expose part of the surface of the top metal layer 11. The patterned mask layer is then removed. The cross-sectional shape of the hole-shaped openings 24 can be rectangular or trapezoidal. The cross-sectional size of the hole-shaped openings 24 can be matched with the size of the subsequent bumps 26.

[0057] In some examples, after the top metal layer 11 surface is exposed by performing an etching process, a portion of the top metal layer 11 may also be etched, for example, to make a hole-like opening 24 extend into the second barrier metal layer.

[0058] In some examples, the diameter of the aperture 24 may be, for example, 20 micrometers to 50 micrometers, and larger than the diameter of the probe on the probe card (for example, 10 micrometers to 25 micrometers). After the aperture 24 is formed in the passivation layer 20, the probe can be inserted into the aperture 24 to perform electrical tests on each chip in the substrate 10.

[0059] Next, step S04 is performed, in which solder material 25 is filled into the hole-shaped opening 24, and the solder material 25 is connected to the corresponding top metal layer 11.

[0060] Please refer to Figure 2DSolder material 25 is formed to cover the surface of the second dielectric layer 22 and fill the orifice 24. Before forming the solder material 25, a barrier adhesion layer may be formed to conformally cover the surface of the second dielectric layer 22 and the inner wall of the orifice 24. Then, for example, solder material 25 is formed to cover the barrier adhesion layer and fill the orifice 24 by PVD or chemical electroplating. The barrier adhesion layer is used to prevent the diffusion of metal materials and to facilitate the adhesion of solder material 25. The barrier adhesion layer may include one or more layers of metal materials, such as titanium, titanium nitride and titanium from bottom to top. Solder material 25 may be tin-based solder, that is, an alloy material including tin.

[0061] Please refer to Figure 2E A polishing process (chemical mechanical polishing) is performed to remove the solder material 25 and the barrier adhesion layer outside the hole opening 24, making the solder material 25 in the hole opening 24 flush with the surface of the surrounding second dielectric layer 22, and matching the thickness (height) of the remaining solder material 25 in the hole opening 24 with the height of the subsequent bump 26. For example, the thickness of the remaining solder material 25 in the hole opening 24 is equal to or slightly greater than the height of the subsequent bump 26. In other words, the thickness of the remaining passivation layer 20 on the top metal layer 11 is substantially equal to the height of the subsequent bump 26. At this time, the thickness of the remaining passivation layer 20 on the top metal layer 11 is the same as the thickness of the solder material 25.

[0062] Next, proceed to step S05, please refer to... Figure 2F Remove the passivation layer 20 of the second thickness H2, so that the solder material 25 protrudes from the hole opening 24, and use the solder material 25 as a bump 26. The second thickness H2 is less than the first thickness H1.

[0063] The passivation layer 20 of the second thickness H2 can be removed by dry etching or wet etching, exposing the surface and part of the sidewalls of the solder material 25 to the surface of the passivation layer 20. This thins the passivation layer 20, and the remaining solder material 25 in the hole-like opening 24 after thinning the passivation layer 20 serves as the bump 26. Thus, the preparation of the bump 26 on the chip is completed simultaneously with the back-end process of the chip structure. The second dielectric layer 22 of the second thickness H2 can be removed by controlling the etching time to achieve the thinning of the passivation layer 20 of the second thickness H2. That is, the height of the bump 26 protruding relative to the surface of the passivation layer 20 after thinning is the second thickness H2. The size of the second thickness H2 can be determined according to the packaging requirements of different products. For example, for BCD devices, the second thickness H2 can be 2 micrometers to 5 micrometers. In some examples, after forming the bump 26, an annealing process can be performed on the bump 26 on the substrate 10 to make the bump 26 a smooth sphere (reflow).

[0064] Compared to forming solder balls as bumps 26 on the chip surface during the packaging process, this application can form bumps 26 with smaller spacing, smaller size, and more uniform size through wafer-level processes (photolithography, deposition, and polishing) in the back-end chip manufacturing process. This is beneficial to improving the success rate and efficiency of packaging (soldering and bonding). Moreover, the process for preparing the bumps 26 can be combined with the process for preparing the passivation layer 20 and adopts common back-end process steps, thus having better practicality.

[0065] This application also provides a method for fabricating a chip structure with bumps.

[0066] Figure 1 A flowchart illustrating a method for fabricating a chip structure with bumps, as provided in an embodiment of this application.

[0067] like Figure 1 As shown in the embodiments of this application, the method for fabricating a chip structure with bumps includes:

[0068] S01: A substrate is provided, wherein a top metal layer is provided on the substrate;

[0069] S02: A passivation layer is formed on the substrate and the top metal layer, wherein the passivation layer extends beyond the thickness of the top metal layer by a first thickness;

[0070] S03: The passivation layer is patterned to form a plurality of hole-like openings in the passivation layer to expose a portion of the surface of the top metal layer;

[0071] S04: Fill the hole-shaped opening with solder material, and the solder material is connected to the corresponding top metal layer;

[0072] S05: Remove the passivation layer of the second thickness, so that the solder material protrudes from the hole opening, and use the solder material as a bump, wherein the second thickness is less than the first thickness.

[0073] Figures 3A-3F This is a schematic diagram of the corresponding steps in the method for fabricating a chip structure with bumps provided in this embodiment. The following will be combined with... Figures 3A-3F This embodiment provides a detailed description of the method for fabricating a chip structure with bumps.

[0074] First, perform step S01, please refer to... Figure 3A A substrate 10 is provided, on which a top metal layer 11 is provided.

[0075] The substrate 10 may be a wafer to be processed in subsequent stages, and may include a semiconductor substrate, a semiconductor device layer, multiple metal interconnect layers, and a top metal layer 11 sequentially disposed. The top metal layer 11 is exposed on the surface of the substrate 10, and may include a first barrier metal layer, a body metal layer, and a second barrier metal layer sequentially disposed. The body metal layer may include aluminum or an aluminum alloy, and the first barrier metal layer and / or the second barrier metal layer may include titanium and / or titanium nitride. Alternatively, the top metal layer 11 may include metal interconnects 11b and metal pads 11a.

[0076] Next, proceed to step S02, please refer to... Figure 3B A passivation layer 20 is formed on the substrate 10 and the top metal layer 11, and the passivation layer 20 extends beyond the thickness of the top metal layer 11 by a first thickness H1.

[0077] The passivation layer 20 may include a first dielectric layer 21, a second dielectric layer 22, and a third dielectric layer 23 sequentially disposed. The first dielectric layer 21 conformally covers the surface of the substrate 10 and the outer wall of the top metal layer 11. The second dielectric layer 22 covers the surface of the first dielectric layer 21, and the third dielectric layer 23 covers the surface of the second dielectric layer 22. The second dielectric layer 22 can serve as the main body for protecting the top metal layer 11; that is, the thickness of the second dielectric layer 22 is greater than the thickness of the first dielectric layer 21. The material of the second dielectric layer 22 may include, for example, silicon nitride. The first dielectric layer 21 can serve as a pad for the second dielectric layer 22; the material of the first dielectric layer 21 may include silicon oxide. The third dielectric layer 23 can serve as a filler layer for reducing the stress of the passivation layer 20; the material of the second dielectric layer 22 may include silicon oxide. It should be understood that compared to a passivation layer 20 that is only used to protect the top metal layer 11, the passivation layer 20 of this application is relatively thicker. If the thickness of the second dielectric layer 22 (e.g., silicon nitride) is too thick, it will lead to excessive stress and affect the yield.

[0078] After forming the first dielectric layer 21, the second dielectric layer 22, and the third dielectric layer 23, a polishing process is performed on the passivation layer 20 (i.e., the third dielectric layer 23) to give it a flat surface. At this point, the thickness of the passivation layer 20 (i.e., the polished passivation layer 20) exceeding the top metal layer 11 is the first thickness H1. This first thickness H1 can be determined based on the height of the bumps 26 on the subsequent top metal layer 11, and is made slightly greater than or equal to the height of the subsequent bumps 26. Furthermore, the thickness of the second dielectric layer 22 can be equal to or slightly greater than the thickness of the passivation layer 20 after thinning; that is, the second dielectric layer 22 can be used as an etching stop layer to control the thinning thickness of the passivation layer 20 (i.e., the subsequent second thickness H2).

[0079] In one example, the thickness of the first dielectric layer 21, the second dielectric layer 22, and the third dielectric layer 23 before polishing can be 4 micrometers to 6 micrometers, the thickness of the first dielectric layer 21 and the second dielectric layer 22 after polishing can be 3 micrometers to 5 micrometers, and the first thickness H1 (the thickness of the passivation layer 20 exceeding the thickness of the top metal layer 11) can be 2.5 micrometers to 4.5 micrometers.

[0080] Next, proceed to step S03, please refer to... Figure 3C The passivation layer 20 is patterned to form several hole-like openings 24 in the passivation layer 20 to expose part of the surface of the top metal layer 11.

[0081] A patterned mask layer is formed on the passivation layer 20. The patterned mask layer has multiple openings that expose the passivation layer 20 above the metal pads 11a. Then, the passivation layer 20 is etched to form a number of hole-shaped openings 24 that expose part of the surface of the top metal layer 11. The patterned mask layer is then removed. The cross-sectional shape of the hole-shaped openings 24 can be rectangular or trapezoidal. The cross-sectional size of the hole-shaped openings 24 can be matched with the size of the subsequent bumps 26.

[0082] In some examples, after the top metal layer 11 surface is exposed by performing an etching process, a portion of the top metal layer 11 may also be etched, for example, to make a hole-like opening 24 extend into the second barrier metal layer.

[0083] In some examples, the diameter of the aperture 24 may be, for example, 20 micrometers to 50 micrometers, and larger than the diameter of the probe on the probe card (for example, 10 micrometers to 25 micrometers). After the aperture 24 is formed in the passivation layer 20, the probe can be inserted into the aperture 24 to perform electrical tests on each chip in the substrate 10.

[0084] Next, step S04 is performed, in which solder material 25 is filled into the hole-shaped opening 24, and the solder material 25 is connected to the corresponding top metal layer 11.

[0085] Please refer to Figure 3D Solder material 25 is formed to cover the surface of the second dielectric layer 22 and fill the orifice 24. Before forming solder material 25, a barrier adhesion layer may be formed to conformally cover the surface of the third dielectric layer 23 and the inner wall of the orifice 24. Then, solder material 25 is formed to cover the barrier adhesion layer and fill the orifice 24, for example, by PVD or chemical electroplating. The barrier adhesion layer is used to prevent the diffusion of metal materials and to facilitate the adhesion of solder material 25. The barrier adhesion layer may include one or more layers of metal materials, for example, titanium, titanium nitride and titanium from bottom to top. Solder material 25 may be tin-based solder, that is, an alloy material including tin.

[0086] Please refer to Figure 3EUsing the passivation layer 20 as an etching stop layer, a polishing process (chemical mechanical polishing) is performed to remove the solder material 25 and the barrier adhesion layer outside the hole opening 24, making the solder material 25 in the hole opening 24 flush with the surface of the surrounding third dielectric layer 23, and matching the thickness (height) of the remaining solder material 25 in the hole opening 24 with the height of the subsequent bump 26. For example, the thickness of the remaining solder material 25 in the hole opening 24 is equal to or slightly greater than the height of the subsequent bump 26. In other words, the thickness of the remaining passivation layer 20 on the top metal layer 11 is approximately equal to the height of the subsequent bump 26. At this time, the thickness of the remaining passivation layer 20 on the top metal layer 11 is the same as the thickness of the solder material 25.

[0087] Next, proceed to step S05, please refer to... Figure 3F Remove the passivation layer 20 of the second thickness H2, so that the solder material 25 protrudes from the hole opening 24, and use the solder material 25 as a bump 26. The second thickness H2 is less than the first thickness H1.

[0088] The passivation layer 20 of the second thickness H2 can be removed by dry etching or wet etching, exposing the surface and part of the sidewalls of the solder material 25 to the surface of the passivation layer 20. This thins the passivation layer 20, and the remaining solder material 25 in the hole-like opening 24 after thinning the passivation layer 20 serves as the bump 26. Thus, the preparation of the bump 26 on the chip is completed simultaneously with the completion of the back-end process of the chip structure. Specifically, the passivation layer 20 of the second thickness H2 can be thinned by controlling the etching time to etch a portion of the thickness of the third dielectric layer 23 and the second dielectric layer 22. That is, the height of the bump 26 protruding relative to the surface of the passivation layer 20 after thinning is the second thickness H2. The size of the second thickness H2 can be determined according to the packaging requirements of different products. For example, for BCD devices, the second thickness H2 can be, for example, 2 micrometers to 5 micrometers. In some examples, after the bumps 26 are formed, an annealing process can be performed on the bumps 26 on the substrate 10 to make the bumps 26 into smooth spheres (reflow).

[0089] In this application, an etching process for the third dielectric layer 23 can be performed first, and the etching can be stopped at the surface of the second dielectric layer 22. Then, an etching process for the second dielectric layer 22 can be performed to accurately remove the third dielectric layer 23 and the second dielectric layer 22 with a second thickness H2, thereby ensuring that the thickness of the remaining second dielectric layer 22 meets the requirements.

[0090] Compared to forming solder balls as bumps 26 on the chip surface during the packaging process, this application can form bumps 26 with smaller spacing, smaller size, and more uniform size through wafer-level processes (photolithography, deposition, and polishing) in the back-end chip manufacturing process. This is beneficial to improving the success rate and efficiency of packaging (soldering and bonding). Moreover, the process for preparing the bumps 26 can be combined with the process for preparing the passivation layer 20 and adopts common back-end process steps, thus having better practicality.

[0091] This application also provides a chip structure with bumps.

[0092] Figure 2F This is a schematic diagram of a chip structure with bumps provided in an embodiment of this application.

[0093] like Figure 2F As shown, the chip structure with bumps provided in this embodiment includes a substrate 10, a passivation layer 20, and bumps 26. A top metal layer 11 is disposed on the substrate 10. The passivation layer 20 covers the surface of the substrate 10 and the outer wall of the top metal layer 11, and a plurality of apertures 24 are provided in the passivation layer 20 to expose a portion of the surface of the top metal layer 11. The bumps 26 are disposed in the apertures 24 and protrude from the surface of the passivation layer 20. The bumps 26 are connected to the corresponding top metal layer 11, and the material of the bumps 26 includes solder material.

[0094] The chip structure of this application can be in the state before and after the packaging process, that is, after the passivation layer 20 and bumps 26 are fabricated in the later stages of the process. Please continue to refer to Figure 2F The top metal layer 11 is exposed on the surface of the substrate 10. The top metal layer 11 may include a first barrier metal layer, a main metal layer, and a second barrier metal layer disposed sequentially. The main metal layer may include aluminum or an aluminum alloy, and the first and / or second barrier metal layers may include titanium and / or titanium nitride. Alternatively, the top metal layer 11 may include metal interconnects 11b and metal pads 11a. The passivation layer 20 may include a first dielectric layer 21 and a second dielectric layer 22 disposed sequentially. The first dielectric layer 21 conformally covers the surface of the substrate 10 and the outer wall of the top metal layer 11, and the second dielectric layer 22 covers the surface of the first dielectric layer 21. The second dielectric layer 22 may serve as a main layer to protect the top metal layer 11, i.e., the thickness of the second dielectric layer 22 is greater than the thickness of the first dielectric layer 21. The material of the second dielectric layer 22 may include, for example, silicon nitride, and the first dielectric layer 21 may serve as a pad for the second dielectric layer 22. The material of the first dielectric layer 21 may include silicon oxide.

[0095] Please continue to refer to Figure 2FThe passivation layer 20 on pad 11a has multiple apertures 24 exposing the surface of the corresponding second barrier metal layer. Multiple bumps 26 are located in the apertures 24 and electrically connected to the corresponding pad 11a, protruding from the surface of the passivation layer 20. The protrusion height of the multiple bumps 26 is the second thickness H2. The material of the bumps 26 may include solder material for packaging with other chips or substrates. The solder material may be, for example, tin-based solder, i.e., an alloy material including tin. The cross-sectional dimensions and formation of the multiple bumps 26 may be the same or different, and may be set according to the size of the apertures 24. The longitudinal cross-sectional shape of the apertures 24 may be rectangular or inverted trapezoidal, and the bottom of the apertures 24 may also extend into the second barrier metal layer.

[0096] In some examples, a barrier adhesion layer may be provided between the bump 26 (solder material) and the passivation layer 20 on the sidewall of the aperture 24 and the pad 11a on the bottom wall. This barrier adhesion layer can prevent the diffusion of metal material and facilitate the adhesion of solder material. The barrier adhesion layer may include one or more layers of metal material, such as titanium, titanium nitride, and titanium from bottom to top. In other examples, the portion of the bump 26 protruding from the passivation layer 20 may also be spherical, which may be formed by annealing and reflowing the bump 26.

[0097] In summary, this invention provides a chip structure with bumps and its fabrication method. The chip structure includes a substrate with a top metal layer; a passivation layer covering the surface of the substrate and the outer wall of the top metal layer, the passivation layer having a plurality of apertures exposing a portion of the surface of the top metal layer; and bumps disposed in the apertures and protruding from the surface of the passivation layer, the bumps being connected to the corresponding top metal layer, the bumps being made of solder material. This application can improve the success rate and effectiveness of chip packaging. Compared to forming solder balls as bumps on the chip surface during the packaging process, this application can form bumps with smaller spacing, smaller size, and more uniform size through wafer-level processes (photolithography, deposition, and polishing) in the back-end chip manufacturing process, which is beneficial to improving the success rate and efficiency of packaging (soldering and bonding). Moreover, the process for preparing the above-mentioned bumps can be combined with the process for preparing the passivation layer and adopts common back-end process steps, thus having better practicality.

[0098] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A chip structure with bumps, characterized in that, include: Substrate, wherein a top metal layer is provided on the substrate; A passivation layer covers the surface of the substrate and the outer wall of the top metal layer, and the passivation layer has a plurality of hole-like openings that expose a portion of the surface of the top metal layer; A bump is provided in the hole-shaped opening and protrudes from the surface of the passivation layer. The bump is connected to the corresponding top metal layer. The material of the bump includes solder material.

2. The chip structure according to claim 1, characterized in that, The passivation layer includes a first dielectric layer and a second dielectric layer formed sequentially. The first dielectric layer covers the surface of the substrate and the surface of the top metal layer, and the second dielectric layer covers the surface of the first dielectric layer. The thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

3. The chip structure according to claim 1, characterized in that, The perforated opening also extends partially into the top metal layer.

4. A method for fabricating a chip structure with bumps, characterized in that, include: A substrate is provided, wherein a top metal layer is disposed on the substrate; A passivation layer is formed on the substrate and the top metal layer, the passivation layer extending beyond the thickness of the top metal layer by a first thickness; The passivation layer is patterned to form a plurality of hole-like openings in the passivation layer to expose a portion of the surface of the top metal layer; Solder material is filled into the hole-shaped opening, and the solder material is connected to the corresponding top metal layer; Remove the passivation layer of the second thickness, so that the solder material protrudes from the hole opening, and use the solder material as a bump, wherein the second thickness is less than the first thickness.

5. The method for preparing a chip structure with bumps according to claim 4, characterized in that, The step of forming the passivation layer and the bumps further includes: A first dielectric layer and a second dielectric layer are sequentially formed to conformally cover the surface of the substrate and the outer wall of the top metal layer, and the first dielectric layer and the second dielectric layer are used as the passivation layer; The passivation layer is patterned to form a plurality of hole-like openings in the passivation layer to expose a portion of the surface of the top metal layer; Solder material is formed to cover the surface of the second dielectric layer and fill the pore-shaped openings; A grinding process is performed to remove solder material outside the hole opening and to make the solder material in the hole opening flush with the surface of the surrounding second dielectric layer. Remove the second dielectric layer of the second thickness, so that the solder material protrudes from the surface of the second dielectric layer, and use the solder material as a bump.

6. The method for fabricating a chip structure with bumps according to claim 5, characterized in that, The first dielectric layer comprises silicon oxide, and the second dielectric layer comprises silicon nitride.

7. The method for fabricating a chip structure with bumps according to claim 4, characterized in that, A first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially formed to conformally cover the surface of the substrate and the outer wall of the top metal layer, and the first dielectric layer, the second dielectric layer, and the third dielectric layer are used as the passivation layer; The passivation layer is patterned to form a plurality of hole-like openings in the passivation layer to expose a portion of the surface of the top metal layer; Solder material is formed to cover the surface of the second dielectric layer and fill the pore-shaped openings; A grinding process is performed to remove solder material outside the hole opening and to make the solder material in the hole opening flush with the surface of the surrounding third dielectric layer. Remove the third dielectric layer and a portion of the second dielectric layer, so that the solder material protrudes from the surface of the second dielectric layer, and use the solder material as a bump.

8. The method for fabricating a chip structure with bumps according to claim 7, characterized in that, The first dielectric layer comprises silicon oxide, the second dielectric layer comprises silicon nitride, and the third dielectric layer comprises silicon oxide.

9. The method for preparing a chip structure with bumps according to any one of claims 4 to 8, characterized in that, After the passivation layer is formed on the substrate and the top metal layer, and before the solder material is formed, a polishing process is performed on the passivation layer to make the passivation layer have a flat surface.

10. The method for fabricating a chip structure with bumps according to claim 9, characterized in that, After the bumps are formed, an annealing process is performed on the substrate to reflow the bumps.

Images