Power supply integrity test method and device for silicon substrate

Abstract

The invention relates to a power supply integrity test method and device for a silicon substrate, and the method and device are applied to an upper computer in a test device connected with a to-be-tested silicon substrate, and the method comprises the steps: carrying out the failure behavior detection of the to-be-tested silicon substrate, and carrying out the detection of the failure behavior of the to-be-tested silicon substrate under the condition that the to-be-tested silicon substrate does not have the failure behavior; acquiring test data information acquired by a plurality of sensors arranged in the to-be-tested silicon substrate through a preset acquisition channel; wherein a plurality of sensors are arranged in different preset areas of the to-be-tested silicon substrate, and each sensor is used for feeding back acquired test data information of the position of the sensor to the upper computer; and determining a target area without errors in each area of the to-be-tested silicon substrate based on the test data information, and executing a reliability test on the target area to obtain an internal state test result of the to-be-tested silicon substrate. According to the invention, an accurate test result of the internal state of the silicon substrate can be obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon substrate testing, in particular to a power integrity test method and device for a silicon substrate. BACKGROUND

[0002] Silicon substrate chips are currently the key to high-density integrated circuits. Multiple chips are integrated on the same silicon substrate through photolithography metal interconnection lines, thereby replacing traditional cable connections and effectively improving space utilization and computing power. However, due to the complex wiring of the silicon substrate and the high process difficulty, the testing operation of the silicon substrate is very important.

[0003] In related technologies, the test method for the silicon substrate is mainly open-circuit test, that is, a test voltage is applied at one end of the silicon substrate, and whether there is an electrical signal at the corresponding other end of the silicon substrate is detected. If there is, it proves that the interconnection circuit in the silicon substrate is conductive and there is no phenomenon such as fracture. However, in related technologies, only a binary test result can be obtained, and the process defects of the internal interconnection structure of the silicon substrate cannot be detected, and an accurate test result of the internal state of the silicon substrate cannot be obtained.

[0004] Therefore, how to obtain an accurate test result of the internal state of the silicon substrate has become a technical problem to be solved. SUMMARY

[0005] Therefore, it is necessary to provide a power integrity test method and device for a silicon substrate in order to solve the above technical problems.

[0006] In a first aspect, the present application provides a test method for a silicon substrate, applied to an upper computer in a test device connected with a to-be-tested silicon substrate, comprising:

[0007] Detecting the failure behavior of the to-be-tested silicon substrate, and acquiring test data information collected by a plurality of sensors arranged in the to-be-tested silicon substrate through a preset acquisition channel in the case that there is no failure behavior in the to-be-tested silicon substrate; wherein a plurality of sensors are arranged in different preset regions of the to-be-tested silicon substrate, and each sensor is used to feed back test data information of the position of the sensor to the upper computer;

[0008] Determining a target region in which there is no error in each region of the to-be-tested silicon substrate based on the test data information, and performing a reliability test on the target region to obtain an internal state test result of the to-be-tested silicon substrate.

[0009] In one of the embodiments, a plurality of logic devices are further arranged in the to-be-tested silicon substrate; the test data information collected by the plurality of sensors arranged in the to-be-tested silicon substrate is acquired through the preset acquisition channel, comprising:

[0010] The test data information of the silicon substrate to be tested collected by each sensor is received by a plurality of logic devices integrated in the silicon substrate to be tested, wherein each sensor is connected with a logic device, and the logic device is connected with the acquisition channel.

[0011] In one of the embodiments, the test data information of the silicon substrate to be tested collected by each sensor is received by a plurality of logic devices integrated in the silicon substrate to be tested, including:

[0012] The acquisition instruction is input to the logic device through the acquisition channel; wherein the logic device is used to control the test data at the location of the connected sensor in response to the acquisition instruction;

[0013] The test data information corresponding to the acquisition instruction fed back by each logic device is obtained.

[0014] In one of the embodiments, the test data information of the silicon substrate to be tested collected by each sensor is received by a plurality of logic devices integrated in the silicon substrate to be tested, including:

[0015] The acquisition channel is controlled to be in the data acquisition state, and the test data information fed back by each logic device is obtained, wherein the logic device is used to control the test data at the location of the connected sensor based on the preset period, and store the obtained test data information, and when it is detected that the acquisition channel is in the data acquisition state, the stored test data information is fed back.

[0016] In one of the embodiments, the test data information of the silicon substrate to be tested collected by each sensor is received by a plurality of logic devices integrated in the silicon substrate to be tested, including:

[0017] The logic device level in the logic device is determined;

[0018] The test data of each sensor in the preset first range of each first-level logic device in the logic device is collected by a plurality of first-level logic devices in the logic device;

[0019] The test data of each sensor in the first-level logic device in the preset second range of each second-level logic device is collected by a plurality of second-level logic devices in the logic device, and the test data information of the silicon substrate to be tested is obtained.

[0020] In one of the embodiments, the failure behavior detection is performed on the silicon substrate to be tested, including:

[0021] The first test equipment is controlled to test the bump at the bottom of the silicon substrate to be tested, the first detection result is obtained, and it is determined whether there is a short-circuit area in the silicon substrate to be tested based on the first detection result, and the short-circuit area is marked as existing failure behavior;

[0022] The second test device is controlled to scan the silicon substrate to be tested to obtain a second detection result, and based on the second detection result, it is determined whether there is a failure region between the top bump and the bottom bump of the silicon substrate to be tested, and the failure region is marked as having a failure behavior.

[0023] In a case where the first detection result indicates that the silicon substrate to be tested does not have a short circuit region and the second detection result indicates that the silicon substrate to be tested does not have a short circuit region, it is determined that the silicon substrate to be tested does not have a failure behavior after bonding.

[0024] In one of the embodiments, the test device further comprises a probe and a core particle bonded to the silicon substrate to be tested, the probe is connected to the host computer, or the core particle is connected to the host computer; test data information collected by a plurality of sensors arranged in the silicon substrate to be tested is obtained through a preset acquisition channel, including:

[0025] Based on the probe, the test data information collected by the sensors is obtained through the probe pads on the silicon substrate to be tested; the probe pads are connected to the acquisition channel;

[0026] Or, based on the core particle, the test data information collected by the sensors is obtained through the acquisition channel, wherein the acquisition channel includes a logical channel between the probe pads and the sensors, and a logical channel between the core particle and the sensors.

[0027] In one of the embodiments, based on the test data information, a target region in which there is no error in each region of the silicon substrate to be tested is determined, including:

[0028] Determine the test data belonging to the same region; wherein the test data belonging to the same region includes through-silicon via input test data, power distribution network input test data and power distribution network output test data;

[0029] In a case where the difference between the through-silicon via input test data, the power distribution network input test data and the power distribution network output test data belonging to the same region and the power supply is less than a preset threshold, it is determined that the region is a target region without error.

[0030] In one of the embodiments, a reliability test is performed on the target region, including:

[0031] Determine a preset test period;

[0032] Based on the test period, the silicon substrate to be tested is repeatedly restarted and powered on, and a reliability test result of the silicon substrate to be tested is obtained from the sensor feedback of the silicon substrate to be tested after the repeated restart and power-on operation;

[0033] Obtain a test result of the silicon substrate to be tested based on the reliability test data.

[0034] In a second aspect, the application further provides a test device for a silicon substrate, comprising:

[0035] The detection module is configured to detect failure behaviors of the silicon substrate to be tested, and obtain test data information collected by a plurality of sensors arranged in the silicon substrate to be tested through a preset acquisition channel in a case where the silicon substrate to be tested does not have a failure behavior, wherein a plurality of sensors are arranged in different preset regions of the silicon substrate to be tested, and each sensor is configured to feed back test data information of a position where the sensor is located to an upper computer.

[0036] The generation module is configured to determine a target region in which there is no error in each region of the silicon substrate to be tested based on the test data information, and perform a reliability test on the target region to obtain an internal state test result of the silicon substrate to be tested.

[0037] The power integrity test method and device for the silicon substrate described above first detect failure behaviors of the silicon substrate to be tested, and obtain test data information collected by a plurality of sensors arranged in the silicon substrate to be tested through a preset acquisition channel in a case where the silicon substrate to be tested does not have a failure behavior, wherein a plurality of sensors are arranged in different preset regions of the silicon substrate to be tested, and each sensor is configured to feed back test data information of a position where the sensor is located to an upper computer. The target region in which there is no error in each region of the silicon substrate to be tested is determined based on the test data information, and a reliability test is performed on the target region to obtain an internal state test result of the silicon substrate to be tested. An accurate test result of the internal state of the silicon substrate can be obtained through the application. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the application or the related art, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the application or the related art. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0039] Figure 1 It is an application environment diagram of the test method for the silicon substrate in one embodiment;

[0040] Figure 2 It is a flowchart of the test method for the silicon substrate in one embodiment;

[0041] Figure 3 It is a flowchart of obtaining test data information in one embodiment;

[0042] Figure 4 a flowchart of a failure behavior detection process in an embodiment;

[0043] Figure 5 a flowchart of a failure behavior detection process in an embodiment;

[0044] Figure 6 a flowchart of a failure behavior detection process in an embodiment;

[0045] Figure 7 a flowchart of a failure behavior detection process in an embodiment;

[0046] Figure 8 a flowchart of a failure behavior detection process in an embodiment; DETAILED DESCRIPTION

[0047] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0048] The technical background of the present application will be described first.

[0049] In the conventional scheme, chips are usually integrated on respective board cards, and then connected between the board cards by cables. Due to these long-distance and large-size cables, the communication bandwidth between the chips is limited. In recent years, the concept of a silicon substrate chip has been proposed, which can integrate multiple chips on the same silicon substrate, and realize direct interconnection between the multiple chips by photoetching metal interconnection lines, thereby replacing the cables for connecting between the board cards. The silicon substrate is relatively large in size and can also be referred to as a silicon interposer. Due to the high number of internal wiring, long wiring distance, and high difficulty in preparing the photo mask splicing process, it is very important to test the on-off state of the metal lines inside the silicon substrate and the manufacturing process of the metal lines.

[0050] In the related art, the test of the internal state of the silicon substrate includes but is not limited to detecting whether there is an electrical signal at both ends of the silicon substrate in an open circuit state. If there is, it proves that the corresponding region of the silicon substrate inside is in a line conduction state and does not exist in a broken state. However, this test scheme can only obtain a binary test result, i.e., the test result only includes whether the metal line inside the silicon substrate is broken, and cannot more finely detect whether the structure inside the silicon substrate has a process defect. For example, in actual application, if a certain structure has a process defect, it can cause the silicon substrate inside to become a high resistance state (i.e., from a normal milliohm level to an ohm level), and the process defect cannot be tested by the method in the related art.

[0051] And further, in the related art, a probe station is often used to perform power-on testing on a silicon substrate, i.e., during the period when the probe pierces the surface of the silicon substrate, the power-on testing is performed. However, this solution can only observe the silicon substrate during the period when the probe pierces the surface of the silicon substrate, and cannot observe the level state of the silicon substrate in a long-term (e.g., 1000 hours) durability test. Moreover, the probe can only test one die at a time, while there are usually dozens of dies on the silicon substrate that need to be repeatedly tested, which will generate a very large amount of testing workload and testing cost.

[0052] In summary, the above description illustrates the main problems existing in the related art: the testing method in the related art is relatively rough, and can only obtain a binary testing result, and cannot accurately detect the state of the internal interconnection structure of the silicon substrate. Moreover, there are some secondary problems in the related art, for example, a large amount of time cost and workload is required for testing the silicon substrate, which will result in a low testing efficiency of the silicon substrate.

[0053] Based on this, the embodiments of the present application provide a testing method for a silicon substrate: based on a plurality of sensors arranged inside a to-be-tested silicon substrate, test data information of the internal interconnection structure of the silicon substrate is collected, and the test data information is analyzed to obtain the accurate state (such as whether it is broken, the specific pressure drop size of the metal structure, etc.) of the internal interconnection structure of the silicon substrate. Then, for a target region of the silicon substrate that does not have an error, a reliability test is performed, and based on the above-mentioned sensors, the reliability test result is collected to obtain the state test result inside the to-be-tested silicon substrate. Through the present application, the specific working condition of the internal interconnection structure of the silicon substrate can be collected by the sensors, and the testing efficiency can be greatly improved. For details, please refer to the following embodiments:

[0054] The testing method for a silicon substrate provided by the embodiments of the present application can be applied to, for example, Figure 1In the application environment shown, the silicon substrate to be tested 102 is connected to the test device 104, and the connection mode includes but is not limited to connecting the silicon substrate to be tested 102 and the test device 104 through a probe, or realizing data transmission between the silicon substrate to be tested 102 and the test device 104 through a die bonded on the silicon substrate to be tested 102. The data storage system can store the data required to be processed by the test device 104. The data storage system can be integrated on the test device 104, or placed on the cloud or other network servers. First, the silicon substrate to be tested is detected for failure behavior. In the case that the silicon substrate to be tested does not have failure behavior, test data information collected by a plurality of sensors arranged in the silicon substrate to be tested is obtained through a preset acquisition channel. A plurality of sensors are arranged in different preset regions of the silicon substrate to be tested, and each sensor is used to feed back test data information of the position of the sensor to the host computer. Based on the test data information, a target region in which there is no error in each region of the silicon substrate to be tested is determined, and reliability testing is performed on the target region to obtain an internal state test result of the silicon substrate to be tested. The silicon substrate to be tested 102 is a passive substrate, that is, there is only a metal interconnection line in the substrate, and there is no active device. The test device 104 can be a stand-alone computer device, or a cluster or distributed system composed of multiple computer devices, and can also include a probe station for testing a silicon substrate, a device for communicating with a die bonded on the silicon substrate to be tested, and the like.

[0055] In one exemplary embodiment, as shown in Figure 2 A test method for a silicon substrate is provided, which is applied to a host computer in a test device connected to a silicon substrate to be tested, and includes:

[0056] In step S210, the silicon substrate to be tested is detected for failure behavior. In the case that the silicon substrate to be tested does not have failure behavior, test data information collected by a plurality of sensors arranged in the silicon substrate to be tested is obtained through a preset acquisition channel. A plurality of sensors are arranged in different preset regions of the silicon substrate to be tested, and each sensor is used to feed back test data information of the position of the sensor to the host computer.

[0057] The different preset regions are divided based on different voltages on the to-be-tested silicon substrate. Specifically, since a plurality of dies are bonded on the to-be-tested silicon substrate, the working voltages required by different dies are different, and accordingly, the voltages provided on the regions of the to-be-tested silicon substrate where the different dies are located are also different. The to-be-tested silicon substrate is divided into different regions based on the different voltages. The acquisition channel is a preset data transmission channel in the to-be-tested silicon substrate, which is a data transmission channel between the host computer and the sensor. The sensor includes but is not limited to a voltage sensor, a current sensor, and a temperature sensor, and can be set by a person skilled in the relevant art according to actual needs. For example, in some embodiments, the to-be-tested silicon substrate only includes sensors of the same type, for example, only voltage sensors or only current sensors. In other embodiments, the to-be-tested silicon substrate can include sensors of different types.

[0058] In the embodiments of the present application, the to-be-tested silicon substrate is subjected to failure behavior detection, including detection of whether there is a short circuit or other failure behavior inside the to-be-tested silicon substrate. For example, after the dies are bonded with the to-be-tested silicon substrate, it can be tested whether there is a short circuit failure behavior caused by die bonding. It can also be detected whether there is a ball short circuit between the top and bottom of the to-be-tested silicon substrate, which is introduced by the failure of the back-end bonding process. In the case where it is detected that the to-be-tested silicon substrate does not have a failure behavior, test data information collected by a plurality of sensors preset in the to-be-tested silicon substrate is acquired. In the embodiments of the present application, a plurality of sensors are preset inside the to-be-tested silicon substrate. The installation positions of the sensors can be set by a person skilled in the relevant art according to actual needs, including but not limited to setting a plurality of sensors for each region with different preset regions on the to-be-tested silicon substrate as the target; or setting the sensors around a through silicon via (TSV) of the to-be-tested silicon substrate to obtain test data at the inlet and outlet of the TSV; or setting the sensors around a power delivery network (PDN) to test the test data around the PDN, and the like.

[0059] Then, the test data information collected by the plurality of sensors is acquired through the acquisition channel. Each sensor is used to collect test data information at the position of the sensor, and the collected test data information is fed back to the host computer through the acquisition channel.

[0060] In step S220, a target region in which there is no error in each region of the to-be-tested silicon substrate is determined based on the test data information, and a reliability test is performed on the target region to obtain an internal state test result of the to-be-tested silicon substrate.

[0061] In the embodiments of the present application, the target region in which no error exists in each region can be determined by the host computer based on the test data information collected by each sensor. For example, in some embodiments, when the sensor is a voltage sensor, if it is detected that the voltage signals collected by one or more sensors in the same region have a sudden change, it means that there is an abnormality in the interconnection device around the region where the sensor is located. Similarly, in other embodiments, when the sensor is a current sensor, if it is detected that the current collected by one or more sensors in the same region has a sudden change, it means that there is an abnormality in the interconnection device around the region where the current sensor is located. Similarly, in other embodiments, when the sensor is a temperature sensor, if it is detected that the temperature collected by one or more sensors has a sudden change, the approximate range of the position where the abnormality exists can be determined. The above gives several methods for determining whether the interconnection structure in each region exists based on the collected test data information. In actual application, one skilled in the art can also determine the region with error and the region without error based on test data information according to other analysis methods.

[0062] Then, for the target region without error, the target region is subjected to reliability testing, such as repeated power-on and power-off for multiple times (such as 1000 times or 800 times), and then the values collected by each sensor in the silicon substrate to be tested are collected again. Based on the values collected by the sensors, it is determined whether there is a failure behavior in the interconnection structure inside the silicon substrate after repeated power-on and power-off, so as to obtain the above-mentioned internal state test result. The internal state test result reflects the state of the internal interconnection device of the silicon substrate to be tested after the reliability test. It can be understood that for the region with error, repair can be tried first. If it can be repaired by regulating the power corresponding to the region, it can be conveniently handled. If it is determined that it is a manufacturing defect introduced by the process flow, only corresponding maintenance or scrapping can be performed, or a fault tolerance strategy can be adopted to avoid and isolate the region with fault.

[0063] In summary, in the embodiments of the present application, the specific state of the interconnection structure in each region of the silicon substrate to be tested can be efficiently obtained by the pre-set sensors in the silicon substrate to be tested, so as to lock the error region of the silicon substrate to be tested, i.e. the source of power integrity problem, and the power supply condition of the core particles in different regions of the silicon substrate to be tested can be directly detected.

[0064] In one exemplary embodiment, a plurality of logic devices are also provided in the silicon substrate to be tested; the test data information collected by the plurality of sensors provided in the silicon substrate to be tested is obtained through the pre-set collection channel, including:

[0065] The test data information of the silicon substrate under test is received by multiple logic devices integrated in the silicon substrate under test from each sensor. Each sensor is connected to a logic device, and the logic device is connected to the acquisition channel. The logic device is used to acquire the test data information collected by the sensor and feed the test data information back to the host computer through the acquisition channel.

[0066] In this embodiment, multiple logic devices are also disposed within the silicon substrate under test. Each logic device is interspersed with sensors, and each sensor is connected to one logic device. The logic devices acquire test data collected by the connected sensors and feed this data back to the host computer via an acquisition channel. For example, a logic device may have four pins, allowing it to connect to three sensors (one pin needs to be connected to the acquisition channel for feedback). The logic device acquires the test data collected by these three connected sensors and feeds it back to the host computer via the acquisition channel. In summary, the multiple logic devices disposed within the silicon substrate under test can all feed back test data collected by connected sensors to the host computer based on the above scheme. Considering the internal circuitry of the silicon substrate under test in practical applications, logic devices can be connected to sensors that are relatively close to each other. The scheme in this embodiment effectively improves the efficiency of the host computer in acquiring test data from each sensor.

[0067] In one exemplary embodiment, test data information of the silicon substrate under test collected by various sensors is received by multiple logic devices integrated in the silicon substrate under test, including:

[0068] The acquisition channel inputs acquisition commands to the logic device; the logic device is used to respond to the acquisition commands and control the connected sensors to acquire test data at the location.

[0069] Obtain test data information corresponding to the acquisition commands fed back by each logic device.

[0070] This application provides a method for acquiring test data information based on logic devices and sensors. First, the host computer inputs acquisition instructions to each logic device through the acquisition channel. These acquisition instructions are used to instruct the logic device to control the connected sensor to start acquiring test data information at its location. After acquiring the test data information, the sensor feeds it back to the connected logic device. The logic device then feeds back the acquired test data information from the sensor. As can be seen from this application embodiment, the logic device only plays an intermediary role in this embodiment, used to control the sensor to acquire data and feed back the test data information acquired by the sensor.

[0071] In one exemplary embodiment, test data information of the silicon substrate under test collected by various sensors is received by multiple logic devices integrated in the silicon substrate under test, including:

[0072] The control acquisition channel is in the data acquisition state and acquires test data information fed back by various logic devices. The logic devices are used to control the connected sensors to acquire test data information at their location based on a preset cycle, and store the acquired test data information. When the acquisition channel is detected to be in the data acquisition state, the stored test data information is fed back.

[0073] In this embodiment, the logic device can be a structure such as a CPU, meaning the logic device itself has certain data processing and decision-making capabilities. In this embodiment, each logic device can periodically control the connected sensors to collect data according to a preset acquisition cycle and save the test data information fed back by the sensors. When the acquisition channel is detected to be in the data acquisition state, that is, when the acquisition channel is turned on, such as when the probe is inserted into the probe pad, the logic device automatically feeds back the stored test data information. It is understood that if the logic device has a large amount of locally stored test data information, it can autonomously delete some of the stored test data information, for example, it can delete the test data information with the oldest storage time.

[0074] In one exemplary embodiment, such as Figure 3 As shown, the test data information of the silicon substrate under test, collected by various sensors, is received by multiple logic devices integrated in the silicon substrate under test, including:

[0075] Step S310: Determine the preset logic device level in the logic device.

[0076] In this embodiment, the different logic device levels of the multiple logic devices can be determined first. In this embodiment, the multiple logic devices can be divided into different levels to realize a multi-level test data information feedback architecture, so as to improve the test data information feedback efficiency of the multiple sensors arranged in the silicon substrate under test.

[0077] Step S320: Collect test data of each sensor within a preset first range of each first-level logic device through multiple first-level logic devices in the logic device.

[0078] In this embodiment, the first-level logic device is first determined. This first-level logic device is the lowest-level logic device and is used to directly connect to the sensor to obtain the test data information collected by the sensor. The first range is a preset area surrounding the logic device. To facilitate circuit layout, the logic device is only connected to the sensors within the first range. Since the number of pins in a logic device is limited, each logic device generally includes multiple first-level logic devices. Each of these multiple first-level logic devices is connected to the sensor within its respective first range to obtain the test data information collected by the connected sensor.

[0079] Step S330: Through multiple second-level logic devices in the logic device, test data of each sensor in the first-level logic device within a preset second range of each second-level logic device is collected to obtain test data information of the silicon substrate under test.

[0080] In this embodiment, a second-level logic device is defined within the logic device set. This second-level logic device is connected to the first-level logic device to acquire test data information from the sensors obtained by the first-level logic device. The second range is a preset range area for each second-level logic device. Considering the circuit layout in practical applications, the second-level logic device is only connected to the first-level logic device within the second range to acquire the test data information fed back by the sensors obtained by the first-level logic device. It is understood that since a logic device typically has multiple pins, the number of second-level logic devices is generally less than the number of first-level logic devices. The second-level logic devices can further perform statistical analysis on the test data information acquired by the first-level logic device.

[0081] It should be noted that the embodiments of this application may also include more than one level of logic devices. Similarly, each third-level logic device is connected to a second-level logic device and is used to statistically analyze the test data acquired by the second-level logic devices, until all data collected by all sensors is aggregated into one or a few logic devices. These one or a few logic devices then feed the aggregated test data back to the host computer. Through the embodiments of this application, the efficiency of multiple sensors feeding back test data can be effectively improved.

[0082] In one exemplary embodiment, such as Figure 4 As shown, failure behavior detection of the silicon substrate under test includes:

[0083] Step S410: Control the preset first test device to test the bumps on the bottom of the silicon substrate to be tested, obtain the first test result, and determine whether there is a short circuit area in the silicon substrate to be tested based on the first test result, and mark the short circuit area as having failed behavior.

[0084] In this application embodiment, a method for detecting the failure behavior of a silicon substrate under test is provided. It should be noted that the failure behavior detection is performed under power-off conditions. Power can only be applied after the failure behavior detection is passed, and subsequent test steps can be executed, thereby avoiding burning of the silicon substrate or chip.

[0085] The first testing device is used to test the bumps on the bottom of the silicon substrate under test. This first testing device is preferably a probe station, which sequentially contacts each bump on the bottom of the silicon substrate in pairs to obtain the first detection result. This allows observation of whether short-circuit failures caused by chip bonding exist. For example, testing every two bumps reveals that the resistance between two bumps in a certain area is significantly lower, such as close to 0Ω, indicating a short-circuit path between these two bumps. This is generally due to bridging caused by metal residue, process contamination, or uneven bonding pressure during silicon substrate assembly. In summary, the above method can determine whether a short-circuit region exists inside the silicon substrate under test.

[0086] Step S420: Control the preset second test device to scan the silicon substrate to be tested, obtain the second test result, and determine whether there is a failure area between the top bump and the bottom bump of the silicon substrate to be tested based on the second test result, and mark the failure area as having failure behavior; wherein, the second test result is obtained by the preset scanning device.

[0087] In this embodiment, a second testing device is controlled to scan the silicon substrate under test. Specifically, X-ray detection can be used to check for failures introduced by the post-bonding process, such as short circuits, voids, or poor soldering between the top and bottom bumps of the silicon substrate under test. If such failures exist, the area is identified as a failure area and marked as having a failure. The aforementioned pre-set scanning device includes, but is not limited to, X-ray inspection equipment, X-ray machines, etc.

[0088] Step S430: If the test silicon substrate does not have a short circuit area based on the first detection result and does not have a failure area based on the second detection result, then the bonded test silicon substrate does not exhibit any failure behavior.

[0089] In summary, if the silicon substrate under test is found to have neither short-circuit nor failure areas, it can be determined that the silicon substrate bonded to the chip does not exhibit any failure behavior. Therefore, the silicon substrate under test can be powered on and subsequent test steps can be performed. This ensures that the power signal can be directly transmitted to the chip load during subsequent test steps, facilitating the testing of actual load behavior after power-on and preventing dry-circuiting.

[0090] In one exemplary embodiment, the testing apparatus further includes a detector and a chip bonded to the silicon substrate under test, wherein the detector is connected to a host computer, or the chip is connected to the host computer; and the apparatus acquires test data information collected by multiple sensors disposed in the silicon substrate under test through a preset acquisition channel, including:

[0091] Based on the detector, test data information collected by the sensor is obtained through the probe pads on the silicon substrate under test; the probe pads are connected to the acquisition channel.

[0092] Alternatively, based on the chip, test data information collected by the sensor is acquired through acquisition channels, where the acquisition channels include the logic channel between the probe pad and the sensor, and the logic channel between the chip and the sensor.

[0093] The aforementioned testing device also includes a detector and a chip bonded to the silicon substrate under test. The detector is connected to a host computer, or the chip is connected to a host computer. The acquisition of test data information from sensors can be achieved through two methods, which can be used simultaneously or either one can be chosen at the same time.

[0094] 1. The host computer is connected to the detector (which can be a probe station). The probe is inserted into the probe pad on the silicon substrate to be tested through the detector. The probe pad is connected to the acquisition channel inside the silicon substrate to be tested. The test data information collected by the sensor is fed back to the detector through the acquisition channel inside the silicon substrate to be tested. The detector then uploads the data to the host computer.

[0095] 2. The host computer is connected to the chip. The chip can be integrated inside the host computer, or it can be connected to the host computer via cable or communication. The chip is connected to the acquisition channel inside the silicon substrate under test. The chip acquires the test data information collected by the sensor through the acquisition channel and feeds the test data information back to the host computer.

[0096] In summary, data is acquired through a logic channel including the connection between the chip and the sensor, and / or a logic channel including the probe pad and the sensor, which is used to transmit the data to be tested.

[0097] In one exemplary embodiment, determining target regions where no errors exist in each region of the silicon substrate under test based on test data information includes:

[0098] Identify test data belonging to the same region; among which, test data belonging to the same region include through-silicon via (TSV) input test data, power distribution network (PDN) input test data, and power distribution network (PDN) output test data.

[0099] If the difference between the input test data of the through-silicon via, the input test data of the power distribution network, and the output test data of the power distribution network belonging to the same region and the power supply is less than a preset threshold, the region is determined to be the target region without error.

[0100] As can be understood, since multiple chips are bonded to the silicon substrate under test, and different chips require different operating voltages, the voltages in different regions of the silicon substrate under test will be different. This embodiment provides a method for determining whether errors exist in each region of the silicon substrate under test:

[0101] Based on the obtained test data information belonging to the same region, the test data information includes the input test data of the through-silicon vias inside the silicon substrate under test, the input test data of the power distribution network inside the silicon substrate under test, and the output test data of the power distribution network. It can be understood that in the embodiments of this application, the input test data of the power distribution network is the output test data of the through-silicon vias. The interconnection structure in the silicon substrate under test includes the above-mentioned through-silicon vias and power distribution network.

[0102] like Figure 5 As shown in the figure, the topmost module represents the chip bonded to the silicon substrate under test, the middle module represents the silicon substrate under test, and the bottommost module represents the power supply module connected to the bottom of the silicon substrate under test. As can be seen from the figure, the silicon substrate under test includes through-silicon vias (TSVs) and a power distribution network (PDN). The rectangles in the figure represent areas where sensors are set, so that the above-mentioned TSV input test data, power distribution network input test data, and power distribution network output test data can be obtained through the sensors. The rectangles in the power supply module represent the reference voltage that can be obtained from the power supply module output.

[0103] Since the power supply output of the power supply module is known, it can be compared with the aforementioned through-silicon via (TSV) input test data, power distribution network (PSN) input test data, and power distribution network (PSN) output test data. Specifically, the differences between the TSV input test data and the power supply, the power distribution network input test data and the power supply, and the power distribution network output test data and the power supply are detected respectively. If the differences between these three data points and the power supply are all less than a preset threshold (which can be set by relevant technical personnel according to actual needs), then it is determined that there is no error in that area; similarly, if the differences are greater than a preset threshold, then... By setting thresholds, the interconnect structures and regions with errors can be quickly identified. For example, if a large difference is detected between the input test data of the power distribution network and the power supply, and the differences between the remaining two sets of data and the power supply are both less than a preset threshold, it indicates an abnormality in the current through the through-silicon via (TSV). This is likely due to excessive impedance or manufacturing defects in the TSV structure. Conversely, if the difference between the input test data of the power distribution network and the power supply is less than a preset threshold, but the difference between the output test data of the power distribution network and the power supply is large, it is likely that the impedance of the power distribution network in that region is too high or there are manufacturing defects. In summary, the above method can determine whether errors exist in different regions, and if errors exist, the regions and interconnect structures with errors can be quickly located.

[0104] Furthermore, in some embodiments, once the source of the error is identified, a repair can be attempted first. For example, if it is determined that the problem is that the output test data voltage of the power distribution network is too low, the impedance of the power distribution network in that area is too high, resulting in an increased voltage drop and failing to reach the power supply voltage required by the chip, feedback can be sent to the corresponding power supply module in that area to raise the voltage in that area until the voltage requirement is met. Thus, the error problem can be repaired by adjusting the power supply module.

[0105] Correspondingly, if the defect is found to be caused by poor bonding between the silicon substrate under test and the top layer chip, or by stress cracking introduced during the molding process, it cannot be repaired by adjusting the electrical signal. Such defects are manufacturing defects introduced by the process flow and can only enter the post-processing procedure for repair or scrapping, or adopt fault-tolerant strategies to avoid and isolate the area of ​​power integrity failure.

[0106] In one exemplary embodiment, such as Figure 6 As shown, reliability testing is performed on the target area, including:

[0107] Step S610: Determine the preset test cycle.

[0108] In the embodiments of this application, it can be understood that in practical applications, servers with high-density integration on silicon substrates need to undergo multiple power-on restarts during their lifecycle, and therefore reliability testing is required after packaging and testing is completed.

[0109] First, determine the preset test cycle. This test cycle can be set by relevant technical personnel according to actual needs, such as 1000 power-on cycles, 800 power-on cycles, etc.

[0110] Step S620: Based on the test cycle, perform repeated restart power-on operations on the silicon substrate under test, and obtain the reliability test data of the silicon substrate under test fed back by the sensor after the repeated restart power-on operations.

[0111] In this embodiment of the application, the silicon substrate under test is repeatedly restarted and powered on based on a preset test cycle. For example, after 1000 consecutive restarts and power-on cycles, the reliability test data collected by the sensor inside the silicon substrate under test is detected. The sensor can feed back the data collected at its location.

[0112] Step S630: Obtain the test results of the silicon substrate under test based on the reliability test data.

[0113] Finally, the reliability test data can determine the test results of the silicon substrate under test after multiple restarts. Specifically, the analysis method for the reliability test data is the same as described above: the input test data of the through-silicon vias, the input test data of the power distribution network, and the output test data of the power distribution network belonging to the same area are compared with the power supply. If the difference between the comparison and the power supply data is less than a preset threshold, the area is considered normal and without error. Otherwise, it is determined that the area has experienced some loss after multiple power-ups, resulting in error. This indicates a reliability failure, requiring a readjustment of the process design.

[0114] Furthermore, in some embodiments, after passing reliability testing, the chips bonded to the silicon substrate under test can be adjusted, allowing real-time monitoring of the voltage inside the silicon substrate without a probe station. For example, during product delivery and use, improper use may lead to failure. Technical personnel can directly view the voltage levels at various points on the silicon substrate under test using visualization software to determine if repair is necessary. If the issue can be repaired by adjusting the power module, return to the factory is unnecessary. However, if the defect is due to dielectric breakdown, dielectric damage, or metal electromigration—issues that cannot be repaired through software adjustment—the product must be returned to the packaging and testing facility for replacement and repair.

[0115] This application also provides a preferred embodiment of a testing method for silicon substrates. Figure 7 This is a schematic diagram of the internal structure of the silicon substrate to be tested in one embodiment.

[0116] The silicon substrate under test (SST) includes a power supply network, a voltage sensor, logic devices, and a redistribution layer. The voltage sensor should cover the metal layer containing the power distribution network in the SST and be directly connected to each voltage domain. Electrical signals are transmitted to the dies bonded to the SST and directly to the probe pads, facilitating testing with a probe station before die integration. The dies are bump-bonded to the top layer of the SST, enabling communication between the dies and transmitting power signals from the power supply module connected to the bottom of the SST to the dies. The power supply module is bonded to the bumps on the bottom layer of the SST. The output voltage and load capacity of this power supply module have been pre-tested and verified, and it has built-in short-circuit protection to prevent the entire module from burning out due to load failure.

[0117] Before powering on, the silicon substrate under test is tested using a probe station and X-ray equipment to detect whether there are short-circuit regions in the interconnect structure inside the silicon substrate under test, or whether there are failure behaviors introduced by the back-end bonding process, such as solder ball short circuits or solder ball voids. Powering on can be performed after no short-circuit regions or areas with failure behaviors are detected.

[0118] Then, a preset power module is bonded to the bottom of the silicon substrate under test, and all chips on the silicon substrate are uniformly powered. Using a probe station and a host computer connected to the probe station, probes are inserted into the silicon substrate under test through probe pads to obtain the voltage levels inside the silicon substrate as fed back by various sensors. In this embodiment, the sensor is a voltage sensor. It is worth noting that the voltage sensor in the silicon substrate under test has multiple layers and the ability to fully reflect the voltage domain at various locations.

[0119] Furthermore, test data collected by voltage sensors is processed through a first-level logic device, which then aggregates the data from each sensor to a second-level logic device. Similarly, the data from the second-level logic device is aggregated to a third-level logic device, thereby improving the efficiency of test data feedback. The test data is analyzed to determine if any failure areas exist within the silicon substrate under test. If a significant difference is detected between the test data from a sensor and the corresponding power supply, an anomaly is identified in the interconnect structure of that area. The abnormal area can then be identified and its repairability assessed. If repair is not possible, the substrate must be returned to the factory for repair or scrapped, or a fault-tolerant strategy can be employed to avoid and isolate areas with power integrity faults.

[0120] For areas without faults, reliability testing is performed by continuously restarting the power supply module. After 1000 restart cycles, the voltage levels at various points inside the silicon substrate under test are checked to observe whether there are any reliability failures. If so, the process design needs to be adjusted.

[0121] Finally, after Tan Zheng tested and confirmed that the power supply at each point was correct, the chip could be adjusted. The chip bonded to the silicon substrate under test could detect the level status collected by each sensor in the silicon substrate under test in real time, i.e., the test data information.

[0122] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0123] Based on the same inventive concept, this application also provides a silicon substrate testing apparatus for implementing the aforementioned silicon substrate testing method. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations of one or more silicon substrate testing apparatus embodiments provided below can be found in the limitations of the silicon substrate testing method described above, and will not be repeated here.

[0124] In one exemplary embodiment, such as Figure 8 As shown, a testing apparatus for a silicon substrate is provided, comprising: a detection module 81 and a generation module 82, wherein:

[0125] The detection module 81 is used to detect failure behavior of the silicon substrate under test. When there is no failure behavior in the silicon substrate under test, the module acquires test data information collected by multiple sensors set in the silicon substrate under test through a preset acquisition channel. Multiple sensors are set in different preset areas of the silicon substrate under test, and each sensor is used to feed back the test data information of the sensor location to the host computer.

[0126] The generation module 82 is used to determine, based on the test data information, target areas in each region of the silicon substrate under test that are free from errors, and to perform reliability testing on the target areas to obtain the internal state test results of the silicon substrate under test.

[0127] Each module in the aforementioned silicon substrate testing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0128] In one exemplary embodiment, the silicon substrate under test is further provided with multiple logic devices and includes a first acquisition module;

[0129] The first acquisition module is used to receive test data information of the silicon substrate under test collected by each sensor through multiple logic devices integrated in the silicon substrate under test. Each sensor is connected to a logic device, and the logic device is connected to the acquisition channel.

[0130] In one exemplary embodiment, a second acquisition module is also included;

[0131] The second acquisition module is used to input acquisition commands to the logic devices through the acquisition channel; wherein, the logic devices are used to respond to the acquisition commands, control the connected sensors to acquire test data at their location, and obtain the test data information corresponding to the acquisition commands fed back by each logic device.

[0132] In one exemplary embodiment, a third acquisition module is also included;

[0133] The third acquisition module is used to control the acquisition channel to be in the data acquisition state and to acquire the test data information fed back by each logic device. The logic device is used to control the connected sensor to acquire the test data information at its location based on a preset period and to store the acquired test data information. When the acquisition channel is detected to be in the data acquisition state, the stored test data information is fed back.

[0134] In one exemplary embodiment, it further includes a fourth acquisition module, a first-level acquisition module, and a second-level acquisition module;

[0135] The fourth acquisition module is used to determine the preset logic device level in the logic device;

[0136] The first-level acquisition module is used to acquire test data of each sensor within a preset first range of each first-level logic device through multiple first-level logic devices in the logic device.

[0137] The second-level acquisition module is used to acquire test data from each sensor in the first-level logic device within a preset second range of each second-level logic device through multiple second-level logic devices in the logic device, so as to obtain test data information of the silicon substrate under test.

[0138] In one exemplary embodiment, it further includes a fifth short-circuit detection module, a fifth failure detection module, and a fifth generation module;

[0139] The fifth short-circuit detection module is used to control the preset first test equipment to test the bumps on the bottom of the silicon substrate to be tested, obtain the first test result, and determine whether there is a short-circuit area in the silicon substrate to be tested based on the first test result, and mark the short-circuit area as having failed behavior.

[0140] The fifth failure detection module is used to control a preset second test device to scan the silicon substrate under test, obtain a second test result, and determine whether there is a failure area between the top bump and the bottom bump of the silicon substrate under test based on the second test result, and mark the failure area as having failure behavior; wherein, the second test result is obtained through a preset scanning device;

[0141] The fifth generation module is used to determine that the bonded silicon substrate does not have a failure behavior if the first detection result determines that there is no short circuit area on the silicon substrate to be tested, and the second detection result determines that there is no short-circuit area on the silicon substrate to be tested.

[0142] In an exemplary embodiment, the testing apparatus further includes a detector and a chip bonded to the silicon substrate to be tested, wherein the detector is connected to a host computer, or the chip is connected to a host computer, and further includes a sixth detector acquisition module and a sixth chip acquisition module.

[0143] The sixth detector acquisition module is used to acquire test data information collected by the sensor through the probe pads on the silicon substrate under test, based on the detector; the probe pads are connected to the acquisition channel; or,

[0144] The sixth chip acquisition module is used to acquire test data information collected by the sensor based on the chip through the acquisition channel. The acquisition channel includes the logic channel between the probe pad and the sensor, and the logic channel between the chip and the sensor.

[0145] In one exemplary embodiment, a seventh determining module and a seventh detecting module are also included;

[0146] The seventh determination module is used to determine test data belonging to the same region; among which, test data belonging to the same region includes through-silicon via input test data, power distribution network input test data, and power distribution network output test data;

[0147] The seventh detection module is used to determine that the area is a target area without error when the difference between the input test data of the through silicon via, the input test data of the power distribution network, and the output test data of the power distribution network belonging to the same area and the power supply is less than a preset threshold.

[0148] In one exemplary embodiment, an eighth determining module and an eighth testing module are also included;

[0149] The eighth module is used to determine the preset test cycle;

[0150] The eighth test module is used to perform repeated restart power-on operations on the silicon substrate under test based on the test cycle, and to obtain the reliability test results of the silicon substrate under test fed back by the sensors after the repeated restart power-on operations; and to obtain the test results of the silicon substrate under test based on the reliability test data.

[0151] In one exemplary embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement any of the silicon substrate testing methods described above.

[0152] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements any of the silicon substrate testing methods described above.

[0153] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements any of the silicon substrate testing methods described above.

[0154] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0155] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0156] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method of testing a silicon substrate, characterized by, The method is applied to an upper computer in a test device connected with a silicon substrate to be tested, and the method comprises the following steps: Failure behavior detection is performed on a silicon substrate to be tested, and test data information collected by a plurality of sensors arranged in the silicon substrate to be tested is acquired through a preset acquisition channel in the case that no failure behavior exists in the silicon substrate to be tested; wherein a plurality of sensors are arranged in different preset regions of the silicon substrate to be tested, and each sensor is used for feeding back the test data information of the position where the sensor is located to the upper computer; A target region in which no error exists in each region of the silicon substrate to be tested is determined based on the test data information, and a reliability test is performed on the target region to obtain an internal state test result of the silicon substrate to be tested.

2. The method of claim 1, wherein, A plurality of logic devices are further arranged in the silicon substrate to be tested; the test data information collected by the plurality of sensors arranged in the silicon substrate to be tested is acquired through a preset acquisition channel, comprising the following steps: The test data information of the silicon substrate to be tested collected by each sensor is received through a plurality of logic devices integrated in the silicon substrate to be tested, wherein each sensor is connected with a logic device, and the logic device is connected with the acquisition channel.

3. The method of claim 2, wherein, The test data information of the silicon substrate to be tested collected by each sensor is received through a plurality of logic devices integrated in the silicon substrate to be tested, comprising the following steps: An acquisition instruction is input to the logic device through the acquisition channel; wherein the logic device is used for controlling the connected sensor to collect the test data of the position where the sensor is located in response to the acquisition instruction; The test data information corresponding to the acquisition instruction fed back by each logic device is acquired.

4. The method of claim 2, wherein, The test data information of the silicon substrate to be tested collected by each sensor is received through a plurality of logic devices integrated in the silicon substrate to be tested, comprising the following steps: The acquisition channel is controlled to be in a data acquisition state, and the test data information fed back by each logic device is acquired, wherein the logic device is used for controlling the connected sensor to collect the test data of the position where the sensor is located based on a preset period, and storing the acquired test data information, and feeding back the stored test data information when it is detected that the acquisition channel is in the data acquisition state.

5. The method of claim 2, wherein, The test data information of the silicon substrate to be tested collected by each sensor is received through a plurality of logic devices integrated in the silicon substrate to be tested, comprising the following steps: A preset logic device level in the logic device is determined; The test data of each sensor in a preset first range of each first-level logic device is collected through a plurality of first-level logic devices in the logic device; The test data of each sensor in a first-level logic device in a preset second range of each second-level logic device is collected through a plurality of second-level logic devices in the logic device, and the test data information of the silicon substrate to be tested is obtained.

6. The method according to any one of claims 1 to 5, characterized in that, The failure behavior detection on the silicon substrate to be tested comprises the following steps: The first test device is controlled to test the bumps on the bottom of the silicon substrate to be tested, to obtain a first detection result, and to determine whether a short-circuit region exists in the silicon substrate to be tested based on the first detection result, and mark the short-circuit region as existing the failure behavior; The second test device is controlled to scan the silicon substrate to be tested to obtain a second detection result, and to determine whether a failure region exists between the top bumps and the bottom bumps of the silicon substrate to be tested based on the second detection result, and mark the failure region as existing the failure behavior; wherein the second detection result is obtained by a preset scanning device; In a case where the first detection result indicates that the silicon substrate to be tested does not have the short-circuit region, and the second detection result indicates that the silicon substrate to be tested does not have the failure region, it is determined that the silicon substrate to be tested does not have the failure behavior after bonding.

7. The method according to any one of claims 1 to 5, characterized in that, The test device further comprises a probe and a core particle bonded to the silicon substrate to be tested, wherein the probe is connected to the host computer, or the core particle is connected to the host computer; the test data information collected by a plurality of sensors arranged in the silicon substrate to be tested is obtained through a preset acquisition channel, including: The test data information collected by the sensors is obtained through a probe pad on the silicon substrate to be tested based on the probe; the probe pad is connected to the acquisition channel; Or, the test data information collected by the sensors is obtained through the acquisition channel based on the core particle, wherein the acquisition channel includes a logical channel between the probe pad and the sensors, and a logical channel between the core particle and the sensors.

8. The method according to any one of claims 1 to 5, characterized in that, The target region in which no error exists in each region of the silicon substrate to be tested is determined based on the test data information, including: Determine the test data belonging to the same region; wherein the test data belonging to the same region includes through-silicon via input test data, power distribution network input test data, and power distribution network output test data; In a case where the difference between the through-silicon via input test data, the power distribution network input test data, and the power distribution network output test data belonging to the same region and a power supply is less than a preset threshold, it is determined that the region is a target region in which no error exists.

9. The method according to any one of claims 1 to 5, characterized in that, The reliability test on the target region includes: Determine a preset test period; Based on the test period, perform a repetitive restart power-on operation on the silicon substrate to be tested, and obtain reliability test data of the silicon substrate to be tested fed back by the sensors of the silicon substrate to be tested after the repetitive restart power-on operation; Obtain a test result of the silicon substrate to be tested based on the reliability test data.

10. A testing apparatus of a silicon substrate, characterized by comprising: The device comprises: The detection module is configured to perform failure behavior detection on a silicon substrate to be tested, and in the case that the silicon substrate to be tested does not have a failure behavior, test data information collected by a plurality of sensors arranged in the silicon substrate to be tested is acquired through a preset acquisition channel; wherein a plurality of sensors are arranged in different preset regions of the silicon substrate to be tested, and each sensor is configured to feed back the test data information of the position of the sensor to an upper computer; The generation module is configured to determine a target region in which there is no error in each region of the silicon substrate to be tested based on the test data information, and perform a reliability test on the target region to obtain an internal state test result of the silicon substrate to be tested.

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