A low cost wafer testing method

Abstract

The application provides a low-cost wafer testing method. The application effectively reduces the total number of dies to be recognized by a probe station by an innovative testing method, i.e. combining multiple actual dies into one testing die during the testing process, so that the existing probe station suitable for 8-inch wafers can test 8-inch wafers with super-multiple total dies, the use of high-priced 12-inch wafer probe stations is avoided, and the cost of wafer testing is reduced.

Description

Technical Field

[0001] This invention relates to the field of wafer testing technology, and more specifically, to a low-cost wafer testing method. Background Technology

[0002] In the semiconductor manufacturing industry, one of the main pieces of equipment used for wafer testing is the probe station. Depending on the wafer size (currently the industry mainstream is 12-inch and 8-inch), there are different models and specifications of probe stations to adapt to different wafer sizes. Generally, a probe station adapted to 12-inch wafers is backward compatible with testing 8-inch wafers, but a probe station adapted to 8-inch wafers is not backward compatible with testing 12-inch wafers. However, a probe station adapted to 8-inch wafers is limited by a specification that identifies the total number of dies, so it cannot test 8-inch wafers with more than 300,000 dies.

[0003] The current industry solution to this problem is to use probe stations adapted for 12-inch wafers to test 8-inch wafers with a large number of total dies. However, wafer testing is typically billed based on the price of the equipment model used, and probe stations adapted for 12-inch wafers are significantly more expensive than those adapted for 8-inch wafers. Therefore, using probe stations adapted for 12-inch wafers to test 8-inch wafers has a significant disadvantage: higher wafer testing costs. Therefore, we propose an improvement, a low-cost wafer testing method. Summary of the Invention

[0004] This invention provides a low-cost wafer testing method, comprising:

[0005] Step 1: Create a test pattern on the probe station: merge the multiple actual dies on the original 8-inch wafer into a single test die on the test pattern;

[0006] Step 2: The test program processes the test dies displayed on the test pattern: Based on the test pattern established in Step 1, the contact definition and test statement in the test program are expanded to adapt to the specifications of multiple actual dies corresponding to a single test die, so that the test program can complete the test of multiple actual dies contained in a single test die in one test action.

[0007] Step 3: Encode and output the test spectrum: After the test is completed, the test results of multiple actual grains corresponding to a single test grain are encoded to form the grade number displayed on the test spectrum of the test grain and output it.

[0008] Step 4: Restore the actual spectrum: Export the test spectrum output in Step 3 from the probe station, split the single test grain on the test spectrum into multiple corresponding actual grains, and restore the grade number corresponding to each actual grain to obtain the actual spectrum that is consistent with the number, position and test results of the grains on the actual wafer.

[0009] As a preferred technical solution of this application, in step 1, the merging method of multiple actual grains is any one or more combinations of left-right adjacent merging, top-bottom adjacent merging, diagonal adjacent merging, or interval merging.

[0010] As a preferred technical solution of this application, in step 1, the number of actual grains is two or more.

[0011] As a preferred technical solution of this application, in step 3, the grade number includes the pass grade number corresponding to the test pass and the failure grade number corresponding to the test failure.

[0012] As a preferred technical solution of this application, in step 3, the encoding process is as follows: according to the arrangement order of the actual dies in the test dies, the hierarchical numbers of each actual die are sequentially spliced ​​together to form the hierarchical number of the test die; if there are untested or invalid actual dies, a preset invalid identifier is used to participate in the splicing.

[0013] As a preferred technical solution of this application, step 4, the restoration process specifically includes: firstly, parsing the grade number of the test grain in the test pattern, obtaining the grade number of each actual grain according to the coding method in step 3; then, determining the actual position of each actual grain on the wafer according to the merging method in step 1, matching the grade number with the actual position, and generating the actual pattern.

[0014] As a preferred technical solution of this application, it also includes a software suite consisting of a test program module and a spectrum conversion tool module, as well as a probe station hardware body;

[0015] The spectrum conversion tool module is used to construct a merged test spectrum based on probe card parameters, encode the test results to generate a test spectrum, and restore the actual spectrum according to the encoding rules.

[0016] The test program module is used to receive the merged specification information from the spectrum conversion tool module, expand the contact definition and test statement, execute single-step multi-grain test and output the test results to the spectrum conversion tool module;

[0017] The probe station hardware is used to load the test pattern constructed by the software suite, execute the test instructions of the test program module, and display the test pattern.

[0018] A low-cost wafer testing method includes the following steps:

[0019] An 8-inch wafer with a large number of total dies is divided into multiple test areas on a probe station adapted to 8-inch wafers. Multiple test areas are tested sequentially. After each area is tested, the 8-inch wafer with a large number of total dies is removed from the probe station and reloaded before testing the next area.

[0020] After each region is tested, a corresponding partition test map is generated.

[0021] After all test areas have been tested, the test patterns of each partition are merged to generate a final test pattern of a complete wafer.

[0022] As a preferred technical solution of this application, when merging the test maps of each partition, image recognition or coordinate alignment is used to align the test maps of each test.

[0023] As a preferred technical solution of this application, the test area is divided into grid division or sector division, and the number of chips in each test area after division does not exceed the total chip recognition limit of the probe station.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] In the scheme of this application:

[0026] This application employs an innovative testing method that combines multiple actual dies into a single test die during the testing process. This effectively reduces the total number of dies that the probe station needs to identify, enabling existing probe stations adapted for 8-inch wafers to test 8-inch wafers with a much larger total number of dies. This avoids the need to use expensive 12-inch wafer probe stations and reduces the cost of wafer testing. Attached Figure Description

[0027] Figure 1 The flowchart of the low-cost wafer testing method provided in this application is intended to illustrate the process.

[0028] Figure 2 A partial view of the distribution of each grain on an actual 8-inch wafer;

[0029] Figure 3 For the localization of the established test map Figure 1 ;

[0030] Figure 4 For the localization of the established test map Figure 2 ;

[0031] Figure 5 This is an example diagram for step 3;

[0032] Figure 6 This is an example diagram for step 4. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other.

[0035] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0036] Example 1, please refer to Figure 1 A low-cost wafer testing method, comprising:

[0037] Step 1: Establish a test pattern on the probe station: merge multiple actual dies on the original 8-inch wafer into one test die on the test pattern; the merging method of multiple actual dies can be any one or more combinations of left-right adjacent merging, top-bottom adjacent merging, diagonal adjacent merging, or interval merging; the number of multiple actual dies is 2 or more, and the specific number is determined according to the total die recognition limit of the probe station and the total number of actual dies on the wafer;

[0038] Reference Figure 2 , Figure 2 It is a partial view of the distribution of each grain on the actual pattern of an 8-inch wafer, with each "T" column representing one actual grain;

[0039] Figure 3 and Figure 4 Two partial views of the established test patterns are shown. The pattern merges two actual dies that were originally adjacent to each other on the left and right of the 8-inch wafer into one test die. It can also merge two or more actual dies that were originally adjacent to each other vertically or diagonally, depending on the arrangement of the probe cards used during the test and the number of dies.

[0040] Step 2: The test program processes the test dies displayed on the test pattern: Based on the test pattern established in Step 1, the contact definitions and test statements in the test program are expanded to adapt to the specifications of multiple actual dies corresponding to a single test die. This allows the test program to complete the testing of multiple actual dies contained in a single test die in a single test action. Because after Step 1, one test die contains two or more actual dies, the contact definitions and other test statements in the test program also need to be expanded synchronously to correspond to testing multiple actual dies. In other words, the test program needs to combine the original two or more test actions for testing two or more actual dies into a single test action.

[0041] Step 3: Encode and output the test spectrum: After the test is completed, the test results of multiple actual dies corresponding to a single test die are encoded to form the grade number displayed on the test spectrum for that test die and output it. The grade number includes the pass grade number corresponding to the test pass and the failure grade number corresponding to the test failure. The failure grade number is defined according to the failure item or parameter based on the actual test requirements. The encoding method is as follows: according to the arrangement order of the actual dies in the test dies, the grade numbers of each actual die are concatenated sequentially to form the grade number of the test die. If there are untested or invalid actual dies, a preset invalid identifier is used to participate in the concatenation.

[0042] The test spectrum can only display the test classification number of the tested die. The test result of a die (whether an actual die or a test die) is usually classified as either "test pass" or "test failure". If the test passes, the die is generally assigned a classification number, such as Class 1. If the test fails, in order to distinguish the specific item or parameter that failed, the failed die is usually further assigned a failure classification number, such as Class 2, Class 3, etc. Because the number of failed items or parameters may be large depending on the test requirements, the number of classification numbers may also be large. These classification numbers will be displayed on the test pattern of this wafer. Now, since one test die contains two or more actual dies, the test results corresponding to this test die must include information on the number and positional relationship of the actual dies in order to be displayed on the test pattern. This requires encoding processing when outputting the test results. For example, if the test failure classification number of the actual die on the left is 2 and the test failure classification number of the actual die on the right is 3, then according to a rule, the classification number of this test die will be output as 23 on the test pattern. For example... Figure 5 As shown;

[0043] Step 4: Reconstruct the Actual Spectrum: Export the test spectrum output in Step 3 from the probe station. Separate the single test die in the test spectrum into multiple corresponding actual dies, and reconstruct the hierarchical number corresponding to each actual die to obtain an actual spectrum consistent with the number, position, and test results of dies on the actual wafer. The reconstruction process specifically includes: first, parsing the hierarchical numbers of the test dies in the test spectrum, obtaining the hierarchical number of each actual die according to the encoding method in Step 3; then, determining the actual position of each actual die on the wafer according to the merging method in Step 1, matching the hierarchical number with the actual position to generate the actual spectrum. For example… Figure 6 As shown.

[0044] This embodiment reduces the total number of chips that the probe station needs to identify by merging multiple actual chips into one test chip, thereby enabling existing probe stations adapted to 8-inch wafers to test 8-inch wafers with a large number of chips.

[0045] Example 2 further optimizes the low-cost wafer testing method provided in Example 1. Specifically, it also includes a software suite consisting of a test program module and a pattern conversion tool module, as well as a probe station hardware body.

[0046] The graph conversion tool module is used to construct a merged test graph based on probe card parameters, encode test results to generate a test graph, and restore the actual graph according to the encoding rules.

[0047] The test program module is used to receive the merged specification information from the spectrum conversion tool module, expand the contact definition and test statement, execute single-step multi-grain test and output the test results to the spectrum conversion tool module;

[0048] The probe station hardware is used to load the test patterns built by the software suite, execute the test instructions of the test program module, and display the test patterns.

[0049] Example 3: A low-cost wafer testing method, comprising the following steps:

[0050] An 8-inch wafer with a large number of total dies is divided into multiple test areas on a probe station adapted to 8-inch wafers. Multiple test areas are tested sequentially. After each area is tested, the 8-inch wafer with a large number of total dies is removed from the probe station and reloaded before testing the next area.

[0051] After each region is tested, a corresponding partition test map is generated.

[0052] After all test areas have been tested, the test patterns of each partition are merged to generate a final test pattern of a complete wafer.

[0053] This embodiment performs partitioned testing on an 8-inch wafer with a large number of total dies, thereby enabling existing probe stations adapted for 8-inch wafers to be used to test 8-inch wafers with a large number of total dies.

[0054] Furthermore, when merging the test maps of each partition, image recognition or coordinate alignment is used to align the test maps of each test.

[0055] When aligning the test patterns for each test using image recognition, the specific steps include: acquiring image information of the test patterns for each partition, extracting feature points from the images, including but not limited to wafer edge points, specific marker points, or corner points of the grains; matching the extracted feature points to determine the relative positional relationship between the test patterns for each partition; and stitching and adjusting the test patterns for each partition according to the relative positional relationship to ensure accurate alignment and form the final test pattern of the complete wafer.

[0056] When aligning test patterns for each test using coordinate alignment, the specific steps include: establishing an independent coordinate system for each partition test pattern; determining the coordinates of key points in each partition test pattern, including but not limited to the wafer center point, partition boundary points, or the center point of a specific grain; calculating the transformation parameters between the coordinate systems based on the actual positional relationship of each partition test pattern on the wafer; and using the transformation parameters to unify the coordinates of each partition test pattern to the same coordinate system, thereby achieving accurate alignment of each partition test pattern and generating the final test pattern of the complete wafer.

[0057] Furthermore, the test area is divided into grid or sector partitions. The specific partitioning rules are determined based on the die arrangement density on the wafer, the effective test range of the probe station, and the distribution characteristics of the dies at the wafer edge. After partitioning, the number of dies in each test area does not exceed the total die recognition limit of the probe station.

[0058] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0059] Obviously, the embodiments described above are merely some embodiments of the present invention, not all embodiments. The accompanying drawings show preferred embodiments of the present invention, but do not limit the patent scope of the present invention. The present invention can be implemented in many different forms; rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the patent protection scope of this invention.

Claims

1. A low-cost wafer testing method, characterized in that, include: Step 1: Create a test pattern on the probe station: merge the multiple actual dies on the original 8-inch wafer into a single test die on the test pattern; Step 2: The test program processes the test dies displayed on the test pattern: Based on the test pattern established in Step 1, the contact definition and test statement in the test program are expanded to adapt to the specifications of multiple actual dies corresponding to a single test die, so that the test program can complete the test of multiple actual dies contained in a single test die in one test action. Step 3: Encode and output the test spectrum: After the test is completed, the test results of multiple actual grains corresponding to a single test grain are encoded to form the grade number displayed on the test spectrum of the test grain and output it. Step 4: Restore the actual spectrum: Export the test spectrum output in Step 3 from the probe station, split the single test grain on the test spectrum into multiple corresponding actual grains, and restore the grade number corresponding to each actual grain to obtain the actual spectrum that is consistent with the number, position and test results of the grains on the actual wafer.

2. The low-cost wafer testing method according to claim 1, characterized in that, In step 1, the merging of multiple actual grains can be any one or more combinations of left-right adjacent merging, top-bottom adjacent merging, diagonal adjacent merging, or spaced merging.

3. The low-cost wafer testing method according to claim 1, characterized in that, In step 1, the number of actual grains is two or more.

4. The low-cost wafer testing method according to claim 1, characterized in that, In step 3, the classification number includes the pass classification number corresponding to the test passing and the failure classification number corresponding to the test failing.

5. The low-cost wafer testing method according to claim 4, characterized in that, In step 3, the encoding process is as follows: according to the arrangement order of the actual dies in the test dies, the hierarchical numbers of each actual die are sequentially spliced ​​together to form the hierarchical numbers of the test dies; if there are untested or invalid actual dies, a preset invalid identifier is used to participate in the splicing.

6. The low-cost wafer testing method according to claim 5, characterized in that, In step 4, the restoration process specifically includes: first, parsing the grade number of the test grain in the test pattern, obtaining the grade number of each actual grain according to the coding method in step 3; then, determining the actual position of each actual grain on the wafer according to the merging method in step 1, matching the grade number with the actual position, and generating the actual pattern.

7. The low-cost wafer testing method according to claim 1, characterized in that, It also includes a software suite consisting of a test program module and a spectrum conversion tool module, as well as the probe station hardware. The spectrum conversion tool module is used to construct a merged test spectrum based on probe card parameters, encode the test results to generate a test spectrum, and restore the actual spectrum according to the encoding rules. The test program module is used to receive the merged specification information from the spectrum conversion tool module, expand the contact definition and test statement, execute single-step multi-grain test and output the test results to the spectrum conversion tool module; The probe station hardware is used to load the test pattern constructed by the software suite, execute the test instructions of the test program module, and display the test pattern.

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