Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first substrate; the first substrate comprises a first substrate, a thin film transistor layer, a pixel electrode layer, a dielectric layer, a common electrode layer and a metal shading layer, and the thin film transistor layer is arranged on one side of the first substrate; the pixel electrode layer is arranged on the side, away from the first substrate, of the thin film transistor layer; the dielectric layer is arranged between the pixel electrode layer and the thin film transistor layer, a first via hole is formed in the dielectric layer, and the pixel electrode layer is electrically connected with the thin film transistor layer through the first via hole; the common electrode layer is arranged on the side, away from the first substrate, of the pixel electrode layer, the metal shading layer comprises a first shading part arranged between the pixel electrode layer and the common electrode layer, and the first shading part and the pixel electrode layer are arranged in an insulated mode.

Description

[0001] This divisional application is based on a Chinese patent application with application number 202411103296.X and titled "Display panel and display device", filed on August 12, 2024, the priority of which is hereby affirmed. TECHNICAL FIELD

[0002] The present application relates to the technical field of display devices, in particular to a display panel and a display device. BACKGROUND

[0003] With the development of 5G communication technology, VR (English full name: Virtual reality, Chinese abbreviation: virtual environment) technology is in a period of rapid development. The array substrate formed by combining LTPO (English full name: Low Temperature Polycrystalline Oxide, Chinese abbreviation: low temperature polycrystalline oxide) technology and COA (English full name: Color Filter on Array, Chinese abbreviation: color filter and array substrate integration) technology is becoming the focus of research and development of various manufacturers. However, the array substrate structure formed by combining LTPO and COA has the risk of electrical contact between the metal light shielding layer and the pixel electrode via in actual process, thereby causing a decrease in panel yield. SUMMARY

[0004] In a first aspect, an embodiment of the present application provides a display panel, The display panel includes a first substrate, and the first substrate includes: a first substrate; a thin film transistor layer disposed on one side of the first substrate; a pixel electrode layer disposed on a side of the thin film transistor layer away from the first substrate; a dielectric layer disposed between the pixel electrode layer and the thin film transistor layer, the dielectric layer being provided with a first via, and the pixel electrode layer being electrically connected to the thin film transistor layer through the first via; a common electrode layer disposed on a side of the pixel electrode layer away from the first substrate; a metal light shielding layer including a first light shielding portion disposed between the pixel electrode layer and the common electrode layer, and the first light shielding portion being insulatively disposed from the pixel electrode layer.

[0005] In an embodiment, the first substrate further includes a first insulating layer disposed between the first light shielding portion and the pixel electrode layer.

[0006] In an embodiment, the first light shielding portion includes a plurality of first sub-portions. The first insulating layer is arranged in a pattern, and the first insulating layer comprises a plurality of first insulating blocks, each of the first insulating blocks being located between one of the first sub-parts and the pixel electrode layer.

[0007] In an embodiment, a normal projection of the first sub-part on the first substrate is a first projection. A normal projection of the first insulating block on the first substrate is a second projection, and the second projection coincides with the first projection.

[0008] In an embodiment, the first light-shielding part comprises a plurality of first sub-parts, and a normal projection of the first sub-part on the first substrate is a first projection. The display panel further comprises a second substrate arranged opposite to the first substrate. The second substrate comprises a second substrate and a black matrix layer arranged on a side surface of the second substrate facing the first substrate, and the black matrix layer comprises a plurality of second light-shielding parts, and a normal projection of the second light-shielding part on the first substrate is a third projection. The plurality of first projections formed by the plurality of first sub-parts and the plurality of third projections formed by the plurality of second light-shielding parts are arranged in a longitudinal and transverse interlaced manner, and define a plurality of pixel regions. The first substrate further comprises a color resistance layer arranged on a side of the thin film transistor layer away from the first substrate. The color resistance layer comprises a plurality of color resistance blocks, each of the color resistance blocks being located in one of the pixel regions. A normal projection of the first via on the first substrate is located within a range of the third projection. The first sub-part is arranged at a junction of two adjacent color resistance blocks.

[0009] In an embodiment, the first substrate further comprises a spacer layer, the spacer layer being filled in the first via and arranged protruding from a periphery of the first via. The display panel further comprises a support column arranged between the second light-shielding part and the spacer layer. The pixel electrode layer covers the spacer layer.

[0010] In an embodiment, the first substrate further comprises a spacer layer, the spacer layer being filled in the first via and arranged protruding from a periphery of the first via. The first substrate further comprises: a first electrode layer arranged on the thin film transistor layer, the first electrode layer being electrically connected to the thin film transistor layer through the first via; and a second electrode layer disposed on the first electrode layer and covering the spacer in the first via, the second electrode layer being electrically connected with the first electrode layer; The first electrode layer and the second electrode layer constitute the pixel electrode layer. The metal light-shielding layer is disposed on a side of the second electrode layer away from the first electrode layer.

[0011] In an embodiment, the display panel has a display area and a frame area located at a periphery of the display area. The first substrate further includes a second insulating layer disposed on a side of the dielectric layer away from the thin film transistor, and the common electrode layer is disposed on a side of the second insulating layer away from the dielectric layer and forms a storage capacitor with the pixel electrode layer. The metal light-shielding layer further includes a third light-shielding portion located in the frame area, and the third light-shielding portion is disposed on a side of the dielectric layer away from the thin film transistor. The first insulating layer further includes a second insulating block located in the frame area, and the second insulating block is located between the third light-shielding portion and the dielectric layer. The second insulating layer covers the pixel electrode layer, the first light-shielding portion, and the third light-shielding portion. The third light-shielding portion is electrically connected with the common electrode layer through a second via.

[0012] In an embodiment, the display panel has a display area and a frame area located at a periphery of the display area. The thin film transistor layer includes a plurality of first thin film transistors and a plurality of second thin film transistors, the plurality of first thin film transistors are disposed in the display area, the first thin film transistors are oxide thin film transistors, the plurality of second thin film transistors are disposed in the frame area, and the second thin film transistors are low-temperature polysilicon thin film transistors. The pixel electrode layer is electrically connected with a first drain of the first thin film transistor through the first via. The metal light-shielding layer further includes a third light-shielding portion located in the frame area, and the third light-shielding portion overlaps the second thin film transistor in a thickness direction of the display panel.

[0013] In a second aspect, the embodiments of the present application further provide a display device including the display panel.

[0014] Beneficial effects: the display panel provided by the present application, the first substrate includes a first substrate, a thin film transistor layer, a pixel electrode layer, a dielectric layer, a common electrode layer and a metal light shielding layer, the pixel electrode layer is electrically connected with the thin film transistor layer through a first via hole; the metal light shielding layer includes a first light shielding part located in the display area; the first light shielding part is arranged between the pixel electrode layer and the common electrode layer, by insulating the first light shielding part from the pixel electrode layer, the risk of short circuit caused by the contact between the first light shielding part and the first via hole is eliminated, thereby improving the product yield of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0015] The technical solutions and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application, combined with the accompanying drawings.

[0016] Figure 1 The film layer diagram of the display panel provided by the present application; Figure 2 The projection diagram of the light shielding layer and the black matrix layer provided by the present application; Figures 3a-3e For Figure 1 The preparation flowchart of the display panel. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely below, combined with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0018] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and cannot be understood as a limitation on the present application. And, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature relative to the second feature only means that the horizontal height of the first feature is higher than that of the second feature or the horizontal height of the first feature is smaller than that of the second feature, and does not mean a direct connection relationship.

[0019] In addition, the terms "first" and "second" are only for descriptive purposes, and the features limited by "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0020] In the description of the present application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, and the connection mode is not limited, and the above terms in the present application can be understood according to the specific meaning of the above terms in the present application.

[0021] The following disclosure provides many different embodiments for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application provides various specific examples of processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0022] In a first aspect, referring to Figure 1 and Figure 2 , the display panel 100 has a display area A and a frame area B located at the periphery of the display area A, and the display panel 100 includes a first substrate 1 and a second substrate 2 arranged opposite to each other. The first substrate 1 includes a first substrate 10, a thin film transistor layer 11, a color resistance layer 12, a pixel electrode layer 13, a dielectric layer 19 and a metal light shielding layer 16; the thin film transistor layer 11 is arranged on the side of the first substrate 10 facing the second substrate 2; the color resistance layer 12 is arranged on the side of the thin film transistor layer 11 away from the first substrate 10; the pixel electrode layer 13 is arranged on the side of the color resistance layer 12 away from the first substrate 10; the dielectric layer 19 is arranged between the pixel electrode layer 13 and the thin film transistor layer 11, and the dielectric layer 19 is provided with a first via hole 191, and the pixel electrode layer 13 is electrically connected with the thin film transistor layer 11 through the first via hole 191; the metal light shielding layer 16 includes a first light shielding part 161 located in the display area A; wherein the first light shielding part 161 is arranged on the side of the pixel electrode layer 13 away from the color resistance layer 12, and the orthographic projection of the first light shielding part 161 on the first substrate 10 is arranged away from the orthographic projection of the first via hole 191 on the first substrate 10.

[0023] In the embodiment of the present application, the thin film transistor layer 11 is made on the side surface of the first substrate 10 facing the second substrate 2, the color resistance layer 12 is made on the side of the thin film transistor layer 11 away from the first substrate 10, the pixel electrode layer 13 is made on the side of the color resistance layer 12 away from the thin film transistor layer 11, the pixel electrode layer 13 is electrically connected with the thin film transistor layer 11 through the first via hole 191, the metal light shielding layer 16 includes the first light shielding part 161 located in the display area A; the first light shielding part 161 is arranged on the side of the pixel electrode layer 13 away from the color resistance layer 12, and the orthographic projection of the first light shielding part 161 on the first substrate 10 is arranged away from the orthographic projection of the first via hole 191 on the first substrate 10, so that the risk of short circuit of the first light shielding part 161 due to contact with the first via hole 191 is eliminated, thereby improving the product yield of the display panel 100.

[0024] In an embodiment of the present application, referring to Figure 1 , the display panel 100 includes the first substrate 1 and the second substrate 2 arranged oppositely, a liquid crystal layer (not shown in the figure) arranged between the first substrate 1 and the second substrate 2, and a support column 3 arranged between the first substrate 1 and the second substrate 2, and the support column 3 is used to maintain the cell thickness of the liquid crystal layer. The first substrate 1 can be arranged as an array substrate, and the second substrate 2 can be arranged as an opposite substrate arranged oppositely to the array substrate.

[0025] Referring to Figure 1 , in an embodiment, the first substrate 1 further includes a first insulating layer 14 arranged between the first light shielding part 161 and the pixel electrode layer 13; by arranging the first insulating layer 14, the first light shielding part 161 and the pixel electrode layer 13 are arranged in an insulating manner, thereby avoiding short circuit of the first light shielding part 161 and the pixel electrode layer 13 due to electrical contact.

[0026] Further, the first substrate 1 further includes a second insulating layer 17 and a common electrode layer 15, the second insulating layer 17 is arranged on the side of the dielectric layer 19 away from the thin film transistor layer 11, and the common electrode layer 15 is arranged on the side of the second insulating layer 17 away from the dielectric layer 19 and forms a storage capacitor with the pixel electrode layer 13.

[0027] In an embodiment, the first light shielding portion 161 comprises a plurality of first sub-portions 1611; the first insulating layer 14 can be provided as an integral layer, or can be provided in a patterned manner. In an embodiment, the first insulating layer 14 is provided in a patterned manner, and comprises a plurality of first insulating blocks 141, each of which is located between one of the first sub-portions 1611 and the pixel electrode layer 13.

[0028] The first sub-portion 1611 forms a first projection on the first substrate 10; the first insulating block 141 forms a second projection on the first substrate 10, which has the same shape as the first projection and is completely coincident with the first projection.

[0029] Meanwhile, the orthographic projection of the common electrode layer 15 on the first substrate 10 is arranged in a staggered manner with the second projection.

[0030] That is, only the first insulating layer 14 under the first sub-portion 1611 is retained, and the rest of the first insulating layer 14 is completely etched; on the one hand, retaining the first insulating layer 14 under the first sub-portion 1611 can enable the first sub-portion 1611 to be insulated from the pixel electrode layer 13; on the other hand, completely etching the rest of the first insulating layer 14 can ensure that the film thickness of the storage capacitor layer between the pixel electrode layer 13 and the common electrode layer 15 is uniform.

[0031] In the embodiments of the present application, please refer to Figure 1 and Figure 2 The black matrix layer 22 comprises a plurality of second light shielding portions 221, which are arranged side by side and spaced apart in the first direction F1, and each of which extends along the second direction F2; the first light shielding portion 161 comprises a plurality of first sub-portions 1611, which are arranged side by side and spaced apart in the second direction F2, and each of which extends along the first direction F1; that is, the plurality of first projections formed by the plurality of first sub-portions 1611 and the plurality of third projections formed by the plurality of second light shielding portions 221 are arranged in a longitudinal and transverse staggered manner, and define a plurality of pixel regions C; the color resistance layer 12 comprises a plurality of color resistance blocks 121, each of which is located in one of the pixel regions C.

[0032] Among them, the first direction F1 and the second direction F2 are arranged in a cross manner; specifically, in an embodiment, the first direction F1 and the second direction F2 are perpendicular to each other.

[0033] It can be understood that, due to the first via hole 191 arranged on the dielectric layer 19, the pixel electrode layer 13 is electrically connected with the thin film transistor layer 11 through the first via hole 191; therefore, when the patterned metal light shielding layer 16 is manufactured on the side of the pixel electrode layer 13 away from the color resistance layer 12, the thickness of the photoresist on the metal light shielding layer 16 is different inside and outside the first via hole 191, thereby causing a large exposure difference of the metal light shielding layer 16 inside and outside the first via hole 191, and further causing a high difficulty in exposure process control of the metal light shielding layer 16.

[0034] In an embodiment of the present application, the orthographic projection of the first via hole 191 on the first substrate 10 is located in the range of the orthographic projection of the second light shielding part 221 on the first substrate 10, that is, the orthographic projection of the first via hole 191 on the first substrate 10 is located in the range of the third projection. The first substrate 1 further comprises a spacer layer 192, which is filled in the first via hole 191 and arranged protruding from the periphery of the first via hole 191; wherein the pixel electrode layer 13 covers the spacer layer 192.

[0035] In this way, when the metal light shielding layer 16 is manufactured on the side of the pixel electrode layer 13 away from the color resistance layer 12, since the first via hole 191 is filled with the spacer layer 192 and the spacer layer 192 is arranged protruding from the periphery of the first via hole 191 to improve the film layer topography, the manufacturing surface of the metal light shielding layer 16 is flat, thereby causing no exposure difference of the patterned metal light shielding layer 16 everywhere, and further reducing the manufacturing difficulty of the metal light shielding layer 16.

[0036] As described above, the orthographic projection of the first via hole 191 on the first substrate 10 is located in the range of the orthographic projection of the second light shielding part 221 on the first substrate 10, and it can be known that the spacer layer 192 forms a fourth projection on the first substrate 10, which is located in the range of the third projection formed by the second light shielding part 221; the display panel 100 further comprises a support column 3 arranged between the second light shielding part 221 and the spacer layer 192; that is, the support column 3 corresponds to the position of the black matrix layer 22, and since the spacer layer 192 is arranged protruding from the periphery of the first via hole 191, the film layer around the spacer layer 192 is farther away from the support column 3 in the thickness direction of the first substrate 1, thereby avoiding that the support column 3 scratches the film layer around the spacer layer 192 due to movement, and further ensuring the yield and display effect of the display panel 100.

[0037] The structure of the spacer layer 192 is not limited in the present application. In some embodiments, the first via hole 191 is filled by the spacer layer 192 to improve the film layer topography, and the spacer layer 192 is filled to form a bump protruding from the surface of the spacer layer 192 at the same time; in another embodiment, the spacer layer 192 includes a first spacer part 1921 and a second spacer part 1922, the first spacer part 1921 fills the first via hole 191, and the second spacer part 1922 is arranged on the first spacer part 1921 and protrudes from the periphery of the first via hole 191.

[0038] In an embodiment of the present application, further referring to Figure 1 , the first substrate 1 further includes a first electrode layer 131 and a second electrode layer 132; the first electrode layer 131 is arranged on the color resist layer 12, and the first electrode layer 131 is electrically connected to the thin film transistor layer 11 through the first via hole 191; the second electrode layer 132 is arranged on the first electrode layer 131 and covers the spacer layer 192 in the first via hole 191, and the second electrode layer 132 is electrically connected to the first electrode layer 131; wherein the first electrode layer 131 and the second electrode layer 132 constitute the pixel electrode layer 13; the metal light shielding layer 16 is arranged on the side of the second electrode layer 132 away from the first electrode layer 131.

[0039] As mentioned above, in an embodiment of the present application, the metal light shielding layer 16 further includes a third light shielding part 162 located in the frame area B, and the third light shielding part 162 is located on the side of the dielectric layer 19 away from the thin film transistor layer 11; the second insulating layer 17 covers the pixel electrode layer 13, the first light shielding part 161 and the third light shielding part 162; the third light shielding part 162 is electrically connected to the common electrode layer 15 through a second via hole and electrically connected to the thin film transistor layer 11 through a third via hole.

[0040] That is, the metal light shielding layer 16 further includes a third light shielding part 162 arranged in the frame area B, and the third light shielding part 162 is inputted with an electrical signal by changing the line in the frame area B, so as to load the electrical signal to the first light shielding part 161, which not only can release the static electricity generated in the first substrate 1, but also can load the stable electrical signal to the first light shielding part 161 to avoid the interference of the signal transmission in the first substrate 1 caused by the large fluctuation of the electrical signal in the first light shielding part 161.

[0041] Specifically, the voltage signal loaded in the first light shielding part 161 is greater than or equal to -500mA and less than or equal to 500mA; and the potential of the third light shielding part 162 is the same as that of the common electrode layer 15.

[0042] In an embodiment, the first substrate 1 further comprises a planar layer 18 disposed on the thin film transistor layer 11 and covering the color resist layer 12, the dielectric layer 19 is disposed on a side of the planar layer 18 away from the thin film transistor layer 11; the planar layer 18 is provided with a first through hole at a position corresponding to the first via hole 191; the third light shielding part 162 is located on a side surface of the dielectric layer 19 away from the planar layer 18; the pixel electrode layer 13 is located on a side surface of the dielectric layer 19 away from the planar layer 18 and is electrically connected to the thin film transistor layer 11 through the first via hole 191 and the first through hole; the first light shielding part 161 is disposed on a side of the pixel electrode layer 13 away from the dielectric layer 19; the third light shielding part 162 is electrically connected to the common electrode layer 15 through a second via hole and electrically connected to the thin film transistor layer 11 through a third via hole.

[0043] Further, the second insulating layer 17 covers the pixel electrode layer 13, the first light shielding part 161 and the third light shielding part 162. The first insulating layer 14 is provided in a pattern and further comprises a plurality of second insulating blocks 142 located in the frame area B, each of the second insulating blocks 142 is located between one of the third light shielding parts 162 and the dielectric layer 19.

[0044] For further reference Figure 1 , the thin film transistor layer 11 comprises a plurality of thin film transistors disposed on the first substrate 10 and a plurality of interlayer insulating layers covering the plurality of thin film transistors. The plurality of thin film transistors comprises a plurality of first thin film transistors 111 located in the display area A and a plurality of second thin film transistors 112 located in the frame area B; the plurality of interlayer insulating layers comprises a first interlayer insulating layer 113, a second interlayer insulating layer 114, a third interlayer insulating layer 115, a fourth interlayer insulating layer 116, a fifth interlayer insulating layer 117 and a sixth interlayer insulating layer 118 disposed on the first substrate 10 in sequence.

[0045] It should be noted that the display panel 100 provided by the embodiments of the present application is suitable for an LTPO (English full name: Low Temperature Poly-Oxide, Chinese abbreviation: low temperature polyoxide) display panel 100; the first thin film transistor 111 is set as an oxide thin film transistor, and the second thin film transistor 112 is set as a low temperature poly-silicon thin film transistor.

[0046] In an embodiment of the present application, the first thin film transistor 111 includes a first gate electrode disposed on the second interlayer insulating layer 114 and covered by the third interlayer insulating layer 115, a first active layer disposed on the third interlayer insulating layer 115 and covered by the fourth interlayer insulating layer 116, a second gate electrode disposed on the fourth interlayer insulating layer 116 and covered by the fifth interlayer insulating layer 117, a first source electrode disposed on the fifth interlayer insulating layer 117 and covered by the sixth interlayer insulating layer 118, and a first drain electrode, wherein the first gate electrode and the second gate electrode are respectively located on the upper and lower sides of the first active layer and are disposed corresponding to the channel region of the first active layer, and the first source electrode and the first drain electrode are respectively connected to the two sides of the first active layer and are respectively located on the opposite sides of the channel region.

[0047] Specifically, one end of the first drain electrode of the first thin film transistor 111 penetrates through the sixth interlayer insulating layer 118, the fifth interlayer insulating layer 117 and the fourth interlayer insulating layer 116 and is connected to the first active layer, and the other end of the first drain electrode extends to the side surface of the sixth interlayer insulating layer 118 away from the fifth interlayer insulating layer 117 and is exposed from the first via hole 191, and the first electrode layer 131 is electrically connected to the first drain electrode through the first via hole 191, and then the first via hole 191 is filled with the spacer layer 192.

[0048] Meanwhile, the color resist block 121 is also filled in the contact hole between the first drain electrode and the first active layer to avoid the concave film layer morphology at the contact hole.

[0049] Based on the structure of the first substrate 1, the present application further provides a manufacturing method of the first substrate 1.

[0050] Please refer to Figure 3a, providing a first substrate 10, manufacturing the thin film transistor layer 11 on the first substrate 10; manufacturing a seventh interlayer insulating layer 119 on the thin film transistor layer 11; manufacturing the color resistance layer 12 on the seventh interlayer insulating layer 119, the color resistance layer 12 comprising a plurality of color resistance blocks 121 arranged in an array; manufacturing the first planar layer 18 on the seventh interlayer insulating layer 119, the first planar layer 18 covering the color resistance layer 12; manufacturing the dielectric layer 19 on the first planar layer 18; disposing the first electrode layer 131 on the dielectric layer 19, the first electrode layer 131 being electrically connected with the thin film transistor layer 11 through the first via 191; filling the first spacer 1921 in the first via 191, manufacturing a second spacer 1922 on the first spacer 1921, the second spacer 1922 being disposed beyond the periphery of the first via 191; manufacturing the second electrode layer 132 on the first electrode layer 131, the second electrode layer 132 covering the second spacer 1922; manufacturing the first insulating layer 14 on the seventh interlayer insulating layer 119; Please refer to Figure 3b , manufacturing the metal light shielding layer 16 on the first insulating layer 14; Please refer to Figure 3c , manufacturing the photoresist layer 4 on the metal light shielding layer 16, and exposing and developing the photoresist layer 4 to form the patterned photoresist layer 4; Please refer to Figure 3d , etching the metal light shielding layer 16 and the first insulating layer 14 with the patterned photoresist layer 4 as a mask to form the first light shielding part 161 and the third light shielding part 162; Please refer to Figure 3e , manufacturing the second insulating layer 17 on the seventh interlayer insulating layer 119, the second insulating layer 17 covering the first electrode layer 131, the second electrode layer 132 and the metal light shielding layer 16.

[0051] As described above, in the embodiments of the present application, the first via 191 is filled with the spacer 192, so as to improve the film layer morphology, thus the manufacturing surface of the first insulating layer 14 and the metal light shielding layer 16 is flat, so that the exposure of the metal light shielding layer 16 is uniform, thereby reducing the manufacturing difficulty of the metal light shielding layer 16; and the metal light shielding layer 16 is manufactured on the second electrode layer 132, and the orthographic projection of the first light shielding part 161 on the first substrate 10 is separately disposed from the orthographic projection of the first via 191 on the first substrate 10; thus the risk of short circuit of the first light shielding part 161 due to contact with the first via 191 is eliminated, thereby improving the product yield of the display panel 100.

[0052] In a second aspect, the embodiments of the present application further provide a display device. The display device comprises the display panel 100. It should be noted that the display panel 100 is the display panel 100 described above, that is, the display panel 100 comprises all the technical features of the display panel 100 described above, and the display device comprises all the embodiments of the display panel 100 described above, and thus has all the technical effects of the embodiments described above, which will not be repeated here.

[0053] In an embodiment, the display device can further comprise a backlight module, and the display panel is arranged on the light exit side of the backlight module.

[0054] In an embodiment, the display device can comprise a mobile phone, a television, a tablet, a computer, or a VR device.

[0055] The display panel and the display device provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a first substrate, the first substrate comprises: a first substrate; a thin film transistor layer disposed on one side of the first substrate; a pixel electrode layer disposed on a side of the thin film transistor layer away from the first substrate; a dielectric layer disposed between the pixel electrode layer and the thin film transistor layer, the dielectric layer being provided with a first via, the pixel electrode layer being electrically connected to the thin film transistor layer through the first via; a common electrode layer disposed on a side of the pixel electrode layer away from the first substrate; a metal light shielding layer comprising a first light shielding portion disposed between the pixel electrode layer and the common electrode layer, the first light shielding portion being disposed in insulation with the pixel electrode layer.

2. The display panel of claim 1, wherein, The first substrate further comprises a first insulating layer disposed between the first light shielding portion and the pixel electrode layer.

3. The display panel of claim 2, wherein, The first light shielding portion comprises a plurality of first sub-portions; The first insulating layer is disposed in a pattern and comprises a plurality of first insulating blocks, each first insulating block being located between one first sub-portion and the pixel electrode layer.

4. The display panel of claim 3, wherein, The first sub-portion has a first projection on the first substrate; The first insulating block has a second projection on the first substrate, the second projection coinciding with the first projection.

5. The display panel of claim 1, wherein, The first light shielding portion comprises a plurality of first sub-portions, the first sub-portion having a first projection on the first substrate; The display panel further comprises a second substrate disposed opposite the first substrate; The second substrate comprises a second substrate and a black matrix layer, the black matrix layer being disposed on a side surface of the second substrate facing the first substrate, the black matrix layer comprising a plurality of second light shielding portions, the second light shielding portions having third projections on the first substrate; A plurality of first projections formed by the plurality of first sub-portions and a plurality of third projections formed by the plurality of second light shielding portions are disposed in a longitudinal and transverse interlaced manner and define a plurality of pixel regions; The first substrate further comprises a color resistance layer disposed on a side of the thin film transistor layer away from the first substrate; The color resistance layer comprises a plurality of color resistance blocks, each color resistance block being located within one pixel region; The first via has a projection on the first substrate within the range of the third projection; The first sub-portion is disposed at the junction of two adjacent color resistance blocks.

6. The display panel of claim 5, wherein, The display panel further comprises a support column disposed between the second light shielding portion and the spacer layer; The pixel electrode layer covers the spacer layer. The first substrate further comprises a spacer layer filled in the first via and protruding from the periphery of the first via; 7. The display panel of claim 1, wherein, The first substrate further comprises: a first electrode layer disposed on the thin film transistor layer, the first electrode layer being electrically connected to the thin film transistor layer through the first via; and ​ A second electrode layer is disposed on the first electrode layer and covers the spacer in the first via, and the second electrode layer is electrically connected with the first electrode layer; The first electrode layer and the second electrode layer constitute the pixel electrode layer; The metal light shielding layer is disposed on a side of the second electrode layer away from the first electrode layer.

8. The display panel of claim 2, wherein, The display panel has a display area and a frame area located at the periphery of the display area; The first substrate further comprises a second insulating layer disposed on a side of the dielectric layer away from the thin film transistor, and the common electrode layer is disposed on a side of the second insulating layer away from the dielectric layer and forms a storage capacitor with the pixel electrode layer; The metal light shielding layer further comprises a third light shielding portion located in the frame area, and the third light shielding portion is disposed on a side of the dielectric layer away from the thin film transistor; The first insulating layer further comprises a second insulating block located in the frame area, and the second insulating block is located between the third light shielding portion and the dielectric layer; The second insulating layer covers the pixel electrode layer, the first light shielding portion, and the third light shielding portion; The third light shielding portion is electrically connected with the common electrode layer through a second via.

9. The display panel of claim 1, wherein, The display panel has a display area and a frame area located at the periphery of the display area; The thin film transistor layer comprises a plurality of first thin film transistors and a plurality of second thin film transistors, the plurality of first thin film transistors are disposed in the display area, the first thin film transistors are disposed as oxide thin film transistors, the plurality of second thin film transistors are disposed in the frame area, and the second thin film transistors are disposed as low-temperature polysilicon thin film transistors; The pixel electrode layer is electrically connected with a first drain of the first thin film transistor through the first via; The metal light shielding layer further comprises a third light shielding portion located in the frame area, and the third light shielding portion overlaps the second thin film transistor in the thickness direction of the display panel.

10. A display device, characterized by comprising: The display panel comprises the display panel as claimed in any one of claims 1-9.

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