Display panel and driving method thereof

Abstract

The invention discloses a display panel and a driving method thereof.The display panel comprises a first substrate and a second substrate which are arranged in a box-to-box mode, the first substrate comprises a clock signal wiring area, a gate driving circuit area and a display area, the second substrate comprises a first electrode area and a second electrode area, a first electrode layer is arranged in the first electrode area, and a second electrode layer is arranged in the second electrode area; a second electrode layer is arranged in the second electrode area, the projection area of the first electrode area is smaller than the sum of the area of the clock signal wiring area and the area of the gate drive circuit area in the direction from the second substrate to the first substrate, and the projection area of the second electrode area is larger than or equal to the display area. A spacer region is arranged between the first electrode region and the second electrode region, and the first electrode layer and the second electrode layer are arranged at an interval through the spacer region. The electrode regions corresponding to the clock signal wiring region, the gate drive circuit region and the display region on the second substrate are arranged at intervals, so that capacitance cannot be formed in the electrode regions corresponding to the clock signal wiring region and the gate drive circuit region, and the load is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a driving method thereof. BACKGROUND

[0002] With the rapid development of technology, the current liquid crystal panel continues to develop towards high integration and low cost. One important application of the technology is the array substrate gate driving (GDL, Gate Driver Less) technology. The GDL circuit can replace the external driving chip. The GDL circuit can be prepared on the left and right sides of the thin film transistor array substrate by using conventional exposure process, which can reduce the production cost of the product and the module failure of the binding process, improve the production capacity, and at the same time, realize the high integration of the liquid crystal panel, and meet the customer's demand for narrow frame and thin product.

[0003] However, the application of the GDL circuit on some high-frequency, large-size and high-resolution liquid crystal panels is very challenging. In the GDL circuit, the clock signal (CK) doubles with the frequency, and the number of charging and discharging of the entire load doubles, which causes the current to double, which increases the heat generation of the signal line, thereby causing reliability problems such as liquid crystal polarization, characteristic drift, and even causing the display to burn out, thereby affecting the normal work of the entire liquid crystal display panel. SUMMARY

[0004] The purpose of the present application is to provide a display panel and a driving method thereof, which aims to reduce the load of the GDL circuit and ensure the stability and reliability of the CK signal.

[0005] The present application discloses a display panel, which comprises a first substrate and a second substrate arranged in a cell, the first substrate comprises a clock signal line area, a gate driving circuit area and a display area, the second substrate comprises a first electrode area and a second electrode area, the first electrode area is provided with a first electrode layer, and the second electrode area is provided with a second electrode layer, the projection area of the first electrode area is less than the sum of the area of the clock signal line area and the gate driving circuit area along the direction of the second substrate towards the first substrate, and the projection area of the second electrode area is greater than or equal to the display area. The first electrode area and the second electrode area are provided with a spacing area, and the first electrode layer and the second electrode layer are provided with a spacing area.

[0006] Optionally, the interval region comprises a hollow part, the hollow part is arranged on the second substrate in a fitting manner, the hollow part is formed by cutting in a laser manner during preparation of a mother board of the display panel, and a length of the hollow part is A in a direction from the first electrode region to the second electrode region, where A=50um+C1+D1 / 2, C1 is an accuracy size of a cutting position, and D1 is an accuracy size of a cutting device.

[0007] Optionally, the first electrode layer comprises at least two first electrodes arranged at intervals, the two first electrodes are not communicated with each other, the clock signal wire region and the gate drive circuit region are arranged at intervals, and projections of the clock signal wire region and the gate drive circuit region cover the second electrode and the first electrode respectively in a direction from the second substrate to the first substrate.

[0008] Optionally, the interval region is provided with a load control switch, an input end of the load control switch is connected to the first electrode layer, an output end of the load control switch is connected to the second electrode layer, and a control end of the load control switch is connected to a clock signal frequency monitoring module, the clock signal frequency monitoring module monitors a frequency of a clock signal line in the clock signal wire region, when the frequency is greater than or equal to a preset frequency, the load control switch is controlled to be in an off state, and the first electrode layer and the second electrode layer are not communicated with each other, and when the frequency is less than the preset frequency, the load control switch is controlled to be in a conductive state, and the first electrode layer and the second electrode layer are communicated with each other.

[0009] Optionally, the interval region is provided with a load control switch, an input end of the load control switch is connected to the first electrode layer, an output end of the load control switch is connected to the second electrode layer, and a control end of the load control switch is connected to a temperature monitoring module, the temperature monitoring module monitors a temperature in the clock signal wire region, when the temperature is greater than or equal to a preset temperature, the load control switch is controlled to be in an off state, and the first electrode layer and the second electrode layer are not communicated with each other, and when the temperature is less than the preset temperature, the load control switch is controlled to be in a conductive state, and the first electrode layer and the second electrode layer are communicated with each other.

[0010] Optionally, a liquid crystal layer is arranged between the first substrate and the second substrate, the liquid crystal layer comprises a first liquid crystal layer and a second liquid crystal layer, the first liquid crystal layer is arranged between the clock signal wire region, the gate drive circuit region and the first electrode region, and the second liquid crystal layer is arranged between the display region and the second electrode region. The liquid crystal in the first liquid crystal layer and the liquid crystal in the second liquid crystal layer are formed by using the same liquid crystal material, and the density of the liquid crystal in the first liquid crystal layer is greater than the density of the liquid crystal in the second liquid crystal layer.

[0011] Optionally, the first electrode layer comprises two first electrodes arranged at intervals, the two first electrodes are not connected to each other, and the two electrodes are a clock trace electrode and a gate circuit electrode respectively, the clock trace electrode corresponds to the clock signal trace area, and the gate circuit electrode corresponds to the gate drive circuit area. The first substrate and the second substrate are provided with a liquid crystal layer, the liquid crystal layer comprises a first liquid crystal layer and a second liquid crystal layer, the first liquid crystal layer is arranged between the gate drive circuit area and the gate circuit electrode, and the second liquid crystal layer is arranged between the display area and the second electrode.

[0012] Optionally, a frame glue is arranged between the clock signal trace area and the gate drive circuit area, one end of the frame glue is arranged to be attached to the second substrate between the clock trace electrode and the gate circuit electrode, and the other end of the frame glue is arranged to be attached to the first substrate between the clock signal trace area and the gate drive circuit area; the thickness of the first electrode layer is less than the thickness of the second electrode layer, and the electrodes in the first electrode layer and the electrodes in the second electrode layer are formed of indium tin oxide.

[0013] Optionally, the frame glue comprises a frame glue body and a spacing column filled in the frame glue body, the frame glue body is formed by mixing an acrylic / epoxy resin matrix, a light / heat curing agent, and conductive particles, oxygen / water vapor resistance additives, etc., and the spacing column is formed by mixing an acrylic / epoxy resin, a photoinitiator, an active monomer, a leveling agent, and an organic solvent, etc.

[0014] The application further discloses a driving method for driving the display panel. The temperature in the clock signal trace area is monitored, and when the temperature is greater than or equal to a first preset temperature, the load control switch is controlled to be in an off state, and the first electrode layer and the second electrode layer are not connected; When the temperature is less than the first preset temperature and greater than a second preset temperature, the frequency of the clock signal line in the clock signal trace area is monitored, and when the frequency is greater than or equal to a preset frequency, the load control switch is controlled to be in an off state, and the first electrode layer and the second electrode layer are not connected; When the temperature is less than the preset temperature, the load control switch is controlled to be in a conductive state, and the first electrode layer and the second electrode layer are connected; or when the frequency is less than the preset frequency, the load control switch is controlled to be in a conductive state, and the first electrode layer and the second electrode layer are connected.

[0015] Compared with the conventional display panel with GDL circuit, the application provides a novel display panel, a clock signal wire area, a gate drive circuit area and a display area are formed on a first substrate, a second substrate forms a first electrode area and a second electrode area, the first electrode area is provided with a first electrode layer, the second electrode area is provided with a second electrode layer, the projection area of the first electrode area is less than the sum of the areas of the clock signal wire area and the gate drive circuit area in the direction of the second substrate towards the first substrate, and the projection area of the second electrode area is greater than or equal to the display area; a spacing area is arranged between the first electrode area and the second electrode area, the first electrode layer and the second electrode layer are arranged in a spaced manner through the spacing area, so that the electrode corresponding to the GDL area on the second substrate is in a floating state and cannot form a capacitor with the wire and device of the GDL, thereby reducing the load, improving the problem that when the CK signal is multiplied with the frequency, the charge and discharge times of the whole load are multiplied, thereby causing the current to be multiplied, which increases the heat generation of the signal wire, thereby causing reliability, such as liquid crystal polarization, characteristic drift and the like, further avoiding the burning of the display, thereby affecting the normal work of the whole liquid crystal display. BRIEF DESCRIPTION OF DRAWINGS

[0016] The included drawings provide further understanding of the embodiments of the application and constitute a part of the specification, which serve to explain the principles of the application together with the text. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor under the premise of the drawings: Figure 1 is a display panel structure schematic diagram of the display panel of the first embodiment of the application; Figure 2 is a sectional structure schematic diagram of AA' in the Figure 1 Figure 3 is a motherboard cutting schematic diagram of the display panel of the first embodiment of the application; Figure 4 is a sectional structure schematic diagram of the display panel of the second embodiment of the application; Figure 5 is a sectional structure schematic diagram of the display panel of the third embodiment of the application; Figure 6 is a sectional structure schematic diagram of the display panel of the fourth embodiment of the application; Figure 7 is a sectional structure schematic diagram of the display panel of the fifth embodiment of the application; Figure 8 ​FIG. 6 is a flow diagram of a driving method of the display panel of the sixth embodiment of the present application.

[0017] 100, display panel; 200, first substrate; 210, clock signal wire area; 220, gate driving circuit area; 230, display area; 300, second substrate; 310, first electrode area; 311, first electrode layer; 312, first electrode; 313, clock wire electrode; 314, gate circuit electrode; 320, second electrode area; 321, second electrode layer; 322, second electrode; 330, spacing area; 331, hollow part; 332, load control switch; 400, clock signal frequency monitoring module; 500, temperature monitoring module; 600, liquid crystal layer; 610, first liquid crystal layer; 620, second liquid crystal layer; 700, frame glue; 710, frame glue main body; 720, spacing column. DETAILED DESCRIPTION

[0018] It is to be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting, and that the application can be practiced by many alternative forms without departing from the spirit thereof.

[0019] The present application will be described in detail below with reference to the accompanying drawings and optional embodiments.

[0020] As a first embodiment of the present application, a display panel 100 is disclosed, as shown in FIG. 1, which comprises a first substrate 200, a second substrate 300, a first electrode layer 311, a second electrode layer 321, a liquid crystal layer 600, and a frame glue 700. Figures 1 to 3As shown, the display panel 100 comprises a first substrate 200 and a second substrate 300 arranged in a cell, the first substrate 200 is an array substrate, and the second substrate 300 is a color film substrate, the first substrate 200 comprises a clock signal wire area 210, a gate drive circuit area 220 and a display area 230, the clock signal wire area 210 mainly arranges clock signal wires CK1-CK4 and a frame start signal line STV, and wires connecting the clock signal wires and the gate drive circuit, the gate drive circuit area 220 arranges a gate drive unit (GOA), the second substrate 300 comprises a first electrode area 310 and a second electrode area 320, the first electrode area 310 is provided with a first electrode layer 311, and the second electrode area 320 is provided with a second electrode layer 321, in the direction of the second substrate 300 towards the first substrate 200, the projection area of the first electrode area 310 is less than the sum of the areas of the clock signal wire area 210 and the gate drive circuit area 220, and the projection area of the second electrode area 320 is greater than or equal to the display area 230; wherein, the first electrode area 310 and the second electrode area 320 are provided with a spacing area 330, the first electrode layer 311 and the second electrode layer 321 are arranged in a spaced manner through the spacing area 330; the first electrode layer 311 and the second electrode layer 321 are not manufactured by mask process Mask in the process, in order to not increase the cost, mainly laser is adopted to cut off, or the mask of HTM is adopted to cut off with other layers to share Mask to form the spacing area 330.

[0021] Generally, the area where the clock signal wire area 210 and the gate drive circuit area 220 are combined together is generally the GDL area, and the interval area 330 is cut by laser during the preparation of the mother board of the display panel 100, and the load of the GDL is mostly from the capacitance formed by the wire in the clock signal wire area 210 and the wire / device in the gate drive circuit and the CF ITO electrode on the color film substrate, and the electrode area on the second substrate 300 is separated into two electrode areas in the present application, and the first electrode layer 311 and the second electrode layer 321 of the two electrode areas are arranged by the interval area 330, so that the electrode corresponding to the GDL area on the second substrate 300 is in a floating state and cannot form a capacitance with the wire and device of the GDL, thereby reducing the load, improving the problem that when the CK signal is multiplied with the frequency, the charge and discharge times of the entire load are multiplied, thereby causing the current to be multiplied, which increases the heat generation of the clock signal wire, thereby causing reliability problems such as liquid crystal polarization and characteristic drift, further avoiding the burning of the display, thereby affecting the normal work of the entire liquid crystal display, and generally, in order to facilitate the process, the first electrode layer 311 and the second electrode layer 321 are formed by the same process and have the same thickness, and the electrodes in the first electrode layer 311 and the electrodes in the second electrode layer 321 are formed by indium tin oxide material, of course, the thickness of the first electrode layer 311 can be less than the thickness of the second electrode layer 321, which can reduce the parasitic capacitance formed by the first electrode layer 311 and the clock signal wire area 210 and the gate drive circuit area 220, and avoid the situation that if there is residual material during the separation of the interval area 330, the electrodes of the two electrode areas are connected after the separation, and the load is too large.

[0022] Reference Figure 4 As shown in the second embodiment of the present application, which is a further refinement of the above-mentioned first embodiment, in the present embodiment, reference Figure 1 , Figure 3 and Figure 4As shown, the interval region 330 is generally not provided with any film layer, and after cutting, a hollow part 331 is formed, which is arranged on the second substrate 300 in a hollow manner. The hollow part 331 is cut by laser during the preparation of the mother board of the display panel 100, and the length of the hollow part 331 in the direction from the first electrode region 310 to the second electrode region 320 is A, where A = 50um + C1 + D1 / 2, C1 is the accuracy of the cutting position, and D1 is the accuracy of the cutting equipment. In order to avoid local short circuit defects at the cutting position, the width of the cutting position, i.e. the length of the hollow part 331, is generally set within a certain range, and the cutting position accuracy measurement and the accuracy of the cutting equipment are comprehensively considered to ensure that the electrode layer between the two electrode regions is too close after cutting, and the residual residues in the interval region 330 may cause the first electrode layer 311 to continue to generate parasitic capacitance with the clock signal wire region 210 and the gate drive circuit region 220, form a load, and affect the reliability and stability of the signal of the clock signal wire.

[0023] Further, in order to further eliminate parasitic capacitance, the first electrode layer 311 includes at least two first electrodes 312 arranged at intervals, and the two first electrodes 312 are not connected to each other. The clock signal wire region 210 and the gate drive circuit region 220 are arranged at intervals, and in the direction from the second substrate 300 to the first substrate 200, the projection of the clock signal wire region 210 covers the first electrode 312, and the projection of the gate drive circuit region 220 covers the second electrode 322. This embodiment mainly takes two electrodes as an example for description. The first electrode layer 311 includes two first electrodes 312 arranged at intervals, and the two first electrodes 312 are not connected to each other. The two electrodes are a clock wire electrode 313 and a gate circuit electrode 314, respectively. The clock wire electrode 313 corresponds to the clock signal wire region 210, i.e. the clock wire electrode 313 corresponds to the upper side of the clock signal wire region 210. The gate circuit electrode 314 corresponds to the gate drive circuit region 220, i.e. the gate circuit electrode 314 is arranged above the gate drive circuit region 220. The first substrate 200 and the second substrate 300 are provided with a liquid crystal layer 600, which includes a first liquid crystal layer 610 and a second liquid crystal layer 620. The first liquid crystal layer 610 is arranged between the gate drive circuit region 220 and the gate circuit electrode 314, and the second liquid crystal layer 620 is arranged between the display region 230 and the second electrode 322.

[0024] In addition, no liquid crystal layer 600 is arranged between the clock line electrode 313 and the clock signal line area 210, and only air is arranged between the clock line electrode 313 and the clock signal line area 210. The dielectric constant of air is smaller than that of liquid crystal, so that the load between the clock line electrode 313 and the clock signal line area 210 is greatly reduced.

[0025] As a third embodiment of the present application, the second embodiment is further refined and improved. Referring to FIG. 8, Figure 4 and Figure 5 As shown in FIG. 8, the spacing area 330 is generally not provided with any film layer, and a hollow part 331 is formed after cutting. The hollow part 331 is arranged on the second substrate 300 in a hollow manner, and is cut and formed by laser during preparation of the mother board of the display panel 100. The clock signal line area 210 and the gate drive circuit area 220 are provided with a frame glue 700. One end of the frame glue 700 is arranged between the clock line electrode 313 and the gate circuit electrode 314 and is attached to the second substrate 300. The other end of the frame glue 700 is arranged between the clock signal line area 210 and the gate drive circuit area 220 and is attached to the first substrate 200. The clock line electrode 313 and the gate circuit electrode 314 are arranged in a spaced manner, and the clock signal line area 210 and the gate drive circuit area 220 are also arranged in a spaced manner. Hollow parts are left, and the hollow parts are hollowed by laser during preparation of the device of the mother board of the display panel 100. Two hollows are formed above and below the hollow parts, the two hollows correspond to each other, and there is no liquid crystal layer 600 between the two hollows. The frame glue 700 is directly arranged in the area corresponding to the two hollows, which can prevent the outflow of liquid crystal and can be used as a support structure of the two substrates. At the same time, the frame glue 700 is adhered to the two substrates, which can prevent the displacement of the two substrates.

[0026] Generally, the frame glue 700 includes a frame glue body 710 and a spacing column 720 filled in the frame glue body 710. The frame glue body 710 is formed by mixing an acrylic / epoxy resin matrix, a light / heat curing agent, conductive particles, and an oxygen / waterproof additive. The spacing column 720 is formed by mixing an acrylic / epoxy resin, a photoinitiator, an active monomer, a leveling agent, and an organic solvent.

[0027] The frame adhesive 700 of the display panel 100 is mainly composed of an acrylic / epoxy resin matrix, photo / thermal curing agents, and various functional fillers (conductive particles, oxygen / moisture barrier additives). Depending on different product requirements (transparency, conductivity, high temperature resistance, low moisture permeability, etc.), appropriate special additives can be added to the formula. This ensures strong adhesion between substrates while also achieving sealing, anti-contamination, and necessary electrical properties for the liquid crystal. The PS spacer pillars 720 inside the frame adhesive 700 are essentially a photosensitive resin (photosensitive polymer), mainly composed of acrylic / epoxy resins, photoinitiators, active monomers, leveling agents, and organic solvents. After photolithography and curing, they form an elastic, heat-resistant, and highly adhesive columnar structure to support the upper and lower substrates and ensure uniform thickness of the liquid crystal layer 600.

[0028] As a fourth embodiment of this application, it further limits and improves upon the first embodiment described above, as referred to... Figure 6 As shown, the interval 330 can be hollowed out without any objects, or it can be equipped with a switch connecting the two electrode layers as needed. It can be turned on when needed and turned off when not needed, thereby improving the diversity of the display. Specifically, the interval 330 is provided with a load control switch 332. The input terminal of the load control switch 332 is connected to the first electrode layer 311, the output terminal is connected to the second electrode layer 321, and the control terminal is connected to the clock signal frequency monitoring module 400. The load control switch 332 includes a thin film transistor, which is formed on the second substrate 300 with a gate, a source, and a drain. The source is connected to the electrode layer, the drain is connected to the second electrode layer 321, and the gate is connected to the clock signal frequency monitoring module 400.

[0029] The clock signal frequency monitoring module 400 monitors the frequency of the clock signal line in the clock signal wire area 210. When the frequency is greater than or equal to a preset frequency, the load control switch 332 is controlled to be in an off state, and the first electrode layer 311 and the second electrode layer 321 are not connected. When the frequency is less than the preset frequency, the load control switch 332 is controlled to be in an on state, and the first electrode layer 311 and the second electrode layer 321 are connected. Considering that the current commonly used display panel 100 has a lower and higher requirement for refresh rate, especially during gaming, an ultra-high refresh rate is required. In the case of high refresh rate, the clock signal frequency will also increase. Assuming that the user is currently playing a game and may require a 120Hz refresh rate display, the corresponding frequency is 120Hz (this is only a hypothetical assumption, and the corresponding value of the refresh rate and the frequency may be different). If the two electrode layers are kept connected, a load will inevitably be generated, causing the clock signal on the clock signal wire to be delayed or lost, thereby failing to meet the requirement for refresh rate. Therefore, at this time, the load control switch 332 can be controlled to be in an off state, and the first electrode layer 311 and the second electrode layer 321 are not connected, thereby ensuring high refresh rate display. However, if the user is watching a book and has a low requirement for refresh rate, the load control switch 332 can be controlled to be in an on state, and the first electrode layer 311 and the second electrode layer 321 are connected. In this way, even if a parasitic capacitance is generated, it has little effect on the clock signal on the clock signal wire. The parasitic capacitance can instead supply power to the electrode layer, and the book display can be maintained even if the voltage input by the power supply is small, thereby reducing the power consumption of the device.

[0030] Further, if it is worried that the capacitance generated when the first electrode layer 311 and the second electrode layer 321 are connected is too large, the liquid crystal layer 600 can also be changed. Specifically, the liquid crystal layer 600 is arranged between the first substrate 200 and the second substrate 300, and includes a first liquid crystal layer 610 and a second liquid crystal layer 620. The first liquid crystal layer 610 is arranged between the clock signal wire area 210, the gate drive circuit area 220, and the first electrode area 310. The second liquid crystal layer 620 is arranged between the display area 230 and the second electrode area 320. The liquid crystal in the first liquid crystal layer 610 and the liquid crystal in the second liquid crystal layer 620 are formed of the same liquid crystal material. The density of the liquid crystal in the first liquid crystal layer is greater than that in the second liquid crystal layer 620, so that the parasitic capacitance between the clock signal wire area 210, the gate drive circuit area 220, and the first electrode area 310 is small and does not have too great an effect on the clock signal.

[0031] Generally, the thin film transistor is selected from a bottom-gate type thin film transistor, and of course, a top-gate type thin film transistor can also be used. The specific preparation process of the bottom-gate type thin film transistor of the application on the second substrate is as follows: A glass or flexible plastic substrate is selected, and cleaning and dust removal are performed first. A metal gate material (Mo, Al, Ti, Cu, etc.) is deposited on the substrate by sputtering, evaporation or electrodeposition, and then photolithography, development, etching and stripping are performed to obtain a gate pattern. If two masks (a gate mask and a semi-transparent mask) are used, the definition of the gate and source / drain patterns can be completed, and the process is more simplified. An insulating layer is deposited on the formed gate, and oxides such as Al2O3, SiO2 and Ta2O5 are commonly used, with a thickness of 50-200 nm. Atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD) is used to ensure high dielectric constant and good uniformity. According to different TFT types, corresponding semiconductor materials are selected. Metal oxide semiconductor (A-OS) such as a-IGZO and a-IZO: a thin layer of 20-40 nm is formed on the gate dielectric by sputtering or metal organic chemical vapor deposition (MOCVD). After deposition, annealing (thermal annealing or laser annealing) is usually performed to improve the crystal quality and carrier mobility. A metal (Al, Mo, Cu, etc.) is deposited on the semiconductor layer with a thickness of about 100 nm. The metal is patterned by photolithography, development and etching (dry or wet) to form source and drain regions. This step is usually completed simultaneously with the patterning of the semiconductor layer to form an S / D mask. For a back channel structure, an opening is made in the source / drain region after lithography to facilitate subsequent metal contact. After completing the S / D pattern, a layer of silicon nitride, siloxane or organic polymer is deposited as a protective layer to prevent environmental moisture and oxygen from entering. Post-annealing (200-300°C) or UV-curing is performed to further reduce defects and improve device stability. Finally, photolithography, stripping and cleaning are performed to obtain a complete TFT structure.

[0032] For example, Figure 7As shown, the fifth embodiment of this application is a further improvement on the first or second embodiment described above. Unlike the fourth embodiment, the interval 330 is provided with a load control switch 332. The input terminal of the load control switch 332 is connected to the first electrode layer 311, the output terminal is connected to the second electrode layer 321, and the control terminal is connected to a temperature monitoring module 500. The temperature monitoring module 500 monitors the temperature in the clock signal trace area 210. When the temperature is greater than or equal to a preset temperature, the load control switch 332 is controlled to be in an open state, and the first electrode layer 311 and the second electrode layer 321 are not connected. When the temperature is less than the preset temperature, the load control switch 332 is controlled to be in a closed state, and the first electrode layer 311 and the second electrode layer 321 are connected.

[0033] In this embodiment, considering that a high refresh rate leads to a high frequency of the clock signal, which increases the heat generated by the clock signal traces, within the normal heat generation range, the corresponding temperature will not affect the clock signal on the clock signal traces. Therefore, there is no need to worry about the load problem caused by parasitic capacitance. On the contrary, parasitic capacitance can charge the electrodes and reduce the power loss of the device. Therefore, this embodiment sets up a temperature monitoring module 500 and a load control switch 332. The input terminal of the load control switch 332 is connected to the first electrode layer 311, the output terminal is connected to the second electrode layer 321, and the control terminal is connected to the temperature monitoring module 500. The temperature monitoring module 500 monitors the temperature in the clock signal area in real time, compares the monitored temperature with the preset temperature, and generates a control signal based on the comparison result to control the load control switch 332, thereby controlling the load control switch 332 to turn on or off, providing multiple possibilities for the display panel 100.

[0034] Generally, the threshold of the temperature control module can be adjusted according to different application scenarios, dynamically learning the optimal value. When the temperature rises slightly, the load intensity is reduced instead of being completely cut off, thus cooling the temperature without significantly impacting performance. By predicting temperature trends through historical data, measures can be taken in advance to achieve intelligent prediction. Based on adaptive algorithms, the threshold can be automatically adjusted according to environmental changes, improving overall efficiency. Multi-zone independent control may be suitable for large displays, with each zone monitored and managed separately, improving accuracy.

[0035] like Figure 8 As shown, as a sixth embodiment of this application, this application also discloses a driving method. The interval region is provided with a load control switch. The input terminal of the load control switch is connected to a first electrode layer, the output terminal is connected to a second electrode layer, and the control terminal is connected to a clock signal frequency monitoring module and a temperature monitoring module. The driving method is used to drive any of the display panels described above. The driving method includes the following steps: S1: monitoring the temperature in the clock signal wire area, when the temperature is greater than or equal to a first preset temperature, then controlling the load control switch to be in an off state, the first electrode layer and the second electrode layer are not connected; S2: when the temperature is less than the first preset temperature and greater than a second preset temperature, monitoring the frequency of the clock signal line in the clock signal wire area, when the frequency is greater than or equal to a preset frequency, then controlling the load control switch to be in an off state, the first electrode layer and the second electrode layer are not connected; S3: when the temperature is less than the preset temperature, then controlling the load control switch to be in an on state, the first electrode layer and the second electrode layer are connected; or, when the frequency is less than the preset frequency, then controlling the load control switch to be in an on state, the first electrode layer and the second electrode layer are connected.

[0036] In the present example, the control switch is arranged in the interval area, the control switch is connected with the clock signal frequency monitoring module and the temperature monitoring module respectively, and whether the first electrode layer and the second electrode layer are connected is controlled based on the monitored temperature and the frequency of the clock signal line. First, the temperature is monitored. Once the temperature is too high, the first electrode layer and the second electrode layer can be directly controlled to be not connected without monitoring the frequency of the clock signal line. If the temperature is within a certain range, the frequency of the clock signal line in the clock signal wire area is monitored to determine whether the first electrode layer and the second electrode layer are connected. Of course, separate execution is also possible, such as only monitoring the temperature, when the temperature is greater than or equal to a preset temperature, then controlling the load control switch to be in an off state, the first electrode layer and the second electrode layer are not connected, when the temperature is less than the preset temperature, then controlling the load control switch to be in an on state, the first electrode layer and the second electrode layer are connected, or only monitoring the frequency of the clock signal line in the clock signal wire area, when the frequency is greater than or equal to a preset frequency, then controlling the load control switch to be in an off state, the first electrode layer and the second electrode layer are not connected, when the frequency is less than the preset frequency, then controlling the load control switch to be in an on state, the first electrode layer and the second electrode layer are connected.

[0037] It should be noted that the inventive concept of the present application can form a very large number of embodiments, but the length of the application file is limited and cannot list them one by one, therefore, on the premise of not conflicting, the above described embodiments or technical features can be combined to form new embodiments, and the combination of each embodiment or technical feature will enhance the original technical effect.

[0038] The technical solution of the present application can be widely used in driving circuits of various display panels, such as driving circuits of TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, MVA (Multi-Domain Vertical Alignment) display panels, and of course, driving circuits of other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, all of which can be applied to the above solution.

[0039] The above is a further detailed description of the present application in combination with specific optional embodiments, and cannot be deemed to limit the specific implementation of the present application to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, some simple deductions or replacements can be made without departing from the concept of the present application, and all of which shall be deemed to fall within the protection scope of the present application.

Claims

1. A display panel comprising a first substrate and a second substrate disposed in a face-to-face arrangement, characterized by, The first substrate comprises a clock signal wire area, a gate drive circuit area and a display area, the second substrate comprises a first electrode area and a second electrode area, the first electrode area is provided with a first electrode layer, the second electrode area is provided with a second electrode layer, and the projection area of the first electrode area is smaller than the sum of the areas of the clock signal wire area and the gate drive circuit area in the direction of the second substrate towards the first substrate, and the projection area of the second electrode area is greater than or equal to the display area. The first electrode area and the second electrode area are provided with a spacing area, and the first electrode layer and the second electrode layer are spaced apart by the spacing area.

2. The display panel of claim 1, wherein, The spacing area comprises a hollow part, the hollow part is arranged on the second substrate in a hollow manner, and the hollow part is cut by laser during the preparation of the mother board of the display panel, and the length of the hollow part in the direction of the first electrode area towards the second electrode area is A, wherein A=50um+C1+D1 / 2, C1 is the accuracy of the cutting position, and D1 is the accuracy of the cutting equipment.

3. The display panel of claim 1 or 2, wherein, The first electrode layer comprises at least two spaced first electrodes, the two first electrodes are not connected to each other, the clock signal wire area and the gate drive circuit area are spaced apart, and the projection of the clock signal wire area covers the first electrode and the projection of the gate drive circuit area covers the second electrode in the direction of the second substrate towards the first substrate.

4. The display panel of claim 1, wherein, The spacing area is provided with a load control switch, the input end of the load control switch is connected to the first electrode layer, the output end is connected to the second electrode layer, the control end is connected to the clock signal frequency monitoring module, the clock signal frequency monitoring module monitors the frequency of the clock signal line in the clock signal wire area, when the frequency is greater than or equal to the preset frequency, the load control switch is controlled to be in the off state, and the first electrode layer and the second electrode layer are not connected, when the frequency is less than the preset frequency, the load control switch is controlled to be in the on state, and the first electrode layer and the second electrode layer are connected.

5. The display panel of claim 1, wherein, The spacing area is provided with a load control switch, the input end of the load control switch is connected to the first electrode layer, the output end is connected to the second electrode layer, the control end is connected to the temperature monitoring module, the temperature monitoring module monitors the temperature in the clock signal wire area, when the temperature is greater than or equal to the preset temperature, the load control switch is controlled to be in the off state, and the first electrode layer and the second electrode layer are not connected, when the temperature is less than the preset temperature, the load control switch is controlled to be in the on state, and the first electrode layer and the second electrode layer are connected.

6. The display panel of claim 4 or 5, wherein, The first substrate and the second substrate are provided with a liquid crystal layer, the liquid crystal layer comprises a first liquid crystal layer and a second liquid crystal layer, the first liquid crystal layer is arranged between the clock signal wire area, the gate drive circuit area and the first electrode area, and the second liquid crystal layer is arranged between the display area and the second electrode area. The liquid crystal in the first liquid crystal layer and the liquid crystal in the second liquid crystal layer are formed by using the same liquid crystal material, and the density of the liquid crystal in the first liquid crystal layer is greater than the density of the liquid crystal in the second liquid crystal layer.

7. The display panel of claim 3, wherein, The first electrode layer comprises two first electrodes arranged at intervals, the two first electrodes are not communicated with each other, and the two electrodes are respectively a clock trace electrode and a gate circuit electrode, the clock trace electrode corresponds to the clock signal trace area, and the gate circuit electrode corresponds to the gate drive circuit area. The first substrate and the second substrate are provided with a liquid crystal layer, the liquid crystal layer comprises a first liquid crystal layer and a second liquid crystal layer, the first liquid crystal layer is arranged between the gate drive circuit area and the gate circuit electrode, and the second liquid crystal layer is arranged between the display area and the second electrode.

8. The display panel of claim 7, wherein, The clock signal trace area and the gate drive circuit area are provided with a frame glue, one end of the frame glue is arranged between the clock trace electrode and the gate circuit electrode and is attached to the second substrate, and the other end of the frame glue is arranged between the clock signal trace area and the gate drive circuit area and is attached to the first substrate. The thickness of the first electrode layer is less than the thickness of the second electrode layer, and the electrodes in the first electrode layer and the electrodes in the second electrode layer are formed by indium tin oxide.

9. The display panel of claim 8, wherein, The frame glue comprises a frame glue body and a spacing column filled in the frame glue body, the frame glue body is formed by mixing an acrylic / epoxy resin matrix, a light / heat curing agent, conductive particles, oxygen / water vapor resistance additives and the like, and the spacing column is formed by mixing an acrylic / epoxy resin, a photoinitiator, an active monomer, a leveling agent and an organic solvent.

10. A driving method for driving the display panel according to any one of claims 1 to 9, characterized by, The spacing area is provided with a load control switch, an input end of the load control switch is connected to the first electrode layer, an output end is connected to the second electrode layer, and a control end is connected to a clock signal frequency monitoring module or a temperature monitoring module, and the driving method comprises the steps of: Monitoring the temperature in the clock signal trace area, when the temperature is greater than or equal to a first preset temperature, the load control switch is controlled to be in an off state, and the first electrode layer and the second electrode layer are not communicated; When the temperature is less than the first preset temperature and greater than a second preset temperature, the frequency of the clock signal line in the clock signal trace area is monitored, when the frequency is greater than or equal to a preset frequency, the load control switch is controlled to be in an off state, and the first electrode layer and the second electrode layer are not communicated; When the temperature is less than the preset temperature, the load control switch is controlled to be in a conductive state, and the first electrode layer and the second electrode layer are communicated; or when the frequency is less than the preset frequency, the load control switch is controlled to be in a conductive state, and the first electrode layer and the second electrode layer are communicated.

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