Decimal bit weight amplitude weight quantizer and quantization method of ten-value logic

Abstract

According to the bit weight amplitude weight quantizer and the quantization discretization method, the maximum amplitude of input continuous simulation information is discretely divided into a plurality of amplitude paragraphs of a content interval GS, the amplitude paragraphs are associated with a carry system, the amplitude of the input continuous simulation information is discretely divided into a plurality of paragraphs through a number of carry systems, and the amplitude of the input continuous simulation information is divided into a plurality of paragraphs. If a decimal system exists, the amplitude of the continuous analog information is discretized into ten paragraphs, the discretized paragraphs are converted into thermometer coding information through a comparator, and then the thermometer coding information is converted into bit weight information through XOR and XNOR logical operation; the value of the bit weight in the bit weight information is generated by comparing the binary states 0 and 1 on the node, one state on the unique node is compared with different states on other nodes to indicate that the node has the weight, and the position number of the node with the weight is used for indicating the bit weight of all the nodes in the bracket.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of computer hardware, and particularly relates to an information conversion device, a ten-value decimal bit weight and amplitude weight quantizer. TECHNICAL BACKGROUND

[0002] Currently, computers are binary multi-bit computers. The binary two-bit computing system cannot meet the computing needs of people due to the excessively short data unit. In order to maintain the binary attribute of a single node (one bit) and express more data, the number of bits in the horizontal direction must be expanded, such as 8 bits, 16 bits, 32 bits, 64 bits, etc. This results in a sharp increase in the connection lines of the binary computer circuit (too many bits), which not only increases the complexity of the circuit, but also dramatically increases the production cost.

[0003] A multi-value computer is a multi-value multi-bit computer that is obtained by expanding the weight bits in the vertical direction on the basis of expanding the bits in the horizontal direction. From a biological perspective, the binary multi-bit computing system is difficult to distinguish, recognize, remember, express, communicate, judge and calculate, and is not suitable for the intellectual needs of intelligent beings. On the contrary, the multi-value multi-bit computing system is more conducive to the memory, counting, distinguishing, recognition, expression, communication, judgment and calculation of intelligent beings. Therefore, the development of the multi-value multi-bit computing system meets the intellectual needs of intelligent beings and conforms to the characteristics and methods of intelligent thinking.

[0004] The present application uses the "quantization logic" thought, adopts the "quantization discrete queue" and "space domain or" and "space domain and" operation methods, realizes the circuit structure of the "bit weight quantizer" and "amplitude weight quantizer", and lays a foundation for decimal array numerical operation and decimal quantization numerical operation, and makes a contribution to the further realization of the "decimal digital computer", "decimal analog computer" and standardized operation scheme. SUMMARY

[0005] Reasons for quantizing information

[0006] Analog information is continuous dynamic information, and logical information is discontinuous static information. In order to perform logical operation on analog information, it is necessary to convert the continuous dynamic analog information into discontinuous static logical information. This method of converting continuous dynamic analog information into discontinuous static logical information is called "quantization". The function of realizing the conversion from dynamic to static is "comparison". Therefore, "comparison quantization" is the primary method of converting analog information into logical information. "Quantization logic" is a thought logic theory that first quantizes analog information and then performs logical operation, or first performs continuous logical operation and then performs digital "quantization".

[0007] "Quantization logic" is a logic theory that specially studies the effect of "quantization interval" or "fault-tolerant interval" or "quantization merging area" in the process of logical operation, mainly involving two kinds of logical ideas generated by two kinds of thinking methods of "boundary quantization" and "identification quantization" (boundary quantization generates binary information, and identification quantization generates unique information), and integrating the thinking logic theory of "boundary quantization", "identification quantization" and "weight multi-value digital quantization".

[0008] The first step of the practical operation of quantization logic is to use the comparison method to divide the continuous chaotic and fuzzy information into a "spatially distributed discrete queue" by "boundary segmentation" method. A discrete queue contains multiple "independent elements", which are expressed by "spatial nodes" in the real circuit. Therefore, "an ordered queue composed of spatial nodes" can represent a multi-value logic value by a combination state. The combination rule of this spatial state is one-to-one corresponding to the "weight number" by using "sparse" "one-hot encoding" method, generating a true "digital logic".

[0009] The two kinds of logical operations of quantization logic are "space domain or" and "space domain combination".

[0010] Space domain or: The "temperature meter code" of the discrete spatial information is converted into a logical operation method related to "bit weight information" of spatial position by using the "XOR" or "XNOR" logical operation of spatial adjacency. The "bit weight information" uses multiple binary nodes in space to represent the representation method of multi-value logic information. When the multi-value logic value is expressed by multiple binary logic node information, the multi-value logic value can also be operated and stored as a multiple digital number by using the same logical operation as binary logic.

[0011] Space domain combination: The "temperature meter code" of the discrete spatial information is converted into a logical operation method related to "amplitude weight information" with ladder properties by using the "stacking" operation of spatial stacking to perform arithmetic accumulation. "Amplitude weight information" is a representation method of multi-value logic information using amplitude ladder. When the multi-value logic value is expressed by a ladder amplitude, it is consistent with the human thinking method, and it is also the definition of standard multi-value logic value. Using this ladder type amplitude for logical operation, storage and numerical operation will be the common goal of multi-value logic researchers.

[0012] Basic information used by the decimal calculation system

[0013] The reason why the numerical operation of contemporary binary logic is so reliable is that people use the "logical operation method" of binary logic to operate the numerical value, so as to obtain reliable operation results.

[0014] Can we use reliable "logical operation" method for decimal and multi-base numerical operation, this is also many designers thinking problem.

[0015] Contemporary logician research "multi-value logic" is actually all with a node on multiple amplitude value of "multi-value logic" expressed. Quantization logic in the method is called "amplitude information". "Amplitude information" is single node multi-weight value logic information, but the information in the logic and numerical operation will produce difficulties.

[0016] "bit weight information", there is no such information before, so the quantization logic definition: "bit weight information" is multi-node single weight information, and "amplitude information" corresponding. The reason to use bit weight information is to use "bit weight information" can realize the same multi-value logic operation and multi-value logic operation method to realize the multi-base numerical operation, which makes the realization of decimal numerical operation can use "bit weight information" of the logic operation method to get reliable numerical operation result.

[0017] Must be clear: "bit weight information" is multi-node single weight information, "amplitude information" is single node multi-weight information.

[0018] "quantization logic" at present the design mainly around the "decimal computer" composition design, the main components are "quantizer", "register", "controller", "operation unit" these four types of different design of the original element.

[0019] I: the basic information definition of quantization logic

[0020] Binary binary is the smallest unit of information, decimal is the most commonly used computing system, to change binary into ten values need at least four storage bits to ensure complete expression of ten logic values (binary code). There is another way to express method is to use ten storage bits to represent ten logic values (hot shift register coding), which needs hot coding (translation), the general "hot coding" can effectively execute decimal numerical operation, so the real decimal computer uses "hot shift register" information of the variant information "bit weight information" and "amplitude information" to carry on the calculation.

[0021] In quantization logic, "bit weight information" and "amplitude information" and "thermometer information" are the main running information, these information always need to transform each other. Bit weight information, amplitude information and thermometer code are all from the integration output of space multi-node binary state information, which is a group of node binary state and amplitude information value group to express multiple logic value "quantization logic" information.

[0022] 1: thermometer code

[0023] A group of multiple binary nodes in a spatial domain, where the number of consecutive "1" states represents the logical value, is called a "thermometer code". Thermometer code is simply a stack of consecutive "1"s.

[0024] Thermometer code LED display as follows Figure 1 As shown

[0025]

[0026] A comparator is a circuit that converts analog information into binary information. Multiple voltage divider (quantization) comparators are circuits that convert analog information into "thermometer code". The block diagram of the analog-to-thermometer code conversion circuit is shown below. Figure 2 As shown.

[0027] "Thermometer information" has a wide range of applications in audio signal display and analog information display.

[0028] 2: Various methods of representing positional information:

[0029] In binary logic systems, the expression of multi-valued logic (three-valued, four-valued, eight-valued, ten-valued, sixteen-valued, etc.) is achieved by using the position number of the "valid" node in a group of multiple binary nodes to represent the logical value of that group. Examples include the output of an eight-valued decoder, the output of a ten-valued decoder, and the output of a sixteen-valued decoder. The understanding that one node represents one decimal digit and multiple decimal digits are represented by multiple nodes is natural; in fact, the "position weight" information we refer to is this natural method of "decimal" representation.

[0030] Positional weight information is "weight" information. "Weight" is a method of representing multi-valued information using a set of spatial binary nodes. In the permutation, the output of each individual node is a binary state A. x or A x For "effective" output, For "invalid" output, it is the only "valid output state A" in a group of spatial nodes. p The spatial position of a node group is what represents its weight. In a node group, only one node outputs a valid state, and R-1 nodes output invalid states. Let's consider a valid node A... p and R-1 invalid nodes Together they express the logical weights at this moment {A} p} R This logical expression is called "position weight expression information". Therefore, "position weight information" is node group information, which is a method of expressing a position weight value by "forming a group" of multiple spatial nodes.

[0031] The LED display and circuit node representation method of "positional information" is as follows: Figure 3 As shown.

[0032]

[0033] ({A x} R Let A be the "state weight" and A be the binary high state. (For binary low-level states, x represents multi-valued weights, and R represents the positional notation) Various methods for expressing multi-valued "positional weight information":

[0034] From another perspective, "positional information" is a method of expressing one-bit multi-ary information using multi-bit binary information.

[0035] ① A method of representing decimal information using "one-hot encoding"

[0036] (1000000000)2 9 The superscript 9 indicates that the 9+1th position from the right is 1, which is equivalent to the decimal number 9.

[0037] (0100000000)2 8 The superscript 8 indicates that the 8+1th position from the right is 1, which is equivalent to the decimal number 8.

[0038] (0010000000)2 7 The superscript 7 indicates that the 7+1th position from the right is 1, which is equivalent to the decimal number 7.

[0039] (0001000000)2 6 The superscript 6 indicates that the 6+1th position from the right is 1, which is equivalent to the decimal number 6.

[0040] (0000100000)2 5 The superscript 5 indicates that the 5+1th position from the right is 1, which is equivalent to the decimal number 5.

[0041] (0000010000)2 4 The superscript 4 indicates that the 4+1th position from the right is 1, which is equivalent to decimal 4.

[0042] (0000001000)2 3 The superscript 3 indicates that the 3+1th position from the right is 1, which is equivalent to the decimal number 3.

[0043] (0000000100)2 2 The superscript 2 indicates that the 2+1th position from the right is 1, which is equal to 2 in decimal.

[0044] (0000000010)2 1The superscript 1 indicates that the position 1+1 from the right is 1, which is equal to 1 in decimal.

[0045] (0000000001)2 0 The superscript 0 indicates that the (0+1)th position from the right is 1, which is equivalent to decimal 0.

[0046] This method of representation requires counting the position of the 1 to know that it represents a decimal digit. It is not intuitive to see what number it represents.

[0047] ② Methods of expressing "state and weight" information

[0048] "State weight" is a more direct way of expressing "position weight information".

[0049] The evolution of the "state-power" relationship:

[0050]

[0051]

[0052]

[0053] Therefore, positional information = one-hot code + numerical weight + cyclic limit (common representation)

[0054]

[0055] (One-hot encoding, also known as one-bit valid encoding, uses an N-bit state register to encode N states. Each state has its own independent register bit, and at any given time, only one bit is valid.)

[0056] (Numerical weight: Natural numbers from 0 to 9 have different values ​​because each number is located in a different spatial position. The different values ​​formed by different spatial positions are called numerical weights.)

[0057] (Cyclic limit: The restriction on the highest position in the counting process. When the count reaches the highest position, the counting starts again from the lowest position. This cyclic limit eventually evolved into a positional number system.)

[0058] This method of expression is very direct; the weights are immediately apparent. The three expressions for "unique value" and "state weight" are explained below:

[0059] "Unique value": A value that is completely independent of each other, with neither continuous nor cyclic attributes.

[0060] {5}10 The base 5 represents the numerical weight. The absence of a mark above 5 indicates a high binary state (omitted). The subscript outside the parentheses indicates the positional numeral system.

[0061] The symbol {A5}10 indicates a binary state, and A represents a high state. The subscript 5 indicates a low state, the subscript 5 indicates a numerical weight, and the subscript outside the parentheses indicates the positional numeral system.

[0062] A single value represents one of ten decimal values, such as {A5}10 indicating convex activation. This indicates a concave activation. A unique value means that only one of the ten decimal values ​​is active, while the other values ​​exist but are not activated. Here, "unique value" is a unique comparison of the states of ten "discrete" counting symbols, while "full value" is an expression of the unique values ​​of the ten counting symbols traversing the ten counting nodes under the action of a clock. The expression methods of "magnitude weight" and "position weight" are very similar.

[0063] As shown below:

[0064]

[0065] so: Represents the full value positional information, {5} 10 {A5} 10 This represents unique bit weight information.

[0066] ③ The "dynamic" and "static" expression of positional information:

[0067] Multi-valued positional information can be expressed in "static" and "dynamic" ways. "Static" means the node number in the network structure; "dynamic" means the comparison of two states on the "static" node number.

[0068] Static representation of position weight information:

[0069] A static representation is simply a static weight sequence; it's a spatial identifier or sequence number for nodes, lines, endpoints, positions, inputs, and outputs. Representations with only "weights" and no "state values" are considered static. For example:

[0070] A x = (a0, a1, a2, ... a R-1 B x = (b0, b1, b2, ... b R-1 (Static representation)

[0071] Or represented as: |0 1 2 3 4 5 6 7 8 9| 10

[0072] This multi-valued representation is an effective descriptive method for layout design.

[0073] Dynamic representation of position weight information:

[0074] Dynamic representation is a method of adding binary states to static representation sequences to indicate activation. It uses the relative comparison of "binary states" in a spatial multi-node group to represent "weights", which is the "state-weight" representation method.

[0075] Character representation:

[0076]

[0077] a0, a1, a2, ...a n Indicates the static distribution number. This is a binary state comparison expression for nodes. In this formula, only a2 is a high state, and the others... Both are in a low state, so the position weight information is the value of 2 in a2; where R is the positional system, a is the position weight state value, the subscript indicates the position weight value, and the parentheses indicate that the position weight information must be expressed by a set of node sequences.

[0078] The practical significance of the concept of "state power":

[0079] Adding logical markers above numbers indicates which binary state the number is in. The presence or absence of an "isolated" state marker above a number determines which of ten numbers the "weight" is. This representation is called "state-weight" representation, where "state" refers to the logical state above the number, and "weight" refers to the position number marked by the isolated state.

[0080]

[0081]

[0082] This is similar to the meaning conveyed by elevator buttons. An illuminated elevator light indicates the start of an operational command, and the specific destination is indicated by the number on the illuminated button. A horizontal bar above the number indicates the button is not pressed and the light is off; no bar indicates the button is pressed and the light is on, indicating a command. The numerical weight on the button moves the elevator car to the location specified by the button number. This is a typical "state-weight" structure. The presence or absence of an illuminated light on a number represents the "state value," the number itself represents the "weight," and the subscript outside the parentheses indicates the "positional unit." This is a typical example of using the brightness of the light to represent the "state value" and the number to represent the weight execution number, expressing the "state-weight" relationship. Having a state without weight has no computational meaning, while having weight without state only reflects a spatial distribution.

[0083] Three-valued logic characteristics of three "one-hot" codes

[0084] The representation of position weight information as "state weight" can be separated into two layers: a state code ("one-hot code") and a counting weight number. This is referred to as "state weight separation" in the previous patent application. After "state weight" separation, the "state value" is transformed into a "one-hot code," and the weight value is transformed into a pure numerical number.

[0085] State: |0 0 0 0 0 0 1 0 0 0| 10 = One-hot code (three-value code with protrusion)

[0086] Weights: |0 1 2 3 4 5 6 7 8 9| 10 = Numerical weight (ten-value digit)

[0087] State: |1 1 1 1 1 1 0 1 1 1| 10 =One-cold code (three-value code with a recessed designation)

[0088] Weights: |0 1 2 3 4 5 6 7 8 9| 10 = Numerical weight (ten-value digit)

[0089] "One-hot code" is a "three-valued logic information code" edited from multiple binary logic state nodes in space. The term "one-hot encoding" already illustrates the fact of this encoding transformation.

[0090] The decimal digit is the one-hot position number of the one-hot encoding of a binary state. Operations on the decimal digit are actually operations on the one-hot encoding of the binary state. This "state-weight relationship" establishes a "dependency" relationship between the decimal digit and the binary state, making the decimal digit, which is only used for counting, logical and operable. This also lays a solid foundation for realizing a "decimal computer." It also demonstrates that decimal digits are one-hot encodings of binary states, a continuation, extension, and supplement to binary logic.

[0091] Numbers are the distribution sequence encodings of spatial nodes. Thermometer codes, one-hot codes, and ternary logic are all expressions of the binary state distribution rules of spatial nodes. These types of information are all related to spatial location, so they can be linked together through spatial location. First, numbers best express spatial location. Numbers are the numbers representing the distribution sequence of spatial nodes. The following is an example of using numbers to represent spatial location and map the state values ​​of each node in thermometer codes, one-hot codes, and ternary logic:

[0092] Spatial location numerical code mapping --- thermometer code ---- unique thermal code ---- three-valued logic (note the bottom-up order)

[0093]

[0094]

[0095] If we use a combination of logical state symbols (characters without a hyphen at the top indicate a "high" state, and characters with a hyphen at the top indicate a "low" state) and ten-value digits to replace thermometer codes, unique thermal codes, and ternary representations, this method of representation is called "state-weighted" representation. The results are listed below (note the order from bottom to top).

[0096]

[0097] It can be seen that each spatial location node has two "high" and "low" states, but can have any "weight" position number; the two "high" and "low" states are binary logic attributes, but multiple spatial nodes with binary states can form a three-valued logic with "three states"; "one-hot encoding" is a typical "three-valued logic one-hot code" composed of binary logic state nodes. Since the essence of one-hot code is the position number of a unique "high" state node in a group of spatial nodes, it is expressed together with numbers as "position weight information", which is convenient to correspond with another information "magnitude weight information".

[0098] In fact, this kind of "dependent" expression of numbers and binary logic codes was clearly explained to us by ancient Chinese sages in the form of the "Luoshu" and the "Nine Palaces Diagram." These ancient sages used diagrams to express the interrelationships and mutual explanations between "space," "position," "state," and "number," illustrating the relationships between binary and ternary logic codes and their transformations. The ancients did not use "coding" for information transformation and textual expression; they could only use visual diagrams to guide these information transformation relationships.

[0099] This type of state weight encoding is called decimal "position weight information". Other positional information encoded using this method is called multi-valued "position weight information".

[0100] The essence and application of four-dimensional one-hot encoding

[0101] The "one-hot encoding" method is ubiquitous in binary logic circuits, such as the input circuit in binary logic operations, where the binary state A at a node is represented by two nodes A1 and A2. This indicates that, regardless of whether the two nodes represent "positive" or "negative", a 1 indicates validity and a 0 indicates invalidity. A 1 for the "positive A" node indicates that the "positive A" in that node is valid; a 0 for the "positive A" node indicates that the "positive A" in that node is invalid. "Negative" When the node output is 1, it indicates that the "reverse" is... The node's "reverse" Effective, "anti" When a node outputs 0, it indicates that the "reverse" is... The node's "reverse" Invalid. Here, "valid 1" and "invalid 0" can be understood as "works" and "does not work", and this "0" and "1" are not symmetrical in a set of node expressions, which is the "one-hot code" expression.

[0102] A = (10)2, This is the binary "one-hot encoding" representation. The connection method for binary "one-hot encoding" is shown in the attached diagram in the manual. Figure 4 This is a typical method and expression of "three-valued logic connection" for "binary logic binary".

[0103] The widespread application of binary one-hot encoding demonstrates that "weighting" one-hot encoding greatly enriches its applications. One-hot encoding expresses a much richer and more comprehensive range of content than ordinary binary representations. Using one-hot encoded inputs in binary logic circuits will completely and comprehensively improve the combination, encoding, and connection characteristics of logic operations. It can provide all the necessary connection nodes for logic compilation. Furthermore, it should be noted that all logical relationships expressed using one-hot encoding are essentially three-valued or higher-valued logic, especially binary one-hot encoding. For example, the binary one-hot encoding expression mentioned above is binary logic expressed using three-valued logic. Figure 4 This connection method is the three-valued representation method of binary logic.

[0104] V. Position Weight Quantizer

[0105] The conversion circuit that converts analog information into "position weight information" is called a "position weight quantizer". One conversion method of the "position weight quantizer" is the voltage divider-compare-XOR method, which takes the "thermometer code" output by the voltage divider-compare method and performs XOR or XOR logic operations to obtain the "position weight information", or "position weight value". The position weight information output by the position weight quantizer is actually the output information of the "traversal operation" in the "quantization logic".

[0106] The flowchart illustrating the structure and principle of the "position weight quantizer" is shown in the attached diagram in the instruction manual. Figure 5

[0107] For simulated information u i Voltage divided by n reference nodes J n Discrete and segmented. The output S of each comparator B in the queue is determined by the following formula:

[0108] S n =u i / J n When u i <J n Time S n =0, when u i >J n Time S n =1. (positive phase)

[0109] S n =u i / J n When u i <J n Time S n =1, when u i >J n Time S n =0. (Inverted)

[0110] J n It is the reference node voltage, where n is 1 to 9 (ten values).

[0111] The "thermometer code" is obtained by comparing data using a comparator queue:

[0112]

[0113] Perform a "spatial domain adjacency XOR (XNOR) operation on the "thermometer code" and output it in parallel" (spatial domain parallel OR).

[0114]

[0115] Obtain positional weight information (unique value)

[0116]

[0117] This kind of "positional information" can then perform "ten-value logic operations" and "decimal numerical logic operations".

[0118] The position weight quantizer is compatible with the "amplitude-position weight transformer", so there is no dedicated "amplitude-position weight transformer".

[0119] Six: Image Weighting Information

[0120] A quantization and arrangement method for outputting "pulse amplitude" values ​​of analog information. This method uses multiple amplitude values ​​on a single node to represent multiple logic values. LED display instructions for "amplitude weighting information" are attached to the manual. Figure 6 .

[0121] 1: "Aspect weight information expression:"

[0122] Static representation and dynamic representation; static representation is "quantization interval G". S The product of the product and the natural number x; the dynamic representation uses binary logic states to represent the amplitude weights, also known as the state weight method, as follows:

[0123] When F0 = 0G S F1 = 1G S F2 = 2G S F3 = 3G S …

[0124] F x G represents the amplitude weight. S This represents the quantization interval value with R-1 as the quantization level, where R is the positional unit.

[0125] Amplitude weighting information can be analog information or "amplitude step information".

[0126] The logical expressions for magnitude weighting information and position weighting information are the same: for example, unique magnitude weighting is written as:

[0127]

[0128] However, the amplitude weight F in the amplitude weight information x It is a function F x =G S x can also be written as:

[0129] {F x} 10 =G S {x} 10

[0130] Therefore, the amplitude weight is equal to the "quantization interval" multiplied by the position weight. S The unit is volt, and the place value is just a purely logical number.

[0131] 2: Amplitude Weight Quantizer

[0132] The conversion circuit that transforms analog information into "amplitude weighting information" is called an "amplitude weighting quantizer." The amplitude weighting quantizer first discretizes the analog information into independent "thermometer code" outputs using a comparator queue. Then, it arithmetically accumulates the identical states of the "thermometer" outputs using the binary states of each independent "thermometer code" output, obtaining "amplitude weight" information with a step-like attribute, called "amplitude weighting information." The logic block diagram and information flow of the amplitude weighting quantizer are shown in the attached diagram in the instruction manual. Figure 7 As shown.

[0133] For simulated information u i Voltage divided by n reference nodes J n Discrete and segmented. The output S of each comparator B in the queue is determined by the following formula:

[0134] S n =u i / J n When u i <J n Time S n =0, when u i >J n Time S n =1. (positive phase)

[0135] S n=u i / J n When u i <J n Time S n =1, when u i >J n Time S n =0. (Inverted)

[0136] J n It is the reference node voltage, where n is 1 to 9 (ten values).

[0137] Obtain the "thermometer code":

[0138]

[0139] The logical information S of the "thermometer code" x The generated current is used as the unit. Arithmetic summation is performed on logic units in the same state within the "thermometer code" to obtain the value x. Then, x is summed with the "quantization interval" G. S The amplitude voltage value F obtained by multiplying the two is... x F x =xG S x = 0, 1, 2, ..., 9

[0140] F x This is the "weighting information". This "weighting information" is "numerical logic" information, or "digital logic" information, which can perform "ten-value logic operations", "continuous logic operations", and "decimal numerical logic operations".

[0141] 7: Position weight, magnitude weight, complementary, loop, and traversal information

[0142] Positional change information

[0143] In multi-valued logic, the logical NOT operator is defined as follows: Here, the minus sign represents arithmetic subtraction (R is the positional radix). The meaning of "logical NOT" is binary; negating "multi-valued logical information" is actually performing a binary inversion operation on the multi-valued logical information. This is essentially a "mixed operation of binary and multi-valued logic." Therefore, the complement of decimal positional information is simply the reversal of the spatial order of the positional values. For example, the decimal "unique hot" state information (◇◇◇◇◇◇1◇◇◇). 10 After the spatial distribution is reversed, it becomes (◇◇◇1◇◇◇◇◇◇) 10 ;

[0144] Such as positional information:

[0145]

[0146] After the complement operation, we get:

[0147]

[0148] This represents a reversal of the spatial arrangement order, conforming to the definition of a non-operator. (See patent application 2017)

[0149] Range weight change information

[0150] Performing operations such as complementing and inverting on multi-valued and ten-valued logical information is actually performing "binary complementing or inverting" operations on ten-valued and multi-valued information. Any binary complementing or inverting of ten-valued and multi-valued logical information is a reversal of "temporal order" and "spatial order". This is because "inverting and complementing" is only "performing binary inversion and complementing operations on multi-valued information", and there are no other logical options with more than two values.

[0151] The "amplitude weight full value complement" information represents the positive and negative loop logic in multi-valued logic, denoted as X. → and X ← There is a positive cycle in terms of "amplitude weight".

[0152]

[0153] and anti-loop

[0154] Positive and negative loops are complementary information of full magnitude weight (decimal).

[0155] It should be noted that this cycle is not necessarily a naturally ordered cycle; it also includes a large number of "unnatural cycles," such as:

[0156]

[0157] and complementary cycles

[0158] This is a return symbol, indicating that the loop returns to the initial value. A circuit that continues to loop after returning to the initial value in a multi-valued loop is called a "multi-valued oscillator," and its oscillation frequency and period are related to the loop.

[0159] The method to achieve these "unnatural cycles" is to connect and edit the "position weight" and "amplitude weight".

[0160] Position weight complement

[0161] Positional complement transformation first determines the "order" direction, then determines the positive or negative according to the "traversal logic direction". Positional complement transformation is "space traversal from left to right X". → "and "right-hand traversal of space X" ←"A positional complement is a spatial 'order' transformation representing positional information, converting it from sequential to inverse order. Or, the order can be from left to right, etc. 'Positional complement' is essentially a reversal of the original arrangement's 'order.' The order direction (left to right or right to left) is primarily determined by the direction of change in the input analog information. Then, referring to the direction of change in the analog information, increasing from small to large is considered positive, and decreasing from large to small is considered negative. (See patent application 2017)"

[0162] Amplitude weighting complement

[0163] An amplitude weighting complement is a logic device that transforms the positive loop logic representing amplitude weight information into a negative loop logic device. (See patent application 2017)

[0164] Loops and traversals

[0165] Looping and traversal are special ways of expressing multi-valued logic. Since multi-valued logic has multiple logical values ​​on a node, and a node can only represent one of the multiple logical values ​​at a specific time, in order to display all the logical values ​​in the multiple values ​​on the node, the only way is to use the loop method to express multiple values ​​one by one in time. This way of running logic is called "looping" expression.

[0166] Similarly, the method of representing multiple values ​​using the binary states of multiple spatial nodes is also a way of expressing multi-valued logic. Therefore, in order to represent each logical value in a multi-valued system in a time-sharing manner, it is necessary to traverse each node in a time-sharing manner to express all the logical values ​​in the multi-valued system. So this way of traversing nodes is called multi-valued "traversal" expression.

[0167] Looping and traversal are periodic representations in multi-valued logic operation methods. The order of loops and traversals does not necessarily have to follow a fixed procedure; they can also be generated randomly without fixed rules. This allows for the acquisition of a "wave source information generation system" with many waveforms, which is beneficial for testing or simulating and approximating naturally collected information, serving as an information model module for identification and control. It can also be used as a control cycle to generate a pre-set control scheme and form a minimum control cycle.

[0168] When the loop and traversal run repeatedly, regardless of the order experienced, it can be regarded as a "multi-valued oscillator". The oscillator frequency is the repetition frequency of the loop traversal, the period is the loop traversal period, and the amplitude is the "amplitude weight" experienced by the loop traversal.

[0169] 8. Methods for converting between different types of information

[0170]

[0171] Thermometer codes, bit weight information, amplitude weight information, analog information, and binary information can be converted using specific logic devices such as bit weight quantizers, amplitude weight quantizers, comparators, encoders, decoders, and XOR / XOR circuits.

[0172] 9. The formation process of actual "position weighting information" and "amplitude weighting information" based on the actual circuit structure is shown in the attached diagram of the instruction manual. Figure 8 As shown.

[0173] 10: The "quantization discretization" method for multi-valued logic and the composition of multi-valued "bit weight" and "amplitude weight" quantizer circuits.

[0174] 1: Comparator Discrete Queue Circuit

[0175] The forward / reverse comparison structure is determined by the output voltage of the comparator's output node. The inverting input of the comparator is used as the reference input, and the non-inverting input is used as the analog voltage input. When the input voltage is greater than the reference voltage, the comparator outputs a high level; when the input voltage is less than the reference voltage, the comparator outputs a low level. This connection method is called a forward comparator queue. The reverse comparator queue uses the non-inverting input as the reference voltage input and the inverting input as the analog voltage input. When the input voltage is greater than the reference voltage, the comparator outputs a low level; when the input voltage is less than the reference voltage, the comparator outputs a high level. This connection method is called an inverting comparator queue. (See attached manual.) Figure 9 As shown.

[0176] Reverse thermometer code generation process:

[0177] S1=u i / x1 when u i When x is less than x1, S1 = 1; when u i When x is greater than x1, S1 = 0.

[0178] S2=u i / x2 when u i When x is less than x2, S2 = 1; when u i When x is greater than x2, S2 = 0.

[0179] S3=u i / x3 when u i When x is less than x3, S3 = 1; when u i When the value is greater than x3, S3 = 0.

[0180] S4 = u i / x4 when u i When x is less than x4, S4 = 1; when u i When the value is greater than x4, S4 = 0.

[0181] S5=u i / x5 when u i When x5 is less than x5, S5 = 1; when ui When the value is greater than x5, S5 = 0.

[0182] S6=u i / x6 when u i When x is less than x6, S6 = 1; when u i When the value is greater than x6, S6 = 0.

[0183] S7=u i / x7dangu i When x7 is less than x7, S7 = 1; when u i When the value is greater than x7, S7 = 0.

[0184] S8=u i / x8dangu i When x is less than x8, S8 = 1; when u i When the value is greater than x8, S8 = 0.

[0185] S9=u i / x9 when u i When x is less than x9, S9 = 1; when u i When the value is greater than x9, S9 = 0. Table of correspondence between reverse thermometer code, input voltage, and voltage divider node:

[0186] Reverse comparator queue

[0187]

[0188] Forward comparator queue circuit: (Instruction manual attached) Figure 10 As shown.

[0189] Forward comparator thermometer code generation process

[0190] S1=u i / x1 when u i When x1 is less than x1, S1 = 0; when u i When x is greater than x1, S1 = 1.

[0191] S2=u i / x2 when u i When x is less than x2, S2 = 0; when u i When x is greater than x2, S2 = 1.

[0192] S3=u i / x3 when u i When x is less than x3, S3 = 0; when u i When the value is greater than x3, S3 = 1.

[0193] S4 = u i / x4 when u i When x is less than x4, S4 = 0; when u i When the value is greater than x4, S4 = 1.

[0194] S5=u i / x5 when u i When x5 is less than x5, S5 = 0; when u i When the value is greater than x5, S5 = 1.

[0195] S6=u i / x6 when u i When x is less than x6, S6 = 0; when u i When the value is greater than x6, S6 = 1.

[0196] S7=u i / x7dangu i When x7 is less than x7, S7 = 0; when u i When the value is greater than x7, S7 = 1.

[0197] S8=u i / x8dangu i When x is less than x8, S8 = 0; when u i When the value is greater than x8, S8 = 1.

[0198] S9=u i / x9 when u i When x is less than x9, S9 = 0; when u i When the value is greater than x9, S9 = 1.

[0199] A table showing the correspondence between positive thermometer codes, input voltage, and voltage divider nodes:

[0200] Forward comparator queue

[0201]

[0202] 2: Composition and working principle of the "position weight quantizer"

[0203] The bit weight quantizer is composed of a comparator queue and space XOR or space XNOR logic circuits. The following is a table showing the expression and connection relationship of the output information of each part of the bit weight quantizer.

[0204] 5V bit-weighted quantizer input / output relationship list

[0205]

[0206] The input analog voltage is spatially discretized into nine binary logic outputs through a voltage divider comparator queue. The combination of these nine binary logic outputs still represents the strength changes of the original analog information. This method of using spatial combinations of discrete binary information to represent the strength of the original analog information is usually called "thermometer coding". For example: |000011111|. The "thermometer code" mainly looks at how many nodes in a set of spatial nodes output a state of 1. The more spatial nodes that output 1, the stronger the original analog information; the fewer spatial nodes that output 1, the weaker the original analog information.

[0207] If the output nodes of the "thermometer code" are connected to adjacent two-input XOR or XNOR combinational logic circuits, then the adjacent input terminals of multiple two-input XOR logic circuits are connected to each other and then to the output terminals of the "thermometer code"; the pairwise adjacent circuits of multiple two-input XOR gates are called "spatial parallel-OR" logic. (See attached manual.) Figure 11 As shown.

[0208] If "space domain OR":

[0209]

[0210] and:

[0211]

[0212] The spatial XOR operation produces ten independent outputs |0,0,0,0,0,0,0,1,0,0|, and these ten independent outputs combine to form the "one-hot code" |0000000100|.

[0213] so:

[0214]

[0215] The "thermometer code" and "unique heat code" are extremely inconvenient because only the number and position of each node's state 1 can reveal the numerical value they represent. Therefore, a horizontal bar above a number indicates state 0, and no horizontal bar indicates state 1. Thus, the presence or absence of a horizontal bar above a number indicates the state, and the number itself represents the "weight." This "state-weight" structure is called "position-weight information." The "unique value of the position-weight information" is represented as:

[0216]

[0217] Or it can be expressed as:

[0218]

[0219] Therefore, the "position weight information" (the full value of the position weight is represented as):

[0220]

[0221] or:

[0222] The "total bit weight value" is equal to the OR operation of the individual bit weight values. This is essentially a spatial OR operation. The output of the bit weight quantizer at any given time is the output of the individual bit weight values. The output of the bit weight quantizer during sequential traversal is the output of the "total bit weight value".

[0223] "Thermometer code", "unique heat code", and "position weight information" are all methods of representing information size using a set of spatial node state names.

[0224] Thus, through the "voltage divider comparison" and "spatial domain OR" logical operations on the analog input, a set of "positional weight information" {x} expressing its magnitude using "spatial location" is obtained. 10 Later, logical and numerical operations can be performed using "positional information," laying the foundation for decimal system calculations.

[0225] 3: Composition and working principle of the "amplitude weight quantizer"

[0226] An amplitude-weighted quantizer consists of a comparator queue and a current mirror accumulator. Below is a list of the input-output relationships of the amplitude-weighted quantizer.

[0227] 5V amplitude-weighted quantizer input / output relationship list

[0228]

[0229] The input analog voltage is spatially discretized into nine binary logic outputs through a voltage divider comparator queue. The combination of these nine binary logic outputs still represents the strength changes of the original analog information. This method of using spatial combinations of discrete binary information to represent the strength of the original analog information is usually called "thermometer coding". For example: |000011111|. The "thermometer code" mainly looks at how many nodes in a set of spatial nodes output a state of 1. The more spatial nodes that output 1, the stronger the original analog information; the fewer spatial nodes that output 1, the weaker the original analog information.

[0230] The characteristic of the "thermometer code" is that it measures the strength of information by accumulating the count of nodes that are in a state of 1 in a set of spatial nodes. Therefore, summing the 1 states in the "thermometer code" also expresses the strength of information. Thus, connecting a summing circuit after each node output by the "thermometer code" is called a "spatial domain merging" circuit. See the attached diagram in the specification. Figure 12 As shown.

[0231] The comparator queue listed in the table above outputs voltage-type S. To achieve accumulation and summation, current-type information is required. The current-type and voltage-type information have the following logical relationship in the circuit above:

[0232]

[0233] Because: S x =0

[0234] R1 = R2 = R3 = ... R s

[0235] then:

[0236] R s I is the unit resistance value of R. s The current is the unit current.

[0237] Therefore, on one side of the current mirror:

[0238]

[0239] The number of times S is in the 0 state determines the number of current I in each path. s The summation and accumulation of current I are achieved by passing current mirrors Q1 and Q2 through resistor R. L The voltage is restored to amplitude-weighted voltage F. x .

[0240] {F x} 10 =x×G S +G S / 2 x=0,1,2....9

[0241] And the quantization range (voltage): G s =I s ×R L In the ten-value thermometer code, the 'x' number represents ten logic values. The number of G S / 2 places the amplitude level in the middle of the quantization range.

[0242] because:

[0243]

[0244] so:

[0245] {F0} 10 =0×G S +G S / 2 {F1} 10 =1×G S +G S / 2

[0246] {F2} 10 =2×G S +G S / 2 {F3} 10 =3×G S +G S / 2

[0247] {F4} 10 =4×G S +G S / 2 {F5} 10 =5×G S +G S / 2

[0248] {F6} 10 =6×G S +G S / 2 {F7} 10 =7×G S +G S / 2

[0249] {F8} 10 =8×G S +G S / 2 {F9} 10 =9×G S +G S / 2

[0250] Or: {F x} 10 =|{F0} 10 , {F ，1} 10 {F2} 10 {F3} 10 {F4} 10 {F5} 10 {F6} 10 {F7} 10 {F8} 10 {F9} 10 |

[0251] The discrete individual magnitude weights are called "unique magnitude weights", such as {F3}. 10 The total magnitude weights after discretization are called the "total magnitude weights", such as {F}. x} 10 The "full amplitude weight" is equal to the "individual amplitude weight" in a parallel OR operation. This is essentially a time-domain AND-OR operation. The output of the amplitude quantizer at any given time is the "individual amplitude weight" output. The time-cycle output of the amplitude quantizer is the "full amplitude weight" output.

[0252] The amplitude weight quantizer may seem to perform unnecessary information transformation, but in essence it quantizes continuous analog information into stepped discrete information, transforming closely connected analog information into multiple loosely connected, multi-valued, discrete "amplitude weight" information with a certain "fault tolerance range".

[0253] 4. The relationship between "position weight information" and "range weight information":

[0254] Amplitude weighting information equals the product of position weighting information and the quantization interval value. That is:

[0255]

[0256] Or: F x =G s {x} 10 =G s |{0} 10 {1} 10 {2} 10 ,{3} 10 {4} 10 ,{5} 10 , {6} 10 , {7} 10 {8} 10 ,{9} 10 |

[0257] Positional output includes "unique hot" output and "traversal" output.

[0258] Amplitude weight output can be either "unique" or "cyclic." "Unique" output means that only one amplitude weight value is output at any given time, and this output value is independent of the others. "Cyclic" output means that the amplitude weight values ​​are output in a fixed order, creating a new cycle. The order of the cycles can be manually edited, and ten amplitude weight values ​​can generate billions of possible arrangements.

[0259] 5: Ten-value and multi-value quantization methods and the composition characteristics of quantizers.

[0260] The quantization method of ten-value logic includes two parts: the "quantization discretization" method of ten-value decimal logic and the "position weight" and "amplitude weight" quantizers of ten-value decimal logic.

[0261] The "quantization and discretization" method of decimal logic is for continuous analog information. The decimal "quantization and discretization" quantizer takes analog information as input and outputs "position weight" and "amplitude weight" logical information.

[0262] The "quantization discretization" method involves discretizing the maximum amplitude of the input continuous analog information into quantization intervals G. SThe amplitude of the input continuous analog information is divided into several segments, and these amplitude segments are associated with the number system. The amplitude of the input continuous analog information is "discretely divided" into several segments by the number system. For example, octal divides the amplitude of continuous analog information into eight segments, decimal divides the amplitude of continuous analog information into ten segments, hexadecimal divides the amplitude of continuous analog information into sixteen segments, etc.

[0263] The "quantization method" uses voltage dividers to equally divide the rated reference voltage into multiple required comparison reference voltage nodes according to the required number of segments, forming a set "quantization interval G". S The reference maximum voltage and the maximum input analog voltage value are equal;

[0264] The "quantization method" uses analog comparators to convert the input analog information into binary information segment by segment of the "quantized discrete" amplitude information. Multiple comparators are used in a queue to simultaneously compare multiple reference nodes, generating binary information at multiple nodes. The binary information output from these multiple nodes is then arranged in an ordered manner to form the thermometer code information, resulting in the ten-node "thermometer code" information as follows:

[0265]

[0266] The "quantization method" converts the "thermometer encoding" information into decimal "position weight encoding" information, also known as "position weight information", through the "spatial domain adjacency multi-node parallel XOR (XNOR) operation output circuit" (spatial domain parallel OR).

[0267]

[0268] Or it can be expressed as:

[0269] "Positioning information" is a "convex representation"; the aforementioned "positioning information" can also be represented as a "recessed representation":

[0270]

[0271]

[0272] The information value conveyed by concave and convex expressions is the same;

[0273] The "quantization method" can also use the "one-hot encoding" method to encode and edit "position weight information".

[0274] The "quantization discretization" method encodes the "thermometer code" information using a "spatial point-by-point mirror current source summation" method, also known as "spatial domain merging," converting the ten-node thermometer code into decimal "discrete amplitude weighting code" information, or "amplitude weighting information." This "amplitude weighting information" is also commonly referred to as "ten-value logic information," represented as:

[0275]

[0276] The "quantization discretization" method can also use analog adders and other summing and accumulating devices to convert thermometer codes into amplitude step information, or "amplitude weighting information," for output.

[0277] The "position weight value" in "position weight information" is generated by comparing the binary states 0 and 1 on the node. The "weight" is represented by comparing a state on a unique node with different states on other nodes. The position number of the "weighted" node is used to represent the "position weight value" of all nodes within the brackets. The number of nodes within the brackets is called the node capacity. The node capacity within the brackets is represented by the positional system and is marked with a subscript outside the brackets.

[0278] Using a number or symbol enclosed in parentheses to represent a unique 1 or 0 value in the "positional information", with the subscript outside the parentheses indicating the positional system, this expression is called "unique positional value".

[0279] The "unique value" of symbolic representation

[0280] Or the "unique value" expressed in numbers.

[0281] "Ten-value full-value expression" is the "ten-node traversal expression" and "ten-amplitude cyclic expression" of "ten-value unique value expression";

[0282]

[0283] Or: {x →} 10 =[{0} 10 {1} 10 {2} 10 ,{3} 10 {4} 10 ,{5} 10 , {6} 10 , {7} 10 {8} 10 ,{9} 10 ]

[0284] The aforementioned "multi-valued unique value {S3}" 10 and multivalued single value {4} 10 " set {x→} 10 This is a full-valued logical expression. The arrow above the character within parentheses indicates "traversal" or "loop," or simply represents...

[0285] A quantizer is a converter that converts the maximum amplitude value u of an input analog signal. max According to the requirements of the "base system", it is divided into equal parts. The ternary system is divided into three equal parts, the quaternary system is divided into four equal parts, the decimal system is divided into ten equal parts, the hexadecimal system is divided into sixteen equal parts, and so on.

[0286] The "quantizer" uses resistors of the same resistance in series to transmit a standard voltage V. REF The voltage is divided into N-1 voltage nodes, where N is a number system, represented as: X1, X2, X3, ... X n-1 node;

[0287] The "quantizer" uses N-1 analog comparators B1, B1, B1, ... B1 n-1 Connect the positive input terminal of the analog comparator to the resistor divider nodes X1, X2, X3, ... X in sequence according to their numbers. n-1 ; Put analog comparators B1, B1, B1, ... B n-1 The inverting input terminals are interconnected to form an input node u. i ;

[0288] The quantizer consists of N-1 analog comparators B1, B1, B1, ... B1. n-1 The components are: N represents the positional number system; the "quantizer" is an analog comparator with outputs out1, out2, out3, ..., out. n-1 indivual;

[0289] Analog comparators B1, B1, B1, ... B n-1 The output terminals are out1, out2, out3, ... out n-1 There are two output connection methods: one is the "position weight" quantization connection method, which connects to form a "position weight quantizer", and the other is the "amplitude weight" quantization connection method, which connects to form an "amplitude weight quantizer".

[0290] A "bit-weighted quantizer" is a quantizer that simulates comparators B1, B1, B1, ... B1. n-1 The output terminals are out1, out2, out3, ... out n-1 Pull-up resistors R1, R1, R1......R are connected at the top. n-1 Resistors R1, R1, R1.......R n-1 The other end is connected to the power supply V.cc Output signals S1, S2, S3, ... S n Lead out at the connection node between the analog comparator output node out and the pull-up resistor R; connect S1, S2, S3, ... S n Analog comparator output and power supply positive node V + The negative terminal of the power supply V - Together they form a new input node group {V - ,S9,S8,S7,S6,S5,S4,S3,S2,S1,V + The input is then fed into the input node of the next-level logic operation circuit, the "spatial domain parallel-OR circuit" (spatial domain adjacency multi-node parallel XOR operation output circuit), and the two-state value multi-weight "state weight" logic output in the form of multi-node "one-hot code" is obtained through spatial multi-node XOR operation. This type of output is called "bit weight information"; this circuit, which combines a "quantizer" circuit and a "spatial domain OR" circuit, is called a "bit weight quantizer";

[0291] The "amplitude-weighted quantizer" is: a comparator B1, B1, B1, ... B1 in the "quantizer". n output terminal

[0292] out1, out2, out3,...out n Connect resistors R1, R1, R1......R n R1, R1, R1.......R n The other end is connected together to the diode side of the "mirror current source" circuit composed of PNP transistors Q1 and Q2. The load resistor R is connected to the collector of the "mirror current source" transistor. L R L The other end is grounded, and the output signal comes from the collector of the "mirror current source" transistor and the load resistor R. L It is brought out from the connection node; output "state weights" The amplitude weight of a feature is called "amplitude weight information"; the "amplitude weight" is the weight number X and the "quantization interval G". S The product is a discrete representation of the amplitude values, each independent of the others. This circuit, which combines a quantizer circuit and a mirror current source arithmetic adder circuit, is called an amplitude-weighted quantizer. Attached Figure Description

[0293] Figure 1 It is a thermometer code LED display image.

[0294] Figure 2 This is a schematic diagram of an analog-to-thermometer code conversion circuit.

[0295] Figure 3This is an LED display diagram of "positional information".

[0296] Figure 4 This is a diagram of a binary "one-hot encoding" connection circuit.

[0297] Figure 5 Flowchart of the structural principle of the "position weight quantizer"

[0298] Figure 6 This is an LED display diagram of "width weight information".

[0299] Figure 7 This is the logic block diagram of the "amplitude weight quantizer".

[0300] Figure 8 This is a diagram illustrating the formation process of "positional weight information" and "amplitude weight information".

[0301] Figure 9 This is a circuit diagram of an inverting comparator queue.

[0302] Figure 10 This is a circuit diagram of a positive comparator queue.

[0303] Figure 11 This is a "space-domain parallel-OR" logic circuit diagram.

[0304] Figure 12 It is a logic circuit diagram of "spatial domain merging". Implementation

[0305] Reference Figure 9 Figure 10 A quantizer is a converter that converts the maximum amplitude value u of an input analog signal. max According to the requirements of the "base system", it is divided into equal parts. The ternary system is divided into three equal parts, the quaternary system is divided into four equal parts, the decimal system is divided into ten equal parts, the hexadecimal system is divided into sixteen equal parts, and so on.

[0306] The "quantizer" uses resistors of the same resistance in series to transmit a standard voltage V. REF The voltage is divided into N-1 voltage nodes, where N is a base number, represented as: {X1, X2, X3, ... X...} n-1} N node;

[0307] The "quantizer" uses N-1 analog comparators {B1, B1, B1, ... B1}. n-1} N Connect the positive input terminal of the analog comparator to the resistor divider nodes X1, X2, X3, ... X in sequence according to their numbers. n-1 ; Put analog comparators B1, B1, B1, ... B n-1 The inverting input terminals are connected to form an input node u. i ;

[0308] The quantizer consists of N-1 analog comparators B1, B1, B1, ... B1. n-1 The components are: N represents the positional number system; the "quantizer" is an analog comparator with outputs out1, out2, out3, ..., out. n-1 indivual

[0309] In analog comparators B1, B1, B1, ... B n-1 The output terminals are out1, out2, out3, ... out n-1 Pull-up resistors R1, R1, R1......R are connected at the top. n-1 R1, R1, R1.......R n-1 The other end is connected to the power supply V. cc Output signals S1, S2, S3, ... S n Lead out at the connection node between the analog comparator output node out and the pull-up resistor R; connect S1, S2, S3, ... S n Analog comparator output and power supply positive node V + The negative terminal of the power supply V - Together they form a new input node group {V - S9 S8S7 S6 S5 S4 S3 S2 S1 V +} and input to the next level logic operation circuit ( Figure 11 The input node of the "spatial domain parallel-OR circuit" (spatial domain adjacency multi-node parallel XOR operation output circuit) obtains a two-state value multi-weight "state weight" logic output in the form of a multi-node "one-hot code" through spatial multi-node XOR operation. This type of output is called "position weight information"; this circuit, which combines a "discrete comparison quantizer" circuit and a "spatial domain OR" circuit, is called a "position weight quantizer".

[0310] Reference Figure 9 Reference Figure 10 A quantizer is a converter that converts the maximum amplitude value u of an input analog signal. max According to the requirements of the "base system", it is divided into equal parts. The ternary system is divided into three equal parts, the quaternary system is divided into four equal parts, the decimal system is divided into ten equal parts, the hexadecimal system is divided into sixteen equal parts, and so on.

[0311] The "quantizer" uses resistors of the same resistance in series to transmit a standard voltage V. REF The voltage is divided into N-1 voltage nodes, where N is a number system, represented as: X1, X2, X3, ... X n-1 node;

[0312] The "quantizer" uses N-1 analog comparators B1, B1, B1, ... B1 n-1 Connect the positive input terminal of the analog comparator to the resistor divider nodes X1, X2, X3, ... X in sequence according to their numbers. n-1 ; Put analog comparators B1, B1, B1, ... B n-1 The inverting input terminals are connected to form an input node u. i ;

[0313] The quantizer consists of N-1 analog comparators B1, B1, B1, ... B1. n-1 The components are: N represents the positional number system; the "quantizer" is an analog comparator with outputs out1, out2, out3, ..., out. n-1 indivual.

[0314] In analog comparators B1, B1, B1, ... B n The output terminals are out1, out2, out3, ... out n Connect resistors R1, R1, R1......R n R1, R1, R1.......R n The other end is connected together to the side of diode Q1 in the "current mirror" circuit composed of PNP transistors Q1 and Q2. Figure 12 The load resistor R is connected to the collector of transistor Q2 on one side of the "current mirror" transistor. L R L The other end is grounded, and the output signal comes from the collector of the "current mirror" transistor Q2 and the load resistor R. L It is brought out from the connection node; output "state weights" The amplitude weight of a feature is called "amplitude weight information"; the "amplitude weight" is the weight number X and the "quantization interval G". S The product is a discrete representation of the amplitude values, each independent of the others. This circuit, which combines a quantizer circuit and a mirror current source arithmetic adder circuit, is called an amplitude-weighted quantizer.

[0315] Beneficial effects

[0316] This invention, a "ten-value decimal position and amplitude weight quantizer," can convert analog information into "position weight information" and "amplitude weight information." The "position weight information" and "amplitude weight information" can perform logical operations and decimal numerical calculations on ten-valued and multi-valued information. This lays the foundation for realizing a ten-valued decimal calculation system.

[0317] "Position weight information" and "amplitude weight information" are logical representation methods that use "discrete binary node groups" and "discrete multi-value amplitude groups" to represent "multi-valued logical values." The capacity of the node group represents the positional number, and the relative comparison of the binary states of multiple nodes generates unique "protruding" or "recessed" nodes. The position number of these isolated "protruding" or "recessed" nodes represents the "multi-valued logical value"—this is "position weight information." The method of representing a "multi-valued logical value" using the unique performance attribute of one of multiple discrete amplitudes is "amplitude weight information."

[0318] By utilizing the characteristics of "position weight information" and "amplitude weight information," "multiple values ​​of analog continuous logic and multi-valued logic" can be transformed into simple "binary logic expressions," "analog continuous logic operations" can be transformed into step-wise multi-valued operations with definite values, and "analog and multi-valued logic operations" and "continuous and multi-valued numerical operations" can be transformed into simple "parallel encoded logic and numerical encoded operations" of "binary logic." This greatly simplifies the complexity of multi-valued logic operations and multi-valued numerical operations, making complex operations into simple, user-friendly operations. Even more advantageously, the use of "position weight information" can immediately digitize analog information, enabling the rapid and efficient digitization of all analog numerical computing devices (such as operational amplifiers) to achieve the same stability and accuracy as binary computers. "Digital computation of analog information" can still be realized, laying the foundation for the realization of "analog-digital computers."

[0319] "Encoding" can still convert multi-valued logic into binary logic, but it only encodes and converts existing multi-valued logic. "Position weight information" generates multi-valued logic from binary logic concepts; it is a process of generating multi-valued logic from "nothing" to "something," and it is not comparable to "encoding." For the process of generating multi-valued logic using binary logic concepts, please refer to the ancient thought logic diagram "Luo Shu."

Claims

1. Ten-value decimal "bit weight" "amplitude weight" quantizer and "quantization discrete" method of ten-value logic, including two parts of "quantization discrete" method of ten-value decimal logic and ten-value decimal "bit weight" "amplitude weight" quantizer; The "quantization discrete" method of ten-value decimal logic is for continuous analog information, and the ten-value decimal "quantization discrete" quantizer outputs "bit weight" and "amplitude weight" logical information from the input analog information; The "quantitative discrete" method comprises a step of dividing the maximum amplitude of the input continuous analog information into several amplitude sections with quantitative intervals G S , and associating the amplitude sections with a number system, so as to "discretely divide" the amplitude of the input continuous analog information into several sections by using a number system, for example, eight sections by using octal system, ten sections by using decimal system, sixteen sections by using hexadecimal system, and the like. ② The "quantization method" equally divides the rated reference voltage into multiple comparison reference voltage nodes as required by using a voltage dividing device, and forms a set "quantization interval G S ”, which is equal to the reference maximum voltage and the maximum input analog voltage value; The "quantization method" converts the analog amplitude segment information into binary information by using analog comparators one by one, uses multiple comparators to form a queue for simultaneous comparison of multiple reference nodes, simultaneously generates binary information on multiple nodes, and uses the ordered combination of binary information output by multiple nodes to form thermometer code information, obtaining ten-node "thermometer code" information as follows: ③ The "quantization method" converts the "thermometer code" information into decimal "position weight code" information, i.e., "bit weight information", through "spatial adjacent multi-node parallel XOR (XOR) operation output circuit", which is referred to as (spatial parallel) for short; or expressed as: The "bit weight information" is "convex expression"; the "bit weight information" can also be expressed as "concave expression": The "weight value" information values represented by concave expression and convex expression are the same, and concave and convex are different "state value" information; The "quantization method" can also use the "one-hot encoding" method to encode and edit "bit weight information". ④ The "quantization discrete" method converts the "thermometer code" information into decimal "discrete amplitude weight code" information, i.e., "amplitude weight information", through the "spatial point-by-point mirror current source accumulation summation" method, which is referred to as (spatial combination) for short, and converts the ten-node thermometer code into "amplitude weight information"; The "quantization discrete" method can also use analog adders and other summation accumulation devices to convert the thermometer code into amplitude step information "amplitude weight information" output; ⑤ The "bit weight value" in the "bit weight information" is generated by comparing the binary states 0 and 1 on the nodes, and is represented by comparing the state of a unique node with different states on other nodes. The position number of the "weighted" node is used to represent the "bit weight value" of all nodes in the parentheses. The number of nodes in the parentheses is called node capacity, and the node capacity outside the parentheses is marked as a subscript on the right. A number or symbol in a parenthesis represents a unique 1 value or 0 value in the "bit weight information", and the subscript on the right outside the parentheses represents the radix. This expression is called "bit weight unique value"; "uniqueness" of symbolic representations "unique" or a numerical representation ⑥ The "ten-value full-value expression" is "ten-node traversal expression" and "ten-amplitude cycle expression" of "ten-value unique value" expression, which is expressed as: Or: {x →} 10 = [{0} 10 , {1} 10 , {2} 10 , {3} 10 , {4} 10 , {5} 10 , {6} 10 , {7} 10 , {8} 10 , {9} 10 ] The set of "multivalued idempotents {S3} 10 and multivalued idempotents {4} 10 " {x →} 10 is the full-valued logic expression. The arrow over the characters in the parentheses indicates a "walk" or "loop" or a transformation into ⑦ The "quantization method" can quantize analog information into binary, ternary, quaternary, quinary, sextenary, etc.

2. The "quantizer" is to divide the maximum amplitude value u of the input analog signal into n equal parts max According to the requirements of the "place value system", the equal division quantization is that the ternary is divided into three equal parts, the quaternary is divided into four equal parts, …, the decimal is divided into ten equal parts, the hexadecimal is divided into sixteen equal parts, etc. REF The "quantizer" divides a standard voltage V n-1 into N-1 voltage nodes, N being a base, represented as X1, X2, X3,... X​ The "quantizer" is composed of N-1 analog comparators B1, B1, B1,... B n-1 The positive input terminals of the analog comparators are connected in order to the resistor dividing nodes X1, X2, X3,... X n-1 The negative input terminals of the analog comparators B1, B1, B1,... B n-1 are connected to each other to form an input node u i ​ iii) said "quantizer" is composed of N-1 analog comparators B1, B1, B1,... B n-1 N being a carry system, the "quantizer" analog comparators output being out1, out2, out3,... out n-1 N-1; IV. The analog comparators B1, B1, B1,... B n-1 out1, out2, out3,... out n-1 There are two output connection methods: one is "bit weight" quantization connection method, connected into "bit weight quantizer", and the other is "amplitude weight" quantization connection method, connected into "amplitude weight quantizer"; ⑤The "bit weight quantizer" is: in the "quantizer" analog comparator B1, B1, B1,......B n-1 the output end out1, out2, out3,......out n-1 the upper pull-up resistor R1, R1, R1,......R n-1 ; the other end of the resistor R1, R1, R1,......R n-1 connected to the power supply V cc , output signal S1, S2, S3,......S n on the connection node of the analog comparator output node out and the pull-up resistor R; S1, S2, S3,......S n analog comparator output and the positive node V + , the negative node V _ together constitute a new input node group {V - , S9, S8, S7, S6, S5, S4, S3, S2, S1, V +} and input to the next level of logic operation circuit "space and or circuit" (space adjacent multi-node parallel XOR operation output circuit) input node, through space multi-node XOR operation to get multi-node "one-hot code" form of two-state value of multi-weight "state weight" logic output This output is called "bit weight information"; this kind of circuit composed of "quantizer" circuit and "space and or" circuit is called "bit weight quantizer"; ⑥The "amplitude weight quantizer" is: in the "quantizer" analog comparator B1, B1, B1,... B n The output end out1, out2, out3,... out n The other end of the resistor R1, R1, R1,... R n , R1, R1, R1,... R n The other end of the resistor R1, R1, R1,... R L , R1, R1, R1,... R L The other end is connected to the ground, the output signal from the "mirror current source" transistor collector and load resistor R L The connection node is drawn out; output "state weight The characteristic amplitude weight is called "amplitude weight information"; the "amplitude weight" is the product of weight number X and "quantization interval G S "; it is a discrete representation of "amplitude value", each value is independent, and the circuit composed of "quantizer" circuit and "mirror current source" arithmetic addition circuit is called "amplitude weight quantizer".

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