Vector access instruction processing method and device, electronic equipment and program product

Abstract

The invention is suitable for the technical field of data processing, and provides a vector memory access instruction processing method and device, electronic equipment and a program product. The method comprises the following steps: splitting a vector memory access instruction into a plurality of sub-operations; for each sub-operation, splitting the sub-operation into a plurality of micro-operations, or determining the sub-operation as the micro-operation; and distributing all the micro-operations to each target scalar assembly line for execution. According to the method and the device, a special vector memory access assembly line can be avoided, so that the problems that the area of a memory access unit is increased, the utilization rate of the vector memory access assembly line is relatively low and the like are avoided, and the realization of a vector with relatively high VLEN can be supported, so that the problem that the overall vector operation capability is relatively low due to the bit width limitation of the assembly line is avoided.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of data processing, and particularly relates to a vector memory access instruction processing method and device, electronic equipment and program product. BACKGROUND

[0002] At present, there are two ways to implement vector memory access operation. The first way is to execute vector memory access instructions through a dedicated vector memory access pipeline to implement high-bit-width vector memory access operation, but this way leads to an increase in the area of the memory access unit, and when there are few vector memory access instructions, the vector memory access pipeline is idle, and the utilization rate of the vector memory access pipeline is low. The second way is to use a lower vector length (VLEN), that is, only a lower vector bit width is implemented on hardware, so that the vector memory access instructions can be executed on a scalar pipeline. For wider vector operations, multiple instructions need to be translated in the instruction decoding stage to complete the operation, but due to the lower VLEN, the overall vector operation capability is low. SUMMARY

[0003] Embodiments of the present application provide a vector memory access instruction processing method, device, electronic equipment and program product, which can avoid using a dedicated vector memory access pipeline, thereby avoiding problems such as an increase in the area of the memory access unit and a low utilization rate of the vector memory access pipeline, and can support higher VLEN vector implementation, thereby avoiding the problem of low overall vector operation capability due to the limitation of the pipeline bit width.

[0004] In a first aspect, embodiments of the present application provide a vector memory access instruction processing method, comprising: splitting a vector memory access instruction into multiple sub-operations; for each sub-operation, splitting the sub-operation into multiple micro-operations, or determining the sub-operation as the micro-operation; distributing all the micro-operations to target scalar pipelines for execution.

[0005] In embodiments of the present application, by splitting a vector memory access instruction into multiple sub-operations, and for each sub-operation, splitting the sub-operation into multiple micro-operations, or determining the sub-operation as the micro-operation, and then distributing all the micro-operations to target scalar pipelines, high-bit-width vector memory access operations can be efficiently implemented on low-bit-width scalar pipelines, and the use of a dedicated vector memory access pipeline can be avoided, thereby avoiding problems such as an increase in the area of the memory access unit and a low utilization rate of the vector memory access pipeline, and higher VLEN vector implementation can be supported, thereby avoiding the problem of low overall vector operation capability due to the limitation of the pipeline bit width.

[0006] In some embodiments of the first aspect, before the distributing all the micro-operations to each target scalar pipeline for execution, further comprising: obtaining a number of free entries of each scalar memory access instruction issue queue; determining a target scalar memory access instruction issue queue from the scalar memory access instruction issue queues whose number of free entries is greater than zero; determining a target scalar pipeline corresponding to the target scalar memory access instruction issue queue as a target scalar pipeline.

[0007] In some embodiments of the first aspect, before the distributing all the micro-operations to each target scalar pipeline for execution, further comprising: for each target scalar memory access instruction issue queue, sending the micro-operations to the target scalar memory access instruction issue queue, wherein the number of the micro-operations sent to the target scalar memory access instruction issue queue does not exceed the number of free entries of the target scalar memory access instruction issue queue; the distributing all the micro-operations to each target scalar pipeline for execution comprises: when the micro-operations are output from the target scalar memory access instruction issue queue, distributing the micro-operations to the target scalar pipeline corresponding to the target scalar memory access instruction issue queue.

[0008] In some embodiments of the first aspect, the sending the micro-operations to the target scalar memory access instruction issue queue comprises: if there is a scalar memory access instruction that needs to enter the target scalar memory access instruction issue queue, arbitrating the micro-operations and the scalar memory access instruction to obtain an arbitration result; if the arbitration result indicates that the micro-operations enter the target scalar memory access instruction issue queue, sending the micro-operations to the target scalar memory access instruction issue queue.

[0009] In some embodiments of the first aspect, before the distributing all the micro-operations to each target scalar pipeline for execution, further comprising: for each sub-operation, detecting whether there is a free entry in an operation queue corresponding to the vector memory access instruction; if there is a free entry in the operation queue, allocating an entry for the sub-operation in the operation queue, wherein the entry comprises a first field, and the first field comprises a state bit of each micro-operation of the sub-operation; after the distributing all the micro-operations to each target scalar pipeline for execution, further comprising: if any micro-operation corresponding to the sub-operation is executed on the target scalar pipeline corresponding to the micro-operation and is completed, setting a state bit of the micro-operation in the field to a preset value; If all the status bits in the domain are set to the preset value, the item is released from the operation queue.

[0010] In some embodiments of the first aspect, before the splitting the sub-operation into a plurality of micro-operations or determining the sub-operation as the micro-operation, further comprising: determining a splitting level of the vector memory instruction based on an instruction type of the vector memory instruction; the splitting the sub-operation into a plurality of micro-operations comprises: if the splitting level of the vector memory instruction is two-level splitting, splitting the sub-operation into a plurality of the micro-operations; the determining the sub-operation as the micro-operation comprises: if the splitting level of the vector memory instruction is one-level splitting, determining the sub-operation as the micro-operation.

[0011] In some embodiments of the first aspect, before the splitting the vector memory instruction into a plurality of sub-operations, further comprising: sending the vector memory instruction to a vector memory instruction issue queue; the splitting the vector memory instruction into a plurality of sub-operations comprises: splitting the vector memory instruction into a plurality of the sub-operations when the vector memory instruction is outputted by the vector memory instruction issue queue.

[0012] In a second aspect, embodiments of the present application provide a vector memory instruction processing apparatus, comprising: an instruction splitting module, configured to split a vector memory instruction into a plurality of sub-operations; an operation processing module, configured to split, for each of the sub-operations, the sub-operation into a plurality of micro-operations or determine the sub-operation as the micro-operation; an operation execution module, configured to dispatch all the micro-operations to respective target scalar pipelines for execution.

[0013] In a third aspect, embodiments of the present application provide an electronic device, comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein the processor executes the computer program to enable the electronic device to implement the method according to any one of the first aspect.

[0014] In a fourth aspect, embodiments of the present application provide a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a computer to implement the method according to any one of the first aspect.

[0015] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program, which, when executed by a computer, causes the method according to any one of the first aspect to be performed.

[0016] It can be understood that the beneficial effects of the above-mentioned second aspect to fifth aspect can refer to the related description in the above-mentioned first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0018] Figure 1 is a flowchart of a vector memory instruction processing method provided by an embodiment of the present application; Figure 2 is another flowchart of a vector memory instruction processing method provided by an embodiment of the present application; Figure 3 is an example diagram of a load operation queue and a vector load data queue provided by an embodiment of the present application; Figure 4 is an example diagram of a store operation queue and a vector store data queue provided by an embodiment of the present application; Figure 5 is still another flowchart of a vector memory instruction processing method provided by an embodiment of the present application; Figure 6 is a structural diagram of a vector memory instruction processing apparatus provided by an embodiment of the present application; Figure 7 is a structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] In the following description, specific details are set forth in order to provide a thorough understanding of embodiments of the present application. However, persons skilled in the art will understand that embodiments of the present application can be practiced without these specific details. In other instances, well-known structures, devices, circuits, and methods have not been described in detail in order to avoid obscuring the description of the present application.

[0020] It should be understood that the word "comprising" when used in the specification and claims of this application indicates the existence of the stated features, integers, steps, operations, elements, and / or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] Reference throughout this application to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in additional embodiments," and the like in various places throughout this specification are not necessarily referring to the same embodiment, unless otherwise expressly specified.

[0022] VLEN, the bit width of a hardware-implemented vector register, is also the basic width of a vector operation. In the related art, a vector memory access instruction is executed through a dedicated vector memory access pipeline to implement a high-bit-width vector memory access operation, but this approach results in an increase in the area of the memory unit and, when there are fewer vector memory access instructions, results in an idle vector memory access pipeline and low utilization of the vector memory access pipeline. Alternatively, if a lower VLEN, such as 128 bits, is used, the bit width of the corresponding vector register is also only 128 bits, so that the vector instruction can be more easily executed on a scalar pipeline, but this limits the processing capacity of the vector operation.

[0023] Based on this, the embodiments of the present application provide a vector memory access instruction processing method and device, an electronic device, and a program product. By splitting a vector memory access instruction into multiple sub-operations, and splitting each sub-operation into multiple micro-operations or determining the sub-operation as a micro-operation, and then distributing all micro-operations to target scalar pipelines, high-bit-width vector memory access operations can be efficiently implemented on low-bit-width scalar pipelines, and the use of a dedicated vector memory access pipeline can be avoided, thereby avoiding problems such as an increase in the area of the memory unit and low utilization of the vector memory access pipeline, and supporting a higher VLEN vector implementation, thereby avoiding the problem of low overall vector operation capacity due to the limitation of the pipeline bit width.

[0024] The vector memory access instruction processing method provided by the embodiments of the present application can be applied to electronic devices such as mobile phones, tablet computers, desktop computers, servers, notebook computers, ultra-mobile personal computers (UMPC), netbooks, personal digital assistants (PDA), and the like. The embodiments of the present application do not make any limitation on the specific type of electronic device.

[0025] In order to illustrate the technical solutions of the present application, specific embodiments are used for illustration in the following.

[0026] Please refer to Figure 1 , Figure 1 A flowchart of a vector memory access instruction processing method provided by the embodiments of the present application is shown, which is used as an example and is not limited, and the method includes the following steps: Step 101, split the vector memory access instruction into multiple sub-operations.

[0027] In some embodiments, the vector memory access instruction can be split into multiple sub-operations (i.e., at least two sub-operations) based on the number of elements to be operated on by the vector memory access instruction (i.e., the number of elements contained in the vector memory access instruction), one element corresponding to one sub-operation, i.e., the number of elements is the same as the number of sub-operations. Taking the RISC-V instruction set as an example, the instruction under the RISC-V instruction set architecture is configured with a register named “vl”, the value of which represents the number of elements to be operated on by the instruction.

[0028] As an example and not limitation, the number of elements to be operated on by the vector memory access instruction is 8, so the vector memory access instruction can be split into 8 sub-operations.

[0029] The embodiments split the vector memory access instruction in the memory access stage, without splitting the vector memory access instruction in the decoding stage, thereby reducing the complexity of the decoding stage.

[0030] Step 102, for each sub-operation, split the sub-operation into multiple micro-operations, or determine the sub-operation as a micro-operation.

[0031] The electronic device can determine the split level of the vector memory access instruction, and determine whether to split the sub-operation into multiple micro-operations based on the split level of the vector memory access instruction.

[0032] It should be understood that the current instruction structure of the vector memory access instruction is usually one layer or two layers, and the above split level can be one-level split or two-level split. The vector memory access instruction with one-layer instruction structure usually only contains multiple elements. The vector memory access instruction with two-layer instruction structure not only contains multiple elements, but each element also includes multiple domains.

[0033] Of course, it can be understood that if the instruction structure of the vector memory access instruction has three layers or more layers, the above-mentioned split level can also be a three-level split or more-level split.

[0034] Since the instruction structure of the vector memory access instruction is usually related to the instruction type, in some embodiments, the electronic device can determine the split level of the vector memory access instruction based on the instruction type of the vector memory access instruction. On this basis, the above-mentioned splitting of the sub-operation into multiple micro-operations includes: If the split level of the vector memory access instruction is two-level split, the sub-operation is split into multiple micro-operations; The sub-operation is determined as a micro-operation, including: If the split level of the vector memory access instruction is one-level split, the sub-operation is determined as a micro-operation.

[0035] In some embodiments, each sub-operation can be split into multiple micro-operations (i.e. at least two micro-operations) based on the number of domains contained in the element to be operated on by the vector memory access instruction, that is, one domain corresponds to one micro-operation, and the number of domains is the same as the number of micro-operations.

[0036] It should be understood that the number of domains contained in different elements of the same vector memory access instruction is usually the same, and on this basis, the number of micro-operations split by different sub-operations of the same vector memory access instruction is also the same.

[0037] As an example but not limitation, each element to be operated on by the vector memory access instruction contains 8 domains, and each sub-operation of the vector memory access instruction can be split into 8 micro-operations.

[0038] Taking Vector Strided Load and Vector Strided Segment Load as examples, Vector Strided Load and Vector Strided Segment Load are two instruction types of Vector instructions under the RISC-V instruction set architecture. The instruction structure of Vector Strided Load is one layer, and only one-level split is needed. The instruction structure of Vector Strided Segment Load is two layers, and two-level split is needed.

[0039] Step 103, distribute all micro-operations to target scalar pipelines for execution.

[0040] Among them, the target scalar pipeline can refer to a scalar pipeline for executing micro-operations. Of course, it can be understood that the target scalar pipeline can also execute scalar memory access instructions. Scalar memory access instructions only contain one element, and vector memory access instructions usually contain multiple elements.

[0041] The scalar pipeline can refer to a pipeline that executes scalar memory access instructions. The embodiment can efficiently implement high-bit-width vector memory access operations on a low-bit-width scalar pipeline by adding micro-operations for executing vector memory access instructions through the scalar pipeline on the basis of the existing scalar pipeline that only executes scalar memory access instructions.

[0042] The bit width of the scalar pipeline is low (for example, the common bit width of the scalar pipeline is 64 bits), and the vector memory access instruction that needs to operate a high bit width (for example, 512 bits) cannot be executed at one time. The embodiment can efficiently implement high-bit-width vector memory access operations on a low-bit-width scalar pipeline by splitting the vector memory access instruction and distributing all micro-operations to each scalar pipeline for execution.

[0043] In the embodiment of the application, the vector memory access instruction is split into multiple sub-operations, and each sub-operation is split into multiple micro-operations or determined as a micro-operation, and then all micro-operations are distributed to each scalar pipeline, which can efficiently implement high-bit-width vector memory access operations on a low-bit-width scalar pipeline, and can avoid using a dedicated vector memory access pipeline, thereby avoiding problems such as an increase in the area of the memory unit and low utilization of the vector memory access pipeline, and supporting higher VLEN vector implementation, thereby avoiding the problem of low overall vector operation capability due to the limitation of the pipeline bit width.

[0044] In some embodiments of the application, before the vector memory access instruction is split into multiple sub-operations, the following steps are further included: The vector memory access instruction is sent to the vector memory access instruction launch queue. The vector memory access instruction is split into multiple sub-operations, including: The vector memory access instruction is split into multiple sub-operations when the vector memory access instruction is output from the vector memory access instruction launch queue.

[0045] The vector memory access instruction launch queue is used to store the vector memory access instruction to be processed.

[0046] In the embodiment, after receiving the vector memory access instruction, the electronic device first sends the vector memory access instruction to the vector memory access instruction launch queue, which can buffer the transmitted vector memory access instruction, reduce the congestion of the front-end pipeline in the processor of the electronic device, and improve the processing efficiency of the entire scalar pipeline.

[0047] Please refer to Figure 2 In some embodiments of the application, before all micro-operations are distributed to each target scalar pipeline for execution, the electronic device can determine the target scalar pipeline through steps 201 to 203.

[0048] Step 201, obtaining the number of free entries of each scalar memory access instruction issue queue.

[0049] The number of free entries of each scalar memory access instruction issue queue can represent the occupation of the scalar memory access instruction issue queue, thereby reflecting the load of the corresponding scalar pipeline. The more the number of free entries of the scalar memory access instruction issue queue, the lower the load of the corresponding scalar pipeline, and the scalar pipeline with lower load can be selected as the target scalar pipeline.

[0050] It should be understood that the number of scalar pipelines (i.e., the number of scalar memory access instruction issue queues) is not limited in the present application, and can be applied to any number of scalar pipelines. For example, the number of scalar pipelines can be one or at least two.

[0051] In the embodiment, both the vector memory access instruction issue queue and the scalar memory access instruction issue queue are provided, which can balance the vector memory access operation and the scalar memory access operation on the scalar pipeline. Splitting the received vector memory access instruction into multiple micro-operations and adding it to the scalar memory access instruction issue queue can block the front pipeline if there is not enough space in the scalar memory access instruction issue queue, and can greatly affect the execution of the scalar memory access instruction if there is enough space (because the entries in the queue are occupied by a large number of micro-operations, which greatly reduces the number of entries available for the scalar memory access instruction). In the embodiment, a separate vector memory access instruction queue and a scalar memory access instruction queue are implemented, the vector memory access instruction is first buffered in the vector memory access instruction queue to avoid blocking the front pipeline, and the splitting of the vector memory access instruction and the decision of which scalar memory access instruction queue to send are made according to the use of the scalar memory access instruction queue, so as to execute on the corresponding scalar pipeline, which can balance the vector and scalar memory access load on the entire scalar pipeline and improve the execution efficiency of the entire processor.

[0052] Step 202, determining the target scalar memory access instruction issue queue from the scalar memory access instruction issue queue with the number of free entries greater than zero.

[0053] The number of free entries of the scalar memory access instruction issue queue can represent the occupation of the scalar memory access instruction issue queue, thereby reflecting the load of the corresponding scalar pipeline. The more the number of free entries of the scalar memory access instruction issue queue, the lower the load of the corresponding scalar pipeline, and the scalar pipeline with lower load can be selected as the target scalar pipeline.

[0054] In some embodiments, the target scalar memory instruction issue queue can be determined from the scalar memory instruction issue queues with the number of free entries greater than zero based on the number of micro-operations each sub-operation is to be split into, and the sum of the number of free entries of all the target scalar memory instruction issue queues is greater than or equal to the number of micro-operations each sub-operation is to be split into.

[0055] By way of example and not limitation, if each element in the vector memory instruction contains 8 fields, i.e., the number of micro-operations each sub-operation is to be split into is 8, and there are 4 scalar pipelines, then there are 4 scalar memory instruction issue queues, and if the number of free entries of 2 of the scalar memory instruction issue queues are both greater than zero and the sum of the number of free entries of the 2 scalar memory instruction issue queues is 8, then the scalar pipelines corresponding to the 2 scalar memory instruction issue queues can be determined as the target scalar pipelines, and after each sub-operation is split into 8 micro-operations, the 8 micro-operations are dispatched to the 2 scalar pipelines for execution.

[0056] In some embodiments, the sum of the number of free entries of all the scalar memory instruction issue queues can be obtained, and if the sum of the number of free entries of all the scalar memory instruction issue queues is greater than or equal to the number of micro-operations each sub-operation is to be split into, then the corresponding vector memory instruction is allowed to be output from the vector memory instruction issue queue, and the vector memory instruction is split each time to obtain all the micro-operations corresponding to each sub-operation, and steps 202 and 203 are performed to determine the target scalar pipelines, and all the micro-operations corresponding to each sub-operation are dispatched to the target scalar pipelines for execution.

[0057] In step 203, the scalar pipelines corresponding to the target scalar memory instruction issue queues are determined as the target scalar pipelines.

[0058] In some embodiments, the number of target scalar pipelines is the same as the number of target scalar memory instruction issue queues.

[0059] In this embodiment, the target scalar pipelines are determined according to the load conditions of the scalar pipelines, which can flexibly adjust the target scalar pipelines to which the micro-operations are to be dispatched, thereby maximizing the execution efficiency of the micro-operations.

[0060] In some embodiments of the present application, before the micro-operations are dispatched to the target scalar pipelines, the method further comprises: For each target scalar memory instruction issue queue, the micro-operations are sent to the target scalar memory instruction issue queue, and the number of micro-operations sent to the target scalar memory instruction issue queue is not more than the number of free entries of the target scalar memory instruction issue queue. The above dispatching all the micro-operations to the target scalar pipelines for execution comprises: When a micro-operation is output from the target scalar memory access instruction issue queue, the micro-operation is dispatched to the corresponding target scalar pipeline.

[0061] At present, the scalar memory access instruction issue queue usually only stores scalar memory access instructions to wait for being dispatched to the corresponding scalar pipeline for execution. By sending a micro-operation to the target scalar memory access instruction issue queue, the embodiment can store the micro-operation in the target scalar memory access instruction issue queue, so that the micro-operation can be executed in the corresponding target scalar pipeline, i.e., the vector memory access instruction can be executed in the target scalar pipeline.

[0062] In some embodiments of the present application, sending the micro-operation to the target scalar memory access instruction issue queue comprises: If there is a scalar memory access instruction that needs to enter the target scalar memory access instruction issue queue, the micro-operation and the scalar memory access instruction are arbitrated to obtain an arbitration result. If the arbitration result indicates that the micro-operation enters the target scalar memory access instruction issue queue, the micro-operation is sent to the target scalar memory access instruction issue queue.

[0063] It should be understood that the present application does not limit the arbitration manner of the micro-operation and the scalar memory access instruction. For example, the above arbitration manner can mean that the scalar memory access instruction and the micro-operation can be selected to enter the target scalar memory access instruction issue queue in turn to balance the scalar memory access instruction and the vector memory access instruction.

[0064] In some embodiments, if the above arbitration result indicates that the scalar memory access instruction enters the target scalar memory access instruction issue queue, the scalar memory access instruction is sent to the target scalar memory access instruction issue queue to store the scalar memory access instruction in the target scalar memory access instruction issue queue.

[0065] In some embodiments of the present application, before all micro-operations are dispatched to the target scalar pipelines for execution, the electronic device can detect, for each sub-operation, whether there is a free entry in the operation queue corresponding to the vector memory access instruction; If there is a free entry in the operation queue, an entry is allocated for the sub-operation in the operation queue, and the entry comprises a first field, and the first field comprises a state bit of each micro-operation of the sub-operation. After all micro-operations are dispatched to the target scalar pipelines for execution, the method further comprises: If any micro-operation corresponding to the sub-operation is executed in the corresponding target scalar pipeline, the state bit of the micro-operation in the field is set to a preset value. If all state bits in the field are set to the preset value, the entry is released from the operation queue.

[0066] After the electronic device adds the sub-operation into the operation queue, the electronic device starts to execute the sub-operation, and the execution of the sub-operation can mean that all micro-operations corresponding to the sub-operation are executed on each target scalar pipeline.

[0067] The preset value represents that the corresponding micro-operation has been executed. For example, the preset value can be 1. If all the state bits in the field are set to the preset value, it means that all micro-operations of the corresponding sub-operation have been executed, and in this case, the item is released from the operation queue, so that the item becomes a free item, and the next sub-operation can be executed conveniently.

[0068] The first field represents the completion of the micro-operations split from the corresponding sub-operation, and the bit width can be determined according to the specific implementation. For example, each sub-operation of a vector memory instruction is split into 8 micro-operations, and the bit width of the first field is 8 bits, and there are 8 state bits. The numbers of the 8 state bits can be bit 7~bit 0. Bit 7 represents that the highest 64 bits in 512 bits have been loaded, and bit 0 represents that the lowest 64 bits in 512 bits have been loaded. When a micro-operation is completed, the corresponding bit is set to 1. When the 8 bits are all 1, the item in the operation queue can be completed and exited. If the micro-operations split from a sub-operation are less than 8, the unused state bits are always 1.

[0069] In some embodiments, the data obtained after the execution of each sub-operation can be added to the corresponding data queue.

[0070] In the operation queue, an item allocated for a sub-operation can also include a second field and a third field, as well as basic information of the sub-operation.

[0071] The bit width of the second field can be 1 bit. When the first field is set to 1, it means that the corresponding item is a vector operation, and when the first field is set to 0, it means that the corresponding item is a scalar operation.

[0072] The bit width of the third field can be 1 bit, which represents the last sub-operation of the vector memory instruction in the corresponding item.

[0073] In some embodiments, if the vector memory operation to be implemented by the vector memory instruction is a load operation, the operation queue can be a load operation queue, and the data queue can be a vector load data queue. If the vector memory operation to be implemented by the vector memory instruction is a store operation, the operation queue can be a store operation queue, and the data queue can be a vector store data queue.

[0074] For example, Figure 3An example diagram of a load operation queue and a vector load data queue is shown. In each entry of the load operation queue, in addition to the basic information of the load operation, there are three extra fields: vvld (i.e., the second field), vend (i.e., the third field), and vstat (i.e., the first field). The basic information varies according to different hardware implementations. For example, the basic information can include: instruction encoding, instruction source operand, instruction destination operand, etc. The instruction encoding is used for further decoding of the instruction on the scalar pipeline to determine the specific instruction information, such as load byte, load word, load double word, etc. The instruction source operand is used to specify the registers and immediate numbers needed to calculate the load address. The instruction destination operand is used to specify the registers to which the loaded data is to be written.

[0075] The vvld field is 1 bit, and vvld = 1 indicates that the entry is a vector load operation, and vvld = 0 indicates that the entry is a scalar load operation.

[0076] The vend field is also 1 bit, and indicates that the entry is the last sub-operation of a vector load instruction. A vector load instruction can need multiple sub-operations to complete (e.g., needs to load data at multiple addresses to multiple vector registers).

[0077] The vstat field indicates the completion of the micro-operations split from the current sub-operation. The bit width is determined according to the specific implementation. For example, if each sub-operation of a vector load instruction is split into 8 micro-operations, then vstat needs 8 bits, and the 8 status bits are numbered as bit 7~bit 0. Bit 7 indicates that the highest 64 bits of 512 bits have been loaded, and so on. Bit 0 indicates that the lowest 64 bits of 512 bits have been loaded. When a micro-operation is completed, the corresponding status bit is set to 1. When all 8 status bits are 1, the entry in the load operation queue can be completed and exited. If the micro-operations split from a sub-operation are less than 8, then the unused status bits are always 1.

[0078] The data loaded by each sub-operation (i.e., vector load data) is placed in the vector load data queue. Before executing a sub-operation of a vector load instruction, it is detected whether there is a free entry in the vector load queue. If not, the sub-operation is not executed, and it is waited until there is a free entry, and then the sub-operation is executed.

[0079] As shown in FIG. 2, the load operation queue 200 and the vector load data queue 210 are shown. The load operation queue 200 is used to store the load operation information of each sub-operation of a vector load instruction. The vector load data queue 210 is used to store the data loaded by each sub-operation of a vector load instruction. Figure 4The shown is an example diagram of a store operation queue and a vector store data queue. In each entry of the load operation queue, in addition to the basic information of the store operation, there are additionally 3 fields: vvld (i.e. the second field), vend (i.e. the third field), and vstat (i.e. the first field). The basic information varies according to different hardware implementations. For example, the basic information can include: instruction encoding, instruction source operand, instruction destination operand, etc. The instruction encoding is used for further decoding of the instruction on the scalar pipeline, to determine specific instruction information, such as store byte, store word, store double word, fence, etc. The instruction source operand is used to specify the register where the data to be stored is located. The instruction destination operand is used to specify the registers and immediate numbers required to calculate the address to be stored.

[0080] The vvld field is 1 bit, and vvld = 1 indicates that the entry is a vector store operation, and vvld = 0 indicates that the entry is a scalar store operation.

[0081] The vend field is also 1 bit, indicating that the entry is the last sub-operation of a vector store instruction. A vector store instruction can require multiple sub-operations to complete (for example, multiple vector registers need to be stored to multiple addresses).

[0082] The vstat field indicates the completion of the micro-operations split from the current sub-operation. The bit width is determined according to the specific implementation. For example, if each sub-operation of a vector store instruction is split into 8 micro-operations, then vstat needs 8 bits, and the 8 status bits are numbered as bit 7~bit 0. Bit 7 indicates that the highest 64 bits of 512 bits have been stored, and so on. Bit 0 indicates that the lowest 64 bits of 512 bits have been stored. When a micro-operation is completed, the corresponding status bit is set to 1. When all 8 status bits are 1, the entry in the store operation queue can be completed and exited. If the micro-operations split from a sub-operation are less than 8, then the unused status bits are always 1.

[0083] The data stored by each sub-operation (i.e. vector store data) is placed in the vector store data queue. Before executing a sub-operation of a vector store instruction, it is detected whether there is a free entry in the vector store queue. If not, the sub-operation is not executed, and it is waited until there is a free entry, and then the sub-operation is executed.

[0084] As shown in Figure 5 The shown is another flowchart of the vector memory instruction processing method provided by the embodiment of the present application. In Figure 5In some embodiments, the decoded instruction can be a vector memory access instruction or a scalar memory access instruction. If the decoded instruction is a vector memory access instruction, the vector memory access instruction can be sent to the vector memory access instruction issue queue via the instruction issue unit. After the vector memory access instruction is output from the vector memory access instruction issue queue, the vector memory access instruction can be split and distributed to the scalar memory access instruction issue queue. If the decoded instruction is a scalar memory access instruction, the scalar memory access instruction can be sent to the scalar memory access instruction issue queue. For each scalar memory access instruction issue queue, the corresponding scalar pipeline can execute the scalar memory access instruction or micro-operation output from the scalar memory access instruction issue queue (e.g., execute the scalar memory access instruction or micro-operation via an adder in an address calculation unit in the scalar pipeline, etc.) to obtain corresponding data, and write the data into the level one data cache for loading the data. If the vector memory access instruction is used to implement a load operation, the data (i.e., vector load data) can be added to the vector load data queue, and the vector load data corresponding to all micro-operations of the vector memory access instruction can be added to the vector load data queue to indicate that the load operation is completed. If the vector memory access instruction is used to implement a store operation, the data (i.e., vector store data) can be added to the vector store data queue, and the vector store data corresponding to all micro-operations of the vector memory access instruction can be added to the vector store data queue to indicate that the store operation is completed.

[0085] It should be understood that the size of the serial number of each step in the above embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0086] According to the vector memory access instruction processing method described in the above embodiments, Figure 6 A structure diagram of a vector memory access instruction processing apparatus provided by an embodiment of the present application is shown. For ease of illustration, only parts related to the embodiments of the present application are shown.

[0087] Referring to Figure 6 The apparatus comprises: An instruction splitting module 601, configured to split a vector memory access instruction into a plurality of sub-operations; An operation processing module 602, configured to split each of the sub-operations into a plurality of micro-operations, or determine the sub-operations as the micro-operations; An operation execution module 603, configured to distribute all the micro-operations to respective scalar pipelines for execution.

[0088] In some embodiments, the apparatus further comprises: A quantity obtaining module, configured to obtain the number of free entries of each scalar memory access instruction issue queue; a target determination module, configured to determine target scalar memory access instruction issue queues from among the scalar memory access instruction issue queues with a number of free entries greater than zero; a pipeline determination module, configured to determine target scalar pipelines corresponding to the target scalar memory access instruction issue queues as target scalar pipelines.

[0089] In some embodiments, the apparatus further includes: an operation sending module, configured to send the micro-operations to each of the target scalar memory access instruction issue queues, and the number of the micro-operations sent to each of the target scalar memory access instruction issue queues does not exceed the number of free entries of the target scalar memory access instruction issue queue; The operation execution module 603 is specifically configured to: When the micro-operations are output from the target scalar memory access instruction issue queue, the micro-operations are distributed to the target scalar pipeline corresponding to the target scalar memory access instruction issue queue.

[0090] In some embodiments, the operation sending module is specifically configured to: If there is a scalar memory access instruction that needs to enter the target scalar memory access instruction issue queue, the micro-operations and the scalar memory access instruction are arbitrated to obtain an arbitration result; If the arbitration result indicates that the micro-operations enter the target scalar memory access instruction issue queue, the micro-operations are sent to the target scalar memory access instruction issue queue.

[0091] In some embodiments, the apparatus further includes: a free entry detection module, configured to, before the micro-operations are distributed to the target scalar pipelines for execution, detect, for each of the sub-operations, whether there is a free entry in an operation queue corresponding to the vector memory access instruction; an entry allocation module, configured to, if there is a free entry in the operation queue, allocate an entry for the sub-operation in the operation queue, the entry including a first field, and the first field including state bits of micro-operations of the sub-operation; a state processing module, configured to, after the micro-operations are distributed to the target scalar pipelines for execution, if any of the micro-operations corresponding to the sub-operation is executed on the target scalar pipeline corresponding to the micro-operation and is completed, set a state bit of the micro-operation in the field to a preset value; a release module, configured to, if all the state bits in the field are set to the preset value, release the entry from the operation queue.

[0092] In some embodiments, the apparatus further includes: determine a split level of the vector memory access instruction based on an instruction type of the vector memory access instruction; The above-mentioned operation processing module 602 is specifically used for: If the splitting level of the vector memory access instruction is two-level splitting, then the sub-operation is split into multiple micro-operations; If the splitting level of the vector memory access instruction is level one, then the sub-operation is determined as the micro-operation.

[0093] In some embodiments, the above-described apparatus further includes: The instruction sending module is configured to, before splitting the vector memory access instruction into multiple sub-operations, further include: sending the vector memory access instruction to the vector memory access instruction sending queue; The aforementioned instruction splitting module 601 is specifically used for: When the vector memory access instruction is output from the vector memory access instruction issuance queue, the vector memory access instruction is split into multiple sub-operations.

[0094] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0095] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 7 As shown, the electronic device 7 of this embodiment includes: at least one processor 70 ( Figure 7 (Only one is shown in the diagram), memory 71, and computer program 72 stored in said memory 71 and executable on said at least one processor 70, which, when executed, implements the steps in any of the above method embodiments.

[0096] The electronic device may include, but is not limited to, a processor 70 and a memory 71. Those skilled in the art will understand that... Figure 7 This is merely an example of electronic device 7 and does not constitute a limitation on electronic device 7. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0097] The processor 70 can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0098] The memory 71 can be an internal storage unit of the electronic device 7 in some embodiments, such as a hard disk or a memory of the electronic device 7. The memory 71 can also be an external storage device of the electronic device 7 in other embodiments, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 7. Further, the memory 71 can include both the internal storage unit and the external storage device of the electronic device 7. The memory 71 is used to store an operating system, an application program, a boot loader, data, and other programs, such as program codes of the computer program, etc. The memory 71 can also be used to temporarily store data that has been output or will be output.

[0099] It can be clearly understood by those skilled in the art that, for the convenience and brevity of description, only the division of the above functional units and modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to complete all or part of the above-described functions. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically independently, or two or more units can be integrated in one unit, and the integrated unit can be realized in the form of hardware or in the form of a software functional unit. In addition, the specific names of the functional units and modules are only for the convenience of mutual distinction, and do not limit the protection scope of the present application. The specific working process of the units and modules in the system can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0100] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the present application can implement all or part of the processes in the above-mentioned embodiment methods through a computer program to instruct related hardware to complete, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by a processor, the steps of each method embodiment described above can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms. The computer readable medium at least includes any entity or device capable of carrying the computer program code to the device / equipment, recording medium, computer memory, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), electrical carrier signal, telecommunication signal and software distribution medium. For example, U disk, mobile hard disk, magnetic disk or optical disk, etc.

[0101] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0102] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0103] In the embodiments provided by the present application, it should be understood that the disclosed apparatus / equipment and method can be implemented by other ways. For example, the above-mentioned apparatus / equipment embodiments are only schematic, for example, the division of the modules or units is only a logical function division, and there can be another division way in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection between each other can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0105] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of processing a vector memory reference instruction, the method comprising: The method comprises: splitting a vector memory access instruction into a plurality of sub-operations; for each of the sub-operations, splitting the sub-operation into a plurality of micro-operations, or determining the sub-operation as the micro-operation; distributing all the micro-operations to target scalar pipelines for execution.

2. The vector memory reference instruction processing method of claim 1, wherein, Before the distributing, the method further comprises: obtaining the number of empty entries in each scalar memory access instruction issue queue; from the scalar memory access instruction issue queues with the number of empty entries greater than zero, determining target scalar memory access instruction issue queues; determining target scalar pipelines corresponding to the target scalar memory access instruction issue queues.

3. The vector memory reference instruction processing method of claim 2, wherein, Before the distributing, the method further comprises: for each of the target scalar memory access instruction issue queues, sending the micro-operations to the target scalar memory access instruction issue queue, the number of the micro-operations sent to the target scalar memory access instruction issue queue being no more than the number of empty entries in the target scalar memory access instruction issue queue; the distributing comprises: when the micro-operations are output from the target scalar memory access instruction issue queue, distributing the micro-operations to the corresponding target scalar pipeline.

4. The vector memory reference instruction processing method of claim 3, wherein, The sending comprises: if there is a scalar memory access instruction that needs to enter the target scalar memory access instruction issue queue, arbitrating the micro-operation and the scalar memory access instruction to obtain an arbitration result; if the arbitration result indicates that the micro-operation enters the target scalar memory access instruction issue queue, sending the micro-operation to the target scalar memory access instruction issue queue.

5. The vector memory reference instruction processing method of any one of claims 1-4, wherein, Before the distributing, the method further comprises: for each of the sub-operations, detecting whether there is an empty entry in an operation queue corresponding to the vector memory access instruction; if there is an empty entry in the operation queue, allocating an entry for the sub-operation in the operation queue, the entry comprising a first field, the first field comprising state bits of micro-operations of the sub-operation; After the distributing, the method further comprises: if any of the micro-operations corresponding to the sub-operation is executed on the corresponding target scalar pipeline, setting the state bit of the micro-operation in the field to a preset value; if all the state bits in the field are set to the preset value, releasing the entry from the operation queue.

6. The vector memory reference instruction processing method of any one of claims 1-4, wherein, Before the splitting or determining, the method further comprises: based on the instruction type of the vector memory access instruction, determining the splitting level of the vector memory access instruction; the splitting comprises: if the splitting level of the vector memory access instruction is two-level splitting, splitting the sub-operation into a plurality of micro-operations; the determining comprises: if the splitting level of the vector memory access instruction is one-level splitting, determining the sub-operation as the micro-operation.

7. The vector memory reference instruction processing method of any one of claims 1-4, wherein, Before the vector memory instruction is split into a plurality of sub-operations, further comprising: sending the vector memory instruction to a vector memory instruction issue queue; the vector memory instruction is split into a plurality of sub-operations, comprising: when the vector memory instruction is outputted from the vector memory instruction issue queue, the vector memory instruction is split into a plurality of the sub-operations.

8. A vector memory reference instruction processing apparatus, characterized by, comprising: an instruction split module, configured to split a vector memory instruction into a plurality of sub-operations; an operation processing module, configured to split, for each of the sub-operations, the sub-operation into a plurality of micro-operations, or determine the sub-operation as the micro-operations; an operation execution module, configured to distribute all the micro-operations to respective target scalar pipelines for execution.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program, so that the electronic device implements the vector memory instruction processing method in any one of claims 1 to 7.

10. A computer program product, characterised in that, The computer program is executed, so that the vector memory instruction processing method in any one of claims 1 to 7 is executed.

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