Fine-grained cache partition locking method based on RISC-V extension instruction and processor

Abstract

The invention is suitable for the technical field of microprocessor system structures, on-chip multi-core systems and embedded real-time computing, and provides a fine-grained cache partition locking method and processor based on RISC-V. The method comprises the steps that a Zicpl extension instruction family is newly added in an RISC-V instruction set system structure, and the Zicpl extension instruction family comprises a LOCK.CP instruction, a UNLOCK.CP instruction, a TESTLOCK.CP instruction and a SET.CP instruction; a partition lock table is additionally arranged on the cache controller side of a processor, the partition lock table comprises a plurality of entries, and each entry comprises an owner field, a timeout field and a valid field; adding a lock flag bit and a partition identification field in a Tag region of the cache memory; the real-time performance and the system energy efficiency can be remarkably improved, the compatibility of software and hardware and the feasibility of large-scale mass production are considered, and remarkable industrial and economic values are achieved.

Description

Technical Field

[0001] This invention relates to the fields of microprocessor architecture, on-chip multi-core systems, and embedded real-time computing technology, specifically a fine-grained cache partitioning lock method and processor based on RISC-V extended instructions. Background Technology

[0002] In current computer systems, the cache, as a critical component between the processor and memory, directly impacts the overall system efficiency. However, numerous problems exist when multi-core processors share a cache, and current technologies have significant shortcomings in cache partition locking: Software spinlocks / mutexes (such as pthread-mutex, POSIX thread mutexes, and spinlocks) are simple to implement and tightly coupled with the operating system, but they require multiple accesses to the cache line during lock contention, which can easily cause bus storms and cannot be perceived by the granularity of the hardware cache. Techniques such as PageColoring, WayPartition, and CAT (ClassofService) color physical pages during the page allocation phase through the operating system or firmware, or use related technologies to set priorities for cache paths. However, static allocation leads to decreased utilization and the inability to preempt / release partitions as needed during task execution. The RISC V-A atomic instruction extension only provides consistency guarantees at the word / double-word granularity of memory and cannot directly perform mutual exclusion on the hardware resource of "cache partition". Intel® Resource Director Technology (RDT) only supports allocation technology for the last level cache (LLC) and cannot achieve fine-grained locking control of L1 / L2 cache; The ARMv8.3 lock extension instructions (STILP, Store-ReleasewithImmediateLoadPair / LDAPR, Load-AcquirePC-Relative) only address memory order consistency issues and do not involve cache physical partition control.

[0003] Existing technologies suffer from several drawbacks, including the lack of "hardware-level" reentrant locks for cache partitions or lines, the consumption of CPU cycles for spinning or polling in purely software solutions, the inability of real-time systems to meet worst-case execution time requirements of relevant functional / safety specifications under high load or jitter scenarios, and the coarse-grained isolation of existing hardware-assisted solutions, which cannot adapt to dynamic task loads. Therefore, there is an urgent need to provide a fine-grained cache partition locking method and processor based on RISC-V extended instructions to overcome the shortcomings in current practical applications. Summary of the Invention

[0004] The purpose of this invention is to provide a fine-grained cache partitioning lock method and processor based on RISC-V extended instructions, which effectively solves the problems in the background art.

[0005] This invention is implemented as follows: a fine-grained cache partition locking method based on RISC-V extended instructions, which includes the following steps: The RISC-V instruction set architecture introduces a new Zicpl extended instruction family, which includes the LOCK.CP, UNLOCK.CP, TESTLOCK.CP, and SET.CP instructions. A partition lock table (PLT) is added on the processor's cache controller side. The partition lock table contains multiple entries, each of which includes an owner field, a timeout field, and a valid field. Add a lock flag (L) and a partition identifier field (part_id) to the Tag area of ​​the cache memory. When the LOCK.CP instruction is executed, the processor accesses the partition lock table. If the valid field of the target partition is 0, the owner field of the partition is set to the current hardware thread ID and the valid field is set to 1, and the lock flag of all existing tags in the partition is updated to 1. If the valid field of the target partition is 1 and the owner field is consistent with the current hardware thread ID, success is returned. If the valid field of the target partition is 1 and the owner field is inconsistent with the current hardware thread ID, failure is returned.

[0006] As a further aspect of the present invention, a timeout mechanism is also included. When the timeout field reaches a predetermined threshold, the lock of the corresponding partition is automatically released, and a CPLOCK_TIMEOUT exception is triggered and submitted to the processor exception controller.

[0007] As a further aspect of the present invention, the SET.CP instruction is used to dynamically modify the mapping relationship between cache lines and partitions to support hot migration.

[0008] As a further aspect of the present invention, it also includes adding a configuration register (CPCFG) in the privileged architecture. The configuration register is used to set the partition granularity; The partitioning granularity includes cache-line level, cache-set level, and cache-way level.

[0009] As a further aspect of the present invention, it also includes a newly added dedicated register and a control and status register (CSR), wherein the dedicated register and the control and status register include: The Cache Partition Identifier (CPID) register, implemented in 5-bit hardware, is used to store the target partition number of the current operation and supports 32 independent partitions. The Cache Partition Lock (CPLK) register has a bit width equal to the maximum number of partitions, and each bit corresponds to the lock state of the cache partition identifier. The Global Partition Lock Status Register (CPLK_STATCSR) is a read-only register used to indicate the global partition lock status.

[0010] As a further aspect of the present invention: the partition lock table uses a dual-port block random access memory (BRAM), the write end of the dual-port block random access memory comes from the CPU, and the read end interacts with the cache state machine.

[0011] As a further aspect of the present invention: the owner field is used to identify the hardware thread ID holding the lock, the timeout field is a counter used for timeout counting, and the valid field is used to indicate whether the entry is valid.

[0012] As a further aspect of the present invention, it also includes an exception handling step: when the mstatus.WFI timer expires or the hart_reset event occurs, the corresponding row of the partition lock table is automatically cleared; it supports manual clearing of dangling locks via mcmiscCSR for use by the debugger; and it implements automatic lock release upon timeout through the timeout field to prevent deadlock.

[0013] As a further aspect of the present invention: the UNLOCK.CP command is used to unlock a specified partition; The TESTLOCK.CP command is used to query the lock status of a specified partition.

[0014] A processor includes an instruction decoder, a partition lock table (PLT), and a cache memory, wherein: The instruction decoder is used to identify and execute the fine-grained cache partition locking method based on RISC-V extended instructions as described above; The partition lock table contains multiple entries, each of which includes an owner field, a timeout field, and a valid field. The owner field is used to identify the hardware thread ID that holds the lock, the timeout field is a counter used for timeout counting, and the valid field is used to indicate whether the entry is valid. The Tag area of ​​the cache memory includes a lock flag (L) and a partition identifier field (part_id).

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. Average latency: A single locking operation is completed in 2-3 cycles, which is 72% lower than Linux spinlock (based on the Xilinx Versal ACAP (Adaptive Compute Acceleration Platform) VC1902 prototype board, tested at 100MHz clock).

[0016] 2. Power consumption: SPEC-cpu2006 (standard performance evaluation suite) *4 parallel compilation, SoC power consumption decreased by 9.4% (Synopsys PrimePower@TSMC28nmHPC process simulation).

[0017] 3. Real-time performance: The peak jitter of the vehicle ECU (Electronic Control Unit) control-loop decreased from 18µs to 6µs (measured by AUTOSAROSv4.3 task scheduler tracker).

[0018] 4. Code intrusiveness: No need to modify the existing kernel scheduler, only need to call relevant instructions at the user level or hypervisor (virtual machine manager).

[0019] This invention can significantly improve real-time performance and system energy efficiency, while taking into account hardware and software compatibility and the feasibility of large-scale mass production, and has significant industrial and economic value. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the overall structure of the processor of the present invention; Figure 2 This is a schematic diagram of the timing waveform of the LOCK.CP instruction in this invention; Figure 3 This is a schematic diagram of the partitioning and cache-way mapping of the present invention; Figure 4 This is a diagram of the PLT data structure format of the present invention; Figure 5 This is the PLT state transition diagram of the present invention. Detailed Implementation

[0022] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] The present invention will be further explained below with reference to specific embodiments.

[0024] Please see Figures 1-5 The present invention provides a fine-grained cache partitioning lock method and processor based on RISC-V extended instructions. The fine-grained cache partitioning lock method based on RISC-V extended instructions includes the following steps: The RISC-V instruction set architecture introduces a new Zicpl extended instruction family, which includes the LOCK.CP, UNLOCK.CP, TESTLOCK.CP, and SET.CP instructions. The SET.CP instruction is used to dynamically modify the mapping relationship between cache lines and partitions to support hot migration; The UNLOCK.CP command is used to unlock a specified partition; The TESTLOCK.CP command is used to query the lock status of a specified partition; A partition lock table (PLT) is added to the processor's cache controller side. The PLT contains multiple entries, each including an owner field, a timeout field, and a valid field. The PLT uses a dual-port block random access memory (BRAM), with the write end of the BRAM coming from the CPU and the read end interacting with the cache state machine. The owner field is used to identify the hardware thread ID holding the lock, the timeout field is a counter used for timeout counting, and the valid field is used to indicate whether the entry is valid. Add a lock flag (L) and a partition identifier field (part_id) to the Tag area of ​​the cache memory. When the LOCK.CP instruction is executed, the processor accesses the partition lock table. If the valid field of the target partition is 0, the owner field of the partition is set to the current hardware thread ID and the valid field is set to 1, and the lock flag of all existing tags of the partition is updated to 1. If the valid field of the target partition is 1 and the owner field is consistent with the current hardware thread ID, success is returned. If the valid field of the target partition is 1 and the owner field is inconsistent with the current hardware thread ID, failure is returned. It also includes a timeout mechanism, which automatically releases the lock of the corresponding partition and triggers a CPLOCK_TIMEOUT exception to be submitted to the processor exception controller when the timeout field reaches a predetermined threshold. This also includes the addition of a configuration register (CPCFG) in the privileged architecture. The configuration register is used to set the partition granularity; The partitioning granularity includes cache-line level, cache-set level, and cache-way level; It also includes new dedicated registers and control and status registers (CSRs), which include: The Cache Partition Identifier (CPID) register, implemented in 5-bit hardware, is used to store the target partition number of the current operation and supports 32 independent partitions. The Cache Partition Lock (CPLK) register has a bit width equal to the maximum number of partitions, and each bit corresponds to the lock state of the cache partition identifier. The Global Partition Lock Status Register (CPLK_STATCSR) is a read-only register used to indicate the global partition lock status. It also includes exception handling steps, such as automatically clearing the corresponding row in the partition lock table when the mstatus.WFI timer expires or the hart_reset event occurs; it supports manual clearing of dangling locks via mcmiscCSR for debugger use; and it implements automatic lock release upon timeout through the timeout field to prevent deadlock.

[0025] In this embodiment, the present invention aims to solve the problems of decreased real-time performance and increased power consumption caused by shared cache contention in multi-core processors, and provides an instruction-level, hardware-accelerated, granularly configurable cache partition locking mechanism to achieve the following: Complete partition locking or unlocking with a minimum of one instruction; Provide a defined cache footprint for applications or virtual machines without intruding on the operating system kernel; It is compatible with the current RISC-V standard and retains the integrity of vector, floating-point, compressed, and privileged architectures. Supports automatic lock reclamation upon lock failure to prevent deadlock; This can be achieved through the following specific technical solutions: 1. Added a special-purpose register and a CSR (Control and Status Register). CPID (CachePartitionIdentifier) ​​register: 5-bit hardware implementation, stores the target partition number of the current operation, and supports 32 independent partitions; CPLK (CachePartitionLoCK) register: bit width = maximum number of partitions, each bit corresponds to the CPID lock state; CPLK_STATCSR: Read-only, global partition lock status; CPCFGCSR: Configures the partition granularity (0: cacheline; 1: cacheset; 2: cacheway).

[0026] 2. Define the Zicpl instruction extension family LOCK.CPrd,rs1: Locks the partition specified by rs1. rd returns 0 (success) / 1 (failure). UNLOCK.CPrs1: Unlock; TESTLOCK.CPrd,rs1: Query the lock status; SET.CPrd,rs1,rs2: Dynamically modify cacheline → partition mapping, supporting hot migration.

[0027] Developers can explicitly enable assembly via `.option arch,+zicpl`.

[0028] Cache controller hardware modification: Add a 1-bit L (lock) bit and a 4-bit part_id (partition number) field to the TagRAM (tag RAM); Design a PartitionLockTable (PLT) with capacity = number of partitions × (owner_hartid + valid + timeout), where: owner: 5 digits (supports up to 32 hardware threads) timeout: 4 bits (timeout threshold = 2^4 * base clock cycle) valid: 1 bit PLT uses a dual-port BRAM (Block RAM) (synchronous), with the write end coming from the CPU and the read end interacting with the cache state machine.

[0029] Microarchitecture process (taking LOCK.CP as an example): a) The ID (Instruction Decode) stage identifies Zicpl and initiates PLT port access; b) If the target partition valid==0, then write hartid&valid=1; and set the L bit of all existing tags in that partition to 1. c) If valid==1 and owner==hartid, return success directly (re-entrant is allowed); d) If owner ≠ hartid, return failure and bootstrap software to either spin or hibernate; e) Timeout mechanism: When the timeout in the PLT is full, a lock release signal is automatically generated and a CPLOCK_TIMEOUT exception is triggered.

[0030] Exception handling: When the mstatus.WFI timer expires or a hart_reset event occurs, the PLT automatically clears the corresponding row.

[0031] Supports manual clearing of hanging locks in mcmisc CSR for debugger use.

[0032] Deadlock prevention: Hardware watchdogs use a timeout field to automatically release the lock upon timeout; The above technical solution can achieve the following technical effects: 1. Average latency: A single locking operation is completed in 2-3 cycles, which is 72% lower than Linux spinlock (based on the Xilinx Versal ACAP (Adaptive Compute Acceleration Platform) VC1902 prototype board, tested at 100MHz clock).

[0033] 2. Power consumption: SPEC-cpu2006 (standard performance evaluation suite) *4 parallel compilation, SoC power consumption decreased by 9.4% (Synopsys PrimePower@TSMC28nmHPC process simulation).

[0034] 3. Real-time performance: The peak jitter of the vehicle ECU (Electronic Control Unit) control-loop decreased from 18µs to 6µs (measured by AUTOSAROSv4.3 task scheduler tracker).

[0035] 4. Code intrusiveness: No need to modify the existing kernel scheduler, only need to call relevant instructions at the user level or hypervisor (virtual machine manager).

[0036] in, Figure 1The display shows the CPU core, L1 / L2 cache, PLT, and Zicpl decoder. The core cluster contains multiple RISC-V hardware threads (Hart) that support Zicpl extensions; the cache hierarchy is a private L1 cache + shared L2 cache (integrated PLT module); the Zicpl path is indicated by red arrows showing the hardware path from LOCK / UNLOCK instructions to the PLT; the PLT structure records the partition lock status (owner + timeout + valid).

[0037] Figure 2 The entire process of requesting, arbitrating, writing the Tag-L bit, and responding is demonstrated. Key signals include PLT access initiated in the ID phase, Tag update completed in the EX phase with cache line locking, and the timeout mechanism activating the hardware watchdog in the WB phase.

[0038] Figure 3 The demonstration shows how 8-way L2 assigns way0-1 to partition 0 and way2-3 to partition 1. In static partitions, Set0 is fixed to allocate way groups (suitable for real-time tasks), while in dynamic partitions, Set1 is dynamically adjusted according to the SET.CP instruction (suitable for cloud environments). The CPCFG register can be configured with three granularities: 00: cache-line granularity, 01: cache-set granularity, and 10: cache-way granularity.

[0039] Figure 4 The data structure is in PLT format, with fields including owner (5 bits), timeout (4 bits), and valid (1 bit). owner is the HartID (0-31) of the lock holder, timeout is a 4-bit binary counter (0-15 cycles), and valid is the lock status flag. When timeout decreases from 15 to 0, it automatically triggers operations such as clearing the valid bit, resetting owner to 0, and committing a CPLOCK_TIMEOUT exception.

[0040] Figure 5 Includes a timeout exception path, where Timeout→Exception indicates that the hardware automatically releases the lock and submits the exception; the security mechanism refers to clearing the owner and valid bits after the exception is triggered.

[0041] Please see Figures 1-5 An embodiment of the present invention provides a processor including an instruction decoder, a partition lock table (PLT), and a cache memory, wherein: The instruction decoder is used to identify and execute the fine-grained cache partition locking method based on RISC-V extended instructions as described above; The partition lock table contains multiple entries, each of which includes an owner field, a timeout field, and a valid field. The owner field is used to identify the hardware thread ID that holds the lock, the timeout field is a counter used for timeout counting, and the valid field is used to indicate whether the entry is valid. The Tag area of ​​the cache memory includes a lock flag (L) and a partition identifier field (part_id).

[0042] In this embodiment, the overall architecture design is as follows: Target instruction set: RV64GC (64-bit RISC-V, including floating-point, compression and other extensions) + Zicpl (this invention) + Sv39 virtual memory; Processor core count: 1 to 128; all share the last level cache (LLC); Cache configuration: L1 32 KiB×2 (I / D); L2 1 MiB, 8-way, can be divided into 16 partitions; L3 optional.

[0043] The detailed encoding of the instruction set extension is shown in Table 1: Table 1. Detailed Encoding of Instruction Set Extensions instruction opcode(6b) funct3(3b) funct7(7b) Format illustrate LOCK.CP 001011 000 0b0111011 I-type Lock UNLOCK.CP 001011 001 0b0111011 I-type Unlock TESTLOCK.CP 001011 010 0b0111011 I-type Query SET.CP 0110011 000 0b0111011 R-type Configuration In Table 1, the instruction parser is independent of the standard ALU / CSR path, and the LSU request queue is reused to avoid pipeline leakage.

[0044] The cache controller hardware implementation is as follows: PLT enables timing-critical path optimization: verilog / / Three-stage flow design always@(posedge clk)begin if(zicpl_req_valid)begin stage1<=PLT[target_id]; / / First beat: Read PLT stage2<=check_owner(stage1); / / Second stage: Ownership verification stage3<=update_tag(stage2); / / Third stage: Tag update end end Tag extension: Original 54-bit Tag + L(1b) + part_id(4b); laid out in one go using SRAM hard macro method; power consumption increase <1%.

[0045] Arbitration logic: If Load / Store hits and Tag.L=1 and part_id is locked by another heart → return NACK; LSU enters retry.

[0046] The system software supports the following: Boot phase: OpenSBI (RISC-V boot firmware) writes the CPID based on the hardware thread ID in sbi_hart_init().

[0047] Linux Kernel (≥6.6): Added ioctl (input / output control) RISCVCACHEP_{LOCK,UNLOCK,SET}; added Lock Miss (lock acquisition failure) events to perf_event_open. Security mechanisms: The S (Supervisor Mode) mode adds a countereren CSR to control user-mode access permissions; The Hypervisor assigns a virtual partition ID to the Guest via hcpcfg CSR.

[0048] Compiler support: The GCC / LLVM backend now includes -march=rv64gc_zicpl; embedded critical code is automatically generated as LOCK.CP / UNLOCK.CP.

[0049] The functional and performance tests are as follows: Lock-Microbench: 8-core CPUs competing for 1 partition, average locking time is 9.2ns; software mutex takes 34.1ns.

[0050] mysql-oltp (Online Transaction Processing): TPS (Transactions Per Second) increased by 7%, P99 (99th percentile) latency decreased by 16%.

[0051] 5G base station applications: Packet loss rate for latency-sensitive services (URLLC, Ultra Reliable Low Latency Communication) decreased by 82%.

[0052] Further improvements are as follows: The PLT was changed from a centralized to a distributed per-bank structure to improve scalability for 64-core and above. Combined with RISC-V PMP (Physical Memory Protection), it achieves integrated access control of "security domain + cache lock"; For AI (artificial intelligence) inference scenarios, row-level locking of the activation graph is performed in conjunction with Tensor cache to reduce DRAM (dynamic random access memory) access.

[0053] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. Average latency: A single locking operation is completed in 2-3 cycles, which is 72% lower than Linux spinlock (based on the Xilinx Versal ACAP (Adaptive Compute Acceleration Platform) VC1902 prototype board, tested at 100MHz clock) (see Table 2 for specific data).

[0054] Table 2: Actual Test Results of Task Scheduling Tracker

[0055] 2. Power consumption: SPEC-cpu2006 (standard performance evaluation suite) *4 parallel compilation, SoC power consumption decreased by 9.4% (Synopsys PrimePower@TSMC28nmHPC process simulation).

[0056] 3. Real-time performance: The peak jitter of the vehicle ECU (Electronic Control Unit) control-loop decreased from 18µs to 6µs (measured by AUTOSAROSv4.3 task scheduler tracker).

[0057] 4. Code intrusiveness: No need to modify the existing kernel scheduler, only need to call relevant instructions at the user level or hypervisor (virtual machine manager).

[0058] In summary, this invention addresses the technical gap in existing multi-core processors' shared cache lacking hardware-level fine-grained locking. It proposes a partitioning locking method based on RISC-V instruction extensions and combined with microarchitectural modifications to the cache controller. This method can significantly improve real-time performance and system energy efficiency, while also ensuring hardware and software compatibility and scalable mass production feasibility, thus possessing significant industrial and economic value.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fine-grained cache partitioning lock based on RISC-V extension instructions, characterized in that, The method comprises the following steps: A Zicpl extended instruction family is added in the RISC-V instruction set architecture, and the Zicpl extended instruction family comprises a LOCK.CP instruction, an UNLOCK.CP instruction, a TESTLOCK.CP instruction and a SET.CP instruction; A partition lock table is additionally arranged on the cache controller side of the processor, and the partition lock table comprises a plurality of entries, and each entry comprises an owner field, a timeout field and a valid field; A lock flag and a partition identifier field are added in the Tag region of the cache memory; When the LOCK.CP instruction is executed, the processor accesses the partition lock table, if the valid field of the target partition is 0, the owner field of the partition is set as the current hardware thread ID and the valid field is set as 1, and the lock flag of all existing Tags of the partition is updated to 1; if the valid field of the target partition is 1 and the owner field is consistent with the current hardware thread ID, success is returned; if the valid field of the target partition is 1 and the owner field is inconsistent with the current hardware thread ID, failure is returned.

2. The method of claim 1, wherein the RISC-V extension instruction is based on, A timeout mechanism is further included, when the timeout field reaches a predetermined threshold, the lock of the corresponding partition is automatically released, and a CPLOCK_TIMEOUT exception is triggered and submitted to the processor exception controller.

3. The method of claim 1, wherein the RISC-V extension instruction based fine-grained cache partitioning lock is based on a RISC-V extension instruction. The SET.CP instruction is used to dynamically modify the mapping relationship between the cache line and the partition, so as to support hot migration.

4. The method of claim 1, wherein the RISC-V extension instruction based fine-grained cache partitioning lock is based on a RISC-V extension instruction. A configuration register is further added in the privileged architecture; The configuration register is used to set the partition granularity; The partition granularity comprises a cache-line level, a cache-set level and a cache-way level.

5. The method of claim 1, wherein the RISC-V extension instruction based fine-grained cache partitioning lock is based on a RISC-V extension instruction. A special register and a control and state register are further added, and the special register and the control and state register comprise: A cache partition identifier register, the cache partition identifier register is implemented by 5-bit hardware, and is used to save the target partition number in the current operation, and supports 32 independent partitions; A cache partition lock register, the cache partition lock register has a bit width equal to the maximum number of partitions, and each bit corresponds to the lock state of the cache partition identifier; A global partition lock state register, the global partition lock state register is a read-only register, and is used to indicate the global partition lock state.

6. The method of claim 1, wherein the RISC-V extension instruction based fine-grained cache partitioning lock is based on a RISC-V extension instruction. The partition lock table adopts a dual-port block random memory, and the write end of the dual-port block random memory comes from the CPU, and the read end interacts with the cache state machine.

7. The method of claim 1, wherein the RISC-V extension instruction based fine-grained cache partitioning lock is based on a RISC-V extension instruction. The owner field is used to identify the hardware thread ID holding the lock, the timeout field is a counter for timeout counting, and the valid field is used to indicate whether the entry is valid.

8. The method of claim 1, wherein the RISC-V extension instruction based fine-grained cache partitioning lock is based on a RISC-V extension instruction. An exception processing step is further included, when the mstatus.WFI timer expires or the hart_reset event occurs, the partition lock table is automatically emptied, the suspended lock is manually cleaned up through the mcmisc CSR, and the debugger is used; the lock is automatically released through the timeout field, so as to prevent deadlock.

9. The method of claim 1, wherein the RISC-V extension instruction based fine-grained cache partitioning lock is based on a RISC-V extension instruction. The UNLOCK.CP instruction is used for unlocking the specified partition. The TESTLOCK.CP instruction is used to query the lock status of a specified partition.

10. A processor, comprising: It comprises an instruction decoder, a partition lock table and a cache memory, wherein: The instruction decoder is used to identify and execute the fine-grained cache partition lock method based on the RISC-V extension instruction as claimed in any one of claims 1-9; The partition lock table comprises a plurality of entries, each entry comprising an owner field, a timeout field and a valid field, wherein the owner field is used to identify the hardware thread ID holding the lock, the timeout field is a counter for timeout counting, and the valid field is used to indicate whether the entry is valid; The Tag area of the cache memory comprises a lock flag bit and a partition identification field.

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