Memory processing method and device, storage medium, electronic equipment and chip

Abstract

The invention provides a memory processing method and device, a storage medium, electronic equipment and a chip, and relates to the technical field of computers.The method comprises the steps that firstly, the application memory size corresponding to a memory application request is obtained; determining a target memory region from the multi-level memory region according to the size of the applied memory; and then performing memory allocation in the target memory area according to the applied memory size. Wherein the multi-level memory area comprises a first memory area, a second memory area and a third memory area which are not overlapped with one another, the first memory area enables small-block memory distribution to be more concentrated, and fragmentation caused by small-block memory discrete distribution in traditional dynamic distribution is avoided; the second memory area is used for centrally managing the resident memory and does not occupy the dynamic memory area; in the third memory area, the small memory and the resident memory are shunted by the first two areas, so that the residual space is more complete, the distribution failure caused by fragments when the large memory is applied is reduced, and the utilization efficiency of the large memory is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a memory processing method, apparatus, storage medium, electronic device and chip. Background Technology

[0002] Memory management technology is one of the core directions for operating system and underlying system optimization. With the popularization of multi-core processors, heterogeneous computing and artificial intelligence (AI) applications, the problem of low memory utilization caused by memory fragmentation is becoming increasingly prominent. Summary of the Invention

[0003] This disclosure provides a memory processing method, apparatus, storage medium, electronic device, and chip, with the main objective of solving the problem of low memory utilization caused by memory fragmentation.

[0004] According to a first aspect of the present disclosure, a memory processing method is provided, characterized in that the method includes: In response to a memory request, obtain the size of the memory to be requested corresponding to the memory request; Based on the requested memory size, a target memory region is determined from a multi-level memory region, wherein the multi-level memory region includes a first memory region, a second memory region, and a third memory region that do not overlap with each other. The first memory region is used to centrally manage memory requests with a memory size less than or equal to a preset threshold. The second memory region is used to centrally manage resident memory. The third memory region is used to centrally manage memory requests with a memory size greater than the preset threshold. Memory is allocated in the target memory region according to the requested memory size.

[0005] Optionally, determining the target memory region from multi-level memory regions based on the requested memory size includes: If the requested memory size is less than or equal to the preset threshold, then the first memory region is determined as the target memory region.

[0006] Optionally, the first memory region includes multi-level memory pools, and the multi-level memory pools have different memory sizes; The process of allocating memory in the target memory region according to the requested memory size includes: Among the multi-level memory pools, at least one memory pool of the smallest size that can meet the requested memory size requirement is determined; If there is an unfilled free memory pool in the at least one memory pool, and there is a free memory block in the free memory pool corresponding to the requested memory size, then memory is allocated in the free memory pool according to the requested memory size, and a memory pointer of the allocated memory is obtained.

[0007] Optionally, the step of allocating memory in the target memory region according to the requested memory size further includes: If there is no free memory pool in the at least one memory pool, a new memory pool with the same memory size as the at least one memory pool is created in the first memory region, and memory is allocated in the newly created memory pool according to the requested memory size to obtain the memory pointer of the allocated memory.

[0008] Optionally, determining the target memory region from multi-level memory regions based on the requested memory size includes: If the requested memory size is greater than the preset threshold, then the third memory region is determined as the target memory region.

[0009] Optionally, the method further includes: In response to a memory release request, obtain a pointer to the memory to be released; Based on the memory pointer, the memory release area is determined from the multi-level memory region; The memory to be released is released in the memory release area.

[0010] Optionally, releasing the memory to be released in the memory release area includes: Based on the memory pointer, the memory release area is determined to be the first memory area; Obtain the memory block corresponding to the memory pointer, and determine the target memory pool to which the memory block belongs in the first memory region; The memory block is marked as free and added to the free list of the target memory pool.

[0011] Optionally, the method further includes: If it is determined from the free list that all memory blocks in the target memory pool are in a free state, then the target memory pool is released back to the first memory region.

[0012] Optionally, before obtaining the requested memory size corresponding to the memory request in response to the memory request, the method further includes: The multi-level memory region is obtained through initialization.

[0013] Optionally, the initialization to obtain the multi-level memory region includes: For the second memory region, at least one of the following will be allocated to the second memory region via a static global variable to form resident memory: The number of times memory is allocated and freed within a preset time window exceeds a preset number; Memory whose lifecycle is the same as the system's runtime cycle will not be released.

[0014] According to a second aspect of the present disclosure, a memory processing apparatus is provided, comprising: The acquisition module is configured to acquire the size of the memory to be requested in response to a memory request request. The determination module is configured to determine a target memory region from a multi-level memory region based on the requested memory size. The multi-level memory region includes a first memory region, a second memory region, and a third memory region that do not overlap. The first memory region is used to centrally manage memory requests with a memory size less than or equal to a preset threshold. The second memory region is used to centrally manage resident memory. The third memory region is used to centrally manage memory requests with a memory size greater than the preset threshold. The allocation module is configured to allocate memory in the target memory region according to the requested memory size.

[0015] Optionally, the determining module is specifically configured to determine the first memory region as the target memory region if the requested memory size is less than or equal to the preset threshold.

[0016] Optionally, the first memory region includes multi-level memory pools, and the multi-level memory pools have different memory sizes; The allocation module is specifically configured to determine at least one memory pool of the minimum size that can meet the requested memory size requirement in the multi-level memory pool; if there is an unfilled free memory pool in the at least one memory pool, and there is a free memory block in the free memory pool that corresponds to the requested memory size, then memory is allocated in the free memory pool according to the requested memory size, and a memory pointer of the allocated memory is obtained.

[0017] Optionally, the allocation module is further configured to, if there is no free memory pool in the at least one memory pool, create a new memory pool with the same memory size as the at least one memory pool in the first memory region, and allocate memory in the newly created memory pool according to the requested memory size to obtain the memory pointer of the allocated memory.

[0018] According to a third aspect of the present disclosure, an electronic device is provided, comprising: processor; A memory connected to the processor, the memory storing a computer program, which, when executed by the processor, implements the memory processing method described in the first aspect.

[0019] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the memory processing method described in the first aspect.

[0020] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, characterized in that the computer program, when executed by a processor, implements the memory processing method described in the first aspect.

[0021] According to a sixth aspect of the present disclosure, a chip is provided, including one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from a memory of an electronic device and send the signals to the processors, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device performs the memory processing method described in the first aspect.

[0022] By employing the above technical solution, this disclosure provides a memory processing method, apparatus, storage medium, electronic device, and chip. In response to a memory request, the requested memory size is first obtained; then, based on the requested memory size, a target memory region is determined from a multi-level memory region; and finally, memory is allocated within the target memory region according to the requested memory size. The multi-level memory region includes a first memory region, a second memory region, and a third memory region that do not overlap. The first memory region is used to centrally manage memory requests with a size less than or equal to a preset threshold, making small memory allocation more concentrated and avoiding fragmentation caused by the discrete distribution of small memory blocks in traditional dynamic allocation. The second memory region is used to centrally manage resident memory; for example, by centrally managing some resident memory, it can be removed from the dynamic memory management process and not occupy dynamic memory regions (i.e., the first and third memory regions), reducing the risk of fragmentation in dynamic regions. The third memory region is used to centrally manage memory requests with a size greater than the preset threshold. Because the first two regions separate small memory and resident memory, the remaining space is more complete, reducing allocation failures caused by fragmentation during large memory requests and improving the utilization efficiency of large memory blocks. By applying the technical solution disclosed herein, the problem of low memory utilization caused by memory fragmentation can be solved.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0025] Figure 1A A schematic diagram illustrating an example provided by an embodiment of this disclosure is shown; Figure 1B A schematic diagram illustrating another example provided by an embodiment of this disclosure is shown; Figure 1C A schematic diagram illustrating yet another example provided by an embodiment of this disclosure is shown; Figure 2 A flowchart illustrating a memory processing method provided in an embodiment of this disclosure is shown. Figure 3 A schematic diagram illustrating an example provided by an embodiment of this disclosure is shown; Figure 4 A flowchart illustrating another memory processing method provided in an embodiment of this disclosure is shown; Figure 5 A flowchart illustrating an example provided by an embodiment of this disclosure is shown; Figure 6 A flowchart illustrating another example provided by an embodiment of this disclosure is shown; Figure 7 A schematic diagram of the structure of a memory processing apparatus provided in an embodiment of this disclosure is shown; Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure is shown. Detailed Implementation

[0026] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0027] Numerous specific details are set forth in the following description to provide a full understanding of this disclosure. However, this disclosure can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this disclosure. Therefore, this disclosure is not limited to the specific implementations disclosed below.

[0028] The terminology used in one or more embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this disclosure. The singular forms “a,” “the,” and “the” as used in one or more embodiments of this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this disclosure refers to and includes any or all possible combinations of one or more associated listed items.

[0029] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this disclosure, and similarly, second may also be referred to as first. Depending on the context, the word “if” as used herein may be interpreted as “when”, “in response to a determination”, or “when…”.

[0030] Memory management technology is a core technology in computer systems responsible for the allocation, reclamation, protection, and optimization of memory resources. Its goal is to efficiently utilize limited memory space, ensure the normal operation of programs, and reduce resource waste. In memory management, the shared heap refers to a dynamic memory area in the system that is uniformly managed by the operating system or runtime environment. It is shared by multiple programs, modules, or threads to meet dynamic memory allocation needs (such as memory temporarily requested during program execution).

[0031] In some examples, such as Figure 1A As shown in Figure 1, all dynamic memory requests are allocated and reclaimed in the common heap. Allocation is done on demand, and adjacent blocks are merged during reclamation. However, due to the release of small memory requests, memory becomes scattered over time, making it impossible to allocate large blocks of memory. As shown in Figure 1, a large number of discontinuous free small blocks are generated in the common heap, causing subsequent large memory requests to fail because, although there is sufficient total free memory, contiguous blocks cannot be found.

[0032] In some examples, such as Figure 1B As shown, several dedicated memory pools can be added on top of the public heap area to manage the allocation and release of small memory blocks. These memory pools are not separated from the public heap area. Figure 1B As shown, a memory pool is allocated from the public heap, and small memory requests are made from this pool. However, the memory pool is still managed by the public heap, leading to memory fragmentation in the public heap. After running for a long time, large memory blocks are still insufficient, meaning that requests for large contiguous memory blocks cannot be fulfilled.

[0033] In some examples, such as Figure 1CAs shown, different from Figure 1B The scheme shown, in Figure 1C In this proposed solution, the memory pool is separated from the common heap area; all memory pools are managed in one centralized area, while the common heap area is the other. However, this approach fails to consider some resident memory within the common heap area, such as memory that is frequently requested and released, and memory whose lifecycle coincides with the system's runtime. These resident memories can completely truncate the common heap, resulting in memory fragmentation and making it impossible to fulfill requests for large, contiguous blocks of memory.

[0034] To address the aforementioned technical problems, this disclosure provides a memory processing method, such as... Figure 2 As shown, the method includes the following steps: Step 101: In response to the memory allocation request, obtain the memory size corresponding to the memory allocation request.

[0035] In some examples, memory allocation requests can be initiated through the general memory allocation interface (malloc / mmalloc). For instance, when the malloc / mmalloc interface is called, the interface parameters will include the size of the memory to be allocated; embodiments of this disclosure extract the size of the memory allocated corresponding to the memory allocation request by parsing the interface parameters.

[0036] Step 102: Determine the target memory region from the multi-level memory regions based on the requested memory size.

[0037] The multi-level memory region includes a first memory region, a second memory region, and a third memory region that do not overlap. For example, as... Figure 3 As shown, the original public heap area is changed into a three-level memory area, including a first memory area (multipool area, i.e., the area that centrally manages the memory pool), a second memory area (or fixed memory area, such as the area that centrally manages resident memory), and a third memory area (such as the public heap area), and the first and second memory areas are separated from the public heap area.

[0038] The first memory region is used to centrally manage memory requests with a size less than or equal to a preset threshold, such as managing the request and release of small memory blocks, making the allocation of small memory blocks more centralized and avoiding the fragmentation caused by the discrete distribution of small memory blocks in traditional dynamic allocation.

[0039] The second memory region is used for centralized management of resident memory. For example, some resident memory can be centrally managed so that it is removed from the dynamic memory management process and does not occupy the dynamic memory region (i.e., the first memory region and the third memory region), thereby reducing the risk of fragmentation of the dynamic region.

[0040] The third memory region is used to centrally manage memory requests that are larger than a preset threshold. Because the first two regions have separated small memory and resident memory, the remaining space is more complete, reducing allocation failures caused by fragmentation when requesting large memory and improving the utilization efficiency of large memory blocks.

[0041] In this embodiment of the disclosure, memory can be managed in a multi-level hierarchical manner. Users can use the general memory allocation interface malloc / mmalloc to allocate memory. Depending on the size of the memory allocated by the user, they can choose whether to allocate the memory in the first memory region (memory pool region) or the third memory region (public heap region).

[0042] This design of non-overlapping multi-level memory regions ensures complete isolation of the three types of memory needs (small memory, resident memory, and large memory), avoiding fragmentation and interference caused by the mixing of different types of memory.

[0043] Step 103: Allocate memory in the target memory area according to the requested memory size.

[0044] For example, when the requested memory size is less than or equal to a preset threshold, the request is directed to the first memory region, and memory is allocated in the first memory region; while when the requested memory size is greater than the preset threshold, the request is directed to the third memory region, and memory is allocated in the third memory region.

[0045] The technical solutions provided in this disclosure are applicable to memory resource management in embedded systems, real-time operating systems (RTOS), virtualization platforms, and large-scale distributed computing. Specific application scenarios include: scenarios requiring efficient handling of numerous small memory allocations, complex memory requests and releases, system memory shortages, and insufficient memory. This disclosure employs multi-level memory region management to address memory fragmentation: through multi-level hierarchical management (memory pool area / fixed memory area / common heap area), multiple memory regions are dedicated to different scenarios, optimizing memory fragmentation and improving memory utilization. Furthermore, it addresses the problem of insufficient large memory blocks: with three-level memory management, the common heap provides ample memory space for large memory requests; and it also improves performance by centrally storing frequently requested and released memory, as well as non-released memory, as resident memory.

[0046] Furthermore, to illustrate the specific implementation process of the above embodiments, as an optional approach, the following is provided: Figure 2 The specific implementation method shown includes the following steps: Step 201: Initialize and obtain multi-level memory regions.

[0047] Multi-level memory regions can include a first memory region, a second memory region, and a third memory region that do not overlap. For example, at system startup, the total memory resources are divided into three non-overlapping regions according to preset rules. The size, location, and management strategy of each region are determined during the initialization phase to avoid region mixing during subsequent dynamic allocation.

[0048] The first memory region is used to centrally manage memory requests with a size less than or equal to a preset threshold. In some examples, the first memory region may include multi-level memory pools with different memory sizes. For example, during system startup, a contiguous block of memory is pre-allocated according to the preset memory pool specifications and quantity as the base space for the first memory region (multipool region). It can then be dynamically expanded according to the demand for small memory requests (e.g., creating a new pool of the same specifications when there is no free pool).

[0049] For example, during the system startup phase, multi-level memory pools are initialized based on different memory sizes (in units of powers of 2, such as 8-byte, 16-byte, 32-byte, etc.). The memory blocks (blk) in the memory pool are organized and managed in a linked list manner.

[0050] The second memory region is used for centralized management of resident memory. In some examples, initializing the second memory region includes: allocating at least one of the following to the second memory region via a static global variable to form resident memory: Memory that is requested and released more than the preset number of times within a preset time interval (i.e., memory that is frequently requested and released); memory whose lifecycle is consistent with the system's running cycle is not released.

[0051] For example, if a user identifies frequently requested and released memory in their business, memory with a lifecycle consistent with the system that is not released, or large blocks of memory (such as fixed business memory larger than 512B), they can directly change the previous allocation method to static global variables. Through static global variable allocation, the compiler associates this type of memory with a specified data segment during the compilation phase, and loads it directly into a fixed memory address when the system starts, without participating in the dynamic memory management process.

[0052] The third memory region is used to centrally manage memory requests whose size exceeds a preset threshold. This third memory region can be a shared heap area. For example, the difference between "total memory size - preset size of the first memory region - actual size occupied by the second memory region" can be calculated, and the contiguous memory corresponding to this difference can be used as the third memory region (i.e., the shared heap area), which can be managed by the system's memory management algorithm.

[0053] Compared to Figures 1A to 1CThe scheme shown in this disclosure ensures that the multi-level memory regions initialized in this embodiment do not overlap, with small memory blocks, resident memory, and large memory blocks each in their designated locations, avoiding fragmentation interference caused by the mixing of different types of memory. Specifically, the memory pool for the first memory region is pre-created, and the static allocation of the second memory region requires no dynamic interface calls, reducing runtime system overhead. Furthermore, sufficient contiguous space is reserved for the third memory region through differential calculation, and there is no small memory fragment crowding out this space, resolving the problem of large memory block allocation failures in the shared heap.

[0054] Step 202: In response to the memory allocation request, obtain the memory size corresponding to the memory allocation request.

[0055] For example, when a user initiates a memory request through a common interface such as malloc / mmalloc, this embodiment of the disclosure extracts the requested memory size from the interface parameters to provide an executable numerical basis for subsequent matching of the target memory region.

[0056] Step 203: Determine the target memory region from the multi-level memory regions based on the requested memory size.

[0057] In some embodiments, step 203 may specifically include: if the requested memory size is less than or equal to a preset threshold, then the first memory region is determined as the target memory region.

[0058] For example, the first memory region (multipool) manages small blocks of memory. This region solves the fragmentation problem caused by the discrete distribution of small blocks of memory by using a memory pool with a power of 2 size and centralized management. If the preset threshold is 64 bytes and a request is made for 32 bytes of memory (≤64 bytes), then the first memory region is determined as the target memory region, and subsequent allocation is made from the multi-level memory pool of this region, avoiding the occupation of large blocks of memory space in the third memory region (public heap).

[0059] In some embodiments, step 203 may further include: if the requested memory size is greater than a preset threshold, then the third memory region is determined as the target memory region.

[0060] For example, since the first memory region (small memory) and the second memory region (resident memory) have already diverted a large amount of demand, the third region has more complete memory space, which can efficiently meet the allocation of large blocks of memory and avoid the problem of small fragments in the public heap crowding out large blocks of space. If the preset threshold is 64 bytes, and 128 bytes of memory are requested (>64 bytes), then the third region will be determined as the target memory region, and a contiguous large block of memory will be allocated through the system's memory management algorithm.

[0061] Step 204: Allocate memory in the target memory area according to the requested memory size.

[0062] In some embodiments, step 204 may specifically include: determining at least one memory pool of the minimum size that can meet the requested memory size requirement in the multi-level memory pool; if there is an unfilled free memory pool in the at least one memory pool, and there is a free memory block in the free memory pool corresponding to the requested memory size, then memory allocation is performed in the free memory pool according to the requested memory size, and a memory pointer of the allocated memory is obtained.

[0063] For example, memory allocation first involves size alignment: requesting 10 bytes → aligning to 16 bytes, requesting 20 bytes → aligning to 32 bytes, etc. This ensures the requested size matches the memory pool specification of the first memory region, avoiding allocation chaos caused by non-standard memory blocks. Within the multi-level memory pools of the first memory region, the smallest pool that meets the aligned memory size is found (e.g., 16 bytes aligned → matching a 16-byte memory pool, not a 32-byte memory pool). This method avoids the space waste caused by allocating small blocks of memory to a large pool.

[0064] In some embodiments, if there is no free memory pool in at least one memory pool (at least one memory pool of the smallest specification among multi-level memory pools that can meet the memory size requirement of the requested memory), a new memory pool with the same specification and memory size as the at least one memory pool is created in the first memory region, and memory is allocated in the newly created memory pool according to the requested memory size to obtain the memory pointer of the allocated memory.

[0065] For example, if the matched minimum size pool contains an unfilled free memory pool with a free memory block corresponding to the aligned size, then memory is allocated directly from that free block, and the memory pointer is returned. If the matched minimum size pool contains no free pool (or no free block), then a new memory pool of the same size is created in the first memory region, memory is allocated from the new pool, and the pointer is returned. If the current 16-byte memory pool is completely full, and a 16-byte memory request is made, a new 16-byte memory pool is created in the first memory region, and memory is allocated from the new pool, without occupying space in other areas.

[0066] In some embodiments, after memory allocation, in response to a memory release request, a memory pointer to the memory to be released is obtained; then, based on the memory pointer to the memory to be released, a memory release region is determined from the multi-level memory regions; and then, the memory to be released is released in the memory release region.

[0067] For example, in response to a memory release request, the memory pointer of the memory to be released determines which memory region in a multi-level memory region it belongs to. Since the address range of each memory region is fixed during the initialization phase, it can be located quickly. In this way, it ensures that the release operation is only performed within the corresponding region, avoiding accidental cross-region operations (such as releasing memory from the first memory region to the third memory region), and ensuring system stability.

[0068] In some examples, the memory to be released is released in the memory release region, which may specifically include: determining the memory release region as the first memory region based on the memory pointer of the memory to be released; obtaining the memory block corresponding to the memory pointer, and determining the target memory pool to which the memory block belongs in the first memory region; then marking the memory block as free and adding it to the free list of the target memory pool.

[0069] For example, based on the memory pointer of the memory to be freed, its corresponding memory block (blk) is located, and then the memory pool to which it belongs is determined by the memory block's identifier (such as specification information) (e.g., a 16-byte block corresponds to a 16-byte memory pool). The memory block to be freed is marked as free and added to the free list of its respective memory pool. In this way, memory block reuse can be achieved, and subsequent memory requests of the same specification can directly retrieve memory blocks from the free list.

[0070] Furthermore, in some examples, if the free list determines that all memory blocks in the target memory pool are free, the target memory pool is released back to the first memory region. For instance, if the free list indicates that all memory blocks in the target memory pool are free, the memory pool is released back to the first memory region, reclaiming the space it occupies. This avoids wasting space in the first memory region due to empty pools and improves the overall utilization of the first memory region. For example, if all memory blocks in a 16-byte memory pool are released, the 16-byte memory pool is reclaimed, and the reclaimed space in the first memory region can be used to create memory pools of other sizes (such as 32-byte memory pools) later.

[0071] Based on the descriptions of the above embodiments, the following application examples are given, but are not limited thereto: For example, the system's memory pool specifications are divided according to powers of 2, such as 8 bytes, 16 bytes, 32 bytes, etc. The preset memory size threshold is 32 bytes, meaning that when the requested memory size is less than or equal to 32 bytes, it is preferentially allocated from the multi-pool area (i.e., the first memory area); when it is greater than 32 bytes, it is allocated from the common heap (i.e., the third memory area). Figure 5As shown, when a user initiates a memory request (malloc / mmalloc), if the program executes malloc(10), it requests the allocation of 10 bytes of memory. Since the memory pool size is a power of 2, the closest power of 2 to 10 bytes is 16 bytes, so the requested 10 bytes are aligned to 16 bytes. Now, a free memory pool with a 16-byte size needs to be found. Assuming a free memory pool with a 16-byte size exists in the system, the allocation process for that memory pool is initiated. If the program executes malloc(16), it is also aligned to 16 bytes first. After finding a memory pool with a 16-byte size, it is found that there are no free memory blocks in this memory pool. At this point, the process of expanding from the multipool region and allocating a memory pool of the same size will be executed. A new 16-byte memory pool is created in the multipool region, and then 16 bytes of memory are allocated from this new memory pool. Finally, the memory pointer is returned. However, if the program executes malloc(40), 40 bytes is greater than the preset threshold of 32 bytes. At this point, the process will jump to the public heap allocation process, directly allocating 40 bytes of memory from the public heap, and then returning the memory pointer.

[0072] The memory release process can be categorized into two cases: memory blocks allocated from the multipool region and memory blocks allocated from the public heap. Figure 6As shown, if the memory block comes from the multipool region, the program executes the `free(ptr)` operation, where `ptr` is a pointer to the memory block previously allocated from the multipool region. The system checks whether the memory block pointed to by `ptr` belongs to the multipool region. Since this memory block was allocated from the multipool, the result is yes, and the multipool release process begins. The corresponding memory block `blk` is found through `ptr`, which is the specific memory unit to be released. It is determined which memory pool within the multipool region `blk` belongs to, for example, a 16-byte memory pool. `blk` is marked as free and added to the free list of its respective memory pool (the 16-byte memory pool). This way, when a 16-byte memory request is made later, it can be allocated from this free list. If all memory blocks in this 16-byte memory pool have been added to the free list (i.e., the memory pool is completely free), the memory pool is released back to the multipool region so that the multipool region can manage memory more efficiently. Finally, `return` is executed to complete the release operation. If the memory block comes from the public heap, and if ptr is a pointer to a memory block previously allocated from the public heap, when the free(ptr) operation is executed, if the result of checking whether ptr is in the multipool area is negative, the public heap release process will be entered, the memory block will be released according to the public heap memory release rules, and finally return will be executed.

[0073] This disclosure addresses the problem of mixed memory areas across different scenarios in traditional memory management schemes through multi-level hierarchical management, improving memory utilization and reducing the number of large memory blocks during long-term operation. It enhances memory allocation and deallocation performance by introducing fixed memory areas, converting resident data, non-dealt memory, and large memory blocks into static global variables, and employing a dynamically expanding, multi-level multipool mechanism to resolve the low memory utilization issue caused by discrete allocations of small memory sizes. Furthermore, it significantly improves multiple metrics such as allocation latency, memory fragmentation rate, maximum contiguous memory block size, and memory allocation efficiency. This disclosure can be applied to embedded and real-time systems; the optimized solution significantly improves performance and reliability while reducing debugging overhead, demonstrating clear technological innovation and commercial value.

[0074] Figure 7 This is a block diagram of a memory processing apparatus according to some embodiments of the present disclosure, which can be configured to execute the functions shown in Figures 1 to 12. Figure 6 The method shown. Refer to... Figure 7 The device includes: an acquisition module 31, a determination module 32, and an allocation module 33.

[0075] The acquisition module 31 is configured to acquire the memory size corresponding to the memory allocation request in response to the memory allocation request; The determination module 32 is configured to determine a target memory region from a multi-level memory region based on the requested memory size. The multi-level memory region includes a first memory region, a second memory region, and a third memory region that do not overlap. The first memory region is used to centrally manage memory requests with a memory size less than or equal to a preset threshold. The second memory region is used to centrally manage resident memory. The third memory region is used to centrally manage memory requests with a memory size greater than the preset threshold. The allocation module 33 is configured to allocate memory in the target memory region according to the requested memory size.

[0076] In some embodiments of this disclosure, the determining module 32 is specifically configured to determine the first memory region as the target memory region if the requested memory size is less than or equal to the preset threshold.

[0077] In some embodiments of this disclosure, the first memory region includes a multi-level memory pool, the multi-level memory pool having different memory sizes; The allocation module 33 is specifically configured to determine at least one memory pool of the minimum size that can meet the requested memory size requirement in the multi-level memory pool; if there is an unfilled free memory pool in the at least one memory pool, and there is a free memory block in the free memory pool that corresponds to the requested memory size, then memory is allocated in the free memory pool according to the requested memory size, and a memory pointer of the allocated memory is obtained.

[0078] In some embodiments of this disclosure, the allocation module 33 is further configured to, if there is no free memory pool in the at least one memory pool, create a new memory pool with the same memory size as the at least one memory pool in the first memory region, and allocate memory in the newly created memory pool according to the requested memory size to obtain the memory pointer of the allocated memory.

[0079] In some embodiments of this disclosure, the determining module 32 is further configured to determine the third memory region as the target memory region if the requested memory size is greater than the preset threshold.

[0080] In some embodiments of this disclosure, the device further includes: a release module; The release module is configured to, in response to a memory release request, obtain a memory pointer to the memory to be released; determine a memory release region from the multi-level memory regions based on the memory pointer; and release the memory to be released in the memory release region.

[0081] In some embodiments of this disclosure, the release module is specifically configured to determine the memory release area as the first memory area based on the memory pointer; obtain the memory block corresponding to the memory pointer, and determine the target memory pool to which the memory block belongs in the first memory area; mark the memory block as free, and add it to the free list of the target memory pool.

[0082] In some embodiments of this disclosure, the release module is further configured to release the target memory pool back to the first memory region if it is determined from the free list that all memory blocks of the target memory pool are in a free state.

[0083] In some embodiments of this disclosure, the determining module 32 is also configured to initialize the multi-level memory region.

[0084] In some embodiments of this disclosure, the determining module 32 is further configured to allocate at least one of the following to the second memory region via a static global variable to form resident memory: Memory that is requested and released more than the preset number of times within a preset time interval; memory whose lifecycle is consistent with the system's running cycle is not released.

[0085] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0086] It should be noted that other corresponding descriptions of the functional units involved in the memory processing apparatus provided in this disclosure embodiment can be found in Figures 1 to 12. Figure 6 The corresponding description in [the document] will not be repeated here.

[0087] Based on the above, as shown in Figures 1 to 1 Figure 6 Accordingly, this disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described methods as shown in Figures 1 to 12. Figure 6 The method shown.

[0088] Based on the above, as shown in Figures 1 to 1 Figure 6 Accordingly, this disclosure also provides a computer program product, including a computer program, which, when executed by a processor, implements the methods described in Figures 1 to 14. Figure 6 The method shown.

[0089] Based on this understanding, the technical solution disclosed herein can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, or portable hard drive) and includes several instructions to cause a computer device (such as a personal computer, server, or network device) to execute the methods of various implementation scenarios of this disclosure.

[0090] Based on the above, as shown in Figures 1 to 1 Figure 6 The method shown, and Figure 7 The virtual device embodiment shown in this disclosure also provides a chip, including one or more interface circuits and one or more processors; the interface circuits are used to receive signals from the memory of an electronic device and send the signals to the processors, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, it causes the electronic device to perform the above-described actions as shown in Figures 1 to 12. Figure 6 The method shown.

[0091] Figure 8 A schematic block diagram of an example electronic device 1000 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0092] like Figure 8 As shown, device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes according to a computer program stored in ROM (Read-Only Memory) 1002 or loaded from storage unit 1008 into RAM (Random Access Memory) 1003. RAM 1003 may also store various programs and data required for the operation of device 1000. The computing unit 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. I / O (Input / Output) interface 1005 is also connected to bus 1004.

[0093] Multiple components in device 1000 are connected to I / O interface 1005, including: input unit 1006, such as keyboard, mouse, etc.; output unit 1007, such as various types of monitors, speakers, etc.; storage unit 1008, such as disk, optical disk, etc.; and communication unit 1009, such as network card, modem, wireless transceiver, etc. Communication unit 1009 allows device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0094] The computing unit 1001 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 1001 performs the various methods and processes described above, such as the methods mentioned earlier. For example, in some embodiments, the methods mentioned earlier can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 1008. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM 1002 and / or communication unit 1009. When the computer program is loaded into RAM 1003 and executed by the computing unit 1001, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to perform the aforementioned method by any other suitable means (e.g., by means of firmware).

[0095] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0096] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0097] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0098] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0099] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0100] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0101] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0102] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0103] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory processing method, characterized by, The method comprises: in response to a memory application request, obtaining an application memory size corresponding to the memory application request; determining a target memory region from a plurality of memory regions according to the application memory size, wherein the plurality of memory regions comprise a first memory region, a second memory region and a third memory region which do not overlap with each other, the first memory region is used for centralized management of memory applications with a memory size less than or equal to a preset threshold, the second memory region is used for centralized management of resident memory, and the third memory region is used for centralized management of memory applications with a memory size greater than the preset threshold; performing memory allocation in the target memory region according to the application memory size.

2. The method of claim 1, wherein, The method further comprises: if the application memory size is less than or equal to the preset threshold, the first memory region is determined as the target memory region.

3. The method of claim 2, wherein, The first memory region comprises a plurality of memory pools with different memory sizes. The method further comprises: determining at least one memory pool with a minimum specification in the plurality of memory pools that can meet the application memory size requirement; if there is an unoccupied free memory pool in the at least one memory pool, and there is a free memory block corresponding to the application memory size in the free memory pool, performing memory allocation in the free memory pool according to the application memory size to obtain a memory pointer of the allocated memory.

4. The method of claim 3, wherein, The method further comprises: if there is no free memory pool in the at least one memory pool, creating a memory pool with the same specification memory size as the at least one memory pool in the first memory region, and performing memory allocation in the created memory pool according to the application memory size to obtain a memory pointer of the allocated memory.

5. The method of claim 1, wherein, The method further comprises: if the application memory size is greater than the preset threshold, the third memory region is determined as the target memory region.

6. The method according to any one of claims 1 to 5, characterized in that, The method further comprises: in response to a memory release request, obtaining a memory pointer of the memory to be released; determining a memory release region from the plurality of memory regions according to the memory pointer; performing release of the memory to be released in the memory release region.

7. The method of claim 6, wherein, The method further comprises: determining the memory release region as the first memory region according to the memory pointer; obtaining a memory block corresponding to the memory pointer, and determining a target memory pool to which the memory block belongs in the first memory region; marking the memory block as free and adding it to a free linked list of the target memory pool.

8. The method of claim 7, wherein, The method further comprises: if all memory blocks of the target memory pool are determined to be in a free state according to the free linked list, releasing the target memory pool back to the first memory region.

9. The method of claim 1, wherein, Before the acquiring the application memory size corresponding to the memory application request in response to the memory application request, the method further comprises: The initialization of the multi-level memory region comprises:

10. The method of claim 9, wherein, The initialization of the multi-level memory region comprises: For the second memory region, at least one of the following is allocated to the second memory region by a static global variable to form a permanent memory: Memory whose number of applications and releases within a preset time interval is greater than a preset number; Memory whose life cycle is consistent with the system running cycle and is not released.

11. A memory processing device, comprising: Comprise: The acquiring module is configured to acquire an application memory size corresponding to a memory application request in response to the memory application request; The determining module is configured to determine a target memory region from a multi-level memory region according to the application memory size, wherein the multi-level memory region comprises a first memory region, a second memory region and a third memory region which do not overlap with each other, the first memory region is used for centralized management of memory applications whose memory size is less than or equal to a preset threshold, the second memory region is used for centralized management of permanent memory, and the third memory region is used for centralized management of memory applications whose memory size is greater than the preset threshold; The allocating module is configured to perform memory allocation in the target memory region according to the application memory size.

12. The apparatus of claim 11, wherein The determining module is specifically configured to determine the first memory region as the target memory region if the application memory size is less than or equal to the preset threshold.

13. The apparatus of claim 12, wherein, The first memory region comprises a multi-level memory pool, and the multi-level memory pool has different specifications of memory size. The allocating module is specifically configured to determine at least one memory pool of the smallest specification that can meet the application memory size demand in the multi-level memory pool, and if there is an unoccupied idle memory pool in the at least one memory pool and there is an idle memory block corresponding to the application memory size in the idle memory pool, perform memory allocation in the idle memory pool according to the application memory size to obtain a memory pointer of the allocated memory.

14. The apparatus of claim 13, wherein The allocating module is specifically further configured to create a memory pool with the same specification of memory size as the at least one memory pool in the first memory region if there is no idle memory pool in the at least one memory pool, and perform memory allocation in the created memory pool according to the application memory size to obtain a memory pointer of the allocated memory.

15. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the method of any one of claims 1 to 10.

16. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the method of any one of claims 1 to 10.

17. A chip, characterized by The electronic device comprises one or more interface circuits and one or more processors; the interface circuit is used to receive a signal from a memory of the electronic device and send the signal to the processor, and the signal comprises computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device executes the method of any one of claims 1 to 10.

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