Data read / write controller

Abstract

The application discloses a data read-write controller, which comprises a data receiving module, a data caching module and a read-write control module. The data receiving module is used for receiving first initialization data issued by a user equipment through a configurable serial interface mode and converting the first initialization data into first standard data conforming to a preset internal bus format. The data caching module is electrically connected with an external memory and is used for receiving second initialization data transmitted by the external memory through the configurable serial interface mode and converting the second initialization data into second standard data conforming to the preset internal bus format. The read-write control module is used for generating an initialization instruction according to one of the first standard data and the second standard data. The data receiving module and the data caching module of the configurable serial interface mode are constructed, flexible adaptation to various serial interfaces is realized, and the efficiency and reliability of target function module initialization are improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit design, and particularly relates to a data read-write controller. BACKGROUND

[0002] In modern computing systems, especially devices containing complex on-chip systems and multiple peripheral interfaces, key functional modules such as PCIe (Peripheral Component Interconnect Express) controllers and network controllers need to be initialized and configured when the system is powered on. This process is usually completed by a data read-write controller, which receives configuration data or firmware from an external host through a low-speed serial interface such as SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), and writes it into the registers or external non-volatile memory of the target module. However, the existing data read-write controller has many limitations:

[0003] First, the interface adaptability is poor. The controller is usually designed to support only one specific serial interface. When the hardware platform needs to replace different types of serial interface memories or cope with different interface standards, the interface logic of the controller must be redesigned, even the entire hardware circuit, resulting in poor development flexibility and high reuse cost.

[0004] Second, the internal architecture is tightly coupled and inefficient. Data reception, protocol processing and memory access functions are usually mixed in a single or highly coupled logic unit, lacking clear internal division and standardized interaction interface. This rigid architecture makes the controller internal data processing path complex and logic redundant, not only increasing the difficulty of timing convergence, but also leading to poor performance, reliability and maintainability of the entire controller, making it difficult to meet the strict requirements of PCIe initialization speed. SUMMARY

[0005] The purpose of the present application is to provide a data read-write controller that can flexibly adapt to multiple serial interfaces, thereby improving the efficiency and reliability of the initialization of the target functional module.

[0006] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0007] According to an aspect of an embodiment of the present application, a data read-write controller is provided, comprising:

[0008] The data receiving module is configured to receive first initialization data issued by a user equipment through a configurable serial interface mode, and convert the first initialization data into first standard data conforming to a preset internal bus format; the preset internal bus format comprises read / write enable signals, address signals, write data signals and read data signals; when the read / write enable signals are valid, the corresponding address signals and data signals are valid;

[0009] The data buffer module is electrically connected with an external memory, and is configured to receive second initialization data transmitted by the external memory through a configurable serial interface mode, and convert the second initialization data into second standard data conforming to a preset internal bus format.

[0010] The read / write control module is electrically connected with the data receiving module and the data buffer module through an internal bus, and is configured to generate an initialization instruction according to one of the first standard data and the second standard data; the initialization instruction is used for initializing and configuring at least one target functional module.

[0011] According to an aspect of an embodiment of the present application, the data receiving module comprises:

[0012] The serial interface mode selection unit is configured to select a serial interface mode, so as to adapt chip physical pins to a serial interface supported by the user equipment.

[0013] The data conversion unit is electrically connected with the chip physical pins configured by the serial interface mode selection unit, and is configured to convert first initialization data output by the serial interface into parallel initialization data, and package the parallel initialization data according to the preset internal bus format, so as to form the first standard data.

[0014] According to an aspect of an embodiment of the present application, the data buffer module comprises:

[0015] The serial interface mode configuration unit is configured to select a serial interface mode, so as to adapt chip physical pins to a serial interface supported by the external memory.

[0016] The data buffer and conversion unit is electrically connected with the chip physical pins configured by the serial interface mode configuration unit, and is configured to convert second initialization data output by the serial interface into parallel initialization data, and package the parallel initialization data according to the preset internal bus format, so as to form the second standard data.

[0017] According to an aspect of the embodiment of the present application, the data buffer and conversion unit is further configured to convert the data transmitted by the read-write control module into a format supported by the external memory and buffer the converted data to the external memory.

[0018] According to an aspect of the embodiment of the present application, the read-write control module comprises:

[0019] An access mode judging unit configured to receive and analyze the first standard data transmitted by the data receiving module, and determine whether the external memory is in place according to the configuration register state.

[0020] If the external memory is not in place, the first standard data is directed to the internal register of the target function module, so that the internal register performs read-write access to the first standard data.

[0021] If the external memory is in place, the first standard data is directed to the external memory, so that the external memory performs firmware flashing or reading operation.

[0022] According to an aspect of the embodiment of the present application, the read-write control module further comprises:

[0023] A data encryption and decryption unit electrically connected to the access mode judging unit in the read-write control module, configured to receive the first standard data, and select an encryption and decryption algorithm to perform encryption and decryption operation on the first standard data according to the initialization time requirement of the target function module.

[0024] A data framing unit electrically connected to the data encryption and decryption unit, configured to frame the standard data subjected to encryption and decryption processing according to the vendor command format of the external memory, including write operation command framing, write operation data framing and read operation command framing.

[0025] According to an aspect of the embodiment of the present application, the read-write control module further comprises a data handshake unit electrically connected to the data framing unit in the read-write control module, configured to control the data flow rate by buffering data and generating a back pressure signal to the internal bus when processing the continuous read data of the external memory.

[0026] According to an aspect of the embodiment of the present application, the read-write control module further comprises a cross-clock domain processing unit configured to perform clock domain synchronization processing on the control signal and data signal transmitted between the data receiving module, the data buffer module and the target function module.

[0027] According to an aspect of the embodiment of the present application, the read-write control module further comprises a data distribution unit, configured to distribute standard data to the target function module for initialization configuration; wherein the standard data comprises one of the first standard data and the second standard data.

[0028] According to an aspect of the embodiment of the present application, the data distribution unit is configured to:

[0029] distribute the standard data to the target function module corresponding to the address information by parsing the address information in the standard data; or

[0030] distribute the standard data to a plurality of target function modules by sequentially pulling up the enable signals of the different target function modules.

[0031] In the technical scheme provided by the embodiment of the present application, a data read-write controller is provided, which comprises: a data receiving module, configured to receive first initialization data issued by a user device through a configurable serial interface mode, and convert the first initialization data into first standard data conforming to a preset internal bus format; the preset internal bus format comprises read-write enable signals, address signals, write data signals and read data signals; wherein when the read-write enable signals are valid, the corresponding address signals and data signals are valid; a data cache module, electrically connected with an external memory, configured to receive second initialization data transmitted by the external memory through a configurable serial interface mode, and convert the second initialization data into second standard data conforming to the preset internal bus format; and a read-write control module, electrically connected with the data receiving module and the data cache module through an internal bus, configured to generate an initialization instruction according to one of the first standard data and the second standard data; the initialization instruction is used for initialization configuration of at least one target function module. The technical scheme of the present application realizes flexible adaptation to a plurality of serial interfaces by constructing the data receiving module and the data cache module of the configurable serial interface mode, and improves the efficiency and reliability of the initialization of the target function module.

[0032] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0034] Figure 1 A system architecture diagram provided by an embodiment of the present application is shown schematically.

[0035] Figure 2 A data read-write controller block diagram provided by an embodiment of the present application is shown schematically.

[0036] Figure 3A A data receiving module structure diagram provided by an embodiment of the present application is shown schematically.

[0037] Figure 3B An interface structure diagram provided by an embodiment of the present application is shown schematically.

[0038] Figure 3C A preset internal bus format diagram provided by an embodiment of the present application is shown schematically.

[0039] Figure 4A A data cache module structure diagram provided by an embodiment of the present application is shown schematically.

[0040] Figure 4B An interface structure diagram of a data cache module provided by an embodiment of the present application is shown schematically.

[0041] Figure 5A A read-write control module structure diagram provided by an embodiment of the present application is shown schematically.

[0042] Figure 5B An encryption and decryption algorithm selection diagram provided by an embodiment of the present application is shown schematically.

[0043] Figure 5C A flowchart of reading continuous data provided by an embodiment of the present application is shown schematically.

[0044] Figure 5D A clock domain diagram provided by an embodiment of the present application is shown schematically.

[0045] Figure 6 A processing flowchart provided by an embodiment of the present application is shown schematically.

[0046] Figure 7 A computer system structure block diagram used to implement the technical solution of the present application is shown schematically. DETAILED DESCRIPTION

[0047] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these example implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example implementations to those skilled in the art.

[0048] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.

[0049] The block diagrams in the drawings show only the functionality of the features and do not necessarily imply a physical structure or organization of the system. That is, the functionality can be implemented in software, hardware, or a combination of the two. For example, the functionality can be implemented in software executed by one or more hardware processors or in hardware without software.

[0050] The flow diagrams depicted in the figures are merely exemplary and do not necessarily include all of the steps or operations, nor do they necessarily indicate the order in which the steps or operations can be performed. For example, some operations can be performed in parallel, some operations can be omitted, and some operations can be performed in a different order than depicted in the figures.

[0051] Figure 1 A system architecture diagram provided by an embodiment of the application is schematically shown. As shown, the data read-write controller is the core hub of the entire system data interaction and function configuration link, and its connection relationship includes: Figure 1

[0052] The data read-write controller is connected with the user side through a serial port, and is responsible for receiving serial initialization instructions and data, and feeding back the read results. The data read-write controller is bidirectionally connected with the external memory, and is used for realizing the caching, storage, and reading operations of the initialization firmware. The data read-write controller is bidirectionally connected with the PCIe controller (which belongs to the target function module in the application scheme), and is used for transmitting the initialization instructions to the PCIe controller to perform initialization configuration.

[0053] Further, the PCIe controller is also connected with multiple downstream controllers (such as controller 1, controller 2, and the like), and these downstream controllers serve as specific target function execution units, receive the initialization configuration through the PCIe controller, and complete the initialization of their own ports or functions. In this way, the complete data flow and function configuration path of “user side-data read-write controller-memory / PCIe controller-downstream controller” is formed.

[0054] ​In the existing data read-write controller, if the serial port needs to switch the interface mode (such as 2 interface to 4 interface), or the memory is replaced by a device of different manufacturers and different interface types, a large amount of controller logic needs to be reconfigured to adapt, and the maintenance and expansion cost is extremely high. And facing multiple downstream controllers (controller 1, 2, etc.), the existing data read-write controller is difficult to achieve timely and accurate data distribution and orderly sequential configuration, so that the initialization efficiency of the multi-port is low.

[0055] Based on this, the present application designs a data read-write controller, which includes three core parts of a data receiving module, a read-write control module and a data cache module, and can at least solve the technical problems of interface adaptation, efficiency and safety balance existing in the existing connection relationship, so as to realize the stable and efficient initialization of the target function module (such as PCIe controller port and downstream multi-controller).

[0056] The data read-write controller provided by the present application will be described in detail in combination with the specific implementation manner.

[0057] Figure 2 The block diagram of the data read-write controller provided by one embodiment of the present application is schematically shown. As shown in Figure 2 The data read-write controller provided by the present embodiment includes a data receiving module 210, a data cache module 220 and a read-write control module 230.

[0058] The data receiving module 210 is an input processing unit of the data read-write controller, which receives the first initialization data issued by the user device through the configurable serial interface mode (such as supporting multiple serial interface mode switching of 2 interface, 4 interface, etc.), and converts it into the first standard data conforming to the preset internal bus format through serial-parallel conversion and other operations. Among them, the first standard data carries the initialization configuration information of the target function module, which is used for initialization configuration of at least one target function module.

[0059] The data cache module 220 is a storage interaction unit of the data read-write controller, which is electrically connected with the external memory. The data cache module 220 is used for receiving the second initialization data transmitted by the external memory through the configurable serial interface mode, and converting the second initialization data into the second standard data conforming to the preset internal bus format, so as to adapt to the external memory of different manufacturers and different interface types, and guarantee the compatibility and stability of data interaction between the internal bus and the external memory.

[0060] The read-write control module 230 is a core processing unit of the data read-write controller, and is electrically connected with the data receiving module 210 and the data cache module 220 through an internal bus. The read-write control module 230 is configured to perform protocol conversion (such as data encryption and decryption, framing adaptation of different memory or command format of a functional module, etc.) and scheduling (such as access mode judgment, data distribution strategy selection, etc.) on one of the first standard data and the second standard data, so as to generate an initialization instruction for controlling an external memory or a target functional module, and to realize safe transmission, accurate distribution and process control of data.

[0061] Specifically, the target functional module is a module that needs to realize a specific function by receiving an initialization configuration, and can include a PCIe controller and various downstream controllers thereof, etc. These functional modules need to complete parameter configuration through the initialization instruction issued by the data read-write controller, so as to realize PCIe port initialization, starting of various functional interfaces, etc. The initialization instruction is configured to perform initialization configuration on at least one target functional module.

[0062] The internal bus is a bus for transmitting data and control signals between the modules in the data read-write controller. The internal bus has a unified signal format, which is configured to simplify the logical interaction between the modules and realize standardized transmission of data and control instructions. For example, the preset internal bus format can include a read-write enable signal, an address signal, a write data signal and a read data signal; and when the read-write enable signal is valid, the corresponding address signal and data signal are valid.

[0063] In the data read-write controller provided in the scheme, the data receiving module and the data cache module flexibly receive initialization data through a configurable serial interface mode and convert the initialization data into standard data conforming to a preset internal bus format, the read-write control module generates accurate initialization instructions by performing protocol conversion and scheduling on the standard data, and the three modules cooperate to enable the data read-write controller to efficiently and compatibly complete initialization configuration on at least one target functional module, thereby effectively improving the flexibility and efficiency of port initialization.

[0064] Figure 3A A structure diagram of the data receiving module provided in an embodiment of the present application is schematically shown. As shown in Figure 3A The data receiving module provided in the embodiment includes a serial interface mode selection unit 310 and a data conversion unit 320.

[0065] In an embodiment of the present application, the serial interface mode selection unit 310 is configured to select a serial interface mode, so as to adapt a physical pin to a serial interface supported by a user equipment, thereby realizing flexible adaptation of the serial interface.

[0066] Specifically, the serial interface is a data transmission interface implemented based on a serial communication protocol (data is transmitted bit by bit), and is a communication link between the user equipment and the data receiving module, and is mainly used for transmitting serial initialization data issued by the user and feeding back read data to the user equipment. The serial interface mode refers to the working mode and configuration specification of the serial interface, and includes key parameter combinations such as the number of pins of the interface, the data transmission rate, and the communication protocol. Selecting different serial interface modes can adapt to the serial communication needs of different user equipment, and is the configuration basis for realizing specific serial communication functions of physical pins.

[0067] The chip physical pin refers to an actual pin terminal on a chip where the data read-write controller is located, and is a physical medium for electrical signal interaction between the chip and external equipment (such as user equipment and memory).

[0068] In an embodiment of the present application, the data conversion unit 320 is electrically connected to the chip physical pin configured by the serial interface mode selection unit 310, and is used to convert the first initialization data output by the serial interface into parallel initialization data, and to package the parallel initialization data according to a preset internal bus format to form the first standard data.

[0069] Specifically, the first initialization data refers to serial data or instructions in serial form issued by the user equipment through the serial interface for initializing and configuring the target functional module; and the parallel initialization data refers to data in parallel form obtained after the first initialization data is converted from serial to parallel.

[0070] Packaging is to structure and package the parallel initialization data converted from serial to parallel according to the preset internal bus format, so as to make it into a data packet (i.e. the first standard data) conforming to the internal module interaction standard, thereby ensuring the effective transmission and analysis of the first standard data on the internal bus.

[0071] In an embodiment of the present application, the serial interface mode can be selected by a chip dial switch. That is, the user sets different on-off states through the dial switch on the chip, and the state is converted into a corresponding high-low level signal (such as the dial switch "closed" corresponding to high level and "open" corresponding to low level). After receiving the electrical signal, the serial interface mode selection unit 310 analyzes it, and configures the functions of the physical pins of the chip according to a preset state-mode mapping relationship (such as a specific on-off combination of the dial switch corresponding to serial port 1 of 2-interface mode and another combination corresponding to serial port 2 of 4-interface mode), such as configuring a specific number of physical pins as data transmission pins, clock pins, and enable pins, to match the pin requirements of the target interface mode and adapt to the serial interface supported by the user equipment.

[0072] In another embodiment of the present application, the selection of the serial interface mode can also be realized by a chip internal register. That is, after the user confirms the target serial interface mode, the configuration instruction carrying the corresponding parameter value is issued by the upper computer or external control signal. After the instruction is written into the preset internal register of the chip through the internal path, the serial interface mode selection unit 310 reads the configuration parameter value in the register according to the preset trigger mechanism, and decodes and identifies the target serial interface mode according to the preset "parameter value-interface mode" mapping relationship. Subsequently, the configuration control signal is output to the physical pin of the chip, and the physical pin function is defined to match the target serial interface requirement.

[0073] Figure 3B The interface structure diagram provided by an embodiment of the present application is schematically shown. As shown in the figure, Figure 3B The data receiving module in the embodiment is realized by a plurality of configurable low-speed interfaces to be compatible with user equipment, which specifically includes a plurality of independently configurable low-speed interfaces (low-speed interface 1, low-speed interface 2, …, low-speed interface N) and an internal interface. Each low-speed interface can be configured as a serial interface mode supported by the user equipment by the serial interface mode selection unit 310.

[0074] The foregoing low-speed interfaces are electrically connected to the data conversion unit 320 through the internal interface. The user can select the corresponding low-speed interface to issue the first initialization data in serial form according to the interface type of the user equipment, such as selecting the low-speed interface 1 if the user equipment only supports a 2-interface serial port, selecting the low-speed interface 2 if the user equipment supports a 4-interface serial port, and so on. After the data is transmitted to the data conversion unit 320 through the internal interface, the serial-parallel conversion and internal bus grouping operations are performed, and finally the first standard data conforming to the preset internal bus format is formed for the initialization configuration of the target functional module.

[0075] In this way, without modifying the core logic such as the data receiving module and the read-write control module, the serial interface types of different user equipment can be compatible, and the interface adaptability is significantly improved. At the same time, the user can flexibly select the corresponding low-speed interface according to the actual interface of the equipment, which reduces the docking threshold of the data read-write controller and different user equipment, reduces the secondary development cost caused by interface incompatibility, and effectively improves the maintainability and expansibility of the scheme.

[0076] In an embodiment of the present application, the preset internal bus format includes a read-write enable signal, an address signal, a write data signal, and a read data signal; wherein when the read-write enable signal is valid, the corresponding address signal and data signal are valid.

[0077] Figure 3C The preset internal bus format diagram provided by an embodiment of the present application is schematically shown. As shown in the figure, Figure 3CAs shown, the preset internal bus format in the embodiment includes clock, reset, write enable, address, write data, read enable, read data and the like signals, and each signal cooperates to realize standard data and control instruction transmission.

[0078] The clock signal provides a unified timing reference, which can ensure that the data receiving module, the read-write control module and the data caching module perform operations at the same time, avoiding data loss or logical errors caused by timing misalignment. The reset signal is used to initialize the bus state when the system is powered on or abnormal, ensuring that each module starts interaction from a consistent initial state.

[0079] When the write enable signal is pulled high, the write operation is triggered, at which time the address signal specifies the target position of the write operation, and the write data signal transmits the initialization data to be written. When the read enable signal is pulled high, the read operation is triggered, and the address signal specifies the target position of the read operation, and the read data signal returns the read result. This design decouples "operation control" and "data transmission", which can avoid the module from triggering data interaction in the non-reading and writing stage, reduce logical conflicts, realize stable and unambiguous internal data and control instruction transmission between modules, and further ensure the efficiency and reliability of the initialization configuration process.

[0080] Figure 4A The structure diagram of the data caching module provided by one embodiment of the application is schematically shown. As shown in Figure 4A The data caching module in the embodiment includes a serial interface mode configuration unit 410 and a data caching and conversion unit 420. The serial interface mode configuration unit 410 is used to select a serial interface mode to adapt the physical pins of the chip to the serial interface supported by the external memory. The data caching and conversion unit 420 is electrically connected with the serial interface mode configuration unit 410, and is used to convert the second initialization data output by the serial interface into parallel initialization data, and package the parallel initialization data according to the preset internal bus format to form the second standard data; and convert the data conforming to the preset internal bus format into a format supported by the external memory, and cache the converted data to the external memory.

[0081] Specifically, the serial interface mode refers to the communication protocol specification followed by the data caching module when interacting with the external memory in a serial data mode, including interface types (such as SPI, I2C, UART, etc.), timing parameters (clock frequency, data sampling time), bit width configuration (8-bit / 16-bit data transmission), signal definition (function allocation of data input / output, chip select, clock signal) and the like core elements.

[0082] The conversion refers to the adaptive processing performed by the data buffer and conversion unit 420 for the difference in data format between the internal bus and the external memory when transmitting data therebetween, and can specifically include converting parallel data of the internal bus into serial data supported by the external memory (when writing), or vice versa, converting serial data supported by the external memory into parallel data conforming to a preset internal bus format (when reading). Meanwhile, data bit width adjustment and coding mode adaptation can also be performed, such as encoding and converting binary data into a frame format specified by the external memory protocol, to ensure that the data can be accurately recognized and processed in different transmission links.

[0083] Packing is to structure and package the parallel initialization data after serial-parallel conversion according to the preset internal bus format, so as to make it into a data packet conforming to the internal module interaction standard (i.e., the second standard data), thereby ensuring the effective transmission and analysis of the second standard data on the internal bus.

[0084] Converting data conforming to the preset internal bus format into a format supported by the external memory refers to the process of packaging the scattered data to be transmitted (such as single-group configuration data transmitted by the internal bus, segmented data returned by the external memory) into a complete data packet containing a command field, an address field, a data field, and a check field according to the requirements of the external memory communication protocol, so that the data conforms to the receiving and analysis logic of the external memory, and the integrity and orderliness of data transmission are ensured.

[0085] For example, a temporary storage area can be built in the data buffer and conversion unit 420, which is used to temporarily store data to be written into the external memory (received from the internal bus) or data to be transmitted to the internal bus from the external memory. The core function of the temporary storage area is to alleviate the difference in transmission rate between the internal bus and the external memory, avoid data loss or transmission blockage caused by rate mismatch, and realize smooth transition and stable interaction of data flow.

[0086] Figure 4B An interface structure diagram of the data buffer module provided by an embodiment of the application is schematically shown. As shown in Figure 4B The interface architecture of the data buffer module can be the same as that of the data receiving module, and includes a plurality of configurable low-speed interfaces (low-speed interface 1 to low-speed interface N) and an internal interface. Each low-speed interface can be independently configured according to the communication protocol (such as SPI, I2C, etc.) of the external memory or the target functional module. Meanwhile, the data buffer module can realize bidirectional data interaction with other functional modules (such as the read-write control module) of the data read-write controller through the internal interface.

[0087] In the data transmission process, external devices (such as memories, target function modules) access through corresponding low-speed interfaces, and after the data is received through the low-speed interface, it is transmitted to the read-write control module through the internal interface for processing; conversely, the processing result of the read-write control module can also be distributed to the corresponding external device through the internal interface and the low-speed interface.

[0088] In this embodiment, the multi-low-speed interface architecture of the data cache module is completely reused with the interface architecture of the data receiving module, and only by differentiating the configuration of the parameters of the serial interface mode configuration unit, the functions of "connecting user equipment" and "connecting external memory" are distinguished, which can effectively reduce the hardware logic redundancy and reduce the chip design and maintenance cost. And this multi-low-speed interface design enables the data cache module to simultaneously adapt to external devices of multiple different communication protocols, improving the compatibility and scalability of the data read-write controller, thereby meeting the initialization data interaction needs of multiple devices in parallel or differentiation.

[0089] Figure 5A The structure diagram of the read-write control module provided by an embodiment of the application is schematically shown. As shown in Figure 5A The read-write control module in this embodiment includes an access mode judgment unit 510, a data encryption and decryption unit 520, a data grouping unit 530, a data handshake unit 540, a cross-clock domain processing unit 550, and a data distribution unit 560.

[0090] In an embodiment of the application, the access mode judgment unit 510 is configured to receive and analyze the first standard data transmitted by the data receiving module, to judge the in-place condition of the external memory according to the configuration register state. If the external memory is not in place and forcibly interacts with the external memory, it will cause the initialization process to be interrupted or the configuration to be invalid, at this time, the first standard data is directed to the internal register of the target function module, and the configuration is immediately effective but lost after power failure, which meets the rapid initialization needs of temporary debugging and external storage-free scenes, so that the internal register reads and writes the standard data. If the external memory is in place, the first standard data is directed to the external memory, and the persistent storage feature is used to realize long-term storage of firmware and reuse in multiple power cycles, so as to perform firmware refreshing or reading operation on the external memory.

[0091] Specifically, the configuration register refers to the register configured in the data read-write controller, and the configuration register state can be represented by the value of the configuration register, which is used to represent the in-place condition of the external memory, such as 0 indicating that the external memory is not in place and 1 indicating that the external memory is in place. Wherein, the in-place condition of the external memory refers to the state of whether the external memory exists and can normally communicate with the data read-write controller.

[0092] The internal register is a register inside a target function module (such as a PCIe controller, various downstream controllers, etc.) for storing initialization configuration parameters, and supports direct read-write access through the first standard data to complete the initialization configuration of the function itself. The firmware refresh refers to the operation of writing new firmware data into the external memory, which is used to update the initialization program or configuration information stored in the external memory, and ensures that the target function module can load the latest initialization logic.

[0093] In this embodiment, by judging the in-place situation of the external memory, the target function module can quickly complete initialization in a lightweight scenario and stably run in a scenario that requires persistent firmware, significantly improving the compatibility and robustness of the scheme, adapting to the initialization needs of different scenarios (such as temporary debugging and long-term deployment), and ensuring the reliability and flexibility of the initialization process.

[0094] In an embodiment of the present application, the data encryption and decryption unit 520 is electrically connected to the access mode judgment unit 510. The data encryption and decryption unit 520 is configured to receive the first standard data and select an encryption and decryption algorithm according to the initialization time requirement of the target function module to perform encryption and decryption operations on the first standard data.

[0095] Specifically, the encryption and decryption algorithm refers to a set of calculation logic that realizes the encryption conversion of "plaintext -> ciphertext that cannot be directly identified" and the decryption restoration of "ciphertext -> original plaintext" through a preset operation rule and a key. In the present application scheme, the encryption and decryption algorithm can be AES-128, AES-192, SM5 (national secret group encryption algorithm), ChaCha20 (lightweight symmetric encryption algorithm), etc., without limitation.

[0096] Figure 5B An encryption and decryption algorithm selection diagram provided by an embodiment of the present application is schematically shown. As shown in Figure 5B The data encryption and decryption unit 520 internally pre-stores a plurality of encryption and decryption algorithms (such as encryption and decryption algorithm 1, algorithm 2, etc.), and "cr_enc_dec" is an algorithm selection control signal (different level combinations or encoding values correspond to the selection identification of different algorithms). When the read-write control module starts the encryption and decryption process, the cr_enc_dec signal will generate a corresponding value according to the preset parameters of the configuration register (or the security level instruction issued by the user), the data encryption and decryption unit 520 receives and parses the encoding of the control signal, matches the encryption and decryption algorithm corresponding to the encoding from the pre-stored algorithm set, and finally uses the matched algorithm as the execution algorithm of the current initialization data encryption and decryption operation, so as to realize the flexible switching of encryption and decryption algorithms in different security levels and different scenarios.

[0097] Based on this, the user can decide what encryption and decryption algorithm to apply to the data flowing through the data encryption and decryption unit 520 according to the actual requirement (such as the initialization time requirement of the target function module) through the state of one or more configuration registers. For example, if the privacy of the access command and the strict initialization time requirement of the initialization high-speed interface (such as the PCIe interface) need to be considered, the user can consider using a relatively simple decoding method as the encryption method, such as the bitwise XOR algorithm. If it is another port with low initialization time requirement, the user can consider using a symmetric encryption algorithm with certain complexity to enhance the privacy.

[0098] In an embodiment of the present application, the data framing unit 530 is electrically connected with the data encryption and decryption unit 520, and is configured to frame the write operation command, frame the write operation data, and frame the read operation command of the standard data subjected to the encryption and decryption processing according to the vendor command format of the external memory, so as to generate the command frame and the data frame conforming to the communication protocol of the external memory, and to realize the firmware refresh or read operation of the external memory.

[0099] Specifically, the vendor command format of the external memory refers to the command structure specification defined by the vendor of the external memory for the read and write operation with the external device (such as the data read and write controller of the present solution), which includes the format, length, and timing requirement of the command field, parameter field, and data field. The memory command format defined by different memory vendors can be different. For example, a certain memory vendor defines that the write operation command needs to include the command identification, target storage address, etc. fields, and the read operation command needs to include the command identification, source storage address, etc. fields, while other memory vendors define that the write operation command does not include the target storage address field.

[0100] The write operation command framing refers to the process of constructing the command frame for triggering the write operation, which includes the command identification, target storage address, data length, etc. necessary information of the write operation, and is used to initiate the write operation request to the external memory. The write operation data framing refers to the process of encapsulating the standard data subjected to the encryption and decryption processing into the data frame, which needs to match the parameters of the write operation command frame, and is used to transmit the firmware data or configuration data to be written into the external memory. The read operation command framing refers to the process of constructing the command frame for triggering the read operation, which includes the command identification, source storage address, data length, etc. necessary information of the read operation, and is used to initiate the read operation request to the external memory.

[0101] In an embodiment of the present application, the data handshake unit 540 is electrically connected with the data framing unit 530, and is configured to control the data flow rate by buffering the data and generating the back pressure signal to the internal bus when processing the continuous read data of the external memory, so as to avoid the data loss or module overload caused by the mismatch of the data transmission rate, and to guarantee the stability of the data interaction.

[0102] Specifically, the continuous read data refers to continuous and uninterrupted groups of data read from the external memory, which is usually used to obtain complete firmware or configuration information, and has the characteristics of large data volume and consistent transmission timing. The cache data is part of the data temporarily stored by the data handshake unit 540 when processing the continuous read data, which is used to alleviate the rate difference between the data read-write module and the data processing module, and to realize smooth transition of the data stream.

[0103] The back pressure signal is a control signal sent by the data handshake unit 540 to the internal bus when the cache data reaches a preset threshold, which can be used to reduce or suspend the data transmission rate of the internal bus to prevent data overflow or module processing overload.

[0104] In an embodiment of the present application, the process of performing a continuous data read operation can be as shown in Figure 5C The read request is first initiated by the read-write control module to the data group framing unit 530, the data group framing unit 530 completes the framing of the read operation command according to the external memory vendor command format, and sends the read command to the external memory. The continuous read data returned by the external memory is finally entered into the data handshake unit 540 for caching through the path of "memory→low-speed interface of data cache control module→internal interface→standard interface of read-write control core module".

[0105] When the amount of cache data of the data handshake unit 540 reaches a preset threshold, an internal back pressure signal is first generated in the read-write control module to directly reduce the receiving rate of the read-write control module for data, avoiding overflow of its own cache.

[0106] If the cache data continues to grow, the internal back pressure signal will be transmitted to the upstream module (internal interface of the data receiving module) through the standard interface, and then control the rate of the low-speed interface data stream in the data receiving module. At this time, the back pressure signal is transmitted from "data handshake unit 540→read-write control module→data receiving module" in layers, forming a step-by-step back pressure: first limiting the rate of the read-write control module, then limiting the input rate of the data receiving module, and finally realizing dynamic matching of the rate from the external memory to the data read-write controller to the data receiving module, avoiding data loss or hardware overload caused by the rate bottleneck of a certain module.

[0107] In an embodiment of the present application, the cross-clock domain processing unit 550 is used for clock domain synchronization processing of the control signals and data signals transmitted between the data receiving module, the data cache module and the target function module.

[0108] Specifically, control signals refer to signals transmitted between the data receiving module, data buffer module, and target function module, used to control the operational logic of each module, such as read / write enable, reset, and handshake signals. Data signals refer to signals that carry actual information such as initialization data and configuration parameters.

[0109] Clock domain synchronization processing is a process for handling signals transmitted between modules operating in different clock domains (circuit regions with different clock frequencies or phases). Through specific circuit designs such as asynchronous first-in, first-out (FIFO) and synchronous register chains, it solves the timing conflict problem caused by different operating clock frequencies and phases of each module, realizes signal timing matching and stable transmission, and avoids problems such as metastability and data loss caused by clock domain differences.

[0110] Figure 5D A schematic diagram of a clock domain provided in one embodiment of this application is shown. Figure 5D As shown, dashed line 1 represents the data flow path of the first initialization data sent by the user, sequentially transmitted from the data receiving module to the read / write control module and the target functional module. The data is transmitted to the read / write control module via the low-speed interface and internal interface of the data receiving module. There, it is processed sequentially by functional units such as the cross-clock domain processing unit 550 (resolving clock domain differences between modules), the data encryption / decryption unit 520 (implementing data security protection), the data framing unit 530 (framing according to the external memory manufacturer's command format), and the data handshake unit 540 (controlling the data flow rate through buffering and backpressure). Finally, it is transmitted to the target functional module for initialization configuration. Since this path mainly transmits critical control signals and a small amount of data, the cross-clock domain processing unit 550 can use a two- or multi-level register synchronization method to synchronize these signals, effectively filtering out metastability with low hardware overhead and ensuring the stability and reliability of the control logic.

[0111] Dashed line 2 represents the data transmission from the read / write control module to the data buffer module: processed command frames or data frames are transmitted to the data buffer module via this path. The data buffer module then converts the data into a format supported by the external memory through its internal and low-speed interfaces to enable firmware refresh or read operations with the external memory. For control signals (such as command valid and write enable) along this path, the cross-clock domain processing unit 550 also uses a time-lapse synchronization method. For continuous data streams, an asynchronous FIFO is used for buffering and synchronization. This is because an asynchronous FIFO can smooth the rate difference between two clock domains, enabling batch and safe data transition and preventing data loss.

[0112] Dotted line 3 is the flow path of data transmitted by the external memory through the data buffer module, the read-write control module and the target function module in turn, which is used to convert the second initialization data transmitted by the external memory into second standard data conforming to the preset internal bus format, and transmit the second standard data to the read-write control module, so that the read-write control module generates an initialization instruction to initialize and configure the target function module.

[0113] For example, dotted line 3 can also be the feedback path of the handshake signal, the status signal and other control signals fed back by the data buffer module, the memory to the read-write control module, which is used to coordinate the timing of each module within the data read-write controller clock domain. For continuous and high-speed data flow on this path, the cross-clock-domain processing unit 550 can use an asynchronous FIFO as the core synchronization mechanism. The data is first written into the FIFO in the source clock domain, and then read out from the FIFO in the target clock domain, thereby safely completing the clock domain switching and ensuring the integrity of large data transmission.

[0114] Through the above differentiated synchronization design, the scheme of the present application realizes low-overhead beat synchronization for control signals to ensure timing convergence and logic correctness. For data flow, an asynchronous FIFO is used for buffering to solve the rate mismatch and metastability problem, and to ensure the integrity of data transmission. At the same time, the boundaries of the clock domains between the modules are clearly defined, so that the timing design of the entire data read-write controller is clear and modular, greatly improving the reliability and maintainability of the system.

[0115] In an embodiment of the present application, the data distribution unit 560 is used to receive and process the data or control signals, and according to the preset distribution rules (such as target module address, data type identifier, etc.), to direct the distribution of the data or control signals to the functional units of different downstream modules such as the data buffer module and the target function module, to realize the configuration of the corresponding initialization port.

[0116] For example, after receiving processed standard data (containing information such as the target module address and port configuration parameters), the data distribution unit 560 can determine the corresponding target functional module and initialization port by parsing the target module address identifier (such as the unique address code of different functional modules such as PCIe controllers and GPIO modules) and port configuration type identifier (such as the encoding of parameters such as port working mode, speed, and enable status). Then, through the internal bus or dedicated interface channel, the standard data is transmitted to the port configuration register group of the target functional module (this register group is a hardware unit within the target functional module used to store port initialization parameters). After receiving the standard data, the target functional module writes the data into the corresponding initialization port register (such as the port mode register, speed configuration register, etc.) according to its own port configuration logic (such as parameter mapping table, register bit field definition). After the register value is updated, the hardware circuit of the target functional module automatically completes the initialization according to the new configuration, realizing the activation of port functions and the effect of parameters.

[0117] For example, the data distribution unit 560 can first parse the target module identifier in the standard data to determine the multiple target functional modules to be distributed and their distribution order; then, according to a preset order, it sequentially pulls up the enable signal (such as write enable or module selection signal) of the first target functional module, and transmits the configuration information corresponding to the module to its configuration interface through the internal bus or dedicated channel; after the data transmission is completed, it pulls down the enable signal of the module, and then pulls up the enable signal of the second target functional module, repeating the data transmission operation, and so on, until the standard data of all target functional modules has been distributed. In this way, through the sequential timing control of the enable signals, each target functional module receives data only within its own dedicated time window, avoiding data conflicts between multiple modules and ensuring the accuracy of data distribution and the independence of the initial configuration of each module.

[0118] Figure 6 A flowchart illustrating a process provided in one embodiment of this application is shown schematically. Figure 6 As shown, when performing a write operation on external memory, the system first confirms that the external memory is in a present state by "memory presence determination". Then, the data to be written is synchronized across clock domains by "received data cross-clock domain processing". If the data is encrypted, it enters "received data decryption operation" to restore the original data. Next, the data framing unit constructs a write operation command frame according to the external memory manufacturer's command format and encapsulates the original data into a write data frame. After that, the data handshake unit performs a "data transfer handshake operation" and controls the data flow rate through buffering and backpressure mechanisms to avoid transmission overload. Finally, the data distribution unit sends the framed data to the external memory to complete the firmware refresh or data write operation.

[0119] When initiating an external memory read operation, the data framing unit constructs a read operation command frame in the vendor command format and sends it to the external memory; after the read data returned by the external memory is restored to the original data by the data encryption and decryption unit performing a "read data decryption operation" (if the data is encrypted), the data handshake unit performs a "data transfer handshake operation", and rate matching is achieved through the buffer and back pressure mechanism; then, the data distribution unit distributes and prioritizes the data to ensure accurate routing of the data to the target functional module.

[0120] The technical solution of the present application first ensures the validity of the operation premise through "memory in place judgment", avoiding invalid interaction when the external memory is not in place, and improving the system robustness. Then, through "cross-clock domain processing", the difference between the clock domains of multiple modules is solved, ensuring the correctness of signal transmission. Next, the encryption and decryption operation can ensure the security of data transmission and storage, preventing data from being stolen or tampered with. In addition, the data framing can adapt to the vendor command format of the external memory, improving the compatibility of different vendor devices. The buffer and back pressure mechanism of the data handshake unit can dynamically control the data flow rate, avoiding module overload or data loss, thereby ensuring the stability of data transmission. The data distribution and arbitration mechanism realizes accurate routing of data, improving the accuracy and efficiency of multi-module data interaction.

[0121] In summary, under the premise of ensuring data security, the processing flow realizes compatible adaptation to different external memories, stable control of data flow, and accurate distribution of data through the cooperation of various units, significantly improving the robustness, compatibility, and efficiency of the data read-write controller in the data interaction process.

[0122] It should be noted that although the steps of the method in the present application are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. In addition or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be divided into multiple steps, etc.

[0123] Figure 7 The structure block diagram of a computer system for implementing the technical solution of the present application is schematically shown.

[0124] It should be noted that, Figure 7 The computer system 700 shown is only an example and should not impose any limitation on the function and use range of the embodiments of the present application.

[0125] As Figure 7As shown, the computer system 700 includes a central processing unit 701 (CPU), which can perform various suitable actions and processes according to programs stored in a read-only memory 702 (ROM) or loaded into a random access memory 703 (RAM) from a storage section 708. In the random access memory 703, various programs and data required for system operation are also stored. The central processing unit 701, the read-only memory 702, and the random access memory 703 are connected to each other through a bus 704. An input / output interface 705 (I / O interface) is also connected to the bus 704.

[0126] Connected to the input / output interface 705 are an input section 706 including a keyboard, a mouse, etc.; an output section 707 including a display such as a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a local area network card, a modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the input / output interface 705 as necessary. A removable recording medium 711 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is attached to the drive 710 as necessary, so that a computer program read out therefrom is installed in the storage section 708 as necessary.

[0127] It should be noted that the computer-readable medium in the embodiments of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination thereof. The computer-readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination thereof. More specific examples of the computer-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (Compact Disc Read-Only Memory, CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus or device. In this application, the computer-readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take many forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium that can transmit, propagate or transport a program for use by or in connection with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium can be transmitted or propagated using any suitable medium, including but not limited to wireless, wired, or the like, or any suitable combination thereof.

[0128] The flowcharts and block diagrams in the drawings illustrate the possible implementation architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment, or a portion of code that contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different orders than that shown in the figures. For example, two blocks noted in succession can actually be executed substantially concurrently, or they can sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the flowcharts or block diagrams, and combinations of blocks in the flowcharts or block diagrams, can be implemented by special-purpose hardware-based systems that perform the specified functions or operations, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0129] It should be noted that, although several modules or units for a device for action execution are mentioned in the above detailed description, such a division is not mandatory. Indeed, according to an embodiment of the application, the features and functionalities of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functionalities of one module or unit described above can be further divided into several modules or units embodied.

[0130] Those skilled in the art can easily understand, through the above description of the embodiments, that the example embodiments described herein can be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solutions according to the embodiments of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a U disk, a mobile hard disk, etc.) or a network, and includes several instructions to make a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) execute the methods according to the embodiments of the present application.

[0131] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the present application cover any and all variations of the application that come within the scope of the present application, along with all equivalents thereof. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0132] It should be understood that the application is not limited to the precise construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A data read / write controller, characterized in that, include: A data receiving module is configured to receive first initialization data sent by a user equipment through a configurable serial interface mode, and convert the first initialization data into first standard data conforming to a preset internal bus format. The preset internal bus format includes a read / write enable signal, an address signal, a write data signal, and a read data signal. When the read / write enable signal is valid, the corresponding address signal and data signal are valid. The data receiving module includes: a serial interface mode selection unit, configured to select a serial interface mode to adapt the chip physical pins to a serial interface supported by the user equipment; and a data conversion unit, electrically connected to the chip physical pins configured by the serial interface mode selection unit, configured to convert the first initialization data output from the serial interface into parallel initialization data, and to package the parallel initialization data according to the preset internal bus format to form the first standard data. A data cache module is electrically connected to an external memory. The data cache module is used to receive second initialization data transmitted by the external memory through a configurable serial interface mode, and convert the second initialization data into second standard data that conforms to the preset internal bus format. The read / write control module is electrically connected to the data receiving module and the data buffer module via an internal bus. The read / write control module is used to generate an initialization instruction based on one of the first standard data and the second standard data. The initialization instruction is used to initialize and configure at least one target functional module.

2. The data read / write controller according to claim 1, characterized in that, The data caching module includes: A serial interface mode configuration unit is used to select a serial interface mode to adapt the chip's physical pins to a serial interface supported by the external memory. The data caching and conversion unit is electrically connected to the chip physical pins configured by the serial interface mode configuration unit. It is used to convert the second initialization data output by the serial interface into parallel initialization data, and to package the parallel initialization data according to the preset internal bus format to form the second standard data.

3. The data read / write controller according to claim 2, characterized in that, The data caching and conversion unit is also used to convert the data transmitted by the read / write control module in accordance with the preset internal bus format into a format supported by the external memory, and to cache the converted data in the external memory.

4. The data read / write controller according to claim 1, characterized in that, The read / write control module includes: The access mode determination unit is used to receive and parse the first standard data transmitted by the data receiving module, so as to determine the presence status of the external memory according to the configuration register status. If the external memory is not in place, the first standard data is directed to the internal register of the target functional module so that the internal register can read and write the first standard data; If the external memory is present, the first standard data is directed to the external memory to perform a firmware refresh or read operation on the external memory.

5. The data read / write controller according to claim 1, characterized in that, The read / write control module also includes: The data encryption / decryption unit is electrically connected to the access mode determination unit in the read / write control module. The data encryption / decryption unit is used to receive the first standard data and select an encryption / decryption algorithm to perform encryption / decryption operations on the first standard data according to the initialization time requirements of the target function module. The data framing unit, electrically connected to the data encryption / decryption unit, is used to perform write operation command framing, write operation data framing, and read operation command framing on the encrypted / decrypted standard data according to the manufacturer's command format of the external memory.

6. The data read / write controller according to claim 1, characterized in that, The read / write control module further includes a data handshake unit, which is electrically connected to the data framing unit in the read / write control module. The data handshake unit is used to control the data flow rate by caching data and generating a backpressure signal to the internal bus when processing continuous read data from the external memory.

7. The data read / write controller according to claim 1, characterized in that, The read / write control module also includes a cross-clock domain processing unit, which is used to perform clock domain synchronization processing on the control signals and data signals transmitted between the data receiving module, the data buffer module and the target function module.

8. The data read / write controller according to claim 1, characterized in that, The read / write control module further includes a data distribution unit for distributing standard data to the target functional module for initialization configuration; wherein the standard data includes one of the first standard data and the second standard data.

9. The data read / write controller according to claim 8, characterized in that, The data distribution unit is configured as follows: By parsing the address information in the standard data, the standard data is dispatched to the target functional module corresponding to the address information; or The standard data is distributed to multiple target functional modules by sequentially raising the enable signals of different target functional modules.

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