Linear interpolation processing device and method

Abstract

The invention relates to the technical field of computers, in particular to a linear interpolation processing device and method. The device comprises a first negation unit used for receiving at least two pieces of source data in an interpolation calculation request and performing sign bit negation processing on each piece of source data to obtain processed data corresponding to each piece of source data; the operation unit is used for calculating the processed data and the preset weight in the interpolation calculation request to obtain a calculation result; and the second negation unit is used for performing sign bit negation processing on the calculation result to obtain an interpolation result. According to the calculation process involved in the whole linear interpolation processing process, the hardware configuration of the device is no longer controlled by the dimension of the source data, the hardware overhead is reduced, the hardware configuration requirement can be simplified, and the occupied area of hardware needed by linear interpolation is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of computer technology, and particularly relates to a linear interpolation processing device and method. BACKGROUND

[0002] Linear interpolation is a mathematical method used to estimate the value of an unknown point between given known data points. Linear interpolation has a wide range of applications in computer technology, especially in the fields of computer graphics, data analysis, and machine learning. For example, linear interpolation is used in image processing, texture mapping, and animation production in computer graphics, in time series analysis and data smoothing in data analysis, in data preprocessing and model optimization in machine learning, and so on.

[0003] However, the linear interpolation calculation process in the related art requires multiple times of taking the complement of data by taking the complement of one to implement the complement code, which results in excessive hardware overhead. Therefore, how to simplify the calculation of linear interpolation and simplify the hardware resources required for linear interpolation is a research focus. SUMMARY

[0004] Therefore, the present disclosure provides a linear interpolation processing device and method.

[0005] According to an aspect of the present disclosure, a linear interpolation processing device is provided, which comprises:

[0006] A first negation unit is configured to receive at least two source data in an interpolation calculation request, and perform sign bit negation processing on each of the source data to obtain processed data corresponding to each of the source data.

[0007] An operation unit is configured to calculate each of the processed data and a preset weight in the interpolation calculation request to obtain a calculation result.

[0008] A second negation unit is configured to perform sign bit negation processing on the calculation result to obtain an interpolation result.

[0009] In a possible implementation, the operation unit comprises a plurality of multipliers and an adder.

[0010] The first negation unit is further configured to send each of the processed data to each of the multipliers.

[0011] Each of the multipliers is configured to multiply the received processed data with a preset weight of the received processed data to obtain a first result corresponding to the processed data, and send the first result to the adder.

[0012] The adder is configured to add the first results to obtain the calculation result and send the calculation result to the second inverting unit.

[0013] In a possible implementation, the numerical values of the source data belong to [-1.0, 1.0], and the source data have the same preset data type, and the source data of the preset data type linearly increases in [-1.0, 1.0].

[0014] In a possible implementation, the preset data type includes normalized signed integers.

[0015] In a possible implementation, the apparatus further includes:

[0016] The converter is configured to, in a case where it is determined that the original data type corresponding to the source data is different from the preset data type, convert the data type of the source data from the original data type to the preset data type.

[0017] The interpolation calculation request further carries description information of the source data, and the description information includes an original data type.

[0018] In a possible implementation, the converter is further configured to, in a case where it is determined that the original data type corresponding to the source data is different from the preset data type, convert the data type of the interpolation result from the preset data type to the original data type to obtain a final interpolation result.

[0019] The interpolation calculation request further carries description information of the source data, and the description information includes an original data type.

[0020] In a possible implementation, the first inverting unit includes at least one first exclusive-OR gate,

[0021] The two inputs of the first exclusive-OR gate are the source data and setting data corresponding to a data bit width of the source data respectively, and the output of the first exclusive-OR gate is processed data corresponding to the source data.

[0022] In a possible implementation, the second inverting unit includes a second exclusive-OR gate,

[0023] The two inputs of the second exclusive-OR gate are the calculation result and setting data corresponding to the data bit width of the source data respectively, and the output of the second exclusive-OR gate is the interpolation result.

[0024] In a possible implementation,

[0025] The interpolation calculation request also carries description information of the source data, and the description information includes a data bit width of the source data.

[0026] The first negation unit is further configured to generate corresponding setting data according to the data bit width of the source data, or select setting data corresponding to the data bit width from a plurality of alternative data.

[0027] The second negation unit is further configured to generate corresponding setting data according to the data bit width of the source data, or select setting data corresponding to the data bit width from a plurality of alternative data.

[0028] According to another aspect of the present disclosure, a linear interpolation processing method is provided, which is applied to a linear difference processing device including a first negation unit, an operation unit and a second negation unit, and the method includes:

[0029] The first negation unit receives an interpolation calculation request, determines at least two source data in the interpolation calculation request, and performs sign bit negation processing on each of the source data to obtain processed data corresponding to each of the source data.

[0030] The operation unit performs calculation on each of the processed data and a preset weight in the interpolation calculation request to obtain a calculation result.

[0031] The second negation unit performs sign bit negation processing on the calculation result to obtain an interpolation result.

[0032] The linear interpolation processing device and method provided by the embodiments of the present disclosure first perform sign bit negation on the source data, then perform calculation, and finally perform sign bit negation to obtain the interpolation result. Compared with the related art which needs to perform multiple complementation on the data, the present solution realizes linear interpolation calculation by a simpler way, reduces hardware overhead, can simplify the hardware configuration requirement, reduces the occupied area of the hardware required for linear interpolation, and the calculation process involved makes the hardware configuration of the device no longer controlled by the dimension of the source data.

[0033] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0035] Figure 1 An implementation process schematic diagram of linear interpolation calculation in the related art is shown.

[0036] Figure 2 A block diagram of a linear interpolation processing apparatus according to an embodiment of the present disclosure is shown.

[0037] Figure 3 A block diagram of a linear interpolation processing apparatus according to an embodiment of the present disclosure is shown.

[0038] Figure 4 An implementation process diagram of linear interpolation calculation by a linear interpolation processing apparatus according to an embodiment of the present disclosure is shown.

[0039] Figure 5 A block diagram of an apparatus for linear interpolation processing according to an exemplary embodiment is shown. DETAILED DESCRIPTION

[0040] Various exemplary embodiments, features, and aspects of the present disclosure will be explained in greater detail below with reference to the accompanying drawings. Like reference numerals may be used to refer to like elements throughout. While various aspects of embodiments will be described with reference to the figures, the drawings are not necessarily to scale, and emphasis will be placed on explaining the principles of the embodiments.

[0041] As used herein, the terms "comprise", "comprising", "have", "having", "include", "including", "contain", "containing", or variants thereof, are open-ended, and include one or more stated features, integers, elements, steps, components, or functions but do not preclude the presence or addition of one or more other features, integers, elements, steps, components, functions, or groups thereof.

[0042] When an element is referred to as being "connected", "coupled", "responsive", or variants thereof, to another element, it can be directly connected, coupled, or responsive to the other element, or intervening elements can be present.

[0043] While the terms "first", "second", "third", etc. can be used in this disclosure to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Thus, a first element / operation in some embodiments could be termed a second element / operation in other embodiments without departing from the teachings of the present inventive concept.

[0044] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0045] In addition, for the purpose of convenience and brevity, detailed descriptions of well-known functions and structures incorporated in the disclosure can be omitted. It will be appreciated that where specific details are given for the purpose of explanation, various embodiments can be practiced without some of these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order to avoid obscuring the present disclosure.

[0046] In the related art, linear interpolation can use two or more source data and corresponding interpolation weights to calculate a new value, and the calculation principle is as follows:

[0047] result=A weight0+B weight1

[0048] wherein A and B are two different source data, result is an interpolation result, weight0 and weight1 are weights corresponding to each source data, and weight0+weight1=1.

[0049] The actual calculation process is taken as an example of source data in the data format of a normalized signed integer (SNORM), as shown in Figure 1 , the source data that is a negative number is converted from a complement (NOT+1) to a true code, and the source data that is a positive number remains unchanged, then the true code and the corresponding weight (weight) are multiplied, and after multiplication, the negative number is converted to a complement, and finally the final result is obtained by addition.

[0050] However, the linear interpolation method shown in Figure 1 needs to implement the complement by inverting and adding one to the data multiple times, and if the dimension of the source data is large, many inversion units and adders are additionally required, resulting in excessive hardware design overhead, that is, the hardware configuration is limited by the dimension of the source data, and the larger the dimension, the more inversion units and adders are used in hardware implementation. Among them, the dimension of the source data refers to the structural dimension and data bit width of the source data, and the larger the structural dimension and data bit width, the more inversion units and adders are required. Among them, the source data can be a tensor, and the structural dimension of the source data is the rank of the tensor. For example, if the source data is (x, y), the dimension of the source data is 2-dimensional. If the source data is (x, y, z), the dimension of the source data is 3-dimensional.

[0051] To solve the above technical problems, the embodiment of the present disclosure provides a linear interpolation processing device and method. A first complementation unit receives at least two source data in an interpolation calculation request, and performs sign bit complementation on each of the source data to obtain processed data corresponding to each of the source data. An operation unit calculates each of the processed data and a preset weight in the interpolation calculation request to obtain a calculation result. A second complementation unit performs sign bit complementation on the calculation result to obtain an interpolation result. In the entire interpolation calculation process, the source data is first subjected to sign bit complementation, then calculation is performed, and finally sign bit complementation is performed to obtain the interpolation result. Compared with the related art which needs to complement the code multiple times, the present scheme realizes linear interpolation calculation by a simpler method, reduces hardware overhead, can simplify the hardware configuration requirement, reduces the occupied area of hardware required for linear interpolation, and the calculation process involved makes the hardware configuration of the device no longer controlled by the dimension of the source data.

[0052] As shown in Figure 2 , the linear interpolation processing device provided by the embodiment of the present disclosure can include a first complementation unit 11, an operation unit 10, and a second complementation unit 14. The linear interpolation processing device can be arranged in a processor such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc. that needs to perform linear interpolation calculation, so that the processor can perform linear interpolation calculation using the linear interpolation processing device. Obviously, compared with the hardware required for linear interpolation calculation, the linear interpolation processing device requires fewer devices (including the first complementation unit 11, the operation unit 10, and the second complementation unit 14), which naturally simplifies the hardware required for linear interpolation calculation, and the use of fewer devices naturally reduces the hardware occupation area of linear interpolation calculation. Figure 1

[0053] The first complementation unit 11 is configured to receive at least two source data in an interpolation calculation request, perform sign bit complementation on each of the source data to obtain processed data corresponding to each of the source data, and send each of the processed data to the operation unit 10. The source data can be known data points that need to be subjected to linear interpolation calculation. The interpolation calculation request is generated and sent to the linear interpolation processing device by a request sending module when it is determined that linear interpolation calculation needs to be performed on at least two source data. The at least two source data carried in the interpolation calculation request are sent to the first complementation unit 11. The request sending module and the linear interpolation processing device can be arranged in the same processor.

[0054] ​The calculation unit 10 is configured to calculate a result based on each of the processed data and the preset weights in the received interpolation calculation request, and send the calculation result to the second inversion unit 14. In some embodiments, the interpolation calculation request also carries preset weights corresponding to each of the source data (that is, preset weights of the processed data corresponding to each of the source data), and each preset weight in the interpolation calculation request is sent to the calculation unit 10. The sum of the preset weights corresponding to each source data is 1 (that is, the sum of the preset weights of each processed data is 1).

[0055] In one possible implementation, such as Figure 3 , Figure 4 As shown, the arithmetic unit 10 may include multiple multipliers 12 and adders 13.

[0056] like Figure 3 , Figure 4 As shown, the first inverting unit 11 is also used to send each of the processed data to each of the multipliers 12.

[0057] like Figure 3 , Figure 4 As shown, each multiplier 12 is used to receive the processed data and the preset weights corresponding to the processed data in the interpolation calculation request, multiply the received processed data by the received preset weights to obtain a first result corresponding to each of the processed data, and send the first result to the adder 13. The preset weights in the interpolation calculation request are sent to the corresponding multipliers 12 through the request sending module.

[0058] like Figure 3 , Figure 4 As shown, the adder 13 is used to add each of the first results to obtain a calculation result, and send the calculation result to the second inverting unit 14.

[0059] In this embodiment, the number of multipliers in the arithmetic unit can be set according to the amount of source data required for linear interpolation calculation. The number of multipliers can be greater than or equal to the amount of source data required for linear interpolation calculation.

[0060] The second inversion unit 14 is used to invert the sign bit of the calculation result to obtain the interpolation result. The second inversion unit 14 can return the interpolation result to the request sending module or the subsequent calculation module so that the request sending module or the subsequent calculation module can use the interpolation result to continue performing other calculations.

[0061] Compared to Figure 1 For the linear interpolation processing device shown, since Figure 1The hardware configuration is limited to the dimension of the source data, the larger the dimension, the more the NOT units and adders used in the hardware implementation, and Figure 2 In the linear interpolation processing device, no matter how large the dimension of the source data is, no additional hardware is needed due to the increase in the dimension, so that the hardware configuration of the device is no longer controlled by the dimension of the source data. Further combining Figure 3 、 Figure 4 The linear interpolation processing device can be compared to determine the scheme of the embodiment of the present disclosure. Even if the dimension of the source data increases, since the first NOT unit is used for source data inversion, the multiplier is used for multiplication, the adder is used for addition, and the second NOT unit is used for inversion again, these calculation steps are not affected by the dimension of the source data, and naturally no additional devices are needed due to the increase in the dimension of the source data, so that the hardware configuration of the device is no longer controlled by the dimension of the source data.

[0062] In a possible implementation, the first NOT unit 11 can include one or more first XOR gates.

[0063] In the case where the first NOT unit includes one first XOR gate, two inputs of the first XOR gate are the source data and the setting data corresponding to the data bit width of the source data, respectively, and the output of the first XOR gate is the processed data corresponding to the input source data. At least two source data are sequentially input into the first XOR gate to obtain the processed data corresponding to each source data sequentially output by the first XOR gate. In this way, one first XOR gate is used to realize the inversion of each source data in a serial manner to obtain the processed data corresponding to each source data. Compared with the design that the subsequent first NOT unit includes multiple first XOR gates, the first NOT unit including one first XOR gate can make the area of the first NOT unit smaller.

[0064] In the case where the first NOT unit includes multiple first XOR gates, two inputs of each first XOR gate are the source data and the setting data corresponding to the bit width of the source data, respectively, and the output of each first XOR gate is the processed data corresponding to the input source data. After grouping at least two source data (for example, dividing the source data into multiple groups according to the number of XOR gates, which is not limited in the present disclosure), the source data in each group is sequentially input into the first XOR gate corresponding to the group to obtain the processed data corresponding to the source data in each group sequentially output by each first XOR gate. In this way, multiple first XOR gates can process in parallel to speed up the processing. In some embodiments, the number of first XOR gates can be the same as the number of source data, so that each first XOR gate performs a sign bit inversion processing of one source data to output the processed data, further speeding up the processing.

[0065] In some embodiments, the interpolation calculation request also carries description information of the source data, and the description information includes a data bit width of the source data. The first inversion unit 11 is also configured to receive the data bit width in the interpolation calculation request, and then generate the corresponding setting data according to the data bit width in the description information, or select the setting data corresponding to the data bit width from a plurality of alternative data.

[0066] In a possible implementation, the second inversion unit 14 includes a second XOR gate. Two inputs of the second XOR gate are respectively the calculation result and the setting data corresponding to the data bit width (i.e., the data bit width of the source data) of the calculation result, and the output is the interpolation result. The second inversion unit 14 is also configured to receive the data bit width in the interpolation calculation request, and then generate the corresponding setting data according to the received data bit width, or select the setting data corresponding to the data bit width from a plurality of alternative data.

[0067] In some embodiments, the setting data mentioned by the first inversion unit 11 and the second inversion unit 14 can be data with the same bit width as the data bit width of the source data and with the sign bit being 1 and the other bits being 0. The plurality of alternative data can be determined in advance according to different data bit widths, and each alternative data has a corresponding data bit width, which is not limited in the present disclosure.

[0068] In some embodiments, the first XOR gate and the second XOR gate can also be replaced by one or more devices (such as a 1-bit adder, a multiplexer (MUX), etc.) capable of implementing the sign bit inversion processing, which is not limited in the present disclosure.

[0069] In a possible implementation, the numerical value of each source data belongs to [-1.0, 1.0], and each source data has the same preset data type, and the source data of the preset data type is linearly increasing in [-1.0, 1.0]. In this way, the linear interpolation processing device can complete the linear interpolation calculation for at least two source data, so that the obtained interpolation result is real and effective.

[0070] In some embodiments, the preset data type can include a normalized signed integer. In this way, the linear interpolation processing device can complete the linear interpolation calculation for at least two source data, so that the obtained interpolation result is real and effective.

[0071] For example, for the linear interpolation calculation of the source data with the data type of SNORM, if the number of source data is 2, the device can implement the linear interpolation calculation based on the following formula:

[0072] result = A weight + B (1 - weight) = (A + 1.0) weight + (B + 1.0) (1 - weight) - 1.0

[0073] wherein the result is an interpolation result, A and B are source data, weight is a preset weight of A, and (1 - weight) is a preset weight of B.

[0074] The device of the embodiments of the present disclosure calculates using the above formula because data of the SNORM type can have a plurality of different bit widths, such as snorm8, snorm16, etc., and no matter how many bits the width is, the range it represents is [-1.0, 1.0]. Taking snorm8 as an example, the highest bit is a sign flag, in which 1 represents a negative number and 0 represents a positive number. If it is a negative number, the data is represented in complement form. The maximum value of snorm8 is 0x7f, that is, the positive number 127, which represents 1.0f in float; the minimum value is 0x80, that is, the negative number -128, which represents -1.0f in float. It should be noted that because the range of negative numbers is one more than the range of positive numbers, here 0x81 also corresponds to -1.0f as 0x80 does.

[0075] The result of linear interpolation cannot be less than the minimum value in the source data or greater than the maximum value in the source data, so as shown in the above formula, we can first invert the sign flag of the source data of the SNORM type. Because the sign flag is inverted, the original source data of the SNORM type is mapped from [0x80, 0x7f] to [0x0, 0xff], and after the sign flag is inverted, the value range is [0.0, 2.0], that is, the source data A→(A + 1.0), and the source data B→(B + 1.0). After processing the inverted data, the data is sequentially subjected to multiplication operation (that is, (A + 1.0) weight and (B + 1.0) (1 - weight) - 1.0 weight + (B + 1.0) (1 - weight) - 1.0 weight + (B + 1.0) (1 - weight) - 1.0, to obtain the interpolation result of the SNORM type.

[0076] In a possible implementation, the apparatus can further include a converter configured to, in a case where it is determined that the original data type corresponding to the source data is different from the preset data type, convert the data type of the source data from the original data type to the preset data type before the first sign inversion unit 11 performs the sign inversion processing. In this way, the source data of other data types can all be converted to the preset data type before linear interpolation calculation, so as to improve the speed and efficiency of linear interpolation calculation of source data of various data types.

[0077] In a possible implementation, the converter can be further configured to, in a case where it is determined that the original data type corresponding to the source data is different from the preset data type, convert the data type of the interpolation result from the preset data type to the original data type, to obtain a final interpolation result. In this way, the obtained interpolation result can be in the original data type and continue to participate in subsequent other calculation processes.

[0078] In some embodiments, the interpolation calculation request further carries description information of the source data, and the description information includes the original data type. The converter is further configured to receive the original data type in the interpolation calculation request.

[0079] In this embodiment, the structure of the converter can be set according to the difference between the original data type and the preset data type, so that the type conversion of the data can be implemented, and the present disclosure does not limit this. The converter can include one or more conversion units, and each conversion unit implements type conversion between an original data type and a preset data type.

[0080] For example, the source data of the original data type float is converted to snorm, and the design idea of the corresponding conversion unit is as follows: float, whether float32 or float16, is composed of 1 bit sign bit and fixed bit length exponent bit and fixed length mantissa bit. Taking float32 as an example, the highest bit is the sign bit A, the next 8 bits are the exponent bit B, and the remaining 23 bits are the mantissa bit C. To convert float32 to snorm, the following operations need to be performed:

[0081] The mantissa bit A is taken out and 1 bit is added in the high bit to become a 24-bit fixed-point number A', which is in the format of "1.23". That is, the original mantissa bit A is all the decimal part, and the fixed-point number A' is a value greater than or equal to 1 but less than 2.

[0082] The exponent bit B of float32 is taken out, and the exponent bit B needs to be reduced by a bias value (that is, offset value, bias or intercept), which corresponds to the bit width of the corresponding float format. Different bit widths of float correspond to different bias values. For example, the bias value of float32 is 127. After subtracting the bias, a new exponent value B' is obtained.

[0083] In the case of positive exponent value B', the 24-bit fixed-point number A' is left shifted; in the case of negative exponent value B', the 24-bit fixed-point number A' is right shifted, to obtain the shifted fixed-point number A". The number of bits moved by left shift or right shift is the absolute value of the exponent value B'. The absolute value of the exponent value B' is used as the number of bits moved because the value of the source data belongs to [-1.0, 1.0], that is, the value of the float type source data is in the interval [-1.0, 1.0], and the exponent value B' is not positive, so the absolute value is taken.

[0084] The shifted fixed-point number A" is truncated from the decimal point to the corresponding snorm length minus 1 bit, to obtain the number C. For example, snorm8 is truncated from the high 7 bits of the decimal part of the shifted fixed-point number A".

[0085] If the original data type float source data is positive, the number C is complemented to a positive snorm8 of 8 bits. If the original data type float source data is negative, the number C is complemented and the high bit is complemented to a negative snorm8 of 8 bits.

[0086] It can be understood that, based on the above examples, the conversion between different original data types and preset data types can be performed according to the difference between the original data type and the preset data type, and the disclosure does not limit the corresponding setting of the conversion unit.

[0087] The embodiment of the disclosure also provides a linear interpolation processing method applied to a linear difference processing device, the linear difference processing device comprising a first complementation unit, an operation unit and a second complementation unit, and the method comprises:

[0088] The first complementation unit receives an interpolation calculation request, determines at least two source data in the interpolation calculation request, and performs a sign bit complementation process on each source data to obtain processed data corresponding to each source data;

[0089] The operation unit calculates each processed data and a preset weight in the interpolation calculation request to obtain a calculation result;

[0090] The second sign inversion unit performs sign inversion on the calculation result to obtain an interpolation result.

[0091] In a possible implementation, the operation unit includes a plurality of multipliers and an adder.

[0092] The first sign inversion unit sends each of the processed data to each of the multipliers.

[0093] Each of the multipliers multiplies the received processed data with a preset weight of the received processed data to obtain a first result corresponding to the processed data, and sends the first result to the adder.

[0094] The adder adds each of the first results to obtain the calculation result, and sends the calculation result to the second sign inversion unit.

[0095] In a possible implementation, the numerical value of each of the source data belongs to [-1.0, 1.0], each of the source data has a same preset data type, and the source data of the preset data type linearly increases in [-1.0, 1.0].

[0096] In a possible implementation, the preset data type includes normalized signed integers.

[0097] In a possible implementation, the apparatus further includes a converter, and the method further includes:

[0098] The converter converts the data type of the source data from an original data type to the preset data type when it is determined that the original data type of the source data is different from the preset data type.

[0099] The interpolation calculation request further carries description information of the source data, and the description information includes an original data type.

[0100] In a possible implementation, the method further includes:

[0101] The converter converts the data type of the interpolation result from the preset data type to the original data type to obtain a final interpolation result when it is determined that the original data type of the source data is different from the preset data type.

[0102] The interpolation calculation request further carries description information of the source data, and the description information includes an original data type.

[0103] In a possible implementation, the performing of the sign inversion on each of the source data to obtain processed data corresponding to each of the source data includes:

[0104] performing a sign bit inversion process on the source data and setting data corresponding to a data bit width of the source data to obtain processed data corresponding to the source data.

[0105] In a possible implementation, the first inversion unit includes at least one first exclusive-OR gate,

[0106] wherein two inputs of the first exclusive-OR gate are the source data and the setting data corresponding to the data bit width of the source data respectively, and an output of the first exclusive-OR gate is the processed data corresponding to the source data.

[0107] In a possible implementation, the second inversion unit includes a second exclusive-OR gate,

[0108] wherein two inputs of the second exclusive-OR gate are the calculation result and the setting data corresponding to the data bit width of the source data respectively, and an output of the second exclusive-OR gate is the interpolation result.

[0109] In a possible implementation, the interpolation calculation request further carries description information of the source data, and the description information includes a data bit width of the source data; and the method further includes:

[0110] the first inversion unit generates the corresponding setting data according to the data bit width of the source data, or selects the setting data corresponding to the data bit width from a plurality of alternative data; and / or,

[0111] the second inversion unit generates the corresponding setting data according to the data bit width of the source data, or selects the setting data corresponding to the data bit width from a plurality of alternative data.

[0112] It should be noted that although the linear interpolation processing device and method are described above as examples, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, users can flexibly set each part and each step according to personal preferences and / or actual application scenarios, as long as the technical solutions of the present disclosure are met.

[0113] In some embodiments, the device provided by the embodiments of the present disclosure has functions or includes modules that can be used to execute the methods described in the above method embodiment, and the specific implementation can refer to the description of the above method embodiment. For brevity, it will not be repeated here.

[0114] The embodiments of the present disclosure also provide a linear interpolation processing device, which includes a memory, a processor, and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the above method.

[0115] The embodiment of the present disclosure further provides a non-volatile computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the above method.

[0116] The embodiment of the present disclosure further provides a computer program product, which comprises a computer program or a non-volatile computer readable storage medium carrying the computer program, and the computer program is executed by a processor to implement the steps of the above method.

[0117] Figure 5 is a block diagram of an apparatus for linear interpolation processing according to an exemplary embodiment. For example, referring to Figure 5 , the apparatus 1900 can be provided as a server or a terminal device. Referring to Figure 5 , the apparatus 1900 comprises a processing component 1922, which further comprises one or more processors, and a memory resource represented by a memory 1932, for storing instructions executable by the processing component 1922, such as an application program. The application program stored in the memory 1932 can comprise one or more than one module each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above method.

[0118] The apparatus 1900 can further comprise a power supply component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input output interface 1958 (I / O interface). The apparatus 1900 can operate based on an operating system stored in the memory 1932, such as Windows Server TM , MacOS X TM , Unix TM , Linux TM , FreeBSD TM or the like.

[0119] The above has described the embodiments of the present disclosure, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles, practical application or technical improvement in the art of the embodiments, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A linear interpolation processing apparatus characterized by comprising: The device comprises: A first negation unit is configured to receive at least two source data in an interpolation calculation request, and perform sign bit negation processing on each of the source data to obtain processed data corresponding to each of the source data; An operation unit is configured to calculate each of the processed data and a preset weight in the interpolation calculation request to obtain a calculation result; A second negation unit is configured to perform sign bit negation processing on the calculation result to obtain an interpolation result.

2. The apparatus of claim 1, wherein, The operation unit comprises a plurality of multipliers and an adder; The first negation unit is further configured to send each of the processed data to each of the multipliers; Each of the multipliers is configured to multiply the received processed data with a preset weight of the received processed data to obtain a first result corresponding to the processed data, and send the first result to the adder; The adder is configured to add each of the first results to obtain the calculation result, and send the calculation result to the second negation unit.

3. The apparatus of claim 1, wherein, The numerical value of each of the source data belongs to [-1.0, 1.0], each of the source data has a same preset data type, and the source data of the preset data type is linearly increased in [-1.0, 1.0].

4. The apparatus of claim 3, wherein, The preset data type comprises a normalized signed integer.

5. The apparatus of claim 1, wherein, The device further comprises: A converter is configured to, in a case where it is determined that the original data type corresponding to the source data is different from the preset data type, convert the data type of the source data from the original data type to the preset data type; The interpolation calculation request further carries description information of the source data, and the description information comprises the original data type.

6. The device of claim 5, wherein The converter is further configured to, in a case where it is determined that the original data type corresponding to the source data is different from the preset data type, convert the data type of the interpolation result from the preset data type to the original data type to obtain a final interpolation result; The interpolation calculation request further carries description information of the source data, and the description information comprises the original data type.

7. The apparatus of any one of claims 1-6, wherein, The first negation unit comprises at least one first XOR gate, The two inputs of the first XOR gate are the source data and setting data corresponding to the data bit width of the source data, respectively, and the output of the first XOR gate is the processed data corresponding to the source data.

8. The apparatus of any one of claims 1-6, wherein, The second negation unit comprises a second XOR gate, The two inputs of the second XOR gate are the calculation result and setting data corresponding to the data bit width of the source data, respectively, and the output of the second XOR gate is the interpolation result.

9. The apparatus of any one of claims 1-6, wherein, The interpolation calculation request further carries description information of the source data, and the description information comprises the data bit width of the source data; The first negation unit is further configured to generate the corresponding setting data according to the data bit width of the source data, or select the setting data corresponding to the data bit width from a plurality of candidate data; and / or, The second complement unit is further configured to generate corresponding setting data according to a data bit width of the source data, or select setting data corresponding to the data bit width from a plurality of alternative data.

10. A linear interpolation processing method characterized by comprising: The method is applied to a linear difference processing device, and the linear difference processing device comprises a first complement unit, an operation unit and a second complement unit. The first complement unit receives an interpolation calculation request, determines at least two source data in the interpolation calculation request, and performs sign bit complement processing on each source data to obtain processed data corresponding to each source data. The operation unit calculates each processed data and a preset weight in the interpolation calculation request to obtain a calculation result. The second complement unit performs sign bit complement processing on the calculation result to obtain an interpolation result.

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