Linear interpolation processing apparatus and method

Abstract

This disclosure relates to the field of computer technology, and more particularly to a linear interpolation processing apparatus and method. The apparatus includes: a first inversion unit, configured to receive at least two source data from an interpolation calculation request, and invert the sign bits of each source data to obtain processed data corresponding to each source data; a computation unit, configured to calculate the calculation result by performing a sign bit inversion on each processed data and a preset weight in the interpolation calculation request; and a second inversion unit, configured to invert the sign bits of the calculation result to obtain the interpolation result. The computational process involved in the entire linear interpolation process makes the hardware configuration of the apparatus no longer controlled by the dimension of the source data, reducing hardware overhead, simplifying hardware configuration requirements, and reducing the hardware footprint required for linear interpolation.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a linear interpolation processing apparatus and method. Background Technology

[0002] Linear interpolation is a mathematical method used to estimate the value of an unknown point among known data points. It has wide applications in computer technology, especially in computer graphics, data analysis, and machine learning. For example, linear interpolation is used in image processing, texture mapping, and animation in computer graphics; in time series analysis and data smoothing in data analysis; and in data preprocessing and model optimization in machine learning, among others.

[0003] However, the linear interpolation calculation process in related technologies requires multiple inversions and additions of data to obtain the two's complement, resulting in excessive hardware overhead. Therefore, how to simplify the calculation of linear interpolation and reduce the hardware resources required for linear interpolation is a key research focus worthy of attention. Summary of the Invention

[0004] In view of this, the present disclosure proposes a linear interpolation processing apparatus and method.

[0005] According to one aspect of this disclosure, a linear interpolation processing apparatus is provided, the apparatus comprising:

[0006] The first inversion unit is used to receive at least two source data in the interpolation calculation request, and to invert the sign bit of each source data to obtain the processed data corresponding to each source data.

[0007] The calculation unit is used to calculate the calculation result by calculating the preset weights in each of the processed data and the interpolation calculation request;

[0008] The second inversion unit is used to invert the sign bit of the calculation result to obtain the interpolation result.

[0009] In one possible implementation, the arithmetic unit includes multiple multipliers and adders;

[0010] The first inverting unit is further configured to send each of the processed data to each of the multipliers respectively;

[0011] Each of the multipliers is used to multiply the received processed data with a preset weight to obtain a first result corresponding to the processed data, and send the first result to the adder;

[0012] The adder is used to add the first results together to obtain the calculation result, and send the calculation result to the second inverting unit.

[0013] In one possible implementation, the values ​​of each source data belong to [-1.0, 1.0], each source data has the same preset data type, and the source data of the preset data type increases linearly in [-1.0, 1.0].

[0014] In one possible implementation, the preset data type includes normalized signed integers.

[0015] In one possible implementation, the device further includes:

[0016] A converter is used to convert the data type of the source data from the original data type to the preset data type when it is determined that the original data type of the source data is different from the preset data type.

[0017] The interpolation calculation request also carries description information of the source data, which includes the original data type.

[0018] In one possible implementation, the converter is further configured to convert the data type of the interpolation result from the preset data type to the original data type when it is determined that the original data type corresponding to the source data is different from the preset data type, so as to obtain the final interpolation result.

[0019] The interpolation calculation request also carries description information of the source data, which includes the original data type.

[0020] In one possible implementation, the first inverting unit includes at least one first XOR gate.

[0021] The first XOR gate has two inputs: the source data and a set data corresponding to the data bit width of the source data. The output of the first XOR gate is the processed data corresponding to the source data.

[0022] In one possible implementation, the second inverting unit includes a second XOR gate.

[0023] The two inputs of the second XOR gate are the calculation result and the set data corresponding to the data bit width of the source data, respectively, and the output of the second XOR gate is the interpolation result.

[0024] In one possible implementation,

[0025] The interpolation calculation request also carries description information of the source data, including the data bit width of the source data;

[0026] The first inverting unit is further configured to generate corresponding set data based on the data bit width of the source data, or to select set data corresponding to the data bit width from multiple candidate data; and / or,

[0027] The second inverting unit is further configured to generate corresponding set data based on the data bit width of the source data, or to select set data corresponding to the data bit width from multiple candidate data.

[0028] According to another aspect of this disclosure, a linear interpolation processing method is provided, applied in a linear interpolation processing device, the linear interpolation processing device including a first inversion unit, a calculation unit, and a second inversion unit, the method comprising:

[0029] The first inversion unit receives an interpolation calculation request, determines at least two source data in the interpolation calculation request, and performs sign bit inversion on each source data to obtain the processed data corresponding to each source data.

[0030] The calculation unit calculates the preset weights in each of the processed data and the interpolation calculation request to obtain the calculation result.

[0031] The second inversion unit inverts the sign bit of the calculation result to obtain the interpolation result.

[0032] The linear interpolation processing apparatus and method provided in this disclosure involve first inverting the sign bit of the source data, then performing calculations, and finally inverting the sign bit again to obtain the interpolation result. Compared with related technologies that require multiple complement operations on the data, this solution achieves linear interpolation calculations in a simpler way, reducing hardware overhead, simplifying hardware configuration requirements, reducing the area occupied by the hardware required for linear interpolation, and making the hardware configuration of the device no longer controlled by the dimension of the source data due to the calculation process involved.

[0033] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0034] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0035] Figure 1 The diagram illustrates the implementation process of linear interpolation calculation in related technologies.

[0036] Figure 2 A block diagram of a linear interpolation processing apparatus according to an embodiment of the present disclosure is shown.

[0037] Figure 3 A block diagram of a linear interpolation processing apparatus according to an embodiment of the present disclosure is shown.

[0038] Figure 4 This diagram illustrates the implementation process of a linear interpolation processing apparatus performing linear interpolation calculations according to an embodiment of the present disclosure.

[0039] Figure 5 This is a block diagram illustrating an apparatus for linear interpolation processing according to an exemplary embodiment. Detailed Implementation

[0040] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0041] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0042] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0043] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0044] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0045] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0046] In related technologies, linear interpolation can use two or more source data and corresponding interpolation weights to calculate a new value. The calculation principle is as follows:

[0047] result=A weight0+B weight1

[0048] Here, A and B are two different source data, result is the interpolation result, weight0 and weight1 are the weights corresponding to each source data, and weight0 + weight1 = 1.

[0049] The actual calculation process, taking the source data format as a normalized signed integer (SNORM) as an example, is as follows: Figure 1 As shown, the source data of negative numbers can be converted from two's complement (invert and add 1) to original code, while the source data of positive numbers remains unchanged. Then, the original code and the corresponding weight are multiplied. After multiplication, the negative numbers are converted back to two's complement, and finally, they are added together to obtain the final result.

[0050] However, due to Figure 1 The linear interpolation method shown requires multiple inversions and additions of the data to achieve two's complement. If the source data has a large dimension, many additional inversion units and adders are needed, resulting in excessive hardware design overhead. This means that hardware configuration is limited by the dimension of the source data; the larger the dimension, the more inversion units and adders are required in the hardware implementation. The dimension of the source data refers to its structural dimension and data bit width. The larger the structural dimension and data bit width, the more inversion units and adders are needed. The source data can be a tensor, and its structural dimension is the rank of the tensor. For example, if the source data is (x, y), then its dimension is 2-dimensional. If the source data is (x, y, z), then its dimension is 3-dimensional.

[0051] To address the aforementioned technical problems, this disclosure provides a linear interpolation processing apparatus and method. A first inversion unit receives at least two source data from an interpolation calculation request and inverts the sign bits of each source data to obtain processed data corresponding to each source data. A computation unit calculates the processed data and the preset weights in the interpolation calculation request to obtain a calculation result. A second inversion unit inverts the sign bits of the calculation result to obtain the interpolation result. In the entire interpolation calculation process, the source data is first inverted, then calculated, and finally inverted again to obtain the interpolation result. Compared to related technologies that require multiple complement operations on the data, this solution achieves linear interpolation calculation in a simpler way, reducing hardware overhead, simplifying hardware configuration requirements, reducing the hardware footprint required for linear interpolation, and the calculation process makes the hardware configuration of the device no longer controlled by the dimension of the source data.

[0052] like Figure 2 As shown, the linear interpolation processing apparatus provided in this embodiment may include a first inversion unit 11, a computation unit 10, and a second inversion unit 14. This linear interpolation processing apparatus can be installed in processors such as CPUs (Central Processing Units) and GPUs that require linear interpolation calculations, so that these processors can utilize the linear interpolation processing apparatus to perform linear interpolation calculations. Obviously, compared to... Figure 1 The hardware required for linear interpolation calculation is less, and the linear interpolation processing device requires fewer components (including the first inversion unit 11, the arithmetic unit 10, and the second inversion unit 14), which naturally simplifies the hardware required for linear interpolation calculation. The use of fewer components can naturally reduce the hardware footprint of linear interpolation calculation.

[0053] The first inversion unit 11 is used to receive at least two source data in the interpolation calculation request, invert the sign bits of each source data to obtain the processed data corresponding to each source data, and send the processed data to the arithmetic unit 10. The source data can refer to known data points that need to be linearly interpolated. The interpolation calculation request is generated by the request sending module when it determines that linear interpolation calculation needs to be performed on at least two source data and sent to the linear interpolation processing device. The at least two source data carried in the interpolation calculation request are sent to the first inversion unit 11. The request sending module and the linear interpolation processing device can both be located in the same processor.

[0054] The calculation unit 10 is configured to calculate a result based on each of the processed data and the preset weights in the received interpolation calculation request, and send the calculation result to the second inversion unit 14. In some embodiments, the interpolation calculation request also carries preset weights corresponding to each of the source data (that is, preset weights of the processed data corresponding to each of the source data), and each preset weight in the interpolation calculation request is sent to the calculation unit 10. The sum of the preset weights corresponding to each source data is 1 (that is, the sum of the preset weights of each processed data is 1).

[0055] In one possible implementation, such as Figure 3 , Figure 4 As shown, the arithmetic unit 10 may include multiple multipliers 12 and adders 13.

[0056] like Figure 3 , Figure 4 As shown, the first inverting unit 11 is also used to send each of the processed data to each of the multipliers 12.

[0057] like Figure 3 , Figure 4 As shown, each multiplier 12 is used to receive the processed data and the preset weights corresponding to the processed data in the interpolation calculation request, multiply the received processed data by the received preset weights to obtain a first result corresponding to each of the processed data, and send the first result to the adder 13. The preset weights in the interpolation calculation request are sent to the corresponding multipliers 12 through the request sending module.

[0058] like Figure 3 , Figure 4 As shown, the adder 13 is used to add each of the first results to obtain a calculation result, and send the calculation result to the second inverting unit 14.

[0059] In this embodiment, the number of multipliers in the arithmetic unit can be set according to the amount of source data required for linear interpolation calculation. The number of multipliers can be greater than or equal to the amount of source data required for linear interpolation calculation.

[0060] The second inversion unit 14 is used to invert the sign bit of the calculation result to obtain the interpolation result. The second inversion unit 14 can return the interpolation result to the request sending module or the subsequent calculation module so that the request sending module or the subsequent calculation module can use the interpolation result to continue performing other calculations.

[0061] Compared to Figure 1 For the linear interpolation processing device shown, since Figure 1The hardware configuration shown is limited by the dimensionality of the source data; the larger the dimensionality, the more inverting units and adders the hardware implementation needs. Figure 2 In the linear interpolation processing device shown, regardless of the dimension of the source data, no additional hardware is needed due to the increase in dimension, making the hardware configuration of the device no longer controlled by the dimension of the source data. Further combining... Figure 3 , Figure 4 By comparing the linear interpolation processing device shown, the solution of this embodiment can be clearly determined. Even if the dimension of the source data increases, the calculation steps of the first inversion unit for inverting the source data, the multiplier for multiplication, the adder for summation, and the second inversion unit for inverting again are not affected by the dimension of the source data. Therefore, there is no need to add devices due to the increase in the dimension of the source data, so the hardware configuration of the device is no longer controlled by the dimension of the source data.

[0062] In one possible implementation, the first inverting unit 11 may include one or more first XOR gates.

[0063] In this design, where the first inversion unit includes a first XOR gate, the two inputs of the first XOR gate are the source data and the set data corresponding to the data bit width of the source data, respectively. The output of the first XOR gate is the processed data corresponding to the input source data. By sequentially inputting at least two source data into the first XOR gate, the processed data corresponding to each source data is obtained by sequentially outputting the first XOR gate. In this way, the inversion of each source data is achieved serially using a single first XOR gate to obtain the processed data corresponding to each source data. Compared to subsequent designs where the first inversion unit includes multiple first XOR gates, including only one first XOR gate in the first inversion unit allows for a smaller area of ​​the first inversion unit.

[0064] In the case where the first inversion unit includes multiple first XOR gates, the two inputs of each first XOR gate are the source data and the set data corresponding to the bit width of the source data, respectively, and the output of each first XOR gate is the processed data corresponding to the input source data. At least two source data can be grouped (e.g., the source data can be divided into multiple groups according to the number of XOR gates; this disclosure does not limit this), and the source data in each group can be sequentially input into the first XOR gate corresponding to that group to obtain the processed data corresponding to the source data in each group, which is sequentially output by each first XOR gate. In this way, multiple first XOR gates process in parallel, which can speed up the processing. In some embodiments, the number of first XOR gates can be the same as the number of source data, so that each first XOR gate performs a sign bit inversion of one source data and outputs the processed data, further accelerating the processing speed.

[0065] In some embodiments, the interpolation calculation request also carries description information of the source data, the description information including the data bit width of the source data. The first inverting unit 11 is further configured to receive the data bit width in the interpolation calculation request, and then generate corresponding set data according to the data bit width in the description information, or select set data corresponding to the data bit width from multiple candidate data.

[0066] In one possible implementation, the second inversion unit 14 includes a second XOR gate. The two inputs of the second XOR gate are the calculation result and the set data corresponding to the data bit width of the calculation result (i.e., the data bit width of the source data), and the output is the interpolation result. The second inversion unit 14 is also used to receive the data bit width in the interpolation calculation request, and then generate corresponding set data based on the received data bit width, or select the set data corresponding to the data bit width from multiple candidate data.

[0067] In some embodiments, the set data mentioned by the first inverting unit 11 and the second inverting unit 14 can be data with the same bit width as the source data, and the sign bit is 1 and the other bits are 0. The multiple candidate data can be pre-designed according to different data bit widths, and each candidate data has a different corresponding data bit width; this disclosure does not impose any limitations on this.

[0068] In some embodiments, the first XOR gate and the second XOR gate may also be replaced by a 1-bit adder, a multiplexer (MUX), or other devices capable of performing sign bit inversion (there may be one or more of these devices), and this disclosure does not limit this.

[0069] In one possible implementation, the values ​​of each source data point belong to the range [-1.0, 1.0], and each source data point has the same preset data type, with the source data of the preset data type increasing linearly within the range [-1.0, 1.0]. This enables the linear interpolation processing device to perform linear interpolation calculations for at least two source data points, resulting in a true and valid interpolation result.

[0070] In some embodiments, the preset data type may include normalized signed integers. This enables the linear interpolation processing device to perform linear interpolation calculations on at least two source data, resulting in accurate and valid interpolation results.

[0071] For example, for linear interpolation calculation of source data of type SNORM, if the number of source data is 2, the device can perform linear interpolation calculation based on the following formula:

[0072] result=A weight+B (1-weight)=(A+1.0) weight + (B + 1.0) (1-weight)-1.0

[0073] Where result is the interpolation result, A and B are the source data, weight is the preset weight of A, and (1-weight) is the preset weight of B.

[0074] The apparatus in this embodiment uses the above formula for calculation because data of type SNORM can have various bit widths, such as snorm8, snorm16, etc., and regardless of the bit width, it represents the range [-1.0, 1.0]. Taking snorm8 as an example, the highest bit is the sign flag, where 1 represents a negative number and 0 represents a positive number. If it is a negative number, the data is represented using two's complement. The maximum value of snorm8 is 0x7f, which is the positive number 127, representing 1.0f in float; the minimum value is 0x80, which is the negative number -128, representing -1.0f in float. It should be noted that because the range of negative numbers is 1 more than the range of positive numbers, 0x81 here also corresponds to -1.0f, just like 0x80.

[0075] The result of linear interpolation will not be less than the minimum value or greater than the maximum value in the source data. Therefore, as shown in the formula above, we can first invert the sign flag of the source data with data type SNORM. Due to the inverted sign flag, the original source data with data type SNORM will be mapped from [0x80, 0x7f] to [0x0, 0xff]. After inverting the sign flag, the value range is [0.0, 2.0], that is, source data A → (A + 1.0), source data B → (B + 1.0). Then, multiplication is performed on the inverted data (i.e., (A + 1.0)). weight and (B+1.0) (1-weight) and addition (A+1.0) weight + (B + 1.0) The second result is calculated after (1-weight), and then this second result is used as the final result, with the sign bit of the final result inverted (A+1.0). weight + (B + 1.0) (1-weight)-1.0 yields the interpolation result with data type SNORM.

[0076] In one possible implementation, the apparatus may further include a converter, configured to convert the data type of the source data from the original data type to the preset data type before the first inversion unit 11 performs sign bit inversion processing, if it is determined that the original data type corresponding to the source data is different from the preset data type. In this way, source data of other data types can be converted to the preset data type before linear interpolation calculation, improving the speed and efficiency of linear interpolation calculation for source data of various data types.

[0077] In one possible implementation, the converter can also be used to convert the data type of the interpolation result from the preset data type to the original data type when it is determined that the original data type corresponding to the source data is different from the preset data type, thereby obtaining the final interpolation result. This allows the obtained interpolation result to continue participating in subsequent calculation processes using the original data type.

[0078] In some embodiments, the interpolation calculation request also carries descriptive information of the source data, the descriptive information including the original data type. The converter is further configured to receive the original data type in the interpolation calculation request.

[0079] In this embodiment, the structure of the converter can be configured according to the difference between the original data type and the preset data type to enable data type conversion. This disclosure does not impose any limitations on this. The converter may include one or more conversion units, each of which implements a type conversion between the original data type and the preset data type.

[0080] For example, to convert source data of type floating-point (Float) to Snorm, the design of the corresponding conversion unit is as follows: Since both float32 and float16 consist of a 1-bit sign bit, a fixed-length exponent bit, and a fixed-length mantissa bit, taking float32 as an example, the highest bit is the sign bit A, the next 8 bits are the exponent B, and the remaining 23 bits are the mantissa C, converting float32 to Snorm requires the following operations:

[0081] Extract the mantissa A and pad it with 1 bit of 1 in the high bits to become a 24-bit fixed-point number A'. This fixed-point number A' is in the format of "1.23". That is to say, the original mantissa A was the fractional part, and the current fixed-point number A' is a value greater than or equal to 1 but less than 2.

[0082] Extract the exponent B from the float32 value. Then, subtract a bias value (also known as offset, bias, or intercept) from the exponent B. This bias value corresponds to the bit width of the corresponding float format; different bit widths of float correspond to different bias values. For example, the bias value for float32 is 127. Subtracting the bias yields a new exponent value B'.

[0083] When the exponent value B' is positive, the 24-bit fixed-point number A' is shifted left; when the exponent value B' is negative, the 24-bit fixed-point number A' is shifted right, resulting in the shifted fixed-point number A'". The number of bits shifted (left or right) is the absolute value of the exponent value B'. The reason for using the absolute value of the exponent value B' as the number of bits shifted is that the source data value belongs to the range [-1.0, 1.0], meaning the value of the float type source data is within the range [-1.0, 1.0]. Since the exponent value B' is not positive, its absolute value is used.

[0084] The shifted fixed-point number A” is truncated from the decimal point by the corresponding snorm length minus 1 bits to obtain the number C. For example, snorm8 is obtained by truncating the high 7 bits of the decimal part from the shifted fixed-point number A”.

[0085] If the source data of the original data type float is positive, then 0s are padded to the logarithm C to form an 8-bit positive snorm8. If the source data of the original data type float is negative, then the two's complement of the logarithm C is taken and 1s are padded to the high-order bits to form an 8-bit negative snorm8.

[0086] It is understood that, based on the above examples, for the conversion between different primitive data types and preset data types, the conversion unit can be set accordingly according to the differences between the primitive data type and the preset data type, and this disclosure does not impose any restrictions on this.

[0087] This disclosure also provides a linear interpolation processing method applied in a linear interpolation processing device, the linear interpolation processing device including a first inversion unit, a calculation unit, and a second inversion unit, the method including:

[0088] The first inversion unit receives an interpolation calculation request, determines at least two source data in the interpolation calculation request, and performs sign bit inversion on each source data to obtain the processed data corresponding to each source data.

[0089] The calculation unit calculates the preset weights in each of the processed data and the interpolation calculation request to obtain the calculation result.

[0090] The second inversion unit inverts the sign bit of the calculation result to obtain the interpolation result.

[0091] In one possible implementation, the arithmetic unit includes multiple multipliers and adders;

[0092] The first inverting unit sends each of the processed data to each of the multipliers respectively;

[0093] Each multiplier multiplies the received processed data with a preset weight to obtain a first result corresponding to the processed data, and sends the first result to the adder;

[0094] The adder adds each of the first results to obtain the calculation result, and sends the calculation result to the second inverting unit.

[0095] In one possible implementation, the values ​​of each source data belong to [-1.0, 1.0], each source data has the same preset data type, and the source data of the preset data type increases linearly in [-1.0, 1.0].

[0096] In one possible implementation, the preset data type includes normalized signed integers.

[0097] In one possible implementation, the apparatus further includes a converter, and the method further includes:

[0098] When the converter determines that the original data type of the source data is different from the preset data type, it converts the data type of the source data from the original data type to the preset data type.

[0099] The interpolation calculation request also carries description information of the source data, which includes the original data type.

[0100] In one possible implementation, the method further includes:

[0101] When the converter determines that the original data type corresponding to the source data is different from the preset data type, it converts the data type of the interpolation result from the preset data type to the original data type to obtain the final interpolation result.

[0102] The interpolation calculation request also carries description information of the source data, which includes the original data type.

[0103] In one possible implementation, after inverting the sign bit of each of the source data, the processed data corresponding to each of the source data is obtained, including:

[0104] The sign bit is inverted based on the source data and the set data corresponding to the data bit width of the source data to obtain the processed data corresponding to the source data.

[0105] In one possible implementation, the first inverting unit includes at least one first XOR gate.

[0106] The first XOR gate has two inputs: the source data and a set data corresponding to the data bit width of the source data. The output of the first XOR gate is the processed data corresponding to the source data.

[0107] In one possible implementation, the second inverting unit includes a second XOR gate.

[0108] The two inputs of the second XOR gate are the calculation result and the set data corresponding to the data bit width of the source data, respectively, and the output of the second XOR gate is the interpolation result.

[0109] In one possible implementation, the interpolation calculation request further carries descriptive information of the source data, the descriptive information including the data bit width of the source data; the method further includes:

[0110] The first inverting unit generates corresponding set data based on the data bit width of the source data, or selects set data corresponding to the data bit width from multiple candidate data; and / or,

[0111] The second inverting unit generates corresponding set data based on the data bit width of the source data, or selects set data corresponding to the data bit width from multiple candidate data.

[0112] It should be noted that although the linear interpolation processing apparatus and method have been described above as examples, those skilled in the art will understand that this disclosure is not limited thereto. In fact, users can flexibly set each part and step according to their personal preferences and / or actual application scenarios, as long as it conforms to the technical solution of this disclosure.

[0113] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0114] This disclosure also provides a linear interpolation processing apparatus, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0115] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0116] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0117] Figure 5 This is a block diagram illustrating an apparatus for linear interpolation processing according to an exemplary embodiment. For example, refer to... Figure 5 Device 1900 can be provided as a server or terminal device. (See reference...) Figure 5 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0118] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0119] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A linear interpolation processing apparatus characterized by comprising: The device comprises: A first negation unit is configured to receive at least two source data in an interpolation calculation request, and perform sign bit negation processing on each of the source data to obtain processed data corresponding to each of the source data; An operation unit is configured to calculate each of the processed data and a preset weight in the interpolation calculation request to obtain a calculation result; A second negation unit is configured to perform sign bit negation processing on the calculation result to obtain an interpolation result; The operation unit comprises a plurality of multipliers and an adder; The first negation unit is further configured to send each of the processed data to each of the multipliers; Each of the multipliers is configured to multiply the received processed data with a preset weight of the received processed data to obtain a first result corresponding to the processed data, and send the first result to the adder; The adder is configured to add each of the first results to obtain the calculation result, and send the calculation result to the second negation unit.

2. The apparatus of claim 1, wherein, The numerical value of each of the source data belongs to [-1.0, 1.0], each of the source data has a same preset data type, and the source data of the preset data type is linearly increased in [-1.0, 1.0].

3. The apparatus of claim 2, wherein, The preset data type comprises a normalized signed integer.

4. The apparatus of claim 1, wherein, The device further comprises: A converter is configured to, in a case where it is determined that the original data type corresponding to the source data is different from the preset data type, convert the data type of the source data from the original data type to the preset data type; The interpolation calculation request further carries description information of the source data, and the description information comprises the original data type.

5. The device of claim 4, wherein The converter is further configured to, in a case where it is determined that the original data type corresponding to the source data is different from the preset data type, convert the data type of the interpolation result from the preset data type to the original data type to obtain a final interpolation result; The interpolation calculation request further carries description information of the source data, and the description information comprises the original data type.

6. The apparatus of any one of claims 1-5, wherein, The first negation unit comprises at least one first XOR gate, The two inputs of the first XOR gate are the source data and setting data corresponding to the data bit width of the source data, respectively, and the output of the first XOR gate is the processed data corresponding to the source data.

7. The apparatus of any one of claims 1-5, wherein, The second negation unit comprises a second XOR gate, The two inputs of the second XOR gate are the calculation result and setting data corresponding to the data bit width of the source data, respectively, and the output of the second XOR gate is the interpolation result.

8. The apparatus of any one of claims 1-5, wherein, The interpolation calculation request further carries description information of the source data, and the description information comprises the data bit width of the source data; The first negation unit is further configured to generate the corresponding setting data according to the data bit width of the source data, or select the setting data corresponding to the data bit width from a plurality of candidate data; and / or, The second complement unit is further configured to generate corresponding setting data according to a data bit width of the source data, or select setting data corresponding to the data bit width from a plurality of candidate data.

9. A linear interpolation processing method characterized by, The method is applied to a linear difference processing device, and the linear difference processing device comprises a first complement unit, an operation unit and a second complement unit. The first complement unit receives an interpolation calculation request, determines at least two source data in the interpolation calculation request, and performs sign bit complement processing on each source data to obtain processed data corresponding to each source data. The operation unit calculates each processed data and a preset weight in the interpolation calculation request to obtain a calculation result. The second complement unit performs sign bit complement processing on the calculation result to obtain an interpolation result. The operation unit comprises a plurality of multipliers and an adder. The first complement unit sends each processed data to each multiplier. Each multiplier multiplies the received processed data and a preset weight of the received processed data to obtain a first result corresponding to the processed data, and sends the first result to the adder. The adder adds each first result to obtain the calculation result, and sends the calculation result to the second complement unit.

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