Short-circuit protection circuit of half-bridge driving chip

Abstract

A short-circuit protection circuit of a half-bridge driving chip relates to the field of short-circuit protection and integrated circuit design, and comprises a pre-driving module for generating a high-side signal and a low-side signal; the half-bridge module is driven, a high-side MOS receives a high-side signal, and a low-side MOS receives a low-side signal; the gate source hardware clamping module is used for carrying out voltage clamping on the high-side MOS when over-current of the over-ground short circuit of the high-side MOS is detected; the phase voltage short-circuit protection module is used for controlling the overcurrent time when the high-side MOS short circuit is over-current, and sending a fault signal to the logic module when detecting that the high / low-side MOS short circuit is over-current; the bus over-current protection module is used for sending a fault signal to the logic module when bus over-current is detected; and the logic module judges whether the short-circuit protection circuit enters a protection state according to the fault signal. According to the invention, the response speed and the protection mechanism are intelligently switched in real time in different overcurrent fault scenes through the three-stage protection circuit, and the circuit has the characteristics of high sensitivity, fast response speed and strong anti-interference capability.

Description

Technical Field

[0001] This invention relates to the fields of short-circuit protection and integrated circuit design, and more specifically, to a short-circuit protection circuit for a half-bridge driver chip. Background Technology

[0002] In modern power electronic systems, half-bridge driver chips play an indispensable role as the core control element of power conversion circuits. However, under high-voltage, high-speed switching conditions, short-circuit faults are one of the most fatal and common threats to half-bridges. Such short-circuit currents can cause a sharp rise in the junction temperature of power devices within microsecond timescales, leading to permanent damage or even system explosion. Gate-source breakdown of MOSFETs is even more extreme; once the gate-source voltage exceeds the rated voltage, permanent damage can occur within hundreds of nanoseconds.

[0003] Therefore, accurate and rapid protection has become a key indicator for short-circuit protection circuits, but traditional short-circuit protection circuits are almost impossible to achieve sub-hundred nanosecond speeds. Even at the microsecond level, they either require complex internal circuitry, increasing chip costs, or they need to reduce detection accuracy, posing a risk of false triggering and causing abnormal operation of the drive circuit.

[0004] Therefore, there is an urgent need for a short-circuit protection circuit for a half-bridge driver chip to solve the above problems. Summary of the Invention

[0005] In view of the above-mentioned technical problems in related technologies, the present invention proposes a short-circuit protection circuit for a half-bridge driver chip.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0007] This invention provides a short-circuit protection circuit for a half-bridge driver chip, comprising the following modules: a pre-drive module I1, a half-bridge driver module I2, a gate-source hardware clamping module I3, a phase voltage short-circuit protection module I4, a bus overcurrent protection module I5, a logic module I6, and a sampling resistor Rs.

[0008] The pre-driving module I1 is used to generate the high-side signal HOX and the low-side signal LOX;

[0009] The driving half-bridge module I2 includes a first NMOS transistor M1 as a high-side bridge and a second NMOS transistor M2 as a low-side bridge; the driving half-bridge module I2 is grounded through a sampling resistor Rs; the high-side bridge receives the high-side signal HOX, and the low-side bridge receives the low-side signal LOX;

[0010] The gate-source hardware clamping module I3 is connected to the driving half-bridge module I2 and is used to clamp the first NMOS transistor M1 when it is short-circuited and overcurrent.

[0011] The gate-source hardware clamping module I3 includes a clamping diode D1, a third PMOS transistor M3, and a first resistor R1;

[0012] The cathode of the clamping diode D1 is connected to one end of the first resistor R1 and the gate of the third PMOS transistor M3; the anode of the clamping diode D1 is connected to the source of the first NMOS transistor M1; the other end of the first resistor R1 is connected to the high-side signal HOX; the source of the third PMOS transistor M3 is connected to the high-side signal HOX, and the drain is connected to the source of the first NMOS transistor M1.

[0013] The phase voltage short-circuit protection module I4 is connected to the drive half-bridge module I2 and is used to control the overcurrent time when the first NMOS transistor M1 is short-circuited and overcurrent, and to send a fault signal to the logic module I6 when the first NMOS transistor M1 or the second NMOS transistor M2 is detected to be short-circuited and overcurrent.

[0014] The bus overcurrent protection module I5 is connected to the sampling resistor Rs and is used to determine whether there is a bus overcurrent based on the voltage across the sampling resistor Rs, and to send a fault signal to the logic module I6 when there is a bus overcurrent.

[0015] The logic module I6 is used to determine whether to shut down the pre-drive module I1 based on the fault signal so that the short-circuit protection circuit enters the protection state.

[0016] Specifically, the driving half-bridge module I2 includes: the high-side signal HOX is connected to the gate of the first NMOS transistor M1, serving as the high-side gate drive of the driving half-bridge module I2; the drain of the first NMOS transistor M1 is connected to the high-voltage power supply VM; the source of the first NMOS transistor M1 is connected to the drain of the second NMOS transistor M2; the low-side signal LOX is connected to the gate of the second NMOS transistor M2, serving as the low-side gate drive of the driving half-bridge module I2; and the source of the second NMOS transistor M2 is connected to the power ground COM through the sampling resistor Rs.

[0017] Specifically, the gate source hardware clamping module I3 also includes:

[0018] When the source potential V2 of the first NMOS transistor M1 is short-circuited to ground, current flows through the first resistor R1 to the clamping diode D1, triggering clamping. The voltage drop across the first resistor R1 causes the third PMOS transistor M3 to turn on. The drive current on the high-side signal HOX flows through the source and drain of the third PMOS transistor M3 to V2, clamping the high-side signal HOX voltage at V2. GS_M3 +V Z_D1 V GS_M3 This is the gate-source voltage difference of the third PMOS transistor M3.

[0019] Specifically, the phase voltage short-circuit protection module I4 includes a VDS_VREF generation circuit and a comparator circuit;

[0020] The VDS_VREF generation circuit includes a first operational amplifier P1, a fourth NMOS transistor M4, a second resistor R2, a third resistor R3, a fourth resistor R4, an internal analog power supply AVDD, a second internal reference voltage VREF1, and a current mirror circuit; the comparator circuit includes a first comparator CP1 and a second comparator CP2.

[0021] The non-inverting input of the first operational amplifier P1 is connected to the second internal reference voltage VREF1, the inverting input is connected to analog ground VSS through the second resistor R2, and the output is connected to the gate of the fourth NMOS transistor M4. The current mirror circuit includes a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, and a ninth NMOS transistor M9. The source of the fourth NMOS transistor M4 is connected to analog ground VSS through the second resistor R2, and its drain is connected to the drain of the sixth PMOS transistor M6. The drain of the fifth PMOS transistor M5 is connected to the internal analog power supply AVDD, its gate is connected to the gate of the sixth PMOS transistor M6, and its source is connected to the drain of the eighth NMOS transistor M8. The drain of the sixth PMOS transistor M6 is connected to the internal analog power supply AVDD, and its gate is connected to its source. The drain of the seventh PMOS transistor M7 is connected to the internal analog power supply AVDD, and its gate is connected to the gate of the ninth NMOS transistor M9. The source of the sixth PMOS transistor M6 is connected to the third resistor R3, and also to the non-inverting input of the second comparator CP2; the drain of the eighth NMOS transistor M8 is connected to the gate, and the source is connected to analog ground VSS; the drain of the ninth NMOS transistor M9 is connected to the fourth resistor R4, the gate is connected to the gate of the eighth NMOS transistor M8, and the source is connected to analog ground VSS; the drain of the first NMOS transistor M1 is connected to the drain of the ninth NMOS transistor M9 and the non-inverting input of the first comparator CP1 via the fourth resistor R4; the source of the first NMOS transistor M1 is connected to the inverting input of the first comparator CP1 and the inverting input of the second comparator CP2; the source of the second NMOS transistor M2 is connected to the non-inverting input of the second comparator CP2 via the third resistor R3; the outputs of the first comparator CP1 and the second comparator CP2 are connected to logic module I6.

[0022] Specifically, the VDS_VREF generation circuit generates a first current I. I1 The second current I I2 Third current I I3 The first current I is replicated by a current mirror circuit. I1 Finally, the second current I I2The current flowing through the third resistor R3 is converted into the low-side bridge reference voltage V. DSL_VREF The third current I I3 The current flowing through the fourth resistor R4 is converted into the high-side bridge reference voltage V. DSH_VREF :

[0023] V DSH_VREF =V VREF1 ,

[0024] V DSL_VREF =V VREF1 ,

[0025] Among them, V VREF1 The voltage value of the second internal reference voltage VREF1; R R2 R is the resistance value of the second resistor R2; R3 R is the resistance value of the third resistor R3; R4 This is the resistance value of the fourth resistor, R4.

[0026] Specifically, the phase voltage short-circuit protection module I4 also includes:

[0027] If the first comparator CP1 detects the source voltage V of the first NMOS transistor M1 V2 If the voltage is lower than the second preset point, a fault is determined, and a high-side bridge fault signal V6 is output; if the second comparator CP2 detects the drain voltage V of the second NMOS transistor M2... V2 If the voltage exceeds the first preset point, a fault is detected, and a low-side bridge fault signal V7 is output; the first preset point voltage is V. V3 +V DSL_VREF The second preset point voltage is V. V1 -V DSH_VREF V V3 V is the voltage corresponding to the source potential V3 of the second NMOS transistor M2; V V1 V1 is the voltage corresponding to the source potential of the first NMOS transistor M1.

[0028] Specifically, the bus overcurrent protection module I5 includes a second operational amplifier P2 and a third comparator CP3;

[0029] The non-inverting input of the second operational amplifier P2 is connected to the source of the first NMOS, the inverting input is connected to analog ground VSS, and the output is connected to the non-inverting input of the third comparator CP3.

[0030] The inverting input of the third comparator CP3 is connected to the first internal reference voltage VREF, and its output is connected to the logic module I6.

[0031] The bus current I is obtained through the sampling resistor Rs. CHOPConverted to the non-inverting input voltage V of the second operational amplifier P2 V4 and the inverting input voltage V V5 After being amplified by the second operational amplifier P2, the amplified voltage is output to the third comparator CP3 and compared with the first internal reference voltage VREF. If the amplified voltage exceeds the first internal reference voltage VREF, it is determined that there is a bus overcurrent, and an overcurrent fault signal V8 is sent to the logic module I6; where V... V4 Bus current I CHOP V is obtained by sampling the voltage value before resistor Rs. V5 This is the voltage value after passing through the sampling resistor Rs.

[0032] Specifically, the bus overcurrent protection module I5 further includes: adjusting the amplification factor Av of the second operational amplifier P2 and the resistance value R of the sampling resistor Rs according to the following formula. SENSE The voltage V of the first internal reference voltage VREF VREF Set bus current I CHOP The rated value;

[0033] ,

[0034] Among them, V IO This is the offset voltage of the second operational amplifier P2.

[0035] Specifically, the logic module I6 includes a digital filter circuit and a timer circuit;

[0036] The logic module I6 performs digital filtering on the high-side bridge fault signal V6 or the low-side bridge fault signal V7 for a first detection duration using a digital filtering circuit. If the high-side bridge fault signal V6 or the low-side bridge fault signal V7 is still at a high level after digital filtering, it is considered that a fault exists. Then, the pre-drive module I1 is turned off by the control signal CTRL to turn off the drive half-bridge module I2. At the same time, the phase voltage short circuit protection module I4 and the bus overcurrent protection module I5 are turned off to prevent false triggering of the fault. Otherwise, it is considered that the fault does not exist, and each module continues to work normally.

[0037] The logic module I6 performs digital filtering on the overcurrent fault signal V8 for a second detection duration using a digital filtering circuit. If the overcurrent fault signal V8 is still at a high level after digital filtering, it is considered that a fault exists. Then, the pre-drive module I1 is turned off by the control signal CTRL to turn off the drive half-bridge module I2, and the phase voltage short circuit protection module I4 and the bus overcurrent protection module I5 are also turned off.

[0038] Specifically, the logic module I6 further includes: when a fault is determined to exist, the logic module I6 re-opens the pre-drive module I1 by controlling the control signal CTRL after timing the second detection duration through the timer circuit, and re-detects whether the fault exists. If the fault is eliminated, the circuit resumes normal operation; otherwise, it continues to re-detect whether the fault exists by timing the second detection duration through the timer circuit.

[0039] This invention provides a short-circuit protection circuit for a high-voltage half-bridge driver chip. Through a three-stage stepped hierarchical protection system, it can intelligently detect the degree of overcurrent under different fault scenarios and automatically switch the response speed and protection mechanism in real time according to different degrees. It can effectively protect the circuit by balancing high precision, fast response speed and strong anti-interference ability. Moreover, the three-stage protection circuit has a simple structure, uses fewer hardware resources, and effectively reduces chip cost. Furthermore, this short-circuit protection circuit can be applied to power electronics, motor drives, switching power supplies and other fields, and has a wide range of application scenarios.

[0040] Furthermore, the short-circuit protection circuit for a high-voltage half-bridge driver chip provided by this invention also has an automatic reset function, enabling automated operation without any control. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a short-circuit protection circuit for a half-bridge driver chip according to an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of a short-circuit protection circuit for a half-bridge driver chip according to an embodiment of the present invention. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0045] In the description of this invention, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order of the technical features indicated.

[0046] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the drawings and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0047] In the description of this invention, it should be noted that, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0048] Example 1

[0049] refer to Figure 1 This embodiment provides a short-circuit protection circuit for a half-bridge driver chip, including a pre-drive module I1, a driver half-bridge module I2, a gate-source hardware clamping module I3, a phase voltage short-circuit protection module I4, a bus overcurrent protection module I5, a logic module I6, and a sampling resistor Rs.

[0050] The pre-drive module I1 is a common pre-drive circuit, used to generate a set of high-side signals HOX and low-side signals LOX with driving capability as inputs to drive the half-bridge module I2.

[0051] The pre-drive module I1 includes a first pre-drive circuit PD1 and a second pre-drive circuit PD2;

[0052] The first pre-drive circuit PD1 is connected to the high-side pre-drive power supply VCP, and outputs the high-side signal HOX after receiving the high-side pre-drive input signal;

[0053] The second pre-drive circuit PD2 is connected to the low-side pre-drive power supply VGLS, and outputs the low-side signal LOX after receiving the low-side pre-drive input signal;

[0054] The pre-drive circuit is a common component in microcontroller circuits. Its function is to provide appropriate signal pre-processing for subsequent drive circuits. The pre-drive circuit adjusts and amplifies the input signal to meet the requirements of the drive circuit in terms of signal amplitude, frequency, and waveform; this is existing technology and will not be elaborated further here.

[0055] The driving half-bridge module I2 includes a first NMOS transistor M1 as a high-side bridge and a second NMOS transistor M2 as a low-side bridge.

[0056] The high-side signal HOX is connected to the gate of the first NMOS transistor M1 and serves as the high-side gate drive of the driving half-bridge module I2; the drain of the first NMOS transistor M1 is connected to the high-voltage power supply VM; the source of the first NMOS transistor M1 is connected to the drain of the second NMOS transistor M2.

[0057] The low-side signal LOX is connected to the gate of the second NMOS transistor M2 and serves as the low-side gate drive for the driving half-bridge module I2; the source of the second NMOS transistor M2 is connected to power ground COM through the sampling resistor Rs.

[0058] In this embodiment, the high-voltage power supply VM is a 48V power supply; the power ground COM is 0V; and the sampling resistor Rs is 10 milliohms.

[0059] The gate-source hardware clamping module I3 is connected to the driving half-bridge module I2 and is used to clamp the gate-source voltage of the first NMOS transistor M1 when the source of the first NMOS transistor M1 is short-circuited to ground.

[0060] The gate-source hardware clamping module I3 includes a clamping diode D1, a third PMOS transistor M3, and a first resistor R1;

[0061] The cathode of the clamping diode D1 is connected to one end of the first resistor R1 and the gate of the third PMOS transistor M3; the anode of the clamping diode D1 is connected to the source of the first NMOS transistor M1; the other end of the first resistor R1 is connected to the high-side signal HOX.

[0062] The source of the third PMOS transistor M3 is connected to the high-side signal HOX, and the drain is connected to the source of the first NMOS transistor M1.

[0063] In the gate-source hardware clamping module I3, the clamping diode D1, the third PMOS transistor M3, and the first resistor R1 are the key circuits for forming the hardware clamping. Traditional structures generally use clamping diodes directly for clamping protection. However, when the high-side MOS transistor (the first NMOS transistor M1) is turned on, there is an ampere-level DC drive current on the HOX, which is difficult to meet the overcurrent capability of the clamping diode. Therefore, the voltage clamping path and the current discharge path are separated in the I3 circuit.

[0064] When the chip is operating normally, the voltage difference between the high-side signal HOX and V2 is lower than V. Z_D1 No current flows through the path from the first resistor R1 to the clamping diode D1, and the third PMOS transistor M3 is turned off; where V Z_D1 V1 is the clamping voltage of clamping diode D1; V2 is the source potential of the first NMOS transistor M1, and V2 is also the drain potential of the second NMOS transistor M2, with a corresponding voltage V0.V2 It is both the source voltage of the high-side bridge and the drain voltage of the low-side bridge.

[0065] In motor applications, exposed phase wires can easily lead to short circuits to ground. Specifically, when the source potential V2 of the first NMOS transistor M1 is short-circuited to ground, current flows through the clamping diode D1 triggered by the first resistor R1. The voltage drop across the first resistor R1 causes the third PMOS transistor M3 to turn on. The drive current on the high-side signal HOX flows through the source and drain of the third PMOS transistor M3 to V2, clamping the high-side signal HOX voltage at V2. GS_M3 +V Z_D1 V GS_M3 The gate-source voltage difference of the third PMOS transistor M3; the clamping diode D1 only needs to carry tens of microamps of current to turn on M3 for gate-source clamping within hundreds of nanoseconds, which has high precision and can greatly reduce chip cost.

[0066] While the gate-source hardware clamping module I3 can clamp quickly, it generates an ampere-level clamping current from the chip to ground, which can damage the chip's internal layout traces over time. Therefore, we also need to use the phase voltage short-circuit protection module I4 to control the duration of this clamping current.

[0067] Because the MOSFETs (first NMOS transistor M1 and second NMOS transistor M2) on each driving half-bridge operate in the deep linear region, according to the formula for the deep linear region of MOSFETs, V DS =I D *R ON , where V DS I is the voltage difference between the source and drain terminals of the MOSFET. D R is the current flowing through the source and drain of the MOSFET. ON The on-resistance of the MOSFET can be obtained from the MOSFET datasheet, so we can monitor the MOSFET's Von. DS Voltage is used to monitor the current on the MOS.

[0068] During motor operation, short circuits to the bus, to ground, or between phases (SHx) can easily occur due to exposed phase wires. In such cases, the voltage difference between the drain and source of the MOSFET will be pulled up to VM. Therefore, we can set an internal reference voltage V. DS_VREF The drain-source voltage difference V with the half-bridge MOSFET DS_MOS Comparison, V DS_VREF The internal reference voltage of the high-side bridge (first NMOS transistor M1) is set to V. DSH_VREF The internal reference voltage of the low-side bridge (second NMOS transistor M2) is set to V. DSL_VREF It does not trigger during normal operation, but triggers when a fault occurs.

[0069] The phase voltage short-circuit protection module I4 is connected to the drive half-bridge module I2 and is used to control the overcurrent time when the first NMOS transistor M1 is short-circuited and overcurrent, and to send a fault signal to the logic module I6 when the first NMOS transistor M1 or the second NMOS transistor M2 is detected to be short-circuited and overcurrent.

[0070] The phase voltage short-circuit protection module I4 includes a VDS_VREF generation circuit and a comparator circuit.

[0071] The VDS_VREF generation circuit includes a first operational amplifier P1, a fourth NMOS transistor M4, a second resistor R2, a third resistor R3, a fourth resistor R4, an internal analog power supply AVDD, a second internal reference voltage VREF1, and a current mirror circuit.

[0072] The first operational amplifier P1 is a high-precision programmable gain amplifier; the internal analog power supply AVDD is a 5V power supply;

[0073] The comparator circuit includes a first comparator CP1 and a second comparator CP2;

[0074] A PGA (Programmable Gain Amplifier) ​​is an amplifier whose gain can be changed by an external control signal. It is often used in applications that require flexible adjustment of signal amplification, such as in analog signal acquisition, data conversion (such as before ADC), and sensor interface circuits.

[0075] A COMP (Comparator) is an indispensable part of the peripheral modules of a microcontroller (MCU). Its core function is to compare the voltage levels of two analog signals and output a digital signal to indicate which input signal has a higher voltage.

[0076] The non-inverting input of the first operational amplifier P1 is connected to the second internal reference voltage VREF1, the inverting input is connected to analog ground VSS through the second resistor R2, and the output is connected to the gate of the fourth NMOS transistor M4.

[0077] The current mirror circuit includes a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, and a ninth NMOS transistor M9.

[0078] The source of the fourth NMOS transistor M4 is connected to analog ground VSS through the second resistor R2, and the drain is connected to the drain of the sixth PMOS transistor M6.

[0079] The drain of the fifth PMOS transistor M5 is connected to the internal analog power supply AVDD, the gate is connected to the gate of the sixth PMOS transistor M6, and the source is connected to the drain of the eighth NMOS transistor M8. Figure 2 IP is the source output current of the fifth PMOS transistor M5, and also the drain input current of the eighth NMOS transistor M8.

[0080] The drain of the sixth PMOS transistor M6 is connected to the internal analog power supply AVDD, and the gate is connected to the source.

[0081] The drain of the seventh PMOS transistor M7 is connected to the internal analog power supply AVDD, the gate is connected to the source of the sixth PMOS transistor M6, and the source is connected to the third resistor R3.

[0082] The drain of the first NMOS transistor M1 is connected to the drain of the ninth NMOS transistor M9 and the non-inverting input of the first comparator CP1 via the fourth resistor R4.

[0083] The source of the first NMOS transistor M1 is connected to the inverting input terminal of the first comparator CP1 and the inverting input terminal of the second comparator CP2, respectively.

[0084] The source of the second NMOS transistor M2 is connected to the non-inverting input of the second comparator CP2 through the third resistor R3;

[0085] The outputs of the first comparator CP1 and the second comparator CP2 are connected to the logic module I6;

[0086] The phase voltage short-circuit protection module I4 mainly consists of a VDS_VREF generation circuit and a comparator. The VDS_VREF generation circuit generates a first current I. I1 The second current I I2 and the third current I I3 The first current I is replicated by a current mirror circuit. I1 Finally, the second current I I2 The current flowing through the third resistor R3 is converted into the low-side bridge reference voltage V. DSL_VREF The third current I I3 The current flowing through the fourth resistor R4 is converted into the high-side bridge reference voltage V. DSH_VREF :

[0087] V DSH_VREF =V VREF1 ,

[0088] V DSL_VREF =V VREF1 ,

[0089] Among them, V VREF1The voltage value of the second internal reference voltage VREF1; R R2 R is the resistance value of the second resistor R2; R3 R is the resistance value of the third resistor R3; R4 Let R4 be the resistance value of the fourth resistor.

[0090] R R4 With R R2 The ratio and R R3 With R R2 The ratio is set according to different application scenarios and different VDS levels, and no specific limit is made here.

[0091] The value of the first resistor R1 is also set according to different voltage thresholds and the different characteristics of the third PMOS transistor M3, and is used for current limiting and voltage division.

[0092] The current mirror circuit generates a corresponding proportional channel current by operating multiple MOSFETs at the same gate-source voltage and adjusting their width-to-length ratio.

[0093] Therefore, we can set different V values ​​by adjusting the current ratio and resistance ratio. DS_VREF .

[0094] The comparator circuit consists of two comparators, a first comparator CP1 and a second comparator CP2, which monitor the first NMOS transistor M1 and the second NMOS transistor M2, respectively. The comparison principle is as follows: if the first comparator CP1 detects the source voltage V of the high-side bridge (first NMOS transistor M1)... V2 Voltage lower than the second preset point (V) V1 -V DSH_VREF If the fault is detected, a high-side bridge fault signal V6 is output; if the second comparator CP2 detects the drain voltage V of the low-side bridge (second NMOS transistor M2), then a fault is detected. V2 Exceeding the first preset point voltage (V) V3 +V DSL_VREF If a fault is detected, a low-side bridge fault signal V7 is output; where V V3 V is the voltage corresponding to the source potential V3 of the second NMOS transistor M2, i.e., the source voltage of the low-side bridge; V V1 V1 is the voltage corresponding to the source potential V1 of the first NMOS transistor M1, which is the drain voltage of the high-side bridge.

[0095] To prevent false triggering caused by voltage spikes on V1, V2, and V3, the phase voltage short-circuit protection module I4 outputs the high-side bridge fault signal V6 or the low-side bridge fault signal V7 to the logic module I6 for digital filtering for the first detection period after judging the fault. If the high-side bridge fault signal V6 or the low-side bridge fault signal V7 still exists, the pre-drive module I1 is turned off to turn off the drive half-bridge module I2.

[0096] The first detection duration is 1 to 2 microseconds. Preferably, in this embodiment, the first detection duration is 2 microseconds, which can be changed according to actual needs.

[0097] However, due to the poor temperature characteristics of the on-resistance of the MOSFET, the phase voltage short-circuit protection module I4 can only be applied to short-circuit high current scenarios and cannot accurately monitor overcurrent scenarios such as motor stall.

[0098] The bus overcurrent protection module I5 is connected to the sampling resistor Rs and is used to determine whether there is a bus overcurrent based on the voltage across the sampling resistor Rs, and to send a fault signal to the logic module I6 when there is a bus overcurrent.

[0099] The bus overcurrent protection module I5 includes a second operational amplifier P2 and a third comparator CP3;

[0100] The non-inverting input of the second operational amplifier P2 is connected to the source of the first NMOS, the inverting input is connected to analog ground VSS, and the output is connected to the non-inverting input of the third comparator CP3.

[0101] The inverting input of the third comparator CP3 is connected to the first internal reference voltage VREF, and its output is connected to the logic module I6.

[0102] Assume the offset voltage of the second operational amplifier P2 is V. IO The bus current I is obtained through the sampling resistor Rs. CHOP Converted to the input voltage V of the second op-amp P2 V4 and V V5 It is understandable that the bus current I CHOP The potential before the sampling resistor Rs is V4, and its voltage value is V. V4 V4 is connected to the non-inverting input of the second operational amplifier P2. The potential after passing through the sampling resistor Rs is V5, and its voltage value is V. V5 V5 is connected to the inverting input of the second operational amplifier P2. After being amplified by the PGA (second operational amplifier P2), the amplified voltage is output to the third comparator CP3 and compared with the first internal reference voltage VREF. If the amplified voltage exceeds the first internal reference voltage VREF, it is determined that the bus is overcurrent and an overcurrent fault signal V8 is sent to the logic module I6.

[0103] because Therefore, we can adjust the amplification factor Av of the second operational amplifier P2 and the resistance R of the sampling resistor Rs. SENSE The voltage V of the first internal reference voltage VREF VREF To accurately set the bus current I CHOPThe rated value. However, due to its high sampling accuracy, in order to reduce false triggering caused by external interference, the digital filtering time of the overcurrent fault signal V8 of the bus overcurrent protection module I5 after being input to the logic module I6 is increased to the second detection duration. If the overcurrent fault signal V8 still exists, the pre-drive module I1 is turned off to turn off the drive half-bridge module I2, and the phase voltage short circuit protection module I4 and the bus overcurrent protection module I5 are turned off to prevent false triggering of faults.

[0104] R SENSE The value is based on the bus current I CHOP The rated value needs to be set;

[0105] The values ​​of the first internal reference voltage VREF and the second internal reference voltage VREF1 are determined by the voltage division of the reference voltage output from the bandgap reference source BG inside the chip, according to the application scenario.

[0106] A bandgap reference (BG) is a circuit module that provides a stable voltage or current reference.

[0107] The second detection duration is 2 to 4 microseconds. Preferably, in this embodiment, the second detection duration is 4 microseconds, which can be changed according to actual needs.

[0108] The logic module I6 is used to determine whether to shut down the pre-drive module I1 based on the fault signal so that the short-circuit protection circuit enters the protection state.

[0109] The logic module I6 is the digital core inside the chip, used to control and process internal logic signals. It includes a digital filtering circuit and a timer circuit. It receives the fault signals output by the first comparator CP1, the second comparator CP2 and the third comparator CP3, filters them and then determines whether to shut down the pre-drive module I1. The fault signals include the high-side bridge fault signal V6, the low-side bridge fault signal V7 and the overcurrent fault signal V8.

[0110] The digital filtering circuit is connected to the timer circuit. The digital filtering circuit receives the fault signal, and the timer circuit is used for timing.

[0111] The logic module I6 performs digital filtering on the high-side bridge fault signal V6 or the low-side bridge fault signal V7 for a first detection duration using a digital filtering circuit. If the high-side bridge fault signal V6 or the low-side bridge fault signal V7 is still at a high level after digital filtering, it is considered that a fault exists. Then, the pre-drive module I1 is turned off by the control signal CTRL to turn off the drive half-bridge module I2. At the same time, the phase voltage short circuit protection module I4 and the bus overcurrent protection module I5 are turned off to prevent false triggering of the fault. Otherwise, it is considered that the fault does not exist, and each module continues to work normally.

[0112] The logic module I6 performs digital filtering on the overcurrent fault signal V8 for a second detection duration using a digital filtering circuit. If the overcurrent fault signal V8 is still at a high level after digital filtering, it is considered that a fault exists. Then, the pre-drive module I1 is turned off by the control signal CTRL to turn off the drive half-bridge module I2. At the same time, the phase voltage short circuit protection module I4 and the bus overcurrent protection module I5 are turned off to prevent false triggering of the fault.

[0113] The logic module I6 further includes that when a fault is determined to exist, the logic module I6 re-opens the pre-drive module I1 by controlling the control signal CTRL after timing the second detection duration through the timer circuit, and re-detects whether the fault exists. If the fault is eliminated, the circuit returns to normal operation; otherwise, it continues to re-detect whether the fault exists by timing the second detection duration through the timer circuit.

[0114] Digital filtering circuits are a mature circuit structure, and will not be elaborated here. They utilize the synchronous sampling and edge-triggered characteristics of DFF to filter out glitches and jitters that last for less than one clock cycle, which cannot be stably sampled and filtered out at consecutive clock edges.

[0115] The timer circuit is a mature circuit structure, so it will not be described in detail here. It uses the memory function of the flip-flop to accumulate the number of input clock pulses to keep track of time.

[0116] It is understood that the NMOS transistor described in this embodiment is an N-type MOS transistor (metal-oxide-semiconductor), and the PMOS transistor is an N-type MOS transistor (metal-oxide-semiconductor).

[0117] In this embodiment, both the NMOS transistor and the PMOS transistor are high-voltage MOS transistors;

[0118] The first operational amplifier P1 and the second operational amplifier P2 are high-precision programmable gain amplifiers (PGAs).

[0119] The gate-source hardware clamping module I3 is the first-level protection circuit, which mainly deals with scenarios such as V2 short circuit to ground and instantaneous overvoltage of the gate-source of the high-side MOSFET (first NMOS transistor M1). When it detects that the gate-source voltage difference of the high-side MOSFET exceeds the normal operating range, that is, the oxide layer breakdown voltage of the MOSFET (which can be obtained from the MOSFET datasheet), it directly clamps the gate-source voltage without going through the logic module I6. It can clamp the gate-source voltage within the rated range within hundreds of nanoseconds to prevent the high-voltage pump gate oxide of the high-side MOSFET from being damaged.

[0120] The phase voltage short-circuit protection module I4 is a second-level protection circuit. It samples the source-drain voltage of the MOSFETs to determine whether a short-circuit overcurrent has occurred. It primarily addresses scenarios such as high-side and low-side MOSFET drain-source overcurrent during phase-to-ground and power supply short circuits. When it detects that the drain-source voltage difference of the MOSFETs exceeds the drain-source voltage difference V of the half-bridge MOSFETs corresponding to the set short-circuit current... DS_MOS When the fault signal is detected, it will be sent to the logic module I6 for judgment, and then the drive circuit will be shut down. The protection circuit is relatively fast and can be controlled within 1~2us.

[0121] The bus overcurrent protection module I5 is a third-level protection circuit. It determines whether there is an overcurrent by sampling the voltage across the resistor Rs. It is mainly used to deal with bus current overcurrent scenarios such as motor stall. It has high sampling accuracy, strong anti-interference ability, and the response speed can be controlled within 2~4us.

[0122] The logic module I6 is the internal digital core of the chip, mainly responsible for controlling and processing internal logic signals. When a fault signal (V6, V7, V8) is input, it is digitally filtered by the internal digital filtering circuit to prevent false triggering caused by external interference. If the fault signal (V6, V7, V8) is still high after digital filtering, the control signal CTRL will be output to shut down modules I1, I2, I4, and I5, and the internal timer circuit will count to 4ms. After 4ms, modules I1, I2, I4, and I5 will be turned on for re-detection. If the fault is cleared, i.e., the fault signal is low after digital filtering, normal operation will resume. If the fault still exists, the half-bridge will be shut down for another 4ms before re-detection.

[0123] The fault protection of the gate source hardware clamping module I3, phase voltage short circuit protection module I4, and bus overcurrent protection module I5 all have automatic reset functions, eliminating the need for external reset.

[0124] When the fault detected by the gate source hardware clamping module I3 is eliminated, it only takes tens of nanoseconds to restore the half-bridge circuit to work.

[0125] When the phase voltage short circuit protection module I4 and the bus overcurrent protection module I5 detect a fault, the half-bridge circuit will be restarted and re-detected every 4ms. If the fault is eliminated, normal operation will resume; if the fault still exists, the half-bridge will be shut down for another 4ms and then re-detected.

[0126] This embodiment presents a short-circuit protection circuit for a high-voltage half-bridge driver chip. Through a three-stage stepped hierarchical protection system, it can intelligently detect the degree of overcurrent under different fault scenarios and automatically switch the response speed and protection mechanism in real time according to different degrees. It can effectively protect the circuit by balancing high precision, fast response speed, and anti-interference capability. Moreover, the three-stage protection circuit has a simple structure, uses fewer hardware resources, and effectively reduces chip costs. Furthermore, this short-circuit protection circuit can be applied to fields such as power electronics, motor drives, and switching power supplies, with a wide range of specific application scenarios.

[0127] Furthermore, the short-circuit protection circuit of the high-voltage half-bridge driver chip in this embodiment also has an automatic reset function, which can achieve automated operation without any control.

[0128] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Those skilled in the art should understand that the present invention includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, and any modifications that do not depart from the functional and structural principles of the present invention, should be included within the protection scope of the present invention.

Claims

1. A short-circuit protection circuit for a half-bridge driver chip, characterized in that, It includes the following modules: pre-drive module I1, drive half-bridge module I2, gate source hardware clamping module I3, phase voltage short circuit protection module I4, bus overcurrent protection module I5, logic module I6, and sampling resistor Rs; The pre-driving module I1 is used to generate the high-side signal HOX and the low-side signal LOX; The driving half-bridge module I2 includes a first NMOS transistor M1 as a high-side bridge and a second NMOS transistor M2 as a low-side bridge; the driving half-bridge module I2 is grounded through a sampling resistor Rs; the high-side bridge receives the high-side signal HOX, and the low-side bridge receives the low-side signal LOX; The gate-source hardware clamping module I3 includes a clamping diode D1, a third PMOS transistor M3 and a first resistor R1, which are used to clamp the first NMOS transistor M1 when it is short-circuited and overcurrent. The cathode of the clamping diode D1 is connected to one end of the first resistor R1 and the gate of the third PMOS transistor M3; the anode of the clamping diode D1 is connected to the source of the first NMOS transistor M1; the other end of the first resistor R1 is connected to the high-side signal HOX; the source of the third PMOS transistor M3 is connected to the high-side signal HOX, and the drain is connected to the source of the first NMOS transistor M1. The phase voltage short-circuit protection module I4 is connected to the drive half-bridge module I2 and is used to control the overcurrent time when the first NMOS transistor M1 is short-circuited and overcurrent, and to send a fault signal to the logic module I6 when the first NMOS transistor M1 or the second NMOS transistor M2 is detected to be short-circuited and overcurrent. The bus overcurrent protection module I5 is connected to the sampling resistor Rs and is used to determine whether there is a bus overcurrent based on the voltage across the sampling resistor Rs, and to send a fault signal to the logic module I6 when there is a bus overcurrent. The logic module I6 is used to determine whether to shut down the pre-drive module I1 based on the fault signal so that the short-circuit protection circuit enters the protection state.

2. The short-circuit protection circuit for the half-bridge driver chip according to claim 1, characterized in that, The driving half-bridge module I2 specifically includes: the high-side signal HOX is connected to the gate of the first NMOS transistor M1, serving as the high-side gate drive of the driving half-bridge module I2; the drain of the first NMOS transistor M1 is connected to the high-voltage power supply VM; the source of the first NMOS transistor M1 is connected to the drain of the second NMOS transistor M2; the low-side signal LOX is connected to the gate of the second NMOS transistor M2, serving as the low-side gate drive of the driving half-bridge module I2; and the source of the second NMOS transistor M2 is connected to the power ground COM through the sampling resistor Rs.

3. The short-circuit protection circuit for the half-bridge driver chip according to claim 1, characterized in that, The gate source hardware clamping module I3 also includes: When the source potential V2 of the first NMOS transistor M1 is short-circuited to ground, current flows through the first resistor R1 to the clamping diode D1, triggering clamping. The voltage drop across the first resistor R1 causes the third PMOS transistor M3 to turn on. The drive current on the high-side signal HOX flows through the source and drain of the third PMOS transistor M3 to V2, clamping the high-side signal HOX voltage at V2. GS_M3 +V Z_D1 V GS_M3 This is the gate-source voltage difference of the third PMOS transistor M3.

4. The short-circuit protection circuit for the half-bridge driver chip according to claim 1, characterized in that, The phase voltage short-circuit protection module I4 includes a VDS_VREF generation circuit and a comparator circuit. The VDS_VREF generation circuit includes a first operational amplifier P1, a fourth NMOS transistor M4, a second resistor R2, a third resistor R3, a fourth resistor R4, an internal analog power supply AVDD, a second internal reference voltage VREF1, and a current mirror circuit; the comparator circuit includes a first comparator CP1 and a second comparator CP2. The non-inverting input of the first operational amplifier P1 is connected to the second internal reference voltage VREF1, the inverting input is connected to analog ground VSS through the second resistor R2, and the output is connected to the gate of the fourth NMOS transistor M4. The current mirror circuit includes a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, and a ninth NMOS transistor M9. The source of the fourth NMOS transistor M4 is connected to analog ground VSS through the second resistor R2, and its drain is connected to the drain of the sixth PMOS transistor M6. The drain of the fifth PMOS transistor M5 is connected to the internal analog power supply AVDD, its gate is connected to the gate of the sixth PMOS transistor M6, and its source is connected to the drain of the eighth NMOS transistor M8. The drain of the sixth PMOS transistor M6 is connected to the internal analog power supply AVDD, and its gate is connected to its source. The drain of the seventh PMOS transistor M7 is connected to the internal analog power supply AVDD, and its gate is connected to the gate of the ninth NMOS transistor M9. The source of the sixth PMOS transistor M6 is connected to the third resistor R3, and also to the non-inverting input of the second comparator CP2; the drain of the eighth NMOS transistor M8 is connected to the gate, and the source is connected to analog ground VSS; the drain of the ninth NMOS transistor M9 is connected to the fourth resistor R4, the gate is connected to the gate of the eighth NMOS transistor M8, and the source is connected to analog ground VSS; the drain of the first NMOS transistor M1 is connected to the drain of the ninth NMOS transistor M9 and the non-inverting input of the first comparator CP1 via the fourth resistor R4; the source of the first NMOS transistor M1 is connected to the inverting input of the first comparator CP1 and the inverting input of the second comparator CP2; the source of the second NMOS transistor M2 is connected to the non-inverting input of the second comparator CP2 via the third resistor R3; the outputs of the first comparator CP1 and the second comparator CP2 are connected to logic module I6.

5. The short-circuit protection circuit for the half-bridge driver chip according to claim 4, characterized in that, The VDS_VREF generation circuit generates a first current I. I1 The second current I I2 Third current I I3 The first current I is replicated by a current mirror circuit. I1 Finally, the second current I I2 The current flowing through the third resistor R3 is converted into the low-side bridge reference voltage V. DSL_VREF The third current I I3 The current flowing through the fourth resistor R4 is converted into the high-side bridge reference voltage V. DSH_VREF : V DSH_VREF =V VREF1 , V DSL_VREF =V VREF1 , Among them, V VREF1 The voltage value of the second internal reference voltage VREF1; R R2 R is the resistance value of the second resistor R2; R3 R is the resistance value of the third resistor R3; R4 This is the resistance value of the fourth resistor, R4.

6. The short-circuit protection circuit for the half-bridge driver chip according to claim 5, characterized in that, The phase voltage short-circuit protection module I4 also includes: If the first comparator CP1 detects the source voltage V of the first NMOS transistor M1 V2 If the voltage is lower than the second preset point, a fault is determined, and a high-side bridge fault signal V6 is output; if the second comparator CP2 detects the drain voltage V of the second NMOS transistor M2... V2 If the voltage exceeds the first preset point, a fault is detected, and a low-side bridge fault signal V7 is output; the first preset point voltage is V. V3 +V DSL_VREF The second preset point voltage is V. V1 -V DSH_VREF V V3 V is the voltage corresponding to the source potential V3 of the second NMOS transistor M2; V V1 V1 is the voltage corresponding to the source potential of the first NMOS transistor M1.

7. The short-circuit protection circuit for the half-bridge driver chip according to claim 1, characterized in that, The bus overcurrent protection module I5 includes a second operational amplifier P2 and a third comparator CP3; The non-inverting input of the second operational amplifier P2 is connected to the source of the first NMOS, the inverting input is connected to analog ground VSS, and the output is connected to the non-inverting input of the third comparator CP3. The inverting input of the third comparator CP3 is connected to the first internal reference voltage VREF, and its output is connected to the logic module I6. The bus current I is obtained through the sampling resistor Rs. CHOP Converted to the non-inverting input voltage V of the second operational amplifier P2 V4 and the inverting input voltage V V5 After being amplified by the second operational amplifier P2, the amplified voltage is output to the third comparator CP3 and compared with the first internal reference voltage VREF. If the amplified voltage exceeds the first internal reference voltage VREF, it is determined that there is a bus overcurrent, and an overcurrent fault signal V8 is sent to the logic module I6; where V... V4 Bus current I CHOP V is obtained by sampling the voltage value before resistor Rs. V5 This is the voltage value after passing through the sampling resistor Rs.

8. The short-circuit protection circuit for the half-bridge driver chip according to claim 7, characterized in that, The bus overcurrent protection module I5 further includes: adjusting the amplification factor Av of the second operational amplifier P2 and the resistance R of the sampling resistor Rs according to the following formula. SENSE The voltage V of the first internal reference voltage VREF VREF Set bus current I CHOP The rated value; ， Among them, V IO This is the offset voltage of the second operational amplifier P2.

9. The short-circuit protection circuit for the half-bridge driver chip according to claim 1, characterized in that, The logic module I6 includes a digital filter circuit and a timer circuit; The logic module I6 performs digital filtering on the high-side bridge fault signal V6 or the low-side bridge fault signal V7 for a first detection duration using a digital filtering circuit. If the high-side bridge fault signal V6 or the low-side bridge fault signal V7 is still at a high level after digital filtering, it is considered that a fault exists. Then, the pre-drive module I1 is turned off by the control signal CTRL to turn off the drive half-bridge module I2. At the same time, the phase voltage short circuit protection module I4 and the bus overcurrent protection module I5 are turned off to prevent false triggering of the fault. Otherwise, it is considered that the fault does not exist, and each module continues to work normally. The logic module I6 performs digital filtering on the overcurrent fault signal V8 for a second detection duration using a digital filtering circuit. If the overcurrent fault signal V8 is still at a high level after digital filtering, it is considered that a fault exists. Then, the pre-drive module I1 is turned off by the control signal CTRL to turn off the drive half-bridge module I2, and the phase voltage short circuit protection module I4 and the bus overcurrent protection module I5 are also turned off.

10. The short-circuit protection circuit for the half-bridge driver chip according to claim 9, characterized in that, The logic module I6 further includes: when a fault is determined to exist, the logic module I6 re-opens the pre-drive module I1 by controlling the control signal CTRL after timing the second detection duration through the timer circuit, and re-detects whether the fault exists. If the fault is eliminated, the circuit resumes normal operation; otherwise, it continues to re-detect whether the fault exists by timing the second detection duration through the timer circuit.

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