A high voltage side under voltage lockout circuit

Abstract

The application discloses a high-voltage side under-voltage lock circuit, and relates to the technical field of integrated circuits. When the power voltage starts to power on, a path from a power supply to the ground is generated from MOS tubes MP1, MP2, MP3, MN1 and MN3. When EN is a high level, the circuit normally works and can play an under-voltage lock function. When the BST voltage decreases to a designed threshold point, the output pin signal becomes a high level, an under-voltage lock signal is generated, and it is represented that the power voltage is abnormal and the subsequent circuit is not started. The application adopts a self-starting structure, omits a comparator and a logic circuit in a traditional UVLO circuit, has the advantages of simple circuit structure, saved layout area, low power consumption, and can design different voltage threshold points for under-voltage locks of different functions, and is more suitable for DCDC circuit types.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-voltage side undervoltage lockout circuit. Background Technology

[0002] Undervoltage lockout (UVLO) is a circuit in electronic devices that cuts off power when the supply voltage drops below the normal operating voltage. In embedded systems, UVLO is often used to monitor battery voltage; if the voltage falls below a certain value, it directly cuts off the power to protect the embedded system's circuitry. Many electronic devices incorporate UVLO functionality. Voltage stability is particularly critical in DC-DC power management chips, thus requiring the integration of undervoltage lockout circuitry to improve power supply reliability and safety. For other integrated circuits, undervoltage lockout circuitry is equally important for enhancing circuit reliability and stability.

[0003] Traditional undervoltage protection circuits are designed with comparators, bandgap reference voltages, and logic circuits, which suffer from problems such as slow response speed, high power consumption, and large circuit area. To address these issues, a new undervoltage protection circuit is needed that can achieve UVLO functionality without using reference voltages, comparators, or other modules. Summary of the Invention

[0004] Based on the above problems, the purpose of this invention is to propose a high-voltage side undervoltage lockout circuit that omits the comparator and logic circuit, and uses a self-starting circuit and a few MOSFETs to achieve the UVLO function, thus solving the problems of excessive layout area and excessive power consumption encountered in the use of traditional UVLO circuits.

[0005] To achieve the above objectives, the technical solution adopted by this invention is a high-voltage side undervoltage lockout circuit, comprising PMOS transistors MP1, MP2, MP3, MP4, and MP5, and NMOS transistors MN1, MN2, MN3, and MN4, wherein:

[0006] The source of PMOS transistor MP1 is connected to the BST pin, the gate is connected to the SW pin through the bias current, and the drain is connected to the source of PMOS transistor MP2.

[0007] The gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP2, and the drain is connected to the source of PMOS transistor MP3.

[0008] The drain of PMOS transistor MP3 is connected to its gate, and also to the drain and gate of NMOS transistor MN1.

[0009] The source of NMOS transistor MN1 is connected to the drain and gate of NMOS transistor MN3;

[0010] The source of NMOS transistor MN3 is connected to pin SW.

[0011] The source of PMOS transistor MP4 is connected to the BST pin, the gate is connected to the gate of PMOS transistor MP1, and the drain is connected to the source of PMOS transistor MP5.

[0012] The gate of PMOS transistor MP5 is connected to the gate of PMOS transistor MP4, and the drain is connected to the drain of NMOS transistor MN2 and the OUT1 output pin.

[0013] The source of NMOS transistor MN2 is connected to the drain of NMOS transistor MN4;

[0014] The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN3, and the source is connected to the SW pin.

[0015] Furthermore, the gate of the NMOS transistor MN2 is connected to the enable signal pin EN.

[0016] Furthermore, it also includes PMOS transistors MP6, MP7, and MP8, and NMOS transistors MN5, MN6, and MN7, among which:

[0017] The source of PMOS transistor MP6 is connected to the BST pin, the gate is connected to the gate of PMOS transistor MP4, and the drain is connected to the source of PMOS transistor MP7.

[0018] The drain of PMOS transistor MP7 is connected to its gate, and also to the drain and gate of NMOS transistor MN5.

[0019] The source of NMOS transistor MN5 is connected to pin SW.

[0020] The source of PMOS transistor MP8 is connected to the BST pin, the gate is connected to the gate of PMOS transistor MP6, and the drain is connected to the drain of NMOS transistor MN7 and the OUT2 output pin.

[0021] The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN6;

[0022] The gate of NMOS transistor MN6 is connected to the gate of NMOS transistor MN5, and the source is connected to the SW pin.

[0023] Furthermore, the gate of the NMOS transistor MN7 is connected to the enable signal pin EN.

[0024] The beneficial effects of this invention are as follows:

[0025] This invention adopts a self-starting structure, omitting the comparator and logic circuit in the traditional UVLO circuit. It has the advantages of simple circuit structure, saving layout area and low power consumption. Furthermore, different voltage threshold points can be designed for undervoltage lockout for different functions, making it more suitable for DC-DC circuit types. Attached Figure Description

[0026] Figure 1 This is a structural diagram of the high-voltage side undervoltage lockout circuit according to an embodiment of the present invention. Detailed Implementation

[0027] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] Figure 1 This illustration shows a specific embodiment of the high-voltage side undervoltage lockout circuit of the present invention, including PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, and MP8, and NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, and MN7, wherein:

[0029] The source of PMOS transistor MP1 is connected to the BST pin, the gate is connected to the SW pin through the bias current, and the drain is connected to the source of PMOS transistor MP2.

[0030] The gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP2, and the drain is connected to the source of PMOS transistor MP3.

[0031] The drain of PMOS transistor MP3 is connected to its gate, and also to the drain and gate of NMOS transistor MN1.

[0032] The source of NMOS transistor MN1 is connected to the drain and gate of NMOS transistor MN3;

[0033] The source of NMOS transistor MN3 is connected to pin SW.

[0034] The source of PMOS transistor MP4 is connected to the BST pin, the gate is connected to the gate of PMOS transistor MP1, and the drain is connected to the source of PMOS transistor MP5.

[0035] The gate of PMOS transistor MP5 is connected to the gate of PMOS transistor MP4, and the drain is connected to the drain of NMOS transistor MN2 and the OUT1 output pin.

[0036] The gate of NMOS transistor MN2 is connected to the enable signal pin EN, and the source is connected to the drain of NMOS transistor MN4.

[0037] The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN3, and the source is connected to the SW pin.

[0038] The source of PMOS transistor MP6 is connected to the BST pin, the gate is connected to the gate of PMOS transistor MP4, and the drain is connected to the source of PMOS transistor MP7.

[0039] The drain of PMOS transistor MP7 is connected to its gate, and also to the drain and gate of NMOS transistor MN5.

[0040] The source of NMOS transistor MN5 is connected to pin SW.

[0041] The source of PMOS transistor MP8 is connected to the BST pin, the gate is connected to the gate of PMOS transistor MP6, and the drain is connected to the drain of NMOS transistor MN7 and the OUT2 output pin.

[0042] The gate of NMOS transistor MN7 is connected to the enable signal pin EN, and the source is connected to the drain of NMOS transistor MN6.

[0043] The gate of NMOS transistor MN6 is connected to the gate of NMOS transistor MN5, and the source is connected to the SW pin.

[0044] Compared to traditional voltage latching circuits, this embodiment can self-start, replacing the resistor voltage divider in traditional circuits. When the voltage difference between BST and SW is less than the designed threshold, an undervoltage lockout signal is generated, and two undervoltage comparison thresholds are used, one for BST refresh and the other for forced shutdown of the circuit.

[0045] Specifically, the working process and principle of this invention are as follows:

[0046] When the power supply voltage is applied, a path from the power supply to ground is established through devices MP1, MP2, MP3, MN1, and MN3. When EN is high, the circuit operates normally and provides undervoltage lockout functionality.

[0047] When the circuit is operating normally, OUT1 and OUT2 output low levels when the voltage difference between BST and SW is normal, and the undervoltage lockout function is not triggered. When the voltage difference between BST and SW begins to decrease, and it drops to approximately 2.1V, the OUT1 output signal flips, generating a high-level signal, which can be used for refreshing the BST signal. When the voltage difference between BST and SW begins to decrease, and it drops to approximately 1.5V, the OUT2 output signal flips, generating a high-level signal, which can be used to forcibly turn off the switching transistor and shut down the high-voltage module circuit.

[0048] In summary, the main optimizations of this invention lie in the layout area and power consumption. By optimizing the structure, the number of components is reduced, and a self-starting structure is adopted for easy triggering. When the voltage difference between BST and SW is less than the designed threshold, an undervoltage lockout signal is generated, and two undervoltage comparison thresholds are used separately: one for BST refresh and the other for forced shutdown of the circuit.

Claims

1. A high-voltage side undervoltage lockout circuit, characterized in that, Including PMOS transistors MP1, MP2, MP3, MP4, MP5, and NMOS transistors MN1, MN2, MN3, MN4, where: The source of PMOS transistor MP1 is connected to the BST pin, the gate is connected to the SW pin through the bias current, and the drain is connected to the source of PMOS transistor MP2. The gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP3, and the drain is connected to the source of PMOS transistor MP3. The drain of PMOS transistor MP3 is connected to its gate, and also to the drain and gate of NMOS transistor MN1. The source of NMOS transistor MN1 is connected to the drain and gate of NMOS transistor MN3; The source of NMOS transistor MN3 is connected to pin SW. The source of PMOS transistor MP4 is connected to the BST pin, the gate is connected to the gate of PMOS transistor MP1, and the drain is connected to the source of PMOS transistor MP5. The gate of PMOS transistor MP5 is connected to the gate of PMOS transistor MP4, and the drain is connected to the drain of NMOS transistor MN2 and the OUT1 output pin. The source of NMOS transistor MN2 is connected to the drain of NMOS transistor MN4; The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN3, and the source is connected to the SW pin. The gate of the NMOS transistor MN2 is connected to the enable signal pin EN; It also includes PMOS transistors MP6, MP7, and MP8, and NMOS transistors MN5, MN6, and MN7, among which: The source of PMOS transistor MP6 is connected to the BST pin, the gate is connected to the gate of PMOS transistor MP4, and the drain is connected to the source of PMOS transistor MP7. The drain of PMOS transistor MP7 is connected to its gate, and also to the drain and gate of NMOS transistor MN5. The source of NMOS transistor MN5 is connected to pin SW. The source of PMOS transistor MP8 is connected to the BST pin, the gate is connected to the gate of PMOS transistor MP6, and the drain is connected to the drain of NMOS transistor MN7 and the OUT2 output pin. The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN6; The gate of NMOS transistor MN6 is connected to the gate of NMOS transistor MN5, and the source is connected to the SW pin. The gate of the NMOS transistor MN7 is connected to the enable signal pin EN.

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