Bus overvoltage fault false alarm control method and device based on double-chip control system

Abstract

The invention discloses a bus overvoltage fault false alarm control method and device based on a dual-chip control system, and relates to the technical field of circuit protection. The method comprises the following steps: a second chip controls a three-phase PFC circuit to start running, and samples bus analog voltage at the output end of the three-phase PFC circuit at a preset sampling frequency to obtain a bus voltage value; when the bus voltage value is larger than a first preset threshold value, first preset duration timing is carried out, and after the first preset duration timing is finished, if it is detected that the bus voltage value is larger than a second preset threshold value, the second chip controls a power switch tube of the three-phase PFC circuit to be closed and carries out second preset duration timing; and after the timing of the second preset duration is finished, the second chip reads the PFC control instruction sent by the first chip, and determines whether to report the bus overvoltage fault signal according to the PFC control instruction. According to the invention, fault misinformation caused by communication delay is solved, so that unnecessary hardware protection locking is prevented from being triggered, and the loss of components caused by overvoltage impact is reduced.

Description

Technical Field

[0001] This application relates to the field of circuit protection technology, and in particular to a method and device for controlling false alarms of bus overvoltage faults based on a dual-chip control system. Background Technology

[0002] In the field of variable frequency drives, such as variable frequency air conditioner compressor drives, a dual-chip control system architecture is commonly used. Typically, one chip is responsible for the drive control of the core load (such as the variable frequency compressor), while another chip is responsible for the control of the PFC (Power Factor Correction) circuit. The two chips communicate with each other via serial communication.

[0003] However, serial communication can cause communication delays. When the chip controlling the compressor decides to shut it down, it cannot transmit the shutdown command to the chip responsible for controlling the PFC circuit in time. The PFC circuit continues to work, and the bus voltage will continue to rise until it reaches the overvoltage protection threshold and generates a false overvoltage fault alarm, which triggers unnecessary hardware protection to lock the machine. Summary of the Invention

[0004] This application provides a bus overvoltage fault false alarm control method and device based on a dual-chip control system. It solves the problem in the dual-chip control system where, due to communication delay, the PFC circuit fails to shut down in time when the compressor is shut down, which leads to bus overvoltage and false overvoltage fault alarms, triggering unnecessary hardware protection lock-up. This avoids false overvoltage fault alarms caused by communication delay and reduces damage to hardware.

[0005] In a first aspect, this application provides a bus overvoltage fault false alarm control method based on a dual-chip control system. The dual-chip control system includes a first chip and a second chip. The first chip is used to control the operation of a variable frequency compressor, and the second chip is used to control a three-phase PFC circuit. The three-phase PFC circuit is used to provide bus voltage to the variable frequency compressor controlled by the first chip. The first chip and the second chip interact via serial communication. The method includes: The second chip controls the three-phase PFC circuit to start running and samples the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value. When the bus voltage value is greater than a first preset threshold, a first preset time is performed. After the first preset time is completed, if the bus voltage value is detected to be greater than a second preset threshold, the second chip controls the power switch of the three-phase PFC circuit to turn off and performs a second preset time. After the second preset timeout period ends, the second chip reads the PFC control command sent by the first chip and determines whether to report a bus overvoltage fault signal based on the PFC control command.

[0006] Optionally, obtaining the bus voltage value includes: The sampled bus analog voltage is then filtered. The filtered analog bus voltage is converted into a digital voltage to obtain the bus voltage value.

[0007] Optional, also includes: During the first preset time period, it is determined whether the bus analog voltage at the output terminal of the three-phase PFC circuit is greater than the third preset threshold. If the bus analog voltage at the output of the three-phase PFC circuit is greater than a third preset threshold, the second chip reports a bus overvoltage fault signal to the first chip.

[0008] Optionally, the second chip controls the power switching transistors of the three-phase PFC circuit to turn off, including: The second chip controls the PWM output channel to stop outputting the PWM signal and outputs a turn-off signal to the three-phase PFC circuit. The three-phase PFC circuit responds to the shutdown signal to control the power switch of the three-phase PFC circuit to turn off.

[0009] Optionally, determining whether to report a bus overvoltage fault signal based on the PFC control command includes: When the PFC control command is a shutdown command, the second chip prevents the first chip from reporting the bus overvoltage fault signal. When the PFC control command is an enable command, the second chip reports a bus overvoltage fault signal to the first chip.

[0010] Optional, also includes: The first chip responds to the bus overvoltage fault signal reported by the second chip and controls the variable frequency compressor to shut down.

[0011] Optionally, determining the second preset duration includes: The second preset duration is determined based on the polling time of the interaction between the first chip and the second chip via serial communication; wherein the second preset duration is longer than the polling time of the interaction between the first chip and the second chip via serial communication.

[0012] Secondly, this application provides a bus overvoltage fault false alarm control device based on a dual-chip control system. The dual-chip control system includes a first chip and a second chip. The first chip is used to control the operation of a variable frequency compressor, and the second chip is used to control a three-phase PFC circuit. The three-phase PFC circuit is used to provide bus voltage to the variable frequency compressor controlled by the first chip. The first chip and the second chip interact via serial communication. The device includes: The bus voltage value acquisition module is used to start the three-phase PFC circuit and sample the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value. The switching transistor control module is used to perform a first preset time count when the bus voltage value is greater than a first preset threshold. After the first preset time count ends, if the bus voltage value is detected to be greater than a second preset threshold, the second chip controls the power switching transistor of the three-phase PFC circuit to turn off and perform a second preset time count. The overvoltage fault reporting module is used to, after the second preset time period ends, read the PFC control command sent by the first chip and determine whether to report the bus overvoltage fault signal according to the PFC control command.

[0013] Thirdly, this application provides a bus overvoltage fault false alarm control device based on a dual-chip control system, comprising: One or more processors; A memory that stores one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the bus overvoltage fault false alarm control method based on a dual-chip control system as described in the first aspect.

[0014] Fourthly, this application provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the bus overvoltage fault false alarm control method based on a dual-chip control system as described in the first aspect.

[0015] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following: In this application, the dual-chip control system includes a first chip and a second chip. The first chip controls the operation of the variable frequency compressor, and the second chip controls the three-phase PFC circuit. The three-phase PFC circuit provides bus voltage to the variable frequency compressor controlled by the first chip. The first chip and the second chip interact via serial communication. The method includes: the second chip controls the three-phase PFC circuit to start operation and samples the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value; if the bus voltage value is greater than a first preset threshold, a first preset time is performed; after the first preset time is completed, if the bus voltage value is detected to be greater than a second preset threshold, the second chip controls the power switch of the three-phase PFC circuit to turn off and performs a second preset time; after the second preset time is completed, the second chip reads the PFC control command sent by the first chip and determines whether to report a bus overvoltage fault signal based on the PFC control command. In the above-mentioned technical means, when the bus voltage value is detected to be greater than the second preset threshold after the first preset time period ends, the power switch of the three-phase PFC circuit is turned off. That is, when the PFC shutdown command of the first chip is not transmitted in time, the second chip autonomously completes the PFC shutdown action, which can quickly cut off the output of the PFC circuit bus voltage value and prevent the bus voltage value from rising further to the overvoltage threshold. Finally, combined with the PFC control command received by the second chip from the first chip after the second preset time period ends, it is determined whether to report the bus overvoltage fault signal. This solves the problem of false alarms caused by communication delay, thereby avoiding the triggering of unnecessary hardware protection lock-up, reducing the wear and tear of components caused by overvoltage impact, and extending the service life of hardware. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the dual-chip control system provided in an embodiment of this application; Figure 2 This is a flowchart of a bus overvoltage fault false alarm control method based on a dual-chip control system provided in an embodiment of this application; Figure 3 This is a flowchart provided in an embodiment of the present application for determining whether to report a bus overvoltage fault signal based on PFC control instructions; Figure 4 This is a schematic diagram of a bus overvoltage fault false alarm control device based on a dual-chip control system provided in an embodiment of this application; Figure 5 This is a schematic diagram of a bus overvoltage fault false alarm control device based on a dual-chip control system provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. A process can be terminated when its operation is completed, but it may also have additional steps not included in the drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0018] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0019] In existing technologies, a dual-chip control system architecture is typically used. One chip is responsible for driving and controlling the core load (such as a variable frequency compressor), while another chip controls the PFC (Power Factor Correction) circuit. The two chips communicate via serial communication. However, serial communication introduces communication delays. When the chip controlling the compressor decides to shut it down, it cannot promptly transmit the shutdown command to the chip controlling the PFC circuit. The PFC circuit continues to operate, causing the bus voltage to rise until it reaches the overvoltage protection threshold, generating a false overvoltage fault alarm and triggering unnecessary hardware protection shutdown.

[0020] To address the issue in dual-chip control systems where communication delays cause the PFC circuit to fail to shut down in time when the compressor is off, leading to false overvoltage faults and triggering unnecessary hardware protection shutdowns, this application provides a bus overvoltage fault false alarm control method based on a dual-chip control system. This method shuts down the power switches of the three-phase PFC circuit when the bus voltage exceeds a second preset threshold after a first preset timeout. Specifically, if the first chip's PFC shutdown command is not delivered in time, the second chip autonomously performs the PFC shutdown action, quickly cutting off the PFC circuit's bus voltage output and preventing the bus voltage from further increasing to the overvoltage threshold. Finally, after the second preset timeout, the second chip receives the PFC control command from the first chip to determine whether to report a bus overvoltage fault signal. This solves the problem of false alarms caused by communication delays, thereby avoiding unnecessary hardware protection shutdowns, reducing component wear caused by overvoltage surges, and extending hardware lifespan.

[0021] The bus overvoltage fault false alarm control method based on a dual-chip control system provided in this embodiment can be executed by a bus overvoltage fault false alarm control device based on a dual-chip control system. The bus overvoltage fault false alarm control device based on a dual-chip control system can be implemented by software and / or hardware. The bus overvoltage fault false alarm control device based on a dual-chip control system can be composed of two or more physical entities, or it can be composed of a single physical entity.

[0022] The bus overvoltage fault false alarm control device based on a dual-chip control system can be equipped with an operating system, including but not limited to Android, Linux, and Windows systems. The device can also have an application installed on the operating system; this application can be a built-in application or an application downloaded from a third-party device or server. In this embodiment, the device can have an application for a bus overvoltage fault false alarm control method based on the dual-chip control system.

[0023] The technical solutions provided by the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0024] Figure 1 A schematic diagram of the dual-chip control system provided in an embodiment of this application is given. Please refer to... Figure 1 The dual-chip control system includes a first chip and a second chip. The first chip is used to control the operation of the variable frequency compressor, and the second chip is used to control the three-phase PFC circuit. The three-phase PFC circuit is used to provide bus voltage to the variable frequency compressor controlled by the first chip. The first chip and the second chip interact through serial communication.

[0025] PFC (Power Factor Correction) is a technology used to improve the power factor of loads in a power system. Its purpose is to reduce reactive power exchange between the grid and the load, lower grid harmonic pollution, and improve energy efficiency. In the field of variable frequency drives (such as variable frequency air conditioner compressor drives), since the load (compressor) is mostly inductive, direct connection to the grid can lead to a mismatch between the input current and voltage phases, resulting in high reactive power. This not only increases grid losses but may also affect the normal operation of other electrical equipment. PFC technology, through a dedicated circuit, corrects the input current to a sine wave in phase with the voltage, bringing the power factor close to 1, thus meeting the grid's power factor requirements for electrical equipment.

[0026] The first chip controls the operation of the variable frequency compressor, acting as a load to consume energy from the bus voltage, causing it to drop below the level of the uncontrolled rectifier. For example, the first chip could be a KM103HFC4K, a microcontroller chip. The second chip controls the operation of the three-phase PFC circuit to increase the bus voltage and improve the input power factor, ensuring the bus voltage is higher than the voltage of the uncontrolled rectifier. The second chip could be a DSPIC33CH128MP208, a high-performance 16-bit dual-core digital signal controller chip.

[0027] A three-phase PFC circuit can be understood as rectifying and boosting three-phase AC power into a stable DC bus voltage, providing the energy source (bus voltage) for the variable frequency compressor controlled by the first chip. Since the variable frequency compressor is an AC load, and the three-phase PFC circuit outputs a DC bus voltage, it is necessary to convert this DC bus voltage into an AC voltage. Based on this AC voltage, the first chip can then control the variable frequency compressor drive. For example, a three-phase inverter bridge drive circuit can be used to convert the DC bus voltage output by the three-phase PFC circuit into a three-phase AC voltage with adjustable frequency and voltage.

[0028] In this embodiment, the first chip and the second chip interact via serial communication. Serial communication is a communication method that transmits data bit by bit through one or a few data lines, resulting in fewer communication lines and lower cost.

[0029] Serial communication introduces a communication delay. When the first chip controlling the variable frequency compressor decides to shut it down, it must simultaneously send a PFC shutdown command to the second chip to ensure the three-phase PFC circuit stops supplying energy (bus voltage) to the bus side. If the three-phase PFC circuit fails to shut down synchronously, its continuously output energy (bus voltage) will accumulate on the bus side as the variable frequency compressor stops consuming it, leading to an increase in bus voltage and overcharging. However, due to the serial communication delay, the PFC shutdown command from the first chip cannot be transmitted to the second chip in time. The second chip will continue to maintain the normal operation of the three-phase PFC circuit, causing the bus voltage to rise continuously until it reaches the overvoltage protection threshold and generates a false overvoltage fault alarm. The three-phase PFC circuit fails to shut down synchronously due to slow communication, resulting in a brief overvoltage at the bus due to no load. This is a normal problem caused by the communication delay between the two chips, not a fault in the circuit, components, or other aspects. This situation should not occur when shutting down the compressor. Therefore, in order to solve the problem in the dual-chip control system where the three-phase PFC circuit fails to shut down in time due to communication delay when the compressor is shut down, thus causing the bus overvoltage to generate a false overvoltage fault alarm and triggering unnecessary hardware protection to lock the machine, this application provides a bus overvoltage fault false alarm control method based on a dual-chip control system.

[0030] Figure 2 A flowchart of a bus overvoltage fault false alarm control method based on a dual-chip control system, provided in an embodiment of this application, is given. Please refer to... Figure 2 The bus overvoltage fault false alarm control method based on a dual-chip control system specifically includes: S110. The second chip controls the three-phase PFC circuit to start running and samples the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value.

[0031] Specifically, when the first chip receives a power-on command from the user (which requires the compressor to start), the first chip will respond to the power-on command and generate a PFC enable command, which will be sent to the second chip via the serial port. The second chip will respond to the PFC enable command sent by the first chip, control the three-phase PFC circuit to start running, and sample the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency, and process the bus analog voltage to obtain the bus voltage value.

[0032] In this embodiment, the bus voltage value refers to the DC bus voltage value in the three-phase PFC circuit. For example, this embodiment samples the analog bus voltage at the output of the three-phase PFC circuit using an ADC (Analog-to-Digital Converter) at a sampling frequency of 25kHz. The 25kHz sampling frequency is considered high-frequency sampling, designed to capture the dynamic changes of the analog bus voltage in real time. High-frequency sampling avoids missing critical voltage spikes, ensuring timely overvoltage threshold judgment. If the sampling frequency is too low, the voltage may exceed the threshold within the sampling interval without being detected. Since the sampled analog bus voltage contains high-frequency interference noise, it needs to be filtered before being converted into a digital voltage to obtain the bus voltage value. For example, this embodiment can connect an RC low-pass filter circuit to the input of the ADC sampling channel. This RC low-pass filter circuit consists of a resistor and a capacitor, and its cutoff frequency is set much higher than the normal frequency of the bus voltage change, but much lower than the ADC sampling frequency. This RC low-pass filter circuit can pre-attenuate high-frequency noise and glitches, preventing them from exceeding the input range of the ADC or causing interference.

[0033] In one embodiment of this application, the filtered analog bus voltage is converted into a digital voltage to obtain the bus voltage value. The steps may include: First, converting the filtered analog bus voltage into a corresponding digital code (i.e., a digital quantity or the original ADC count value). For example, a 12-bit ADC will map the analog voltage to an integer value between 0 and 4095. Second, calculating the digital voltage value of the analog bus voltage, i.e., the bus voltage value, using a preset conversion relationship (e.g., the conversion relationship is: actual bus voltage value = (ADC digital quantity / ADC maximum range) × voltage division ratio × ADC reference voltage).

[0034] S120. When the bus voltage value is greater than the first preset threshold, a first preset duration is started. After the first preset duration is finished, if the bus voltage value is detected to be greater than the second preset threshold, the second chip controls the power switch of the three-phase PFC circuit to turn off and starts a second preset duration.

[0035] The first preset threshold is a custom target bus voltage value (e.g., 567V), which equals the uncontrolled rectifier bus voltage plus 30V. The uncontrolled rectifier bus voltage is the natural voltage level when the three-phase PFC circuit is not enabled. The 30V is a compensation amount to ensure the bus voltage meets the drive requirements of the inverter compressor.

[0036] In this embodiment, when the second chip first enables the three-phase PFC circuit, the circuit suddenly transitions from standby to operation. During this time, the bus capacitor charges rapidly, and the initial conduction parameters of the power switch are unstable, leading to a transient overshoot phenomenon where the bus voltage briefly spikes and then drops back. This overshoot is a normal physical phenomenon during the startup of the three-phase PFC circuit. If the PFC is directly shut down based on the overvoltage threshold, the system will fail to start normally. Therefore, this embodiment first performs a first preset timeout when the bus voltage exceeds a first preset threshold. After the first preset timeout, it then checks whether the bus voltage exceeds a second preset threshold, allowing time for the overshoot to fall back. This effectively avoids the normal voltage overshoot phenomenon after the first chip enables the three-phase PFC circuit, preventing the normal voltage fluctuations during startup from being misjudged as overvoltage. For example, the first preset timeout can be set to 1 second.

[0037] In one embodiment of this application, only hardware overvoltage detection is performed during the first preset time period. Hardware overvoltage detection refers to determining whether the analog voltage of the bus is overvoltage through hardware circuits (such as comparators or overvoltage protection chips). Upon detecting hardware overvoltage, overvoltage protection (compressor shutdown) is implemented. This is a physical-level, fast-response protection that does not require software intervention. Specifically, hardware overvoltage detection is performed by determining whether the analog voltage of the bus at the output of the three-phase PFC circuit is greater than a third preset threshold. If the analog voltage of the bus at the output of the three-phase PFC circuit is greater than the third preset threshold, the second chip reports a bus overvoltage fault signal to the first chip. The first chip responds to the bus overvoltage fault signal reported by the second chip and controls the inverter compressor to shut down. That is, if the analog voltage value of the bus is greater than the third preset threshold within the first preset time period, a fault exists. Therefore, the compressor needs to be shut down to avoid hardware damage. The third preset threshold is the threshold for hardware overvoltage; for example, the third preset threshold can be set to 740V.

[0038] After the first preset duration ends, if the bus voltage value is detected to be greater than the second preset threshold, the second chip controls the power switch of the three-phase PFC circuit to turn off and perform the second preset duration. The second preset threshold is a software overvoltage threshold, that is, after the first preset duration ends, software overvoltage detection is performed. Software overvoltage detection refers to the logic of the software program of the second chip to determine whether the digital voltage value (bus voltage value) exceeds the software overvoltage threshold. For example, the second preset threshold can be set to 695V.

[0039] In one embodiment of this application, the second chip controls the power switching transistors of the three-phase PFC circuit to turn off. The steps include: the second chip controls the PWM output channel to stop outputting the PWM signal and outputs a turn-off signal to the three-phase PFC circuit; the three-phase PFC circuit responds to the turn-off signal to control the power switching transistors of the three-phase PFC circuit to turn off. Here, the PWM output channel refers to the module / unit inside the second chip used to generate pulse width modulation signals; the PWM signal is a periodic square wave signal used to control the on / off state of the power switching transistors in the three-phase PFC circuit. Therefore, when the second chip controls the PWM output channel to stop the PWM signal and generates a turn-off signal, the power switching transistors of the three-phase PFC circuit are immediately turned off. After turning off, the three-phase PFC circuit stops working and will no longer output bus voltage, thus cutting off the energy output of the three-phase PFC circuit and preventing the bus voltage from rising further, thereby avoiding triggering unnecessary hardware lock-up.

[0040] S130. After the second preset timeout period ends, the second chip reads the PFC control command sent by the first chip and determines whether to report a bus overvoltage fault signal based on the PFC control command.

[0041] Among them, PFC control commands refer to commands used to control the start and stop of a three-phase PFC circuit.

[0042] For example, Figure 3 This application provides a flowchart illustrating how to determine whether to report a bus overvoltage fault signal based on PFC control commands. For example... Figure 3 As shown, the steps for determining whether to report a bus overvoltage fault signal according to the PFC control command include S1301-S1302: S1301. When the PFC control command is a shutdown command, the second chip prohibits the reporting of the bus overvoltage fault signal to the first chip.

[0043] Specifically, when the second chip detects that the bus voltage value is greater than the second preset threshold and shuts down the power switch of the three-phase PFC circuit, after the second preset timeout period ends, if it reads the PFC control command sent by the first chip as a shutdown command, it means that the first chip has the intention to control the compressor to shut down (since the PFC circuit provides the bus voltage to the compressor for its operation, the three-phase PFC circuit should also be shut down when the compressor shuts down). However, due to the serial communication delay, the shutdown command for shutting down the three-phase PFC circuit did not reach the second chip in time. At this time, the bus voltage value is greater than the second preset threshold, which is an overvoltage. The essence of this overvoltage is that after the compressor shuts down, the three-phase PFC circuit does not shut down synchronously due to slow communication, resulting in a brief overvoltage due to no load on the bus. This is a normal problem under the communication delay of the two chips, rather than an overvoltage caused by circuit, component or other faults. Therefore, the second chip does not need to report the bus overvoltage fault signal to the first chip.

[0044] S1302, When the PFC control command is an enable command, the second chip reports a bus overvoltage fault signal to the first chip.

[0045] When the second chip detects that the bus voltage value is greater than the second preset threshold and shuts down the power switch of the three-phase PFC circuit, after the second preset timeout period ends, it reads the PFC control command sent by the first chip as an on command. This means that the first chip is still controlling the compressor to run, and the three-phase PFC circuit still needs to continue to work. At this time, the bus voltage value is greater than the second preset threshold, which is an overvoltage. This overvoltage is not a temporary overvoltage caused by the compressor shutting down and the bus being unloaded, but rather caused by other faults. Therefore, the second chip needs to report a bus overvoltage fault signal to the first chip. The first chip responds to the bus overvoltage fault signal reported by the second chip and controls the inverter compressor to shut down to prevent the compressor from running under overvoltage conditions and to prevent hardware damage.

[0046] Furthermore, in one embodiment of this application, the second preset duration is determined based on the polling time of the interaction between the first chip and the second chip via serial communication, and the second preset duration is longer than the polling time of the interaction between the first chip and the second chip via serial communication. For example, if the polling time of the interaction between the first chip and the second chip via serial communication is 1.5 seconds, the second duration can be set to 2 seconds to cover the 1.5-second communication delay.

[0047] In this embodiment, PFC control commands are sent to the second chip via serial communication. However, due to communication delay, the commands may not arrive in time. Therefore, this application uses the second chip to autonomously decide to turn off the power switching transistors of the three-phase PFC circuit when it detects a potential danger of overvoltage. This is to compensate for the problem that the PFC circuit continues to work due to the serial communication delay, and the bus voltage will continue to rise until it reaches the overvoltage protection threshold and generates a false overvoltage fault alarm, which would trigger unnecessary hardware protection lock-up.

[0048] In summary, this application provides a bus overvoltage fault false alarm control method based on a dual-chip control system. The dual-chip control system includes a first chip and a second chip. The first chip controls the operation of the variable frequency compressor, and the second chip controls the three-phase PFC circuit. The three-phase PFC circuit provides bus voltage to the variable frequency compressor controlled by the first chip. The first chip and the second chip interact via serial communication. The method includes: the second chip controls the three-phase PFC circuit to start operation and samples the bus analog voltage at the output of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value; if the bus voltage value is greater than a first preset threshold, a first preset time is performed; after the first preset time is completed, if the bus voltage value is detected to be greater than a second preset threshold, the second chip controls the power switch of the three-phase PFC circuit to turn off and performs a second preset time; after the second preset time is completed, the second chip reads the PFC control command sent by the first chip and determines whether to report a bus overvoltage fault signal based on the PFC control command. In the above-mentioned technical means, when the bus voltage value is detected to be greater than the second preset threshold after the first preset time period ends, the power switch of the three-phase PFC circuit is turned off. That is, when the PFC shutdown command of the first chip is not transmitted in time, the second chip autonomously completes the PFC shutdown action, which can quickly cut off the bus voltage output of the PFC circuit and prevent the bus voltage value from rising further to the overvoltage threshold. Finally, combined with the PFC control command received by the second chip from the first chip after the second preset time period ends, it is determined whether to report the bus overvoltage fault signal. This solves the problem of false alarms caused by communication delay, thereby avoiding triggering unnecessary hardware protection lock-up, reducing the wear and tear of components caused by overvoltage impact, and extending the service life of hardware.

[0049] Figure 4 This is a schematic diagram of a bus overvoltage fault false alarm control device based on a dual-chip control system, provided as an embodiment of this application. (Reference) Figure 4 This embodiment provides a bus overvoltage fault false alarm control device based on a dual-chip control system. The dual-chip control system includes a first chip and a second chip. The first chip is used to control the operation of the variable frequency compressor, and the second chip is used to control the three-phase PFC circuit. The three-phase PFC circuit is used to provide bus voltage to the variable frequency compressor controlled by the first chip. The first chip and the second chip interact through serial communication. The device includes: a bus voltage value acquisition module 21, a switching transistor control module 22, and an overvoltage fault reporting module 23.

[0050] The bus voltage value acquisition module 21 is used to start the three-phase PFC circuit and sample the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value. The switching transistor control module 22 is used to perform a first preset time count when the bus voltage value is greater than a first preset threshold. After the first preset time count ends, if the bus voltage value is detected to be greater than a second preset threshold, the second chip controls the power switching transistor of the three-phase PFC circuit to turn off and perform a second preset time count. The overvoltage fault reporting module 23 is used to, after the second preset time period ends, read the PFC control command sent by the first chip and determine whether to report the bus overvoltage fault signal according to the PFC control command.

[0051] Based on the above embodiments, the bus voltage value acquisition module 21 includes: A filtering unit is used to filter the sampled bus analog voltage; The bus voltage value acquisition module unit is used to convert the filtered analog bus voltage into a digital voltage to obtain the bus voltage value.

[0052] Based on the above embodiments, the switching transistor control module 22 includes: The shutdown signal output unit is used to control the PWM output channel of the second chip to stop outputting the PWM signal and output a shutdown signal to the three-phase PFC circuit. A switching control unit is used by the three-phase PFC circuit in response to the shutdown signal to control the power switching transistors of the three-phase PFC circuit to turn off.

[0053] Based on the above embodiments, the switching transistor control module 22 further includes: The analog voltage judgment unit is used to determine whether the bus analog voltage at the output terminal of the three-phase PFC circuit is greater than a third preset threshold during the first preset time period. The first fault signal reporting unit is used to report a bus overvoltage fault signal from the second chip to the first chip when the bus analog voltage at the output terminal of the three-phase PFC circuit is greater than a third preset threshold.

[0054] Based on the above embodiments, the switching transistor control module 22 further includes a second preset duration determination unit, which is specifically used for: The second preset duration is determined based on the polling time of the interaction between the first chip and the second chip via serial communication; wherein the second preset duration is longer than the polling time of the interaction between the first chip and the second chip via serial communication.

[0055] Based on the above embodiments, the overvoltage fault reporting module 23 includes: The fault signal reporting prohibition unit is used to prevent the second chip from reporting the bus overvoltage fault signal to the first chip when the PFC control command is a shutdown command. The second fault signal reporting unit is used to report a bus overvoltage fault signal to the first chip when the PFC control command is an enable command.

[0056] Based on the above embodiments, the first fault signal reporting unit and the second fault signal reporting unit further include a compressor shutdown subunit, which is specifically used for: The first chip responds to the bus overvoltage fault signal reported by the second chip and controls the variable frequency compressor to shut down.

[0057] In summary, the bus overvoltage fault false alarm control device based on a dual-chip control system provided in this application embodiment controls the three-phase PFC circuit to start operation via a second chip, and samples the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value. If the bus voltage value is greater than a first preset threshold, a first preset time is performed. After the first preset time is completed, if the bus voltage value is detected to be greater than a second preset threshold, the second chip controls the power switch of the three-phase PFC circuit to turn off and performs a second preset time. After the second preset time is completed, the second chip reads the PFC control command sent by the first chip and determines whether to report a bus overvoltage fault signal based on the PFC control command. In the above-mentioned technical means, when the bus voltage value is detected to be greater than the second preset threshold after the first preset time period ends, the power switch of the three-phase PFC circuit is turned off. That is, when the PFC shutdown command of the first chip is not transmitted in time, the second chip autonomously completes the PFC shutdown action, which can quickly cut off the bus voltage output of the PFC circuit and prevent the bus voltage value from rising further to the overvoltage threshold. Finally, combined with the PFC control command received by the second chip from the first chip after the second preset time period ends, it is determined whether to report the bus overvoltage fault signal. This solves the problem of false alarms caused by communication delay, thereby avoiding triggering unnecessary hardware protection lock-up, reducing the wear and tear of components caused by overvoltage impact, and extending the service life of hardware.

[0058] The bus overvoltage fault false alarm control device based on a dual-chip control system provided in this application embodiment can be used to execute the bus overvoltage fault false alarm control method based on a dual-chip control system provided in the above embodiment, and has corresponding functions and beneficial effects.

[0059] Figure 5 This is a schematic diagram of a bus overvoltage fault false alarm control device based on a dual-chip control system provided in an embodiment of this application. (Refer to...) Figure 5The bus overvoltage fault false alarm control device based on a dual-chip control system includes: a processor 31, a memory 32, a communication device 33, an input device 34, and an output device 35. The number of processors 31 and the number of memories 32 in this dual-chip control system-based bus overvoltage fault false alarm control device can be one or more. The processor 31, memory 32, communication device 33, input device 34, and output device 35 of this dual-chip control system-based bus overvoltage fault false alarm control device can be connected via a bus or other means.

[0060] The memory 32, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the bus overvoltage fault false alarm control method based on a dual-chip control system in any embodiment of this application (e.g., the bus voltage value acquisition module 21, the switching transistor control module 22, and the overvoltage fault reporting module 23 in the bus overvoltage fault false alarm control device based on a dual-chip control system). The memory 32 may mainly include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a function; the data storage area may store data created based on the use of the device, etc. Furthermore, the memory 32 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0061] The communication device 33 is used for data transmission.

[0062] The processor 31 executes various functional applications and data processing of the device by running software programs, instructions and modules stored in the memory 32, thereby realizing the above-mentioned bus overvoltage fault false alarm control method based on the dual-chip control system.

[0063] Input device 34 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the device. Output device 35 may include display devices such as a display screen.

[0064] The bus overvoltage fault false alarm control device based on the dual-chip control system provided above can be used to execute the bus overvoltage fault false alarm control method based on the dual-chip control system provided in the above embodiments, and has corresponding functions and beneficial effects.

[0065] This application embodiment also provides a storage medium containing computer-executable instructions. When executed by a computer processor, the computer-executable instructions are used to execute a bus overvoltage fault false alarm control method based on a dual-chip control system. The bus overvoltage fault false alarm control method based on a dual-chip control system includes: a second chip controlling a three-phase PFC circuit to start operation and sampling the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value; if the bus voltage value is greater than a first preset threshold, a first preset time is performed; after the first preset time is performed, if the bus voltage value is detected to be greater than a second preset threshold, the second chip controls the power switch of the three-phase PFC circuit to turn off and performs a second preset time; after the second preset time is performed, the second chip reads the PFC control instruction sent by the first chip and determines whether to report a bus overvoltage fault signal according to the PFC control instruction.

[0066] Storage medium – any type of memory device or storage device. The term “storage medium” is intended to include: mounting media, such as CD-ROM, floppy disk, or magnetic tape devices; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory, magnetic media (e.g., hard disk or optical storage); registers or other similar types of memory elements, etc. Storage medium may also include other types of memory or combinations thereof. Furthermore, storage medium may reside in a first computer system in which the program is executed, or it may reside in a different second computer system connected to the first computer system via a network (such as the Internet). The second computer system can provide program instructions to the first computer for execution. The term “storage medium” can include two or more storage media residing in different locations (e.g., in different computer systems connected via a network). Storage medium may store program instructions (e.g., specifically implemented as a computer program) executable by one or more processors.

[0067] Of course, the computer-executable instructions provided in the embodiments of this application are not limited to the bus overvoltage fault false alarm control method based on the dual-chip control system described above, but can also execute related operations in the bus overvoltage fault false alarm control method based on the dual-chip control system provided in any embodiment of this application.

[0068] The bus overvoltage fault false alarm control device, storage medium, and bus overvoltage fault false alarm control equipment based on a dual-chip control system provided in the above embodiments can execute the bus overvoltage fault false alarm control method based on a dual-chip control system provided in any embodiment of this application. For technical details not described in detail in the above embodiments, please refer to the bus overvoltage fault false alarm control method based on a dual-chip control system provided in any embodiment of this application.

[0069] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application. The scope of this application is determined by the scope of the claims.

Claims

1. A method for controlling false alarms of bus overvoltage faults based on a dual-chip control system, wherein the dual-chip control system includes a first chip and a second chip, the first chip is used to control the operation of a variable frequency compressor, the second chip is used to control a three-phase PFC circuit, the three-phase PFC circuit is used to provide bus voltage to the variable frequency compressor controlled by the first chip, and the first chip and the second chip interact via serial communication; the method includes: The second chip controls the three-phase PFC circuit to start running and samples the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value. When the bus voltage value is greater than a first preset threshold, a first preset time is performed. After the first preset time is completed, if the bus voltage value is detected to be greater than a second preset threshold, the second chip controls the power switch of the three-phase PFC circuit to turn off and performs a second preset time. After the second preset timeout period ends, the second chip reads the PFC control command sent by the first chip and determines whether to report a bus overvoltage fault signal based on the PFC control command.

2. The bus overvoltage fault false alarm control method based on a dual-chip control system according to claim 1, characterized in that, The process of obtaining the bus voltage value includes: The sampled bus analog voltage is then filtered. The filtered analog bus voltage is converted into a digital voltage to obtain the bus voltage value.

3. The bus overvoltage fault false alarm control method based on a dual-chip control system according to claim 1, characterized in that, Also includes: During the first preset time period, it is determined whether the bus analog voltage at the output terminal of the three-phase PFC circuit is greater than the third preset threshold. If the bus analog voltage at the output of the three-phase PFC circuit is greater than a third preset threshold, the second chip reports a bus overvoltage fault signal to the first chip.

4. The bus overvoltage fault false alarm control method based on a dual-chip control system according to claim 1, characterized in that, The second chip controls the power switching transistors of the three-phase PFC circuit to turn off, including: The second chip controls the PWM output channel to stop outputting the PWM signal and outputs a turn-off signal to the three-phase PFC circuit. The three-phase PFC circuit responds to the shutdown signal to control the power switch of the three-phase PFC circuit to turn off.

5. The bus overvoltage fault false alarm control method based on a dual-chip control system according to claim 1, characterized in that, The step of determining whether to report a bus overvoltage fault signal based on the PFC control command includes: When the PFC control command is a shutdown command, the second chip prevents the first chip from reporting the bus overvoltage fault signal. When the PFC control command is an enable command, the second chip reports a bus overvoltage fault signal to the first chip.

6. The bus overvoltage fault false alarm control method based on a dual-chip control system according to any one of claims 3 or 5, characterized in that, Also includes: The first chip responds to the bus overvoltage fault signal reported by the second chip and controls the variable frequency compressor to shut down.

7. The bus overvoltage fault false alarm control method based on a dual-chip control system according to claim 1, characterized in that, Determining the second preset duration includes: The second preset duration is determined based on the polling time of the interaction between the first chip and the second chip via serial communication; wherein the second preset duration is longer than the polling time of the interaction between the first chip and the second chip via serial communication.

8. A bus overvoltage fault false alarm control device based on a dual-chip control system, wherein the dual-chip control system includes a first chip and a second chip, the first chip is used to control the operation of a variable frequency compressor, the second chip is used to control a three-phase PFC circuit, the three-phase PFC circuit is used to provide bus voltage to the variable frequency compressor controlled by the first chip, and the first chip and the second chip interact via serial communication; the device includes: The bus voltage value acquisition module is used to start the three-phase PFC circuit and sample the bus analog voltage at the output terminal of the three-phase PFC circuit at a preset sampling frequency to obtain the bus voltage value. The switching transistor control module is used to perform a first preset time count when the bus voltage value is greater than a first preset threshold. After the first preset time count ends, if the bus voltage value is detected to be greater than a second preset threshold, the second chip controls the power switching transistor of the three-phase PFC circuit to turn off and perform a second preset time count. The overvoltage fault reporting module is used to, after the second preset time period ends, read the PFC control command sent by the first chip and determine whether to report the bus overvoltage fault signal according to the PFC control command.

9. A bus overvoltage fault false alarm control device based on a dual-chip control system, characterized in that, include: One or more processors; The memory stores one or more programs that, when executed by the one or more processors, enable the one or more processors to implement the bus overvoltage fault false alarm control method based on a dual-chip control system as described in any one of claims 1-7.

10. A storage medium containing computer-executable instructions, characterized in that, The computer-executable instructions, when executed by a computer processor, are used to perform the bus overvoltage fault false alarm control method based on a dual-chip control system as described in any one of claims 1-7.

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