Electrostatic discharge circuit
By designing an electrostatic discharge protection circuit that includes resistors, capacitors, and transistors, and utilizing a voltage gap provider to provide a voltage drop, the problem of low-voltage process transistors being prone to failure under high voltage is solved, thus achieving safe operation and protection of the circuit.
Patent Information
- Application Number
- CN202510823538.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-07-15
- Filing Date
- 2025-06-19
- Publication Date
- 2026-01-16
AI Technical Summary
Existing electrostatic discharge protection circuits are prone to damage under high-voltage operation, especially transistors manufactured using low-voltage processes, which can break down when receiving high voltage, leading to circuit failure.
An electrostatic discharge protection circuit is designed, comprising a resistor, a capacitor, P-type and N-type transistors, and a voltage gap provider. The voltage gap provider provides a voltage drop to ensure the transistors operate safely under high voltage and to form an effective discharge path in the event of an electrostatic discharge, protecting the circuit from damage.
It effectively protects transistors manufactured using low-voltage processes from collapse under high voltage, ensuring safe operation of the circuit in normal mode and during electrostatic discharge events, and preventing circuit damage.
Smart Images
Figure CN121355855A_ABST
Abstract
Description
[0001] Cross Reference to Related Applications
[0002] This application claims priority to U.S. Patent Application 63 / 671,307, filed July 15, 2024, entitled “Non-Volatile Memory,” the entire contents of which are incorporated herein by reference. TECHNICAL FIELD
[0003] The present disclosure relates to an electrostatic discharge (ESD) circuit, and more particularly, to an ESD protection circuit for high voltage operation. BACKGROUND
[0004] Electrostatic discharge (ESD) is a common phenomenon in the electronics field. Specifically, ESD occurs when two charged objects come into contact, and the charge in one object flows through a discharge path to the other object. ESD can generate a large amount of current in a very short time, and can damage integrated circuits (ICs). To protect integrated circuits from being damaged by a large amount of ESD current, an ESD protection circuit is usually used on the external pins of an integrated circuit.
[0005] Furthermore, for ease of manufacturing, the ESD protection circuit is often fabricated using a low voltage process used by the integrated circuit that it is intended to protect. In this case, the elements in the ESD protection circuit can only operate at low voltage during normal mode. However, some integrated circuits can need to receive high voltage from the external pins for certain applications, such as the one-time programmable memory can need high voltage for write or erase operation. As such, the elements such as transistors fabricated by the low voltage process in the ESD protection circuit can break down, resulting in circuit failure.
[0006] The section titled “PRIOR ART” provides background information only. The statements in this section are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and any part of this section is not admitted to be prior art to any part of this application, including the prior art section. SUMMARY
[0007] One embodiment of this disclosure provides an electrostatic discharge (ESD) protection circuit coupled between a voltage pad and a circuit to be protected. The ESD protection circuit includes a resistor, a capacitor, a first P-type transistor, a first N-type transistor, a first voltage gap provider, a second N-type transistor, and a second voltage gap provider. The resistor has a first terminal coupled to the voltage pad for receiving a high operating voltage, and a second terminal. The capacitor has a first terminal coupled to the second terminal of the resistor, and a second terminal coupled to a system voltage node for receiving a system voltage lower than the high operating voltage. The first P-type transistor has a first terminal coupled to the voltage pad, a second terminal, and a control terminal coupled to the second terminal of the resistor. The first N-type transistor has a first terminal, a second terminal coupled to the system voltage node, and a control terminal coupled to the second terminal of the resistor. The first voltage gap provider is coupled between the second terminal of the first P-type transistor and the first terminal of the first N-type transistor and provides a first voltage drop from the second terminal of the first P-type transistor to the first terminal of the first N-type transistor. The second N-type transistor has a first terminal, a second terminal coupled to the system voltage node, and a control terminal coupled to the first terminal of the first N-type transistor. The second voltage gap provider is coupled between the voltage pad and the first terminal of the second N-type transistor, and is used to provide a second voltage drop from the voltage pad to the first terminal of the second N-type transistor. When a positive voltage polarity electrostatic discharge event occurs, the second terminal of the resistor is at the system voltage, the first P-type transistor and the second N-type transistor are turned on, the first N-type transistor is turned off, and the electrostatic discharge current flows from the voltage pad through the second voltage gap provider to the second N-type transistor. Attached Figure Description
[0008] A more complete understanding of the contents disclosed in this invention can be derived by referring to the embodiments and claims when considering the illustrations in conjunction with them, wherein the same reference numerals refer to similar elements throughout the illustrations.
[0009] Figure 1 This is a schematic diagram of an electrostatic discharge (ESD) protection circuit according to an embodiment of the present invention.
[0010] Figure 2 During normal mode, Figure 1 A schematic diagram of the electrostatic discharge protection circuit in this scenario.
[0011] Figure 3 When an ESD event occurs, Figure 1 A schematic diagram of the electrostatic discharge protection circuit in this scenario.
[0012] Figure 4This is another embodiment of the electrostatic discharge protection circuit disclosed in this invention.
[0013] Figure 5 During normal mode, Figure 4 A schematic diagram of the electrostatic discharge protection circuit in this scenario.
[0014] Figure 6 When an ESD event occurs, Figure 4 A schematic diagram of the electrostatic discharge protection circuit in this scenario.
[0015] Figure 7 This is a schematic diagram of an electrostatic discharge protection circuit according to another embodiment of the content disclosed in this invention.
[0016] [Symbol Explanation]
[0017] 100: Electrostatic Discharge (ESD) Protection Circuit
[0018] 110: Voltage gap provider
[0019] 120: Voltage gap provider
[0020] 200, 300: Electrostatic discharge protection circuit
[0021] 230: Protective switch
[0022] 240: Latch unit
[0023] 350: Voltage gap provider
[0024] C1: Capacitor
[0025] CT1: Circuit
[0026] D1, D2, D3, D4: Diodes
[0027] I1: Charging current
[0028] I2: Electrostatic discharge current
[0029] IN1, IN2: Input terminals
[0030] R1: Resistor
[0031] M1N: N-type transistor
[0032] M1P: P-type transistor
[0033] M2N: N-type transistor
[0034] M2P, M3P: P-type transistors
[0035] PD1: Voltage pad
[0036] VA, VB, VC: Voltage
[0037] VD1, VD2: Voltage drop
[0038] VDD: Power supply voltage
[0039] VPP: High operating voltage
[0040] VSS: System Voltage Detailed Implementation
[0041] Figure 1 This is a schematic diagram of an electrostatic discharge (ESD) protection circuit 100 according to an embodiment of the present invention. The ESD protection circuit 100 includes a resistor R1, a capacitor C1, a P-type transistor M1P, an N-type transistor M1N, a voltage gap provider 110, an N-type transistor M2N, and a voltage gap provider 120. In a specific embodiment of the invention, the ESD protection circuit 100 is arranged between the input terminal IN1 of the circuit CT1 to be protected and a voltage pad PD1 that receives a high operating voltage VPP from an external power source. In this case, the ESD protection circuit 100 can protect the circuit CT1 from damage caused by electrostatic discharge current when the voltage pad PD1 is coupled to an external power source. In some embodiments, the circuit CT1 may include non-volatile memory cells, and the high operating voltage VPP can be used for write (i.e., programming) or erase operations on these non-volatile memory cells. Circuit CT1 can further receive a power supply voltage VDD for reading (i.e., reading voltage) operations on such non-volatile memory cells, and the high operating voltage VPP is higher than the power supply voltage VDD.
[0042] Furthermore, in a specific embodiment of the present invention, the P-type transistor M1P and the N-type transistors M1N and M2N can be low-voltage devices manufactured using a low-voltage process. In this case, the voltage drop provided by the voltage gap providers 110 and 120 allows the P-type transistors M1P and M1N and M2N to operate within their safe operating area (SOA), and even if the high operating voltage VPP is higher than the junction breakdown voltage of the P-type transistors M1P and M1N and M2N, the P-type transistors M1P and M1N and M2N will not break down when the circuit CT1 receives the high operating voltage VPP from the voltage pad PD1 during normal mode.
[0043] like Figure 1As shown, resistor R1 has a first terminal coupled to voltage pad PD1 and a second terminal. Capacitor C1 has a first terminal coupled to the second terminal of resistor R1 and a second terminal coupled to the system voltage node to receive the system voltage VSS. The system voltage VSS is lower than the high operating voltage VPP, and in some embodiments, the system voltage node may be grounded, the system voltage VSS may be grounded, and circuit CT1 may also be coupled to the system voltage VSS via input terminal IN2.
[0044] P-type transistor M1P has a first terminal and a second terminal coupled to voltage pad PD1, and a control terminal coupled to the second terminal of resistor R1. N-type transistor M1N has a first terminal, a second terminal coupled to the system voltage node, and a control terminal coupled to the second terminal of resistor R1. Voltage gap provider 110 is coupled between the second terminal of P-type transistor M1P and the first terminal of N-type transistor M1N. N-type transistor M2N has a first terminal, a second terminal coupled to the system voltage node, and a control terminal coupled to the first terminal of N-type transistor M1N. Voltage gap provider 120 is coupled between voltage pad PD1 and the first terminal of N-type transistor M2N.
[0045] Figure 2 This is a schematic diagram of the electrostatic discharge protection circuit 100 during normal mode. During normal mode, voltage pad PD1 receives a high operating voltage VPP. In this situation, capacitor C1 is charged and the voltage VA at the second terminal of resistor R1 is at the high operating voltage VPP. Therefore, N-type transistor M1N is turned on, while P-type transistor M1P is turned off. Accordingly, the voltage VB at the first terminal of N-type transistor M1N can be pulled down to the system voltage VSS, thereby turning off N-type transistor M2N. As a result, the charging current I1 can flow from voltage pad PD1 into the input terminal IN1 of circuit CT1, allowing the input terminal IN1 of circuit CT1 to receive the high operating voltage VPP in normal mode.
[0046] In a specific embodiment of the invention, the voltage gap provider 110 provides a voltage drop VD1 from the second terminal of the P-type transistor M1P to the first terminal of the N-type transistor M1N, such that the voltage VC at the second terminal of the P-type transistor M1P is equal to the system voltage VSS plus the voltage drop VD1. Thus, the voltage across the first and second terminals of the P-type transistor M1P is VPP minus the voltage drop VD1. In this specific embodiment, the voltage drop VD1 is sufficiently high to ensure that the voltage across the first and second terminals of the P-type transistor M1P is less than the breakdown voltage of the P-type transistor M1P. For example, if the breakdown voltage of the P-type transistor M1P is 9V and the high operating voltage VPP is 10V, then the voltage drop VD1 provided by the voltage gap provider 110 can be 1.8V. Therefore, the voltage across the first and second terminals of the P-type transistor M1P will be 8.2V, which is less than the breakdown voltage of the P-type transistor M1P, thus protecting the P-type transistor M1P from breakdown.
[0047] Furthermore, the voltage gap provider 120 can provide a voltage drop VD2 from the voltage pad PD1 to the first terminal of the second N-type transistor M2N. Therefore, the voltage across the first and second terminals of the N-type transistor M2N will be VPP minus the voltage drop VD2. In a specific embodiment of the invention, the voltage drop VD2 is sufficiently high to ensure that the voltage across the first and second terminals of the N-type transistor M2N is less than the breakdown voltage of the N-type transistor M2N. For example, if the breakdown voltage of the N-type transistor M2N is 9V, the voltage drop VD2 provided by the voltage gap provider 120 can be 1.8V. Therefore, the voltage across the first and second terminals of the N-type transistor M2N will be 8.2V, which is less than the breakdown voltage of the N-type transistor M2N, thus protecting the N-type transistor M2N from breakdown.
[0048] In a specific embodiment of the invention, the voltage gap provider 110 may include at least one diode D1 connected in series. In some embodiments, the number of diodes D1 in the voltage gap provider 110 may be determined by the required voltage drop VD1. For example, if the required voltage drop VD1 to be provided is 1.8V and the forward voltage of the diodes D1 is 0.6V, then the voltage gap provider 110 may include three diodes D1.
[0049] Similarly, the voltage gap provider 120 may include at least one diode D2 connected in series, and the number of diodes D2 in the voltage gap provider 120 may be determined by the required voltage drop VD2.
[0050] Figure 3This is a schematic diagram of the electrostatic discharge protection circuit 100 during an ESD event. When a positive voltage ESD event occurs, capacitor C1 can act as a short circuit, and the voltage VA at the second terminal of resistor R1 can be pulled down to the system voltage VSS, thereby turning on P-type transistor M1P and turning off N-type transistor M1N. In this case, the voltage VB at the first terminal of N-type transistor M1N can be pulled up to a high voltage through P-type transistor M1P and voltage gap provider 110, thus turning on N-type transistor M2N. In this way, the electrostatic discharge current I2 can flow into the low-impedance path formed by voltage gap provider 120 and N-type transistor M2N, and will not enter the input terminal IN1 of circuit CT1.
[0051] In a specific embodiment of the invention, the anode of each diode D1 can be coupled to the second terminal of the P-type transistor M1P or the cathode of another diode D1, while the cathode of each diode D1 can be coupled to the first terminal of the N-type transistor M1N or the anode of another diode D1. Furthermore, the anode of each diode D2 can be coupled to the voltage pad PD1 or the cathode of another diode D2, while the cathode of each diode D2 can be coupled to the first terminal of the second N-type transistor M2N or the anode of another diode D2. In this case, the discharge path provided by the voltage gap provider 120 and the N-type transistor M2N is directional, allowing only positive (i.e., from the voltage pad PD1 to the ground) electrostatic discharge current to pass through. Therefore, when a negative voltage polarity electrostatic discharge event occurs, to provide a reverse (i.e., from the system voltage node to the voltage pad PD1) discharge path, the electrostatic discharge protection circuit 100 may further include at least one diode D3 connected in series between the voltage pad PD1 and the system voltage VSS. In a specific embodiment of the present invention, the anode of diode D3 may be coupled to a system voltage node, while the cathode of diode D3 may be coupled to voltage pad PD1. In some embodiments, diode D3 may be a parasitic capacitor formed by the P-wells and N-wells of the transistor in the electrostatic discharge protection circuit 100, in order to reduce the circuit area. However, the present invention is not limited thereto.
[0052] Furthermore, in some embodiments, since the electrostatic discharge current can flow through diodes D2 or D3, diodes D2 and D3 must withstand higher rated currents. In this case, diodes D2 and D3 can be designed to have larger dimensions than diode D1. Similarly, since the electrostatic discharge current can flow through N-type transistor M2N, the size of N-type transistor M2N can be larger than the size of N-type transistor M1N and P-type transistor M1P.
[0053] Figure 4This is a schematic diagram of an electrostatic discharge protection circuit 200 according to another embodiment of the present invention. The electrostatic discharge protection circuit 200 differs from the electrostatic discharge protection circuit 100 in that the electrostatic discharge protection circuit 200 further includes a protection switch 230 and a latching unit 240.
[0054] The protective switch 230 is coupled between voltage pad PD1 and input terminal IN1 of the circuit CT1 to be protected. The protective switch 230 cuts off the electrical connection between voltage pad PD1 and input terminal IN1 in the event of an ESD event, thus protecting circuit CT1 from receiving severe and large electrostatic discharge currents.
[0055] In an embodiment of the present invention, the protection switch 230 includes a P-type transistor M2P, which has a first terminal coupled to a voltage pad PD1, a second terminal coupled to an input terminal IN1 of a circuit CT1, and a control terminal coupled to the second terminal of the P-type transistor M1P.
[0056] Figure 5 This is a schematic diagram of the electrostatic discharge protection circuit 100 in the event of an electrostatic discharge incident. (Example) Figure 5 As shown, when an electrostatic discharge event occurs, the voltage VC at the second terminal of the P-type transistor M1P can rise to a high voltage, so the P-type transistor M2P will be turned off, thereby preventing the electrostatic discharge current from entering the circuit CT1.
[0057] Figure 6 This is a schematic diagram of the electrostatic discharge protection circuit 200 during normal mode. Figure 6 As shown, when the electrostatic discharge protection circuit 200 operates in normal mode, the voltage VC at the second terminal of the P-type transistor M1P will be pulled low, and thus the P-type transistor M2P will be turned on, thereby enabling the input terminal IN1 to receive a high operating voltage VPP. Note that since the voltage drop VD1 provided by the voltage gap provider 110 can be appropriately specified, the voltage across the first and second terminals of the P-type transistor M2P can also be lower than its breakdown voltage, thereby enabling the P-type transistor M2P to operate in its SOA.
[0058] Latch unit 240 can be coupled between voltage pad PD1 and the second terminal of resistor R1. In embodiments of the invention, an electrostatic discharge (ESD) event occurs when voltage pad PD1 is coupled to a high operating voltage VPP, and after such an ESD event, the ESD protection circuit 200 remains in normal operation. However, when the high operating voltage VPP is used for certain operations by circuit CT1, the high operating voltage VPP may fluctuate due to load variations. Such voltage fluctuations may trigger the ESD protection circuit 200 to turn on N-type transistor M2N, forming a discharge path. In this case, circuit CT1 will not be able to receive the high operating voltage VPP as needed. To solve this problem, once the ESD protection circuit 200 enters normal mode after an ESD event, latch unit 240 can maintain the voltage VA at the second terminal of resistor R1 at the high operating voltage VPP, thus keeping P-type transistor M1P off and N-type transistor M1N on, thereby preventing N-type transistor M2N from being mistakenly turned on.
[0059] like Figure 6 As shown, latching unit 240 may include P-type transistor M3P, having a first terminal coupled to voltage pad PD1, a second terminal coupled to a second terminal of resistor R1, and a control terminal coupled to the second terminal of P-type transistor M1P. It can be noted that, thanks to the voltage drop VD1 provided by voltage gap provider 110, the voltage across the first and second terminals of P-type transistor M3P can also be lower than its breakdown voltage, thereby enabling P-type transistor M3P to maintain operation in its SOA under normal electrostatic discharge protection circuit 200 conditions.
[0060] Figure 7 This is a schematic diagram of an electrostatic discharge (ESD) protection circuit 300 according to another embodiment of the invention disclosed herein. The ESD protection circuit 300 differs from the ESD protection circuit 200 in that it further includes a voltage gap provider 350 having a first terminal and a second terminal. The first terminal of the voltage gap provider 350 is coupled to the second terminal of the P-type transistor M3P, the second terminal of the resistor R1, and the control terminal of the P-type transistor M1P. The second terminal of the voltage gap provider 350 is coupled to the first terminal of the capacitor C1 and the control terminal of the N-type transistor M1N. The voltage gap provider 350 provides a voltage drop from the control terminal of the P-type transistor M1P to the control terminal of the N-type transistor M1N to ensure that transistors M1N and M1P can operate within their safe operating area (SOA). In this way, even if the gate oxide of transistors M1P and M1N is thin (whether due to unintentional process variations or intentional process selection), the voltage gap provider 350 can still help protect transistors M1P and M1N from breakdown during operation.
[0061] In a specific embodiment of the present invention, the voltage gap provider 350 may include at least one diode D4, which is connected in series between the first terminal and the second terminal of the voltage gap provider 350. Specifically, the anode of each diode D4 may be coupled to the first terminal of the voltage gap provider 350 or the cathode of another diode D4, while the cathode of each diode D4 may be coupled to the second terminal of the voltage gap provider 350 or the anode of another diode D2.
[0062] In this case, the voltage drop can be equal to the sum of the forward voltages of each diode D4. In some embodiments, in normal mode, the voltage drop provided by the voltage gap provider 350 can be high enough to ensure that the voltage between the control terminal and the second terminal of the N-type transistor M1N is less than the breakdown voltage of the N-type transistor M1N. Furthermore, during an electrostatic discharge event, the voltage drop provided by the voltage gap provider 350 can be high enough to ensure that the voltage between the control terminal and the first terminal of the P-type transistor M1P is less than the breakdown voltage of the P-type transistor M1P.
[0063] In summary, the electrostatic discharge protection circuit provided by the embodiments disclosed in this invention enables low-voltage components to operate under high voltage conditions, while effectively protecting the circuit from damage by electrostatic discharge current.
[0064] While this specification and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made to this document without departing from the spirit and scope defined by the appended claims. For example, many of the processes discussed above can be implemented in different ways and may be replaced by other processes or combinations thereof.
[0065] Furthermore, the scope of this application is not limited to the specific processes, machines, manufacturing methods, material compositions, means, methods, and steps described in the specification. As will be readily understood by those skilled in the art from this specification, any existing or future-developed processes, machines, manufacturing methods, material compositions, means, methods, or steps that can perform substantially the same function or achieve substantially the same effect as the corresponding embodiments described herein may be utilized in accordance with this specification. Therefore, the appended claims are intended to include such processes, machines, manufacturing methods, material compositions, means, methods, and steps within their scope.
Claims
1. An electrostatic discharge protection circuit coupled between a voltage pad and a circuit to be protected, the electrostatic discharge protection circuit comprising: a resistor having a first terminal coupled to the voltage pad for receiving a high operating voltage, and a second terminal; a capacitor having a first terminal coupled to the second terminal of the resistor, and a second terminal coupled to a system voltage node for receiving a system voltage lower than the high operating voltage; a first P-type transistor having a first terminal coupled to the voltage pad, a second terminal, and a control terminal coupled to the second terminal of the resistor; a first N-type transistor having a first terminal, a second terminal coupled to the system voltage node, and a control terminal coupled to the first terminal of the first N-type transistor; a first voltage gap provider coupled between the second terminal of the first P-type transistor and the first terminal of the first N-type transistor, and operative to provide a first voltage drop from the second terminal of the first P-type transistor to the first terminal of the first N-type transistor; a second N-type transistor having a first terminal, a second terminal coupled to the system voltage node, and a control terminal coupled to the first terminal of the first N-type transistor; and a second voltage gap provider coupled between the voltage pad and the first terminal of the second N-type transistor, and operative to provide a second voltage drop from the voltage pad to the first terminal of the second N-type transistor; wherein when an electrostatic discharge event of a positive voltage polarity occurs, the second terminal of the resistor is at the system voltage, the first P-type transistor and the second N-type transistor are on, the first N-type transistor is off, and an electrostatic discharge current flows from the voltage pad through the second voltage gap provider to the second N-type transistor.
2. The electrostatic discharge protection circuit of claim 1, further comprising a protection switch coupled between the voltage pad and an input terminal of the circuit to be protected, and operative to break an electrical connection between the voltage pad and the input terminal when the electrostatic discharge event occurs.
3. The electrostatic discharge protection circuit of claim 2, wherein the protection switch comprises a second P-type transistor having a first terminal coupled to the voltage pad, a second terminal coupled to the input terminal of the circuit to be protected, and a control terminal coupled to the second terminal of the first P-type transistor, and when the electrostatic discharge event of the positive voltage polarity occurs, the second terminal of the first P-type transistor is at a high voltage to turn off the protection switch to break the electrical connection.
4. The electrostatic discharge protection circuit of claim 1, further comprising a latch unit coupled between the voltage pad and the second terminal of the resistor, and operative to maintain a voltage of the second terminal of the resistor at the high operating voltage in a normal mode so as to keep the first P-type transistor off and keep the first N-type transistor on. 5. The electrostatic discharge protection circuit of claim 4, wherein the latch unit comprises a third P-type transistor having a first terminal coupled to the voltage pad, a second terminal coupled to the second terminal of the resistor, and a control terminal coupled to the second terminal of the first P-type transistor, wherein in the normal mode after the electrostatic discharge event, the capacitor is charged and the second terminal of the resistor is at a high voltage to turn on the first N-type transistor, a first terminal of the first N-type transistor is at the system voltage, and the second terminal of the first P-type transistor is at a voltage equal to the system voltage plus the first voltage drop to turn on the third P-type transistor.
6. The electrostatic discharge protection circuit of claim 1, wherein the first voltage gap provider comprises at least one first diode coupled in series, and the first voltage drop is equal to a sum voltage of a turn-on voltage of each first diode.
7. The electrostatic discharge protection circuit of claim 6, wherein the second voltage gap provider comprises at least one second diode coupled in series, and the second voltage drop is equal to a sum voltage of a turn-on voltage of each second diode.
8. The electrostatic discharge protection circuit of claim 7, further comprising at least one third diode coupled in series between the voltage pad and the system voltage node, the third diode providing a discharge path for an electrostatic discharge current from the system voltage node to the voltage pad when an electrostatic discharge event of a negative voltage polarity occurs.
9. The electrostatic discharge protection circuit of claim 8, wherein: an anode of the at least one second diode is coupled to the voltage pad, and a cathode of the at least one second diode is coupled to the first terminal of the second N-type transistor; and an anode of the at least one third diode is coupled to the system voltage node, and a cathode of the at least one third diode is coupled to the voltage pad.
10. The electrostatic discharge protection circuit of claim 9, wherein a size of the at least one third diode and a size of the at least one second diode are greater than a size of the at least one first diode.
11. The electrostatic discharge protection circuit of claim 9, wherein the at least one third diode is a parasitic capacitor formed from a P-well region and an N-well region of a transistor in the electrostatic discharge protection circuit.
12. The electrostatic discharge protection circuit of claim 1, wherein a size of the second N-type transistor is greater than a size of the first N-type transistor and a size of the first P-type transistor.
13. The electrostatic discharge protection circuit of claim 1, wherein during a normal mode after the electrostatic discharge event, the second terminal of the resistor is at the high operating voltage supplied from the voltage pad, the first N-type transistor is on, the first P-type transistor and the second N-type transistor are off, and the first voltage drop is sufficiently high to ensure a voltage between the first terminal of the first P-type transistor and the second terminal of the first P-type transistor is less than a breakdown voltage of the first P-type transistor.
14. The electrostatic discharge protection circuit of claim 13, wherein during the normal mode, the second voltage drop is sufficiently high to ensure a voltage between the first terminal of the second N-type transistor and the second terminal of the second N-type transistor is less than a breakdown voltage of the second N-type transistor.
15. The electrostatic discharge protection circuit of claim 14, wherein the circuit to be protected comprises a memory cell, and the high operating voltage is used to program the memory cell, and the high operating voltage is higher than a read voltage used to read the memory cell.
16. The electrostatic discharge protection circuit of claim 15, further comprising a third P-type transistor having a first terminal coupled to the voltage interface pad, a second terminal coupled to the second terminal of the resistor, and a control terminal coupled to the second terminal of the first P-type transistor, and operative to maintain a voltage of the second terminal of the resistor at the high operating voltage in a normal mode so as to keep the first P-type transistor off and keep the first N-type transistor on, and wherein: the first voltage gap provider comprises at least one first diode coupled in series, and the first voltage drop is equal to a sum voltage of a forward voltage of each of the at least one first diode, and the second voltage gap provider comprises at least one second diode coupled in series, and the second voltage drop is equal to a sum voltage of a forward voltage of each of the at least one second diode.
17. The electrostatic discharge protection circuit of claim 16, further comprising at least one third diode coupled in series between the voltage interface pad and the system voltage, the third diode providing a discharge path for an electrostatic discharge current from the system voltage node to the voltage interface pad when an electrostatic discharge event of a negative voltage polarity occurs.
18. The electrostatic discharge protection circuit of claim 16, further comprising a third voltage gap provider having a first terminal and a second terminal, wherein: the first terminal of the third voltage gap provider is coupled to the second terminal of the third P-type transistor, the second terminal of the resistor, and the control terminal of the first P-type transistor, and the second terminal of the third voltage gap provider is coupled to the first terminal of the capacitor and the control terminal of the first N-type transistor; the third voltage gap provider is operative to provide a third voltage drop from the control terminal of the first P-type transistor to the control terminal of the first N-type transistor; and the third voltage gap provider comprises at least one fourth diode coupled in series between the first terminal and the second terminal of the third voltage gap provider, and the third voltage drop is equal to a sum voltage of a forward voltage of each of the at least one fourth diode.