A 4&2 phase non-overlapping clock circuit for high-order op-amp sharing

Abstract

The present application relates to non-overlapping clock circuit, specifically relates to a kind of 4&2 phase non-overlapping clock circuit for high-order operational amplifier sharing;Clock signal frequency division unit is connected with clock input terminal Clk by clock signal input unit;Clock signal frequency division unit is four-frequency to clock signal, and it is transmitted to four-phase non-overlapping clock unit, and four-phase non-overlapping clock unit is shaped as four-phase non-overlapping clock signal after four-frequency to clock signal;Four-phase non-overlapping clock signal is transmitted to four-phase non-overlapping delay clock unit, two-phase non-overlapping clock unit;Four-phase non-overlapping clock signal is delayed after four-phase non-overlapping delay clock unit, and four-phase non-overlapping delay clock signal is output;Four-phase non-overlapping clock signal is integrated after two-phase non-overlapping clock unit, and two-phase non-overlapping clock signal is output.The present application will not limit the number of times of multiplexing operational amplifier of analog-digital converter, also will not promote package cost and test complexity.

Description

Technical Field

[0001] This invention relates to non-overlapping clock circuits, and more specifically to a 4&2 phase non-overlapping clock circuit for sharing by high-order operational amplifiers. Background Technology

[0002] Multiphase non-overlapping clocks play a crucial role in analog and mixed-signal circuits by strictly separating the clock phases, avoiding signal contention and short-circuit currents while ensuring precise timing control. This technique is particularly important in switched-capacitor circuits of analog-to-digital converters (ADCs), where it ensures signal integrity by precisely managing the charging and discharging process of the capacitors, while reducing nonlinear distortion and charge injection errors. Meanwhile, with the increasing demand for low-power designs, op-amp sharing technology has emerged. This technology optimizes power consumption and area by time-division multiplexing a single op-amp. However, in low-power designs, its common-mode stability relies on switched-capacitor common-mode negative feedback (SC-CMFB) circuits. The implementation of SC-CMFB requires a strictly synchronized two-phase non-overlapping clock to maintain correct switching timing and prevent charge sharing and common-mode misalignment.

[0003] Therefore, from traditional switched-capacitor circuits to modern low-power operational amplifier shared architectures, multiphase non-overlapping clocks have always been a key timing control method to ensure circuit reliability and performance, providing important guarantees for the design of high-performance, low-power analog integrated circuits.

[0004] In the field of analog-to-digital converters, op-amp sharing is often achieved by using two non-overlapping clocks or by adding extra pins to introduce higher frequency clock signals to complete second- or third-order op-amp sharing. If the analog-to-digital converter and the operational amplifier use the same two-phase non-overlapping clock, it will greatly limit the number of times the analog-to-digital converter can reuse the operational amplifier, thus failing to fully utilize the power-saving advantage of the operational amplifier sharing technology. Adding extra pins will increase packaging costs and testing complexity, and affect signal integrity. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problems in the field of existing analog-to-digital converters (ADCs) where op-amp sharing is often achieved by using two-phase non-overlapping clocks or adding extra pins to introduce higher frequency clock signals to complete second- or third-order op-amp sharing, which limits the number of times the op-amp can be reused in the ADC, and increases packaging costs and testing complexity. The invention provides a 4&2 phase non-overlapping clock circuit for sharing high-order op-amps.

[0006] To solve the above-mentioned technical problems, the technical solution provided by the present invention is as follows: A 4&2 phase non-overlapping clock circuit for high-order operational amplifiers includes a connected clock signal divider unit and a four-phase non-overlapping clock unit. The clock signal frequency division unit is connected to the clock input terminal Clk via the clock signal input unit; The four-phase non-overlapping clock unit is provided with a four-phase non-overlapping delay clock unit and a two-phase non-overlapping clock unit; A 4fs clock signal is input to the clock signal input unit via the clock input terminal Clk. The clock signal divider divides the clock signal by four and transmits it to the four-phase non-overlapping clock unit. The four-phase non-overlapping clock unit shapes the divided clock signal into a four-phase non-overlapping clock signal. The four-phase non-overlapping clock unit transmits the four-phase non-overlapping clock signal to the four-phase non-overlapping delay clock unit and the two-phase non-overlapping clock unit respectively; the four-phase non-overlapping clock signal is delayed by the four-phase non-overlapping delay clock unit and then outputs the four-phase non-overlapping delayed clock signal. The four-phase non-overlapping clock signals are integrated by the two-phase non-overlapping clock unit to output a two-phase non-overlapping clock signal.

[0007] Furthermore, the clock signal input unit includes latches LATCH1 and LATCH2; the Clk pins of latches LATCH1 and LATCH2 are connected to the clock input terminal Clk. The D pin of latch LATCH1 is connected to the Qi pin of latch LATCH2; the Qi pin of latch LATCH1 is connected to the D pin of latch LATCH2. The Q pin and Qi pin of latch LATCH1 are connected to output terminal A and inverting output terminal Ai, respectively; The Q pin and Qi pin of latch LATCH2 are connected to output terminal B and inverting output terminal Bi, respectively; Output terminal A, inverting output terminal Ai, output terminal B, and inverting output terminal Bi are all connected to the clock signal divider unit.

[0008] Furthermore, the clock signal frequency division unit includes a first clock signal frequency division module, a second clock signal frequency division module, a third clock signal frequency division module, and a fourth clock signal frequency division module; The first clock signal frequency division module includes a NAND gate NAND1 and an inverter INV1 whose input is connected to the output of the NAND gate NAND1; the two inputs of the NAND gate NAND1 are respectively connected to the inverting output terminal Ai and the inverting output terminal Bi. The structures of the second, third, and fourth clock signal frequency divider modules are the same as those of the first clock signal frequency divider module; The two input terminals of the NAND gate NAND2 of the second clock signal divider module are connected to the inverting output terminal Ai and the output terminal B, respectively; The two input terminals of the NAND gate NAND3 of the third clock signal frequency divider module are connected to the output terminal B and the output terminal A, respectively. The two input terminals of the NAND gate NAND4 of the fourth clock signal frequency divider module are connected to the output terminal A and the inverting output terminal B, respectively.

[0009] Furthermore, the four-phase non-overlapping clock unit includes a first signal expansion module, a second signal expansion module, a third signal expansion module, and a fourth signal expansion module, which are respectively connected to the first clock signal frequency divider module, the second clock signal frequency divider module, the third clock signal frequency divider module, and the fourth clock signal frequency divider module; The first signal expansion module includes, in sequence, buffers BUF1 and BUF12, NAND gate NAND5, and inverter INV5; The input of buffer BUF1 is connected to the output of inverter INV1 and one of the inputs of NAND gate NAND5; The output of buffer BUF1 is connected to the other input of NAND gate NAND5; The output of NAND gate NAND5 is connected to the input of inverter INV5; The input terminal of buffer BUF12 is connected to the output terminal of inverter INV5, and the output terminal of buffer BUF12 is connected to the clock signal output terminal S1. The structures of the second, third, and fourth signal expansion modules are the same as those of the first signal expansion module.

[0010] Furthermore, the four-phase non-overlapping delay clock unit includes a first non-overlapping clock module, a second non-overlapping clock module, a third non-overlapping clock module, and a fourth non-overlapping clock module that output four clock signals that do not overlap and have an ordered timing sequence. The first non-overlapping clock module, the second non-overlapping clock module, the third non-overlapping clock module, and the fourth non-overlapping clock module are respectively connected to the first signal expansion module, the second signal expansion module, the third signal expansion module, and the fourth signal expansion module; The first non-overlapping clock module includes buffers BUF5 and BUF11, NOR gate NOR1 and inverter INV9; The input of buffer BUF5 and one of the inputs of NOR gate NOR1 are connected to the output of inverter INV5, and the output of buffer BUF5 is connected to the other input of NOR gate NOR1. The output of NOR1 is connected to the input of INV9, the output of INV9 is connected to the input of BUF11, and the output of BUF11 is connected to the delayed clock signal output terminal S1D. The structures of the second, third, and fourth non-overlapping clock modules are the same as those of the first non-overlapping clock module.

[0011] Furthermore, the two-phase non-overlapping clock unit includes a first shaping module and a second shaping module; The first shaping module includes buffers BUF21 and BUF22, NOR gates NOR7 and NOR8, and inverters INV15 and INV16; The input of the buffer BUF21 and one of the inputs of the NOR gate NOR7 are connected to the output of the inverter INV5. The output of buffer BUF21 is connected to the other input of NOR7; The output of NOR7 is connected to the input of INV15, the output of INV15 is connected to one of the inputs of NOR8, and the other input of NOR8 is connected to the output of INV6 of the second signal expansion module. The output of NOR8 is connected to the input of INV16, the output of INV16 is connected to the input of BUF22, and the output of BUF22 is connected to the clock signal output terminal CLK. AMP1 ; The structure of the second shaping module is the same as that of the first shaping module.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The 4&2 phase non-overlapping clock circuit for high-order op-amp sharing provided by this invention, through a clock signal division unit, a four-phase non-overlapping clock unit, a two-phase non-overlapping clock unit, and a four-phase non-overlapping delay clock unit, transforms the input clock signal into a digital signal waveform that simultaneously possesses four-phase non-overlapping clocks, two-phase non-overlapping clocks, and four-phase non-overlapping delay clocks. This facilitates clock support for analog technologies (such as fourth-order op-amp sharing technology) that simultaneously require four-phase non-overlapping clocks, two-phase non-overlapping clocks, and four-phase non-overlapping delay clocks. Compared to the traditional op-amp sharing in the field of analog-to-digital converters, which often uses two-phase non-overlapping clocks or adds additional pins to introduce higher frequency clock signals, high-order op-amp sharing can be achieved without limiting the number of times the op-amp can be reused in the analog-to-digital converter, without increasing packaging costs and testing complexity, ensuring signal integrity, and leveraging the power consumption reduction advantage of op-amp sharing technology.

[0013] 2. The 4&2 phase non-overlapping clock circuit for high-order operational amplifiers provided by this invention can control the non-overlapping time and delay time between digital signal waveforms by adjusting the buffer BUF in the four-phase non-overlapping clock unit, the four-phase non-overlapping delay clock unit, and the two-phase non-overlapping clock unit; so that the delay between the four-phase non-overlapping clock and the two-phase non-overlapping clock is in the nanosecond range. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of an embodiment of the present invention; Figure 2 This is the output waveform of an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] like Figure 1 As shown, a high-order operational amplifier shared 4&2 phase non-overlapping clock circuit is constructed from a latch, a NAND gate, a NOR gate, an inverter, and a buffer. Its specific structure is as follows: It includes a connected clock signal divider unit and a four-phase non-overlapping clock unit; the clock signal divider unit is connected to the clock input terminal Clk through a clock signal input unit; the four-phase non-overlapping clock unit is provided with a four-phase non-overlapping delay clock unit and a two-phase non-overlapping clock unit; A clock signal with a frequency of 4fs is input to the clock signal input unit via the clock input terminal Clk. The clock signal frequency divider divides the clock signal by four and transmits it to the four-phase non-overlapping clock unit. The four-phase non-overlapping clock unit shapes the divided clock signal into four-phase non-overlapping clock signals S1, S2, S3 and S4. The four-phase non-overlapping clock unit transmits the four-phase non-overlapping clock signals S1, S2, S3, and S4 to the four-phase non-overlapping delay clock unit and the two-phase non-overlapping clock unit, respectively; the four-phase non-overlapping clock signals S1, S2, S3, and S4 are delayed by the four-phase non-overlapping delay clock unit and then output as the four-phase non-overlapping delayed clock signal S. 1D S 2D S 3D and S 4D The four-phase non-overlapping clock signals S1, S2, S3, and S4 are integrated by a two-phase non-overlapping clock unit to output a two-phase non-overlapping clock signal CLK. AMP1 and CLK AMP2 .

[0017] like Figure 1 As shown, the clock signal input unit includes latches LATCH1 and LATCH2; the Clk pins of latches LATCH1 and LATCH2 are connected to the clock input terminal Clk. The D pin of latch LATCH1 is connected to the Qi pin of latch LATCH2; The Qi pin of latch LATCH1 is connected to the D pin of latch LATCH2; The Q pin and Qi pin of latch LATCH1 are connected to output terminal A and inverting output terminal Ai, respectively; The Q pin and Qi pin of latch LATCH2 are connected to output terminal B and inverting output terminal Bi, respectively; Output terminal A, inverting output terminal Ai, output terminal B, and inverting output terminal Bi are all connected to the clock signal divider unit.

[0018] like Figure 1 As shown, the clock signal frequency division unit includes a first clock signal frequency division module, a second clock signal frequency division module, a third clock signal frequency division module, and a fourth clock signal frequency division module; The first clock signal divider module includes a NAND gate NAND1 and an inverter INV1 whose input is connected to the output of the NAND gate NAND1; the two inputs of the NAND gate NAND1 are respectively connected to the inverting output terminal Ai and the inverting output terminal Bi. The second clock signal divider module includes a NAND gate NAND2 and an inverter INV2 whose input is connected to the output of the NAND gate NAND2; the two inputs of the NAND gate NAND2 are connected to the inverted output terminal Ai and the output terminal B, respectively. The third clock signal divider module includes a NAND gate NAND3 and an inverter INV3 whose input is connected to the output of the NAND gate NAND3; the two inputs of the NAND gate NAND3 are connected to the output terminal B and the output terminal A, respectively. The fourth clock signal divider module includes a NAND gate NAND4 and an inverter INV4 whose input is connected to the output of the NAND gate NAND4; the two inputs of the NAND gate NAND4 are connected to the output terminal A and the inverted output terminal B, respectively.

[0019] like Figure 1 As shown, the four-phase non-overlapping clock unit includes a first signal expansion module, a second signal expansion module, a third signal expansion module, and a fourth signal expansion module; The first signal expansion module includes, in sequence, a buffer BUF1, a NAND gate NAND5, and an inverter INV5; The input of buffer BUF1 is connected to the output of inverter INV1 and one of the inputs of NAND gate NAND5; The output of buffer BUF1 is connected to the other input of NAND gate NAND5; The output of NAND gate NAND5 is connected to the input of inverter INV5; The second signal expansion module includes, in sequence, a buffer BUF2, a NAND gate NAND6, and an inverter INV6; The input of buffer BUF2 is connected to the output of inverter INV2 and one of the inputs of NAND gate NAND6; The output of buffer BUF2 is connected to the other input of NAND gate NAND6; The output of NAND gate NAND6 is connected to the input of inverter INV6; The third signal expansion module includes, in sequence, a buffer BUF3, a NAND gate NAND7, and an inverter INV7; The input of buffer BUF3 is connected to the output of inverter INV3 and one of the inputs of NAND gate NAND7; The output of buffer BUF3 is connected to the other input of NAND gate NAND7; The output of NAND gate NAND7 is connected to the input of inverter INV7; The fourth signal expansion module includes, in sequence, a buffer BUF4, a NAND gate NAND8, and an inverter INV8; The input of buffer BUF4 is connected to the output of inverter INV4 and one of the inputs of NAND gate NAND8; The output of buffer BUF4 is connected to the other input of NAND gate NAND8; The output of NAND gate NAND8 is connected to the input of inverter INV8; like Figure 1 As shown, the four-phase non-overlapping delay clock unit includes a first non-overlapping clock module, a second non-overlapping clock module, a third non-overlapping clock module, and a fourth non-overlapping clock module that output four clock signals that do not overlap and have an ordered timing sequence. The first non-overlapping clock module includes a first delayed clock signal output module and a first clock signal output module; The first delayed clock signal output module includes a buffer BUF5, a NOR gate NOR1, an inverter INV9, and a buffer BUF11; The input of buffer BUF5 and one of the inputs of NOR gate NOR1 are connected to the output of inverter INV5, and the output of buffer BUF5 is connected to the other input of NOR gate NOR1. The output of NOR1 is connected to the input of INV9, the output of INV9 is connected to the input of BUF11, and the output of BUF11 is connected to the delayed clock signal output terminal S1D. The first clock signal output module includes a buffer BUF12. The input terminal of the buffer BUF12 is connected to the output terminal of the inverter INV5, and the output terminal of the buffer BUF12 is connected to the clock signal output terminal S1. The second non-overlapping clock module includes a second delayed clock signal output module and a second clock signal output module; The second delayed clock signal output module includes a buffer BUF6, a NOR gate NOR2, an inverter INV10, and a buffer BUF14. The input of buffer BUF6 and one of the inputs of NOR2 are connected to the output of inverter INV6, and the output of buffer BUF6 is connected to the other input of NOR2. The output of NOR2 is connected to the input of INV10, the output of INV10 is connected to the input of BUF14, and the output of BUF14 is connected to the delayed clock signal output terminal S2D. The second clock signal output module includes a buffer BUF13. The input terminal of the buffer BUF13 is connected to the output terminal of the inverter INV6, and the output terminal of the buffer BUF13 is connected to the clock signal output terminal S2. The third non-overlapping clock module includes a third delayed clock signal output module and a third clock signal output module; The third delayed clock signal output module includes a buffer BUF7, a NOR gate NOR3, an inverter INV11, and a buffer BUF15. The input of buffer BUF7 and one of the inputs of NOR3 are connected to the output of inverter INV7, and the output of buffer BUF7 is connected to the other input of NOR3. The output of NOR3 is connected to the input of INV11, the output of INV11 is connected to the input of BUF15, and the output of BUF15 is connected to the delayed clock signal output terminal S3D. The third clock signal output module includes a buffer BUF16. The input terminal of the buffer BUF16 is connected to the output terminal of the inverter INV7, and the output terminal of the buffer BUF16 is connected to the clock signal output terminal S3. The fourth non-overlapping clock module includes a fourth delayed clock signal output module and a fourth clock signal output module; The fourth delayed clock signal output module includes a buffer BUF9, a NOR gate NOR4, an inverter INV12, and a buffer BUF19. The input of buffer BUF9 and one of the inputs of NOR4 are connected to the output of inverter INV8, and the output of buffer BUF9 is connected to the other input of NOR4. The output of NOR4 is connected to the input of INV12, the output of INV12 is connected to the input of BUF19, and the output of BUF19 is connected to the delayed clock signal output terminal S4D. The fourth clock signal output module includes a buffer BUF18. The input of the buffer BUF18 is connected to the output of the inverter INV8, and the output of the buffer BUF18 is connected to the clock signal output terminal S4.

[0020] like Figure 1 As shown, the two-phase non-overlapping clock unit includes a first shaping module and a second shaping module; The first shaping module includes buffers BUF21 and BUF22, NOR gates NOR7 and NOR8, and inverters INV15 and INV16; The input of buffer BUF21 and one of the inputs of NOR7 are connected to the output of inverter INV5. The output of buffer BUF21 is connected to the other input of NOR7; The output of NOR7 is connected to the input of INV15, the output of INV15 is connected to one of the inputs of NOR8, and the other input of NOR8 is connected to the output of INV6 of the second signal expansion module. The output of NOR8 is connected to the input of INV16, the output of INV16 is connected to the input of BUF22, and the output of BUF22 is connected to the clock signal output terminal CLK. AMP1 ; The second shaping module includes buffers BUF10 and BUF20, NOR gates NOR5 and NOR6, and inverters INV13 and INV14; The input of buffer BUF10 and one of the inputs of NOR5 are connected to the output of inverter INV7. The output of buffer BUF10 is connected to the other input of NOR5; The output of NOR5 is connected to the input of INV13, the output of INV13 is connected to one of the inputs of NOR6, and the other input of NOR6 is connected to the output of INV8 of the fourth signal expansion module. The output of NOR6 is connected to the input of INV14, the output of INV14 is connected to the input of BUF20, and the output of BUF20 is connected to the clock signal output terminal CLK. AMP2 .

[0021] like Figure 1 As shown, to facilitate quantization of the output clock signal, the output of inverter INV8 is connected to the input of buffer BUF8, the output of buffer BUF8 is connected to the input of buffer BUF17, and the output of buffer BUF17 is connected to the clock CLK of the single-bit quantizer. Q .

[0022] The 4&2 phase non-overlapping clock circuit for high-order op-amp sharing provided in this embodiment is applied to the fourth-order op-amp sharing technology in a Sigma-Delta modulator. In the fourth-order op-amp sharing technology, the 4&2 phase non-overlapping clock circuit of this embodiment is used to control the modulator to perform sampling and integration operations, and its output waveform is as follows: Figure 2 As shown.

[0023] exist Figure 2 In this context, T represents the time of a single cycle; t N For S iD The non-overlapping time for (i=1, 2, 3, 4) is approximately 2 ns; t D For S iD (i=1, 2, 3, 4) compared to S i The delay time for (i=1, 2, 3, 4) is approximately 2ns; t Q The delay time for quantization by a single-bit quantizer.

[0024] S i The delayed clock S of (i=1, 2, 3, 4) iD (i=1, 2, 3, 4) is to allow the op-amp's switching capacitors to turn off at different times to avoid charge injection effects, while the rising edge of the clock has almost no delay, and the switches turn on at approximately the same time.

[0025] CLK AMPi (i=1.2) are two synchronous, non-overlapping two-phase clocks used to control the switched capacitor common-mode negative feedback (SC-CMFB) circuit of the operational amplifier.

[0026] Since charge transfer and switch activation both require time, the output of the modulator's adder module needs a certain amount of time to stabilize. Therefore, the single-bit quantizer needs to stabilize within t... Q Quantization is performed after a delay time.

[0027] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A 4&2 phase non-overlapping clock circuit for high-order operational amplifiers, characterized in that: It includes connected clock signal divider units and four-phase non-overlapping clock units; The clock signal frequency division unit is connected to the clock input terminal Clk via the clock signal input unit; The four-phase non-overlapping clock unit is provided with a four-phase non-overlapping delay clock unit and a two-phase non-overlapping clock unit; A 4fs clock signal is input to the clock signal input unit via the clock input terminal Clk. The clock signal divider divides the clock signal by four and transmits it to the four-phase non-overlapping clock unit. The four-phase non-overlapping clock unit shapes the divided clock signal into a four-phase non-overlapping clock signal. The four-phase non-overlapping clock unit transmits the four-phase non-overlapping clock signal to the four-phase non-overlapping delay clock unit and the two-phase non-overlapping clock unit respectively; the four-phase non-overlapping clock signal is delayed by the four-phase non-overlapping delay clock unit and then outputs the four-phase non-overlapping delayed clock signal. The four-phase non-overlapping clock signal is integrated by the two-phase non-overlapping clock unit to output a two-phase non-overlapping clock signal; The clock signal input unit includes latches LATCH1 and LATCH2; the Clk pin of latches LATCH1 and LATCH2 is connected to the clock input terminal Clk. The D pin of latch LATCH1 is connected to the Qi pin of latch LATCH2; the Qi pin of latch LATCH1 is connected to the D pin of latch LATCH2. The Q pin and Qi pin of latch LATCH1 are connected to output terminal A and inverting output terminal Ai, respectively; The Q pin and Qi pin of latch LATCH2 are connected to output terminal B and inverting output terminal Bi, respectively; Output terminal A, inverting output terminal Ai, output terminal B, and inverting output terminal Bi are all connected to the clock signal divider unit; The clock signal frequency division unit includes a first clock signal frequency division module, a second clock signal frequency division module, a third clock signal frequency division module, and a fourth clock signal frequency division module; The first clock signal frequency division module includes a NAND gate NAND1 and an inverter INV1 whose input is connected to the output of the NAND gate NAND1; the two inputs of the NAND gate NAND1 are respectively connected to the inverting output terminal Ai and the inverting output terminal Bi. The structures of the second, third, and fourth clock signal frequency divider modules are the same as those of the first clock signal frequency divider module; The two input terminals of the NAND gate NAND2 of the second clock signal divider module are connected to the inverting output terminal Ai and the output terminal B, respectively. The two input terminals of the NAND gate NAND3 of the third clock signal frequency divider module are connected to the output terminal B and the output terminal A, respectively. The two input terminals of the NAND gate NAND4 of the fourth clock signal frequency divider module are connected to the output terminal A and the inverting output terminal B, respectively.

2. The 4&2 phase non-overlapping clock circuit for high-order operational amplifier sharing according to claim 1, characterized in that: The four-phase non-overlapping clock unit includes a first signal extension module, a second signal extension module, a third signal extension module, and a fourth signal extension module, which are respectively connected to the first clock signal frequency division module, the second clock signal frequency division module, the third clock signal frequency division module, and the fourth clock signal frequency division module; The first signal expansion module includes, in sequence, buffers BUF1 and BUF12, NAND gate NAND5, and inverter INV5; The input of buffer BUF1 is connected to the output of inverter INV1 and one of the inputs of NAND gate NAND5; The output of buffer BUF1 is connected to the other input of NAND gate NAND5; The output of NAND gate NAND5 is connected to the input of inverter INV5; The input terminal of buffer BUF12 is connected to the output terminal of inverter INV5, and the output terminal of buffer BUF12 is connected to the clock signal output terminal S1. The structures of the second, third, and fourth signal expansion modules are the same as those of the first signal expansion module.

3. The 4&2 phase non-overlapping clock circuit for high-order operational amplifier sharing according to claim 2, characterized in that: The four-phase non-overlapping delay clock unit includes a first non-overlapping clock module, a second non-overlapping clock module, a third non-overlapping clock module, and a fourth non-overlapping clock module that output four clock signals that do not overlap and have an ordered timing sequence. The first non-overlapping clock module, the second non-overlapping clock module, the third non-overlapping clock module, and the fourth non-overlapping clock module are respectively connected to the first signal expansion module, the second signal expansion module, the third signal expansion module, and the fourth signal expansion module; The first non-overlapping clock module includes buffers BUF5 and BUF11, NOR gate NOR1 and inverter INV9; The input of buffer BUF5 and one of the inputs of NOR gate NOR1 are connected to the output of inverter INV5, and the output of buffer BUF5 is connected to the other input of NOR gate NOR1. The output of NOR1 is connected to the input of INV9, the output of INV9 is connected to the input of BUF11, and the output of BUF11 is connected to the delayed clock signal output terminal S1D. The structures of the second, third, and fourth non-overlapping clock modules are the same as those of the first non-overlapping clock module.

4. The 4&2 phase non-overlapping clock circuit for high-order operational amplifier sharing according to claim 3, characterized in that: The two-phase non-overlapping clock unit includes a first shaping module and a second shaping module; The first shaping module includes buffers BUF21 and BUF22, NOR gates NOR7 and NOR8, and inverters INV15 and INV16; The input of the buffer BUF21 and one of the inputs of the NOR gate NOR7 are connected to the output of the inverter INV5. The output of buffer BUF21 is connected to the other input of NOR7; The output of NOR7 is connected to the input of INV15, the output of INV15 is connected to one of the inputs of NOR8, and the other input of NOR8 is connected to the output of INV6 of the second signal expansion module. The output of NOR8 is connected to the input of INV16, the output of INV16 is connected to the input of BUF22, and the output of BUF22 is connected to the clock signal output terminal CLK. AMP1 ; The structure of the second shaping module is the same as that of the first shaping module.

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