switching chip

Abstract

The application discloses a kind of exchange chips.The exchange chip is connected with the input end of bus and loopback interface by service access interface, for receiving original flow, and the original flow is directed into loopback interface;The output end of loopback interface is connected with the input end of link aggregation interface, for the original flow is shaped by pre-configured shaping parameter, and the original flow after shaping is transmitted to link aggregation interface by pre-binding relationship;The output end of link aggregation interface is connected with external network, for the original flow after shaping is transmitted to external network by preset mechanism.The application can realize the technical effect of meeting the demand of efficient, flexible, fine flow control of link aggregation interface under modern complex network environment.

Description

Technical Field

[0001] This invention relates to the field of communication technology applications, and more particularly to a switching chip. Background Technology

[0002] Link aggregation interfaces, also known as port aggregation interfaces or bundled interfaces, are technologies that combine multiple physical network interfaces (such as Ethernet ports) into a single logical interface. The core purpose of link aggregation interfaces is to improve network performance, reliability, and flexibility through "bundling," and they are widely used in high-speed connection scenarios between servers and switches, and between switches themselves. With the rapid development of cloud computing, big data, and high-definition video services, network traffic is experiencing explosive growth, and the requirements of these services on Quality of Service (QoS) parameters such as bandwidth, latency, and jitter are becoming increasingly stringent. Therefore, fine-grained traffic management through link aggregation interfaces has become crucial for ensuring network stability.

[0003] Traffic shaping, as one of the core technologies for network QoS assurance, controls the data packet transmission rate to avoid network congestion and ensure the transmission quality of services with different priorities. Currently, there are two main implementation methods for traffic shaping schemes on link aggregation interfaces:

[0004] Method 1: Independent Shaping Based on Physical Interfaces: Traffic shaping parameters (such as Committed Information Rate (CIR) and Peak Information Rate (PIR)) are configured individually on each physical member port of the link aggregation group. Traffic control is achieved by limiting the transmission rate of a single physical interface. The drawbacks of this method are: the shaping parameters of each physical interface within the aggregation group are difficult to coordinate, which may result in the total bandwidth failing to reach the theoretical bandwidth of the aggregation interface (e.g., when each physical interface is shaped individually, the total rate may be far lower than the total bandwidth limit of the aggregation group); when a physical interface within the aggregation group fails and switches over, the shaping state of the original interface cannot be smoothly migrated to the backup interface, easily causing traffic bursts or interruptions; and it is impossible to globally control the overall traffic characteristics of the aggregation interface (such as total bandwidth requirements and service priority distribution), making it difficult to meet the QoS requirements of complex service scenarios.

[0005] Method 2: Overall Traffic Shaping Based on Aggregation Interfaces: This method configures unified traffic shaping parameters at the logical aggregation interface level to rate-limit the total traffic entering the aggregation interface. Then, a load balancing algorithm distributes the shaped traffic to each physical member port. While this method ensures the overall rate of the aggregation interface is controllable, it has the following drawbacks: It ignores the actual carrying capacity differences of each physical member port (e.g., some physical interfaces may have a lower actual carrying rate than the average allocated rate due to hardware performance, link quality, etc.), leading to overload of some physical interfaces and increased packet loss or latency; the load balancing algorithm and traffic shaping strategy lack coordination, and the shaped traffic distribution may disrupt the original load balancing mechanism, resulting in uneven traffic distribution among physical interfaces and reduced link utilization; and it is difficult to implement differentiated shaping control within the aggregation group for different service flows (e.g., high-priority real-time services and low-priority ordinary data services), failing to meet the fine-grained QoS requirements of services.

[0006] In summary, existing link aggregation interface traffic shaping methods suffer from low bandwidth utilization, insufficient QoS guarantee capabilities, and poor adaptability, failing to meet the demands for efficient, flexible, and refined traffic management of link aggregation interfaces in modern complex network environments.

[0007] There is currently no effective solution to the problem that existing technologies suffer from low bandwidth utilization, insufficient QoS guarantee capabilities, and poor adaptability, which makes it impossible to meet the needs of efficient, flexible, and refined traffic control for link aggregation interfaces in modern complex network environments. Summary of the Invention

[0008] To address the aforementioned technical problems, embodiments of the present invention aim to provide a switching chip that at least solves the problems of low bandwidth utilization, insufficient QoS guarantee capabilities, and poor adaptability in the prior art, which in turn fail to meet the demands for efficient, flexible, and refined traffic control of link aggregation interfaces in modern complex network environments.

[0009] The technical solution of this invention is implemented as follows:

[0010] This invention provides a switching chip, comprising: a service access interface, a loopback interface, and a link aggregation interface. The service access interface is connected to the input of the loopback interface via a bus, and is used to receive raw traffic and direct it to the loopback interface. The output of the loopback interface is connected to the input of the link aggregation interface, and is used to shape the raw traffic using pre-configured shaping parameters, and transmit the shaped raw traffic to the link aggregation interface through a pre-binding relationship. The output of the link aggregation interface is connected to an external network, and is used to transmit the shaped raw traffic to the external network through a preset mechanism.

[0011] Optionally, the loopback interface is also used to load a preset configuration via the CPU before the service access interface receives the raw traffic. The preset configuration includes: configuring the logical interface identifier of the loopback interface and setting a binding relationship with the link aggregation interface based on the identifier; configuring integer parameters, including: committed information rate, peak information rate and priority adaptation strategy.

[0012] Furthermore, optionally, the loopback interface also includes: a loopback interface software module, an integer parameter configuration module, and a storage module. The loopback interface software module is used to create a logical interface identifier in the CPU, configure a maximum transmission unit consistent with the link aggregation interface, and disable physical layer verification. The integer parameter configuration module is used to receive input integer parameters and write the integer parameters to the storage module.

[0013] Optionally, the link aggregation interface includes: a link aggregation software module, which is used to start the LACP protocol, configure the identifiers of all member ports, bind the logical interface identifiers to the identifiers of all member ports, and configure the load balancing algorithm.

[0014] Optionally, the service access interface is also used to allow raw traffic to enter the device through the service access interface and be directed to the input end of the loopback interface via internal routing or forwarding rules.

[0015] Furthermore, optionally, the loopback interface is also used to determine the priority of multi-priority packets by using the packet header identifier of the multi-priority packets according to the priority adaptation strategy in the pre-configured shaping parameters when the original traffic includes multi-priority packets; to perform rate limiting based on the priority of the multi-priority packets using the committed information rate and peak information rate in the pre-configured shaping parameters, thereby obtaining rate-limited multi-priority packets; and to transmit the rate-limited multi-priority packets to the link aggregation interface.

[0016] Furthermore, optionally, the loopback interface is also used to transmit multi-priority packets to the link aggregation interface when the traffic rate of multi-priority packets is less than or equal to the committed information rate; to cache and forward multi-priority packets using P-bucket tokens when the traffic rate is greater than the committed information rate and less than or equal to the peak information rate; and to mark multi-priority packets with a traffic rate greater than the peak information rate as discarded when the traffic rate is greater than the peak information rate.

[0017] Optionally, the link aggregation interface is also used to receive rate-limited multi-priority packets, distribute the rate-limited multi-priority packets evenly to each member port through a load balancing algorithm, and send the rate-limited multi-priority packets to the external network through each member port.

[0018] Furthermore, optionally, the link aggregation interface is also used to automatically switch the traffic carried by the failed member port to the normal member port when a member port fails. During the switching process, the traffic characteristics of the normal member port remain consistent with the output of the loopback interface, where the traffic characteristics include: rate and priority.

[0019] This invention provides a switching chip where a service access interface is connected to the input of a loopback interface via a bus to receive raw traffic and direct it to the loopback interface. The output of the loopback interface is connected to the input of a link aggregation interface to shape the raw traffic using pre-configured shaping parameters and transmit the shaped traffic to the link aggregation interface via a pre-binding relationship. The output of the link aggregation interface is connected to an external network to transmit the shaped raw traffic to the external network via a preset mechanism. This achieves the technical effect of meeting the needs of efficient, flexible, and refined traffic control for link aggregation interfaces in modern complex network environments. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0021] Figure 1 A schematic diagram of a switching chip provided in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of a system architecture in a switching chip provided by an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of the software execution flow in a switching chip provided by an embodiment of the present invention;

[0024] Figure 4 This is a flowchart illustrating a link aggregation interface traffic shaping method based on a loopback interface, provided in an embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish different objects, rather than to limit a specific order.

[0027] It should also be noted that the various embodiments of the present invention described below can be executed individually or in combination with each other, and the embodiments of the present invention do not impose specific limitations in this regard.

[0028] This invention provides a switching chip. Figure 1 A schematic diagram of a switching chip provided in an embodiment of the present invention; as shown. Figure 1 As shown, the switching chip provided in this embodiment includes:

[0029] The system includes a service access interface 12, a loopback interface 14, and a link aggregation interface 16. The service access interface 12 is connected to the input of the loopback interface 14 via a bus to receive raw traffic and direct it to the loopback interface 14. The output of the loopback interface 14 is connected to the input of the link aggregation interface 16 to shape the raw traffic using pre-configured shaping parameters and transmit the shaped raw traffic to the link aggregation interface 16 through a pre-binding relationship. The output of the link aggregation interface 16 is connected to an external network to transmit the shaped raw traffic to the external network through a preset mechanism.

[0030] Optionally, the loopback interface 14 is also used to load a preset configuration via the CPU before the service access interface 12 receives the original traffic. The preset configuration includes: configuring the logical interface identifier of the loopback interface 14 and setting a binding relationship with the link aggregation interface 16 based on the identifier; configuring shaping parameters, including: committed information rate, peak information rate and priority adaptation strategy.

[0031] Furthermore, optionally, the loopback interface 14 also includes: a loopback interface software module, a shaping parameter configuration module, and a storage module. The loopback interface software module is used to create a logical interface identifier in the CPU, configure a maximum transmission unit consistent with the link aggregation interface 16, and disable physical layer verification. The shaping parameter configuration module is used to receive input shaping parameters and write the shaping parameters to the storage module.

[0032] Optionally, the link aggregation interface 16 includes: a link aggregation software module, wherein the link aggregation software module is used to start the LACP protocol, configure the identifiers of all member ports, bind the logical interface identifiers to the identifiers of all member ports, and configure the load balancing algorithm.

[0033] Optionally, the service access interface 12 is also used to direct raw traffic into the device through the service access interface 12 and to the input end of the loopback interface 14 via internal routing or forwarding rules.

[0034] Furthermore, optionally, the loopback interface 14 is also used to determine the priority of the multi-priority packets by using the packet header identifier of the multi-priority packets according to the priority adaptation strategy in the pre-configured shaping parameters when the original traffic includes multi-priority packets; to perform rate limiting based on the priority of the multi-priority packets by using the committed information rate and peak information rate in the pre-configured shaping parameters to obtain rate-limited multi-priority packets; and to transmit the rate-limited multi-priority packets to the link aggregation interface 16.

[0035] Furthermore, optionally, the loopback interface 14 is also used to transmit the multi-priority message to the link aggregation interface 16 when the traffic rate of the multi-priority message is less than or equal to the committed information rate; to buffer and forward the multi-priority message using a P-bucket token when the traffic rate is greater than the committed information rate and less than or equal to the peak information rate; and to mark the multi-priority message with a traffic rate greater than the peak information rate as discarded when the traffic rate is greater than the peak information rate.

[0036] Optionally, the link aggregation interface 16 is also used to receive rate-limited multi-priority packets, distribute the rate-limited multi-priority packets evenly to each member port through a load balancing algorithm, and send the rate-limited multi-priority packets to the external network through each member port.

[0037] Furthermore, optionally, the link aggregation interface 16 is also used to automatically switch the traffic carried by the failed member port to the normal member port when a member port fails. During the switching process, the traffic characteristics of the normal member port are kept consistent with the output of the loopback interface 14, wherein the traffic characteristics include: rate and priority.

[0038] Specifically, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a system architecture in a switching chip provided by an embodiment of the present invention; the switching chip provided in this application embodiment includes: a service access interface ( Figure 2 Marked as 1), loopback interface ( Figure 2 Marked as 2) and link aggregation interface ( Figure 2 (marked as 3), where the link aggregation interface is in Figure 2 The example includes member port 1 and member port 2;

[0039] In this embodiment, the service access interface 12 can be a physical Ethernet interface (such as GE0 / 0 / 1) for receiving external raw traffic and is connected to the input of the loopback interface 14 (logical interface) via an internal bus (hardware connection). The output of the service access interface 12 is connected to the input of the loopback interface 14 via an internal forwarding channel (i.e., internal bus), and the raw traffic is directed into the loopback interface 14 via the internal forwarding channel.

[0040] In this embodiment, the loopback interface 14 is configured in software and presented as a logical interface. That is, it is a virtual interface (identified as Loopback1) configured in the CPU of the switching chip provided in this embodiment. The output of the loopback interface 14 is bound to the input of the link aggregation interface 16 through an internal forwarding channel (a software-mapped memory address link) to perform traffic shaping. The output of the loopback interface 14 is directly associated with the input of the link aggregation interface 16 through the internal loopback channel. The shaped traffic is injected into the link aggregation interface 16 through this channel.

[0041] In this embodiment, the interface attribute configuration of loopback interface 14 is as follows:

[0042] Configure a unique identifier (i.e., the logical interface identifier in this embodiment, such as Loopback1) to form a fixed binding relationship with the target link aggregation interface 16 (such as Eth-Trunk1) to ensure the directed flow of traffic;

[0043] Disable physical layer checks (such as Cyclic Redundancy Check, CRC, and inter-frame check) on loopback interface 14 to reduce additional processing latency and avoid affecting traffic shaping accuracy.

[0044] The MTU (Maximum Transmission Unit) of loopback interface 14 is consistent with that of link aggregation interface 16 to prevent packets from being fragmented during loopback.

[0045] In this embodiment, the flow shaping parameters of the loopback interface 14 are configured as follows:

[0046] Configure the following shaping parameters independently in the outgoing direction of loopback interface 14 (i.e., the direction pointing to link aggregation interface 16) to achieve global control over the total traffic of link aggregation interface 16:

[0047] Basic rate limit: Configure Committed Information Rate (CIR) and Peak Information Rate (PIR). CIR is the long-term stable rate allowed by the link aggregation interface 16 (e.g., 8Gbps), and PIR is the maximum rate that can burst in the short term (e.g., 10Gbps). Together, they constrain the total traffic limit of the link aggregation interface 16.

[0048] Service priority adaptation: Based on the priority marking of the message (such as Differentiated Services Code Point (DSCP) or 802.1p), different rate quotas are configured for different service flows. For example, high-priority services (such as voice) can occupy 60% of CIR, while low-priority services (such as file transfer) can occupy the remaining 40%, and high-priority services can use the burst bandwidth of PIR first.

[0049] In this embodiment, the link aggregation interface 16 is configured based on physical ports and software through a combination of hardware and software. The link aggregation interface 16 consists of multiple physical member ports (such as GE0 / 0 / 2, GE0 / 0 / 3 hardware), which are bound to the logical interface Eth-Trunk1 through the link aggregation protocol (at the software level). That is, the logical interface Eth-Trunk1 of the link aggregation interface 16 is bound to the loopback interface 14, which is identified as Loopback1. The physical interface is connected to the external network (e.g., peer devices and servers) through the backplane bus (hardware) to realize the final forwarding of traffic.

[0050] It should be noted that the switching chip provided in this application embodiment is described using the link aggregation interface 16 including member port 1 and member port 2 as an example, in order to implement the switching chip provided in this application embodiment, and is not specifically limited.

[0051] The switching chip provided in this application provides a separate loopback interface 14 at the front end of the link aggregation interface 16, which concentrates the traffic shaping function in the outgoing direction of the loopback interface 14. The loopback interface 14 and the link aggregation interface 16 form a fixed binding relationship, and the shaped traffic is injected into the link aggregation interface 16 through the internal loopback channel.

[0052] like Figure 3 As shown, Figure 3 This is a schematic diagram of the software execution flow in a switching chip according to an embodiment of the present invention. The switching chip provided in this application implements traffic shaping in four stages: loopback interface 14 initialization, traffic access, traffic shaping processing, and link aggregation forwarding, as detailed below:

[0053] Phase 1: Initialization, which includes initializing the service access interface 12, loopback interface 14, and link aggregation interface 16; details are as follows:

[0054] 1. Hardware initialization (after the device is powered on)

[0055] Service access interface 12 (GE0 / 0 / 1) and link aggregation management member ports (GE0 / 0 / 2-3) complete self-tests through hardware drivers.

[0056] The storage module loads the preset configuration: the binding relationship between Loopback1 of Loopback interface 14 and Eth-Trunk1 of Link Aggregation interface 16, the rate (1Gbps) of physical member ports, and the duplex mode (full duplex).

[0057] 2. Software configuration (configured by the administrator via CLI)

[0058] For loopback interface 14:

[0059] Loopback Interface 14 Software Module: Create a logical interface Loopback1 in the CPU, configure MTU=1500 (consistent with the physical interface), and disable physical layer verification.

[0060] The shaping parameter configuration module receives the CIR and PIR configurations and priority mapping rules (i.e., the priority adaptation strategy in this application embodiment) input by the administrator and writes the parameters into the storage module.

[0061] For link aggregation interface 16:

[0062] Link aggregation software module: Start the LACP protocol, bind member ports to Eth-Trunk1, and configure the load balancing algorithm.

[0063] Phase Two: Traffic Access and Targeting

[0064] The original service traffic (i.e., the original traffic in this embodiment, including multi-priority packets) enters the device through the service access interface 12 and is directed to the input end of the loopback interface 14 by internal routing or forwarding rules.

[0065] Phase 3: Loopback Interface 14 Traffic Shaping

[0066] Loopback interface 14 performs independent shaping operations on the input traffic:

[0067] Message classification: Traffic is classified according to preset priority rules (such as the DSCP value in the message header) to distinguish between high, medium and low priority service flows (that is, in this embodiment, the priority of multi-priority messages is determined by the message header identifier of multi-priority messages according to the priority adaptation strategy in the pre-configured shaping parameters).

[0068] Rate control: Each type of service flow is rate-limited through a corresponding token bucket—when the traffic rate does not exceed the CIR, it passes directly; when it exceeds the CIR but does not exceed the PIR, it is buffered and forwarded using the P-bucket token; when it exceeds the PIR, the excess packets are marked as "dropped" (i.e., in this embodiment, when the traffic rate of a multi-priority packet is less than or equal to the committed information rate, the multi-priority packet is transmitted to the link aggregation interface 16; when the traffic rate is greater than the committed information rate and less than or equal to the peak information rate, the multi-priority packet is buffered and forwarded using the P-bucket token; when the traffic rate is greater than the peak information rate, the multi-priority packet with a traffic rate greater than the peak information rate is marked as dropped).

[0069] Post-reshaping aggregation: Various service flows that have undergone rate control are re-merged into a unified traffic flow and output to the link aggregation interface 16 through the loopback channel.

[0070] It should be noted that, in this embodiment, the independent shaping function of the loopback interface 14 is achieved through the configuration of the loopback interface 14. That is, the traffic shaping function is centralized in the loopback interface 14, decoupling it from the load balancing and redundancy functions of the link aggregation interface 16, simplifying the configuration logic; end-to-end traffic control is achieved by “pre-shaping” the total traffic of the link aggregation interface 16 through the loopback interface 14, ensuring that the traffic entering the aggregation interface meets the rate requirements and avoiding shaping conflicts between physical interfaces; and compatibility design is achieved, the introduction of the loopback interface 14 does not change the original load balancing and fault switching mechanism of the link aggregation interface 16, and it can be adapted to existing mainstream link aggregation protocols (such as LACP) and device models.

[0071] Phase 4: Link Aggregation Interface 16 Forwarding

[0072] Link aggregation interface 16 receives the shaped traffic output from loopback interface 14 and forwards it using its inherent mechanism:

[0073] Load balancing distribution: Based on the original load balancing algorithm of link aggregation interface 16 (such as based on source / destination IP and MAC address), the shaped traffic is evenly distributed to each physical member port;

[0074] Fault redundancy handling: When a physical member port fails, the link aggregation interface 16 automatically switches the traffic carried by that interface to other normal interfaces. During the switching process, the traffic characteristics (rate, priority) remain consistent with the output of the loopback interface 14.

[0075] Final transmission: Traffic is sent to the external network via the physical member port, completing the entire forwarding process.

[0076] The switching chip provided in this application embodiment can achieve precise control over the traffic of the link aggregation interface 16, while retaining the original advantages of bandwidth superposition and redundancy backup of link aggregation, thus solving the problems of low bandwidth utilization and insufficient QoS guarantee in the prior art.

[0077] The switching chip provided in this application embodiment accurately shapes the overall traffic of the link aggregation interface 16, ensuring that the total traffic of the aggregation interface meets the preset rate limits (such as CIR, PIR), while avoiding the problem that the total bandwidth cannot reach the theoretical upper limit of the aggregation interface due to independent shaping of each physical member port. It coordinates the traffic shaping strategy with the load balancing mechanism of the link aggregation, enabling the shaped traffic to be reasonably allocated according to the actual carrying capacity of each physical member port, avoiding overload or bandwidth waste of some physical interfaces, and improving the overall resource utilization of the aggregation group. It supports differentiated traffic shaping for different priority service flows carried by the link aggregation interface 16, meeting the QoS requirements of various services (such as low latency and low jitter), and ensuring that high-priority services are given priority protection during traffic management. When a physical interface within the link aggregation group experiences a failover, it ensures a smooth transition of the traffic shaping state, avoiding traffic bursts or interruptions caused by interface switching, and enhancing network stability and reliability. Furthermore, the architecture design of loopback interface 14 simplifies the configuration and management of traffic shaping, enabling the shaping strategy to focus on the traffic characteristics of aggregated interfaces at the logical level, and reducing the management complexity caused by changes in the number of physical interfaces or differences in configuration.

[0078] The switching chip provided in this application embodiment achieves traffic shaping by introducing a loopback interface 14 at the front end of the link aggregation interface 16, which has the following significant advantages compared to the prior art:

[0079] Effect 1: Improves the overall bandwidth utilization of link aggregation interface 16, resolving the issue that the total bandwidth cannot reach the theoretical upper limit of the aggregation interface due to the existing independent shaping based on physical interfaces. By pre-shaping the overall traffic of the aggregation interface through loopback interface 14, it ensures that the total traffic can fully utilize the superimposed bandwidth of each physical member port (e.g., after aggregating 4 1Gbps physical interfaces, the total rate can stably reach 4Gbps), improving bandwidth utilization by more than 30%.

[0080] Effect 2. Enhanced QoS guarantee capability. The switching chip provided in this application supports differentiated shaping based on service priority. It allocates dedicated bandwidth quotas to high-priority services (such as voice and real-time video) through a multi-token bucket mechanism, ensuring that their packet loss rate is less than 0.1% and latency jitter is less than 10ms, thus solving the defect of existing "overall shaping" that cannot distinguish service priority.

[0081] Effect 3. Optimize traffic stability during failover. When a physical member port failsover occurs, the traffic rate and priority status can remain continuous because the shaping logic is concentrated on loopback interface 14. This avoids the traffic bursts or interruptions caused by state transitions in the traditional "physical interface independent shaping". The traffic fluctuation during failover is reduced to less than 5%.

[0082] Effect 4. Reduced configuration complexity and operation and maintenance costs. The switching chip provided in this application embodiment is fixed through the binding relationship between the loopback interface 14 and the link aggregation interface 16. The administrator only needs to configure a set of shaping parameters (such as CIR, PIR) on the loopback interface 14 to achieve global control of the aggregation interface. There is no need to configure each physical member port separately. The configuration steps are reduced by 60%, and parameter coordination conflicts are avoided.

[0083] This invention provides a switching chip where a service access interface is connected to the input of a loopback interface via a bus to receive raw traffic and direct it to the loopback interface. The output of the loopback interface is connected to the input of a link aggregation interface to shape the raw traffic using pre-configured shaping parameters and transmit the shaped traffic to the link aggregation interface via a pre-binding relationship. The output of the link aggregation interface is connected to an external network to transmit the shaped raw traffic to the external network via a preset mechanism. This achieves the technical effect of meeting the needs of efficient, flexible, and refined traffic control for link aggregation interfaces in modern complex network environments.

[0084] This invention provides a method for shaping link aggregation interface traffic based on a loopback interface. Figure 4 This is a flowchart illustrating a link aggregation interface traffic shaping method based on a loopback interface, provided by an embodiment of the present invention; as follows: Figure 4 As shown, applied to Figure 1 The loopback interface in the switching chip, and the link aggregation interface traffic shaping method based on the loopback interface provided in this application embodiment include:

[0085] Before the service access interface receives the raw traffic, the loopback interface loads a preset configuration via the CPU. The preset configuration includes: configuring the logical interface identifier of the loopback interface and setting a binding relationship with the link aggregation interface based on the identifier; configuring integer parameters, which include: committed information rate, peak information rate and priority adaptation strategy.

[0086] Step S402: Receive the raw traffic directed into the service access interface;

[0087] Step S404: The raw traffic is shaped using pre-configured shaping parameters to obtain the shaped raw traffic.

[0088] When the original traffic includes multi-priority packets, the priority of the multi-priority packets is determined by the priority adaptation strategy based on the packet header identifier of the multi-priority packets; the rate is limited based on the priority of the multi-priority packets by the committed information rate and the peak information rate, resulting in rate-limited multi-priority packets.

[0089] Specifically, when the traffic rate of a multi-priority message is less than or equal to the committed information rate, the multi-priority message is transmitted to the link aggregation interface; when the traffic rate is greater than the committed information rate and less than or equal to the peak information rate, the multi-priority message is cached and forwarded using a P-bucket token; when the traffic rate is greater than the peak information rate, the multi-priority message with a traffic rate greater than the peak information rate is marked as discarded.

[0090] Step S406: Transmit the shaped raw traffic to the link aggregation interface through the pre-binding relationship;

[0091] Specifically, based on the rate-limited multi-priority packets obtained in step S404, the packets of various priorities are merged back into a unified traffic flow and output to the link aggregation interface through the loopback channel.

[0092] This invention provides a method for shaping traffic on a link aggregation interface based on a loopback interface. The method receives raw traffic directed from a service access interface; shapes the raw traffic using pre-configured shaping parameters to obtain shaped raw traffic; and transmits the shaped raw traffic to the link aggregation interface through a pre-binding relationship. This achieves the technical effect of meeting the needs of efficient, flexible, and refined traffic control for link aggregation interfaces in modern complex network environments.

[0093] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention.

Claims

1. A switch chip, characterized by The application relates to a switching chip, which comprises a service access interface, a loopback interface and a link aggregation interface, wherein, the service access interface is connected with the input end of the loopback interface through a bus and is used for receiving original traffic and directing the original traffic into the loopback interface; the output end of the loopback interface is connected with the input end of the link aggregation interface and is used for performing traffic shaping on the original traffic through preconfigured shaping parameters and transmitting the shaped original traffic to the link aggregation interface through a prebinding relationship; the output end of the link aggregation interface is connected with an external network and is used for transmitting the shaped original traffic to the external network through a preset mechanism; the loopback interface is further used for transmitting multi-priority packets to the link aggregation interface when the traffic rate of the multi-priority packets is less than or equal to a committed information rate; when the traffic rate is greater than the committed information rate and less than or equal to a peak information rate, the multi-priority packets are buffered and forwarded through P bucket tokens; when the traffic rate is greater than the peak information rate, the multi-priority packets with the traffic rate greater than the peak information rate are marked as discarded; the link aggregation interface is further used for automatically switching the traffic borne by a faulty member port to a member port in a normal state when the member port is faulty, and the traffic characteristics of the member port in the normal state remain consistent with the output of the loopback interface during the switching process, wherein the traffic characteristics include rate and priority.

2. The switching chip according to claim 1, wherein, the loopback interface is further used for loading a preset configuration through a CPU before the service access interface receives the original traffic, wherein the preset configuration comprises configuring a logical interface identifier of the loopback interface, setting a binding relationship with the link aggregation interface according to the identifier and configuring shaping parameters, wherein the shaping parameters comprise a committed information rate, a peak information rate and a priority adaptation strategy. the loopback interface further comprises a loopback interface software module, a shaping parameter configuration module and a storage module, wherein, 3. The switch chip of claim 2, wherein, the loopback interface software module is used for creating the logical interface identifier in the CPU, configuring a maximum transmission unit consistent with the link aggregation interface and closing a physical layer check; the shaping parameter configuration module is used for receiving the input shaping parameters and writing the shaping parameters into the storage module. the link aggregation interface comprises a link aggregation software module, wherein, 4. The switch chip of claim 3, wherein, the link aggregation software module is used for starting an LACP protocol, configuring identifiers of all member ports, binding the logical interface identifier with the identifiers of all the member ports and configuring a load balancing algorithm.

5. The switching chip according to claim 1 or 4, wherein, the service access interface is further used for entering the original traffic into a device through the service access interface, directing the original traffic to the input end of the loopback interface through internal routing or forwarding rules.

6. The switching chip according to claim 5, wherein, ​ The loopback interface is further configured to, in a case where the original traffic comprises a multi-priority packet, identify a priority of the multi-priority packet according to a priority adaptation strategy in the preconfigured shaping parameter through a packet header of the multi-priority packet; limit a rate of the multi-priority packet through a committed information rate and a peak information rate in the preconfigured shaping parameter according to the priority of the multi-priority packet to obtain the multi-priority packet after rate limiting; and transmit the multi-priority packet after rate limiting to the link aggregation interface.

7. The switch chip of claim 6, wherein, the link aggregation interface is further configured to receive the multi-priority packet after rate limiting, uniformly distribute the multi-priority packet after rate limiting to each member port through a load balancing algorithm, and send the multi-priority packet after rate limiting to the external network through the each member port.

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