Bump electroplating method
By using pulse control signals to control the peak and trough times during the electroplating process, the coplanarity problem in the manufacturing of copper pillar bumps was solved, and the coplanarity of copper pillar bumps was improved without reducing the electroplating rate, thereby increasing production efficiency.
Patent Information
- Application Number
- CN202410980780.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-19
- Publication Date
- 2026-01-20
AI Technical Summary
In the existing technology for manufacturing copper pillar bumps, different sizes of openings cause differences in the height of the copper pillar bumps, affecting coplanarity. Furthermore, reducing the electroplating rate to improve coplanarity leads to a decrease in production efficiency.
The current density is controlled during the electroplating process using a pulse control signal, with the peak duration being longer than the trough duration. This ensures that the electroplating solution has time to be renewed in a small opening. The coplanarity of the copper pillar bumps is improved by using the pulse current density signal without reducing the electroplating rate.
Without affecting the electroplating rate, the height difference between copper pillar bumps is reduced, coplanarity is improved, and production efficiency is increased.
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Figure CN121363025A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, and in particular to a bump plating method. Background Technology
[0002] Copper pillar bump technology is a next-generation chip interconnect technology commonly used in integrated circuit packaging processes to connect chips (dies) to substrates. Benefiting from the properties of copper, copper pillar bumps offer superior conductivity, thermal performance, and reliability. The manufacturing process of copper pillar bumps requires a close integration of photolithography and electroplating processes. In general, thick-film photolithography is first used to obtain a mask for the copper pillar bump pattern, forming the opening to be filled. Then, electroplating is used to fill the opening with metallic copper, resulting in a copper pillar bump of a certain height.
[0003] like Figure 1 As shown, Figure 1 A top view of an exemplary wafer is shown. Multiple chips 1000 are formed on wafer 100, which are then connected to a substrate or other packaging structure in subsequent packaging processes. With the development of semiconductor packaging technology, copper pillar bumping technology faces new challenges. Due to the integration of different types of chips and the different functions of different I / O signal pins within the same chip, copper pillar bumps of different sizes are required within each chip 1000. Correspondingly, in the manufacturing process of copper pillar bumps, forming copper pillar bumps of different sizes requires filling openings of different sizes with metallic copper, which places increasingly higher demands on electroplating equipment and processes. Because the electroplating rates differ in openings of different sizes, this results in height differences in the copper pillar bumps formed in openings of different sizes. Furthermore, as the electroplating rate increases and the current density increases, this height difference becomes more significant, causing the coplanarity of the copper pillar bumps to fail to meet process requirements, affecting subsequent soldering processes. To improve the coplanarity of the copper pillar bumps, it is usually necessary to reduce the electroplating current density and slow down the electroplating rate, leading to reduced production efficiency.
[0004] Therefore, how to provide a bump plating method that improves the coplanarity of copper pillar bumps without affecting the plating rate has become a technical problem that needs to be solved. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a bump electroplating method that improves the coplanarity of bumps without affecting the electroplating rate.
[0006] To achieve the above object and other related objects, one aspect of the present application provides a bump plating method, comprising: placing a wafer in a plating device, the wafer having a plurality of openings; providing a pulse control signal to the plating device to control the plating device to plating in the openings to form bumps, in one pulse cycle, a peak duration t1 is greater than a valley duration t2, and both the peak duration t1 and the valley duration t2 are greater than 1 second.
[0007] In some embodiments, the pulse control signal is a pulse current density signal, and a peak value of the pulse current density signal is 10-50 ASD.
[0008] In some embodiments, the peak value of the pulse current density signal is 20-50 ASD.
[0009] In some embodiments, the peak value of the pulse current density signal is 20-40 ASD.
[0010] In some embodiments, a valley value of the pulse current density signal is 0-5 ASD.
[0011] In some embodiments, the peak duration t1 ranges from 1 second < t1 ≤ 4 seconds, and the valley duration t2 ranges from 1 second < t2 ≤ 2 seconds.
[0012] In some embodiments, the peak duration t1 is 3 ± 3*20% seconds, and the valley duration t2 is 1.5 ± 1.5*20% seconds.
[0013] In some embodiments, the peak duration t1 is 4 ± 4*20% seconds, and the valley duration t2 is 2 ± 2*20% seconds.
[0014] In some embodiments, the pulse current density signal has a plurality of peak values, and the plurality of peak values gradually increase from front to back.
[0015] In some embodiments, the bump comprises a copper pillar bump.
[0016] As described above, the present application provides a bump plating method. By providing a pulse control signal to the plating device, the plating solution in the openings with smaller sizes can have time to update and recover in the valley duration t2 during the plating process, which can make up for the difference in mass transfer efficiency of the plating solution between the openings with smaller sizes and the openings with larger sizes, thereby reducing the height difference between different bumps on the same chip. In other words, by using the bump plating method of the present application, the plating rate can be improved without deteriorating the coplanarity (COP) of the bumps. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 shows a top view schematic diagram of an exemplary wafer;
[0018] Figures 2a to 2f shows an exemplary flow chart of fabricating copper pillar bumps;
[0019] Figure 3 shows a flow chart of the bump plating method of the present application;
[0020] Figure 4 shows a schematic diagram of an exemplary plating apparatus;
[0021] Figure 5 shows a waveform diagram of the pulse control signal of Embodiment 1 of the present application;
[0022] Figure 6 shows a waveform diagram of the pulse control signal of Embodiment 2 of the present application; and
[0023] Figure 7 shows a waveform diagram of the pulse control signal of other embodiments of the present application. DETAILED DESCRIPTION
[0024] The forgoing detailed description of the application has been presented for the purposes of elucidation and will not limit the application as construed. It is intended that the description of the application as set forth above be regarded as illustrative and not in a limiting sense, and that various modifications and alterations to the illustrative embodiments of the application will be apparent to persons of skill in the art from the teaching of the present application contained herein. Thus, it should be appreciated that there is no intention to limit the application to the specific embodiments described herein, but rather the intention is to cover all modifications and alternatives coming within the spirit and scope of the application as defined by the appended claims.
[0025] It is also noted that the figures may not be drawn to scale, and that elements of one figure can be used with elements of another figure. It is intended that all such modifications and alterations come within the spirit and scope of the present application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.
[0026] The following description relates to the drawings, in which the same numbers represent the same or similar elements. The implementations described in the following example embodiments are not meant to represent all implementations in which one can practice the present application. On the contrary, they are meant to represent a number of example embodiments in which the present application can be practiced.
[0027] The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the description of the application and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It also should be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
[0028] In the description of the present application, unless otherwise specified and limited, it is necessary to explain that the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be mechanical connection or electrical connection, it can be the communication inside two elements, it can be direct connection or indirect connection through intermediate medium, and the specific meaning of the above terms can be understood by the person skilled in the art according to the specific circumstances.
[0029] It should be understood that although the terms first, second, third, etc. can be used in this application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
[0030] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.
[0031] The flow of manufacturing copper pillar bump is described exemplarily as follows, Figures 2a to 2f The flow of manufacturing copper pillar bump is described exemplarily as follows, Figures 2a to 2f is an exemplary flow chart of manufacturing copper pillar bump. First, step one, as shown in Figure 2a , a wafer 100 is provided, which has a plurality of metal pads 101, such as aluminum pads, on the wafer 100. In addition, the copper pillar bump packaging structure will cause a large structural stress to the wafer 100, so before manufacturing the copper pillar bump, a layer of PI (Polyimide) film is usually grown on the surface of the wafer 100 to reduce the stress of the wafer 100. Step two, as shown in Figure 2bUBM (Underbump metallurgy) is deposited on the wafer 100 by sputtering or other physical vapor deposition. The UBM includes a barrier layer and a seed layer. The barrier layer is below the seed layer, usually Ti or TiW. The seed layer is above the barrier layer, usually copper or other metal. The barrier layer prevents the mutual diffusion of the metal pad 101 and the seed layer metal, while forming a good bonding force with the metal pad 101 and the seed layer. Step three, as shown in Figure 2c The photoresist 102 is coated on the wafer 100 by rotation coating to a certain thickness. After pre-baking, exposure and development, the pattern to be electroplated is formed. Step four, as shown in Figure 2d The copper pillar bump 104 is filled with copper in the opening 103 by electroplating. Step five, as shown in Figure 2e The solder 105 is deposited on the top of the copper pillar bump 104. Finally, step six, as shown in Figure 2f The subsequent processes such as photoresist stripping, UBM etching and reflow soldering are performed to form a complete copper pillar bump packaging structure. It should be understood that the above process is only exemplary. The copper pillar bump includes various types, for example, some types of copper pillar bump do not need to deposit solder.
[0032] In combination with Figure 2c and Figure 2d , in this example, two different sizes of openings 103 formed on the wafer 100 are shown, denoted as opening 103a and opening 103b. Since the size of the opening 103b is larger than that of the opening 103a, the deposition rate of the copper pillar bump 104b in the opening 103b is greater than that of the copper pillar bump 104a in the opening 103a during the electroplating process, resulting in the height of the copper pillar bump 104b being greater than that of the copper pillar bump 104a, and further causing the height difference between different copper pillar bumps 104.
[0033] The COP (Coplanarity) value is usually used to represent the height difference between different copper pillar bumps 104 on the same die. The COP value is the difference between the maximum and minimum heights of the copper pillar bumps 104 on the same die. In order to improve the interconnection reliability of the die and the product yield, the COP value should be controlled within a reasonable range, as small as possible, i.e. the height difference between different copper pillar bumps 104 on the same die should be as small as possible. Generally speaking, the size of the COP value is positively correlated with the current density in the electroplating process, i.e. the greater the current density, the greater the COP value. Therefore, in order to meet the coplanarity index of the copper pillar bump 104, it is usually necessary to reduce the current density, which leads to a decrease in the electroplating rate, which greatly affects the production efficiency.
[0034] At least to solve the above problems, the application provides a bump plating method, which combines Figure 3 and Figure 4 wherein, Figure 3 a flow chart of the bump plating method is shown, Figure 4 a structural schematic diagram of an exemplary plating device is shown. The bump plating method comprises: placing a wafer 100 in the plating device 200, the wafer 100 has a plurality of openings 103 (see Figure 2c ); providing a pulse control signal to the plating device 200 to control the plating device 200 to plating in the openings 103 to form bumps (see Figure 2d copper pillar bumps 104 in Figure 4 ), in a pulse period, the peak duration t1 is greater than the valley duration t2, and both the peak duration t1 and the valley duration t2 are greater than 1 second (s). As , the plating device 200 comprises a plating tank 201 and a plating clamp 204, the plating tank 201 contains a plating solution 202 and an anode 203, the plating clamp 204 is connected to the negative pole of a power supply, the anode 203 is connected to the positive pole of the power supply, and the wafer 100 is clamped by the plating clamp 204 and placed in the plating tank 201 for plating. It should be understood that the anode 203 has various implementations, for example, it can be a single anode, a double anode or a multiple anode.
[0035] Figures 5 to 6 Figure 5 a waveform diagram of the pulse control signal of the first embodiment of the application is shown, Figure 6 a waveform diagram of the pulse control signal of the second embodiment of the application is shown. Specifically, in the first and second embodiments, the pulse control signal is a pulse current density signal, the waveform is a square wave, the duty cycle is 2 / 3, and the plated bump is a copper pillar bump 104 (see Figure 2d copper pillar bump 104 in Figure 5 ). In the first embodiment, the peak value is 30 ASD, the valley value is 0, and the equivalent current density is 20 ASD (as shown by the dashed line in Figure 6 , which is equivalent to a constant current density of 20 ASD); in the second embodiment, the peak value is 20 ASD, the valley value is 0, and the equivalent current density is 13 ASD (as shown by the dashed line in , which is equivalent to a constant current density of 13 ASD).
[0036] Optionally, in other embodiments, the peak value of the current density is between 10 and 50 ASD, preferably, considering that the peak value affects the plating rate, in some embodiments, the peak value of the current density is between 20 and 50 ASD. More preferably, considering that the plating solution can only withstand a limited current density, in some embodiments, the peak value of the current density is between 20 and 40 ASD. Optionally, in some embodiments, the pulse control signal can also be a pulse current signal, i.e., the waveform of the pulse control signal has a vertical coordinate of current size.
[0037] In combination Figure 2d In the plating process, the mass transfer efficiency of the plating solution in the openings 103 is different, the mass transfer efficiency of the plating solution in the smaller openings 103a is lower, and the mass transfer efficiency of the plating solution in the larger openings 103b is higher, resulting in different plating rates of the copper pillar bumps 104 in openings 103 of different sizes, and causing height differences between different copper pillar bumps 104 on the same chip. In some embodiments of the present application, by providing a pulse current density signal with a valley value of 0 to the plating device, the current density is 0 and the plating is temporarily interrupted during the valley duration t2, so that the plating solution in the smaller openings 103a has time to update and recover, which can make up for the difference in mass transfer efficiency of the plating solution in the smaller openings 103a and the larger openings 103b, and further reduce the height difference between different copper pillar bumps 104 on the same chip, and improve the coplanarity of the copper pillar bumps 104. And the equivalent current density can be improved by increasing the peak value or duty cycle of the pulse current density signal, thereby maintaining the plating rate. Therefore, the coplanarity of the copper pillar bumps 104 can be improved under the condition that the equivalent current density is the same (i.e., the plating rate is the same).
[0038] Optionally, in some embodiments, the mass transfer efficiency of the plating solution is high (e.g., the concentration of the plating solution is high, the temperature of the plating solution is high, etc.), and only intermittently reducing the current density is also sufficient to allow the plating solution in the smaller openings 103a to update and recover, so the valley value of the pulse current density signal can not be zero, but a smaller (relative to the peak value) current density close to 0, for example, the valley value of the pulse current density signal is 0-5 ASD.
[0039] Continuing to refer to Figures 5 to 6 In one pulse cycle, Figure 5 The peak duration t1 is 3 seconds, and the valley duration t2 is 1.5 seconds; Figure 6 The peak duration t1 is 4 seconds, and the valley duration t2 is 2 seconds. Under the experimental conditions shown in Table 1, a plurality of experiments were performed using the ECP ap device of ACM Research Company, and the experimental results shown in Table 2 were obtained.
[0040] Table 1
[0041]
[0042] Table 2
[0043]
[0044] Referring to Table 2, the first control group is plated using a constant current density of 20 ASD, the second control group and the first example are plated using a pulsed current density having a peak value of 30 ASD and a valley value of 0, and an equivalent current density of 20 ASD. In one pulse cycle, the peak duration tl of the pulsed current density in the second control group is 0.5 seconds, and the valley duration t2 is 0.25 seconds. In the first example, the peak duration tl of the pulsed current density is 3 seconds, and the valley duration t2 is 1.5 seconds. The third control group is plated using a constant current density of 13 ASD, and the second example is plated using a pulsed current density having a peak value of 20 ASD and a valley value of 0, and an equivalent current density of 13 ASD. In one pulse cycle, the peak duration tl of the pulsed current density in the second example is 4 seconds, and the valley duration t2 is 2 seconds. In addition, COP refers to the difference between the maximum value and the minimum value of the height of the copper pillar bump on the same chip, which reflects the coplanarity of the copper pillar bump on the same chip. The smaller the COP value, the better the coplanarity of the copper pillar bump on the same chip.
[0045] As can be seen from Table 2, in the case where the constant current density and the equivalent current density are the same, in the first example, the COP value of the copper pillar bump is 6.04 um, which is smaller than the COP value in the first control group and the second control group. That is, using the plating method in the first example, compared with the first control group and the second control group, in the case where the equivalent current density is the same (i.e., the plating rate is unchanged), a copper pillar bump with better coplanarity can be obtained. Similarly, in the second example, the COP value of the copper pillar bump is 1.64 um, and in the third control group, the COP value of the copper pillar bump is 3.49 um. Compared with the third control group, in the case where the plating rate is unchanged, using the second example, a copper pillar bump with better coplanarity can be obtained.
[0046] In addition, in the control group one, the control group two and the example one, the COP value of the control group one is the largest, which is 7.28 um, the COP value of the control group two is between the control group one and the example one, which is 7.02 um. It can be seen that the problem of poor co-planarity is more significant in the control group one which uses the conventional constant current density for electroplating. The co-planarity is improved to a certain extent in the control group two which uses the pulse current density for electroplating, but there is still a gap with the example one. This shows that only using the pulse current density cannot better improve the co-planarity of the copper pillar bumps on the same chip. The peak duration t1 and the valley duration t2 of the pulse current density signal also need to meet certain conditions. On the one hand, the valley duration t2 needs to be greater than 1 second, so that the electroplating solution in the opening with smaller size can have sufficient time to update and recover. On the other hand, the peak duration t1 needs to be greater than 1 second and greater than the valley duration t2, in order to maintain the equivalent current density and meet the requirement of the electroplating rate. In this way, the co-planarity of the copper pillar bumps can be improved without reducing the electroplating rate. In addition, since the co-planarity of the copper pillar bumps is strongly related to the electroplating rate, as the electroplating rate increases, the co-planarity of the copper pillar bumps will decrease. Therefore, without making the co-planarity of the copper pillar bumps worse, the electroplating rate can be improved by using the bump electroplating method of the present application.
[0047] It should be understood that the above example one and example two are only examples of the present application, and in some embodiments, the range of the peak duration t1 is 1 second < t1 < 4 seconds, and the range of the valley duration t2 is 1 second < t2 < 2 seconds. The values of t1 and t2 can be selected by the person skilled in the art according to the actual needs.
[0048] In some embodiments, the peak duration tl can be about 3 seconds and the valley duration t2 can be about 1.5 seconds. In other embodiments, the peak duration tl can be about 4 seconds and the valley duration t2 can be about 2 seconds. It should be understood that the modifier "about", "approximately", or "substantially" used to modify a number in this application indicates that the number allows for a ±20% variation. In other words, in some embodiments, the peak duration tl is 3 ± 3*20% seconds, e.g., 2.7 seconds, 2.9 seconds, 3.3 seconds, etc., and the valley duration t2 is 1.5 ± 1.5*20% seconds, e.g., 1.3 seconds, 1.6 seconds, 1.7 seconds, etc. In other embodiments, the peak duration tl is 4 ± 4*20% seconds, e.g., 3.6 seconds, 3.7 seconds, 4.4 seconds, etc., and the valley duration t2 is 2 ± 2*20% seconds, e.g., 1.8 seconds, 2.1 seconds, 2.2 seconds, etc. Accordingly, in some embodiments, the numerical parameters used in this application are approximations, and the numerical values can vary depending on the desired properties of the individual embodiments. In some embodiments, the numerical parameters should be considered in the context of the number of significant digits and errors inherent to measuring and calculating.
[0049] Optionally, as Figure 7 , Figure 7 Waveform diagrams of pulse control signals of other embodiments of the application are shown. In some embodiments, the pulse current density signal has a plurality of peak values that gradually increase from the first to the last. In these embodiments, during the electroplating process, the electroplating is first performed at a small current density, which on one hand allows the plating solution to have more time to diffuse in the small-sized openings, and on the other hand allows the seed layer to be repaired, thereby reducing the resistance of the seed layer, which can further improve the coplanarity of the copper pillar bumps. In addition, the gradually increasing current density can maintain the equivalent current density and meet the requirement of the plating rate.
[0050] It should be understood that in other possible embodiments, the bumps to be electroplated can also be bumps of other metals, such as gold bumps, etc.
[0051] The above-described embodiments are merely illustrative for the principles and effects of the application, and are not configured to limit the application. Any person skilled in the art can modify or adjust the above-described embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or adjustments made by those skilled in the art without departing from the spirit and technical thought of the application should be covered by the claims of the application.
Claims
1. A bump plating method characterized by, The method comprises: placing a wafer in an electroplating device, the wafer having a plurality of openings; providing a pulse control signal to the electroplating device to control the electroplating device to electroplate in the openings to form bumps, wherein a peak duration t1 is greater than a valley duration t2 in a pulse cycle, and both the peak duration t1 and the valley duration t2 are greater than 1 second.
2. The method of claim 1, wherein: the pulse control signal is a pulse current density signal, and a peak value of the pulse current density signal is 10-50 ASD.
3. The method of claim 2, wherein: the peak value of the pulse current density signal is 20-50 ASD.
4. The method of claim 2, wherein: the peak value of the pulse current density signal is 20-40 ASD.
5. The method of any one of claims 2-4, wherein: a valley value of the pulse current density signal is 0-5 ASD.
6. The method of claim 1, wherein: the peak duration t1 is in a range of 1 second < t1 < 4 seconds, and the valley duration t2 is in a range of 1 second < t2 < 2 seconds.
7. The method of claim 1, wherein: the peak duration t1 is 3 ± 3*20% seconds, and the valley duration t2 is 1.5 ± 1.5*20% seconds.
8. The method of claim 1, wherein: the peak duration t1 is 4 ± 4*20% seconds, and the valley duration t2 is 2 ± 2*20% seconds.
9. The method of claim 2, wherein: the pulse current density signal has a plurality of peak values, and the plurality of peak values gradually increase from front to back.
10. The method of claim 1, wherein: the bumps comprise copper pillar bumps.