Pressure sensor chip and preparation method thereof

Abstract

The invention relates to the technical field of pressure sensors, in particular to a pressure sensor chip and a preparation method thereof, and the method comprises the steps: etching a p-type silicon carbide bonding layer of a silicon carbide epitaxial wafer to form a metal electrode opening region, a p-type isolation channel and a bonding region; etching the n-type silicon carbide device layer to form an n-type isolation channel, a resistance strip lead and an n-type silicon carbide piezoresistor; arranging a silicon dioxide layer on the side wall of the p-type isolation channel, the side wall of the n-type isolation channel and a passivation region where the wedge-shaped through hole is not in contact with the p-type silicon carbide bonding layer; a metal electrode layer is arranged in the metal electrode opening area and makes contact with the n-type silicon carbide device layer; the bottom of the n-type silicon carbide substrate is etched to form an annular stepped pressure cavity, a blind groove and a wedge-shaped through hole are formed in the center of the silicon carbide sealing cover plate, and the silicon carbide sealing cover plate is bonded to the top of the silicon carbide epitaxial wafer, so that the problem that the silicon carbide pressure sensor chip is difficult to meet the high-precision pressure measurement requirement is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of pressure sensor, in particular to a pressure sensor chip and a preparation method thereof. BACKGROUND

[0002] In the field of high-temperature pressure testing, especially in harsh environments above 600 DEG C, such as strong radiation, electromagnetic interference and strong corrosion conditions, the measurement accuracy and reliability of the pressure sensor are put forward more stringent requirements. Silicon carbide material becomes an ideal choice for realizing high-temperature pressure sensing due to its excellent high-temperature stability, but needs to overcome the challenges of processing and reliability to meet the actual application requirements.

[0003] Early pressure sensors mostly use silicon-based materials to realize pressure sensing through MEMS technology. Silicon-based sensors use PN junction characteristics for signal conversion, but in high-temperature environments, the electrical properties of silicon material are limited, affecting stability. The sensor based on SOI technology adopts an intermediate oxide layer isolation structure to improve the working temperature range, but due to the plastic deformation of silicon material itself at high temperature, its application temperature is difficult to break through 500 DEG C or above.

[0004] When silicon carbide pressure sensor chip realizes high-temperature application, it still faces problems such as great difficulty in processing pressure cavity, poor pattern fidelity and low front bonding strength, resulting in insufficient reliability and measurement accuracy of the sensor in high-temperature harsh environments, which is difficult to meet the demand of high-precision pressure measurement. SUMMARY

[0005] The present application provides a pressure sensor chip and a preparation method to solve the problem that silicon carbide pressure sensor chip is difficult to meet the demand of high-precision pressure measurement.

[0006] The first aspect of the present application provides a pressure sensor chip, comprising: a silicon carbide epitaxial wafer, a silicon dioxide layer, a metal electrode layer and a silicon carbide sealing cover plate; The silicon carbide epitaxial wafer comprises a p-type silicon carbide bonding layer, an n-type silicon carbide device layer, a p-type silicon carbide isolation layer, an n-type silicon carbide buffer layer and an n-type silicon carbide substrate connected in turn from top to bottom; The p-type silicon carbide bonding layer is etched to form a metal electrode opening area, a p-type isolation channel and a bonding area; The n-type silicon carbide device layer is etched to form an n-type isolation channel, a resistance strip lead and four n-type silicon carbide voltage-dependent resistors; the n-type isolation channel is arranged at the bottom of the p-type isolation channel, and the n-type silicon carbide voltage-dependent resistor is provided with a p-type silicon carbide bonding layer at the top; The silicon dioxide layer is arranged on the sidewalls of the p-type isolation channel and the n-type isolation channel, and the passivation area not in contact with the p-type silicon carbide bonding layer of the wedge-shaped through hole; The metal electrode layer is arranged in a metal electrode opening area and is in contact with the n-type silicon carbide device layer. The bottom of the n-type silicon carbide substrate is etched to form a ring-shaped stepped pressure cavity. The silicon carbide sealing cover plate is centrally provided with a blind groove and peripherally provided with four wedge-shaped through holes.

[0007] The pressure sensor chip of the present application improves the electrical insulation performance, reduces signal interference, and thus improves the accuracy of pressure measurement through the design of the multi-layer silicon carbide structure and the silicon dioxide. Meanwhile, the ring-shaped stepped pressure cavity and the silicon carbide sealing cover plate cooperate to help uniformly distribute pressure, optimize the response stability and sensitivity of the sensor, so as to solve the problem that the silicon carbide pressure sensor chip is difficult to meet the high-precision pressure measurement requirement.

[0008] Optionally, the n-type isolation channel and the p-type isolation channel have the same width; the four n-type silicon carbide voltage-dependent resistors have the same resistance and are distributed around the ring-shaped stepped pressure cavity; and the n-type silicon carbide voltage-dependent resistor has a π-shaped structure for improving the pressure sensing capability and measurement accuracy.

[0009] The uniformity of electrical isolation is improved by using the n-type and p-type isolation channels with the same width; the four voltage-dependent resistors with the same resistance and distributed around the cavity can reduce the influence of temperature change on the output and improve the measurement consistency; and the π-shaped voltage-dependent resistor can enhance the strain sensing capability, thereby improving the sensitivity and accuracy of pressure measurement.

[0010] Optionally, the four n-type silicon carbide voltage-dependent resistors are connected in sequence by four resistance strip leads, and the four resistance strip leads have the same pattern and are symmetrically distributed outside the stress area to form a Wheatstone bridge in a closed bridge form.

[0011] The four voltage-dependent resistors are connected in sequence by the same resistance strip leads and are symmetrically distributed outside the stress area, which helps to realize the consistency of the lead pattern and the positional symmetry, thereby reducing the influence of process deviation and uneven stress distribution on the balance of the bridge; the Wheatstone bridge in a closed bridge form can improve the stability of the output signal, improve the common-mode noise rejection capability, and thus improve the accuracy and reliability of pressure measurement.

[0012] Optionally, the thickness of the silicon dioxide layer is 50-200 nanometers; and the metal electrode layer comprises at least one metal combination of titanium, platinum, tungsten, titanium nitride, and gold.

[0013] The thickness range of the silicon dioxide layer helps to reduce the stress of the dielectric layer while providing sufficient electrical insulation capability, thereby optimizing the reliability of long-term operation of the device; the selected material combination of the metal electrode layer can take into account good ohmic contact, adhesion and anti-electromigration performance, which helps to improve the stability of the electrode structure and the quality of signal transmission.

[0014] Optionally, the inner wall and / or the outer wall of the annular stepped pressure cavity are in an annular stepped structure; the annular stepped structure has one or more annular steps, and when there are multiple annular steps, the multiple annular steps are concentric annular steps.

[0015] The design of the annular stepped structure helps to disperse and buffer the stress concentration under pressure, reducing the risk of structural rupture; when there are multiple concentric annular steps, the uniformity of stress distribution can be further optimized, thereby improving the structural stability and measurement consistency of the pressure sensor under high pressure or cyclic load conditions.

[0016] Optionally, the wedge-shaped through hole is opened in the position of the silicon carbide sealing cover plate close to the metal electrode layer; the blind groove is opened in the position of the silicon carbide sealing cover plate close to the annular stepped pressure cavity; the silicon carbide sealing cover plate and the p-type silicon carbide bonding layer are homogeneously bonded by a surface activation bonding technology, and the bonding strength is greater than 32 MPa.

[0017] By setting the wedge-shaped through hole near the metal electrode layer, it helps to reduce the difficulty of electrode lead connection and reduce the parasitic effect of the signal transmission path; the blind groove is located above the annular stepped pressure cavity, which can optimize the uniformity of pressure transmission and improve the consistency of sensor response; the surface activation bonding technology is used to realize the homogeneous bonding of the silicon carbide sealing cover plate and the bonding layer, and the bonding strength helps to improve the packaging airtightness and interface stability, thereby enhancing the long-term working reliability of the device in harsh environments.

[0018] The second aspect of the present application provides a pressure sensor chip preparation method for processing the pressure sensor chip of the first aspect, the method comprising: A five-layer structure of double-etched silicon carbide epitaxial wafer is selected as a processing substrate, and the silicon carbide epitaxial wafer comprises, from top to bottom, a p-type silicon carbide bonding layer, an n-type silicon carbide device layer, a p-type silicon carbide isolation layer, an n-type silicon carbide buffer layer, and an n-type silicon carbide substrate; A dry etching process is used to etch the p-type silicon carbide bonding layer to form a metal electrode opening area, a p-type isolation channel, and a bonding area; A dry etching process is used to etch the n-type silicon carbide device layer to form an n-type isolation channel, four resistance strip leads, and four n-type silicon carbide voltage-dependent resistors; A thermal oxidation process is used to grow a layer of silicon dioxide on the upper surface of the silicon carbide epitaxial wafer; The dry etching process is used to etch the silicon dioxide layer to reserve the p-type isolation channel sidewall, n-type isolation channel sidewall and oxide layer of the passivation region; The metal electrode layer is formed on the metal electrode opening area by using a stripping process combined with an electron beam evaporation method, and annealing treatment is performed to form an ohmic contact; The bottom of the n-type silicon carbide substrate is etched by using a multi-time laser processing process to form a ring-shaped stepped pressure cavity, and a deep dry etching technique is used to remove the laser damage layer; The first etching process is used to etch the silicon carbide material to form a blind groove and a wedge-shaped via hole, and a silicon carbide sealing cover plate is obtained; The silicon carbide sealing cover plate is homogeneously bonded with the p-type silicon carbide bonding layer by using a surface activation bonding technology.

[0019] The above preparation method selects a five-layer structure silicon carbide epitaxial wafer as a substrate, which helps to ensure the consistency of the material and the process compatibility; the dry etching process is used to form the isolation channel and the resistance pattern, which can improve the etching precision and pattern uniformity, and reduce the size deviation; the silicon dioxide layer is grown by thermal oxidation and combined with selective etching, which can optimize the coverage quality and passivation effect of the insulating layer; the metal electrode is prepared by stripping process and electron beam evaporation and annealing, which helps to form stable ohmic contact and reduce contact resistance; the ring-shaped stepped pressure cavity is formed by using multi-time laser processing and deep dry etching to remove the damage layer, which can reduce the stress concentration introduced by processing and improve the integrity of the cavity structure; the homogenous bonding is realized by using the surface activation bonding technology, which helps to improve the bonding strength and air tightness of the packaging interface, thereby enhancing the overall reliability and measurement stability of the device.

[0020] Optionally, the first etching process uses one or more of deep dry etching process, laser processing process, and mechanical grinding process; the dry etching process and deep dry etching process both use inductively coupled plasma etching process or reactive ion etching process.

[0021] By using a combination of multiple processing techniques in the first etching process, the flexibility of process selection is provided, which helps to adapt to the processing needs of different structural features; the dry etching process and deep dry etching process both use inductively coupled plasma etching or reactive ion etching, which can improve the precision and uniformity of the etching pattern, reduce the sidewall roughness and material damage in the etching process, thereby improving the integrity of the device structure and the stability of the electrical performance.

[0022] Optionally, the deep dry etching process has an etching power of 1000-1500W, an RF bias of 100-300W, a working pressure of 0.34-1Pa, and a depth of 5-10μm; the deep dry etching process uses a mixture of sulfur hexafluoride and oxygen or a mixture of carbon tetrafluoride and oxygen; If the deep dry etching process uses a mixture of sulfur hexafluoride and oxygen, the flow rate of sulfur hexafluoride is 100-120sccm, and the flow rate of oxygen is 5-15sccm. If the deep dry etching process uses a mixture of carbon tetrafluoride and oxygen, the flow rate of carbon tetrafluoride is 100-120sccm, and the flow rate of oxygen is 5-15sccm.

[0023] The deep dry etching process, by setting specific etching power, RF bias, working pressure, and depth range, and combining the mixture of sulfur hexafluoride and oxygen or carbon tetrafluoride and oxygen and its flow rate control, helps to optimize etching rate and directionality, reduce sidewall roughness and lattice damage during etching, thereby improving the precision and structural integrity of etched patterns, and enhancing the consistency and stability of device performance.

[0024] Optionally, during the deep dry etching process, an oxidation layer is formed on the sidewall by controlling the gas composition and etching parameters, so as to reduce lateral etching and improve the aspect ratio.

[0025] By controlling the gas composition and etching parameters to form an oxidation layer on the sidewall, lateral etching is inhibited, the verticality and aspect ratio of the etched structure are improved, thereby improving the precision and consistency of structural size of pattern transfer, and enhancing the performance stability of devices at the microscale.

[0026] It can be known from the above technical solution that the application provides a pressure sensor chip and a preparation method, by selecting a five-layer structure double-etched silicon carbide epitaxial wafer as a processing substrate, using a dry etching process to etch the p-type silicon carbide bonding layer to form a metal electrode opening area, a p-type isolation channel and a bonding area; using a dry etching process to etch the n-type silicon carbide device layer to form an n-type isolation channel, four resistance strip leads and four n-type silicon carbide pressure sensitive resistors; using a thermal oxidation process to grow a layer of silicon dioxide on the upper surface of the silicon carbide epitaxial wafer; using a dry etching process to etch the silicon dioxide layer to retain the sidewalls of the p-type isolation channel, the sidewalls of the n-type isolation channel and the oxide layer of the passivation area; using a stripping process combined with an electron beam evaporation method to form a metal electrode layer on the metal electrode opening area, and performing annealing treatment to form an ohmic contact; using a multiple laser processing process to etch the bottom of the n-type silicon carbide substrate to form a ring-shaped stepped pressure cavity, and removing the laser damage layer by deep dry etching technology; using a first etching process to etch the silicon carbide material to form a blind groove and a wedge-shaped via hole, and obtaining a silicon carbide sealing cover plate; using a surface activation bonding technology to homogeneously bond the silicon carbide sealing cover plate with the p-type silicon carbide bonding layer, so as to solve the problem that the silicon carbide pressure sensor chip is difficult to meet the high-precision pressure measurement requirement. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the application, the drawings required in the embodiments will be briefly introduced below. Obviously, other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0028] Figure 1 A planar structure schematic diagram of the pressure sensor chip provided by the embodiments of the application is provided. Figure 2 A processing flow schematic diagram of the pressure sensor chip preparation method provided by the embodiments of the application is provided. Figure 3 A photolithography mask layout for etching the p-type silicon carbide bonding layer in the pressure sensor chip preparation method provided by the embodiments of the application is provided. Figure 4 A photolithography mask layout for etching the n-type silicon carbide device layer in the pressure sensor chip preparation method provided by the embodiments of the application is provided. Figure 5 A photolithography mask layout for etching the silicon dioxide layer in the pressure sensor chip preparation method provided by the embodiments of the application is provided. Figure 6 A photolithography mask layout for preparing the metal electrode layer in the pressure sensor chip preparation method provided by the embodiments of the application is provided.

[0029] Illustration: Wherein, 1-n type silicon carbide substrate; 2-n type silicon carbide buffer layer; 3-p type silicon carbide isolation layer; 4-n type silicon carbide device layer; 5-p type silicon carbide bonding layer; 6-metal electrode opening area; 7-p type isolation channel; 8-bonding area; 9-n type isolation channel; 10-n type silicon carbide voltage-dependent resistor; 11-resistor lead; 12-silicon dioxide layer; 13-passivation area; 14-metal electrode layer; 15-ring-shaped stepped pressure cavity; 16-blind groove; 17-wedge-shaped via. DETAILED DESCRIPTION

[0030] The embodiments will be described in detail below with reference to examples thereof as illustrated in the accompanying drawings. When the description below refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following embodiments are not meant to represent all implementations consistent with the present disclosure. Rather, they are merely examples of systems and methods consistent with some aspects of the present disclosure.

[0031] To solve the problem that the silicon carbide pressure sensor chip is difficult to meet the demand of high-precision pressure measurement, see Figures 1-6 Some embodiments of the present disclosure provide a pressure sensor chip, comprising: a silicon carbide epitaxial wafer, a silicon dioxide layer 12, a metal electrode layer 14 and a silicon carbide sealing cover plate.

[0032] It should be understood that the silicon carbide epitaxial wafer and the silicon carbide sealing cover plate of the pressure sensor chip are both made of 4H-SiC material. 4H-SiC material refers to a silicon carbide polytype with a hexagonal crystal structure, where "4H" indicates that there are four double-layer periodic stacking units along the c-axis direction in its crystal structure. This material has excellent physical and chemical properties, such as high hardness, high thermal conductivity, high chemical stability and good high-temperature stability, making it have a wide range of applications in extreme environments such as high pressure, high frequency and high temperature. In particular, in the manufacture of pressure sensor chips, 4H-SiC material is favored for its outstanding performance.

[0033] The silicon carbide epitaxial wafer includes: a p-type silicon carbide bonding layer 5, an n-type silicon carbide device layer 4, a p-type silicon carbide isolation layer 3, an n-type silicon carbide buffer layer 2 and an n-type silicon carbide substrate 1; the p-type silicon carbide bonding layer 5, the n-type silicon carbide device layer 4, the p-type silicon carbide isolation layer 3, the n-type silicon carbide buffer layer 2 and the n-type silicon carbide substrate 1 are connected in order from top to bottom.

[0034] It should be understood that the n-type silicon carbide buffer layer 2 arranged above the n-type silicon carbide substrate 1 can greatly reduce the defects of the epitaxial layer and improve the quality of the epitaxial layer; the p-type silicon carbide isolation layer 3 arranged between the n-type silicon carbide buffer layer 2 and the n-type silicon carbide device layer 4 can realize electrical isolation between the n-type silicon carbide device layer 4 and the substrate, avoid device short circuit, and be applicable to high-temperature environments above 600°C; the p-type silicon carbide bonding layer 5 arranged above the n-type silicon carbide device layer 4 and homogeneously bonded with the silicon carbide sealing cover plate, the p-type silicon carbide bonding layer 5 and the silicon carbide sealing cover plate have the same thermal expansion coefficient, which can reduce the stress of the bonding interface; the n-type silicon carbide device layer 4 is not in direct contact with the silicon carbide sealing cover plate, which avoids the influence of the bonding interface on the electrical and mechanical properties of the device layer; the p-type silicon carbide bonding layer 5 can be used as a shielding layer to effectively protect the n-type silicon carbide device layer 4, reduce signal interference such as radiation and electromagnetic interference, and improve reliability.

[0035] The p-type silicon carbide bonding layer 5 is etched to form a metal electrode opening area 6, a p-type isolation channel 7, and a bonding area 8.

[0036] It should be understood that the metal electrode opening area 6 is used for the preparation of a subsequent metal electrode to realize the electrical connection between the device and the external circuit; the p-type isolation channel 7 can further enhance the electrical isolation effect between the device layer and the substrate and prevent the occurrence of the leakage phenomenon; and the bonding area 8 is a key area for homogenous bonding with the silicon carbide sealing cover plate, and the accurate control of the size and shape of the bonding area 8 is crucial to ensure the bonding quality. By reasonably designing the layout and parameters of these areas, the performance and reliability of the pressure sensor chip can be significantly improved.

[0037] The n-type silicon carbide device layer 4 is etched to form an n-type isolation channel 9, four resistance strip leads 11, and four n-type silicon carbide voltage-dependent resistors 10; the n-type isolation channel 9 is arranged at the bottom of the p-type isolation channel 7, and the n-type silicon carbide voltage-dependent resistor 10 has the p-type silicon carbide bonding layer 5 arranged at the top thereof.

[0038] It should be understood that the four resistance bar leads 11 are completely the same in pattern and symmetrically distributed outside the stress area, sequentially connecting the four n-type silicon carbide varistors 10 (R1, R2, R3, R4) to form a Wheatstone bridge in the form of a closed bridge. The main role of the n-type isolation channel 9 is to further enhance the electrical isolation performance inside the device, ensuring that unnecessary electrical interference does not occur between the various functional areas. The four resistance bar leads 11 are respectively connected to the four n-type silicon carbide varistors 10, and these leads are responsible for transmitting the electrical signals generated by the varistors due to pressure changes, so that the subsequent circuit can process and analyze them. The four n-type silicon carbide varistors 10, as the core sensitive element of the pressure sensor, will have their resistance values change accordingly with the change in pressure. By detecting this change in resistance value, the magnitude of the pressure can be indirectly obtained. The p-type silicon carbide bonding layer 5 is arranged on the top of the n-type silicon carbide varistor 10. Not only can it protect the varistor to a certain extent, but it can also take advantage of the characteristics of p-type silicon carbide to further optimize the electrical performance and reliability of the sensor chip.

[0039] The silicon dioxide layer 12 is arranged on the sidewalls of the p-type isolation channel 7 and the n-type isolation channel 9, as well as the passivation area 13 of the wedge-shaped through hole 17 that does not contact the p-type silicon carbide bonding layer 5.

[0040] The metal electrode layer 14 is arranged in the metal electrode opening area 6 and contacts the n-type silicon carbide device layer 4, while achieving electrical insulation with the p-type silicon carbide bonding layer 5 through the silicon dioxide layer 12 on the sidewall.

[0041] The bottom of the n-type silicon carbide substrate 1 is etched to form a ring-shaped stepped pressure cavity 15.

[0042] The center of the silicon carbide sealing cover plate is provided with a blind groove 16, and four wedge-shaped through holes 17 are arranged around it. The silicon carbide sealing cover plate is bonded to the top of the silicon carbide epitaxial wafer.

[0043] It should be understood that the silicon carbide sealing cover plate can be front-bonded to the silicon carbide epitaxial wafer to form a front packaging structure, which can realize a leadless packaging structure of the sensor and improve the natural frequency of the sensor. The use of silicon carbide homogenous bonding, with the same thermal expansion coefficient, can reduce the stress at the bonding interface and increase the application temperature of the sensor to above 500°C.

[0044] The pressure sensor chip of the present application improves the electrical insulation performance and reduces signal interference through the design of multiple layers of silicon carbide structure and silicon dioxide layer 12, thereby improving the accuracy of pressure measurement. At the same time, the ring-shaped stepped pressure cavity 15 and the silicon carbide sealing cover plate cooperate to help distribute pressure uniformly, optimize the response stability and sensitivity of the sensor, and solve the problem that the silicon carbide pressure sensor chip is difficult to meet the high-precision pressure measurement requirement.

[0045] In some embodiments, the n-type isolation channel 9 and the p-type isolation channel 7 have the same width; the four n-type silicon carbide varistors 10 have the same resistance and are distributed along the periphery of the annular stepped pressure cavity 15; the n-type silicon carbide varistors 10 have a π-shaped structure to improve the pressure sensing capability and measurement accuracy.

[0046] It should be understood that the n-type silicon carbide varistors 10 having a π-shaped structure means that the cross section of the resistor is designed to be π-shaped, which can ensure that the four varistors have the same resistance, fully considers the lateral strain and longitudinal strain, and at the same time realizes that the resistance strip leads 11 have the same pattern and are symmetrically distributed outside the stress area, thereby reducing the measurement error caused by the asymmetric structure design and improving the measurement accuracy.

[0047] By using n-type and p-type isolation channels with the same width, the uniformity of electrical isolation can be improved; the four varistors with the same resistance and distributed along the periphery of the cavity can reduce the influence of temperature change on the output and improve the measurement consistency; the π-shaped varistors can enhance the strain sensing capability, thereby improving the sensitivity and accuracy of pressure measurement.

[0048] In some embodiments, the silicon carbide epitaxial wafer is a double-throw wafer, and the total thickness of the silicon carbide epitaxial wafer is 300-500 microns; the thickness of the p-type silicon carbide bonding layer 5 is 200 nanometers to 2 microns, and the corresponding doping concentration is 3×10 15 cm3to 3×10 18 cm3; the thickness of the n-type silicon carbide device layer 4 is 200 nanometers to 2 microns, and the corresponding doping concentration is 1×10 19 cm3to 3×10 20 cm3; the thickness of the p-type silicon carbide isolation layer 3 is 200 nanometers to 5 microns, and the corresponding doping concentration is 3×10 15 cm3to 3×10 18 cm3; the thickness of the n-type silicon carbide buffer layer 2 is 200 nanometers to 2 microns, and the corresponding doping concentration is 3×10 15 cm3to 3×10 18 cm3; the thickness of the n-type silicon carbide substrate 1 is 300-500 microns.

[0049] It should be understood that the thickness of 200 nanometers to 2 microns and the corresponding doping concentration of 3×10 15 cm3to 3×10 18The n-type silicon carbide buffer layer 2 with a volume of 1 cubic centimeter can relieve stress and inhibit defect generation. Stress can be generated between the silicon carbide substrate and the epitaxial layer due to the difference in lattice constants (for example, lattice mismatch caused by the difference in concentration between the substrate and the epitaxial layer), and the buffer layer can release this stress through its own structure to prevent cracks, dislocations and other defects in the epitaxial layer due to stress concentration, thereby ensuring the structural integrity of the epitaxial layer. On the other hand, it can block the diffusion of defects and improve the purity of the epitaxial layer. Native defects such as dislocations and microtubules in the substrate can diffuse to the epitaxial layer, and the buffer layer can effectively block the transmission of these defects, reduce the defect density in the epitaxial layer, and improve the crystal quality of the epitaxial layer, thereby improving the yield of the device, such as reducing the leakage current and avoiding failure. The thickness is 200 nanometers to 5 microns, and the corresponding doping concentration is 3×10 15 1 cubic centimeter to 3×10 18 The p-type silicon carbide isolation layer 3 with a volume of 1 cubic centimeter has a thickness of 200 nanometers to 2 microns, and a corresponding doping concentration of 1×10 19 1 cubic centimeter to 3×10 20 The n-type silicon carbide device layer 4 with a volume of 1 cubic centimeter can ensure that the p-type silicon carbide isolation layer 3 and the n-type silicon carbide device layer 4 form a PN junction to achieve isolation between the n-type silicon carbide device layer 4 and the substrate; at the same time, the n-type silicon carbide voltage-dependent resistor 10 can have a high sensitivity output and a low temperature drift characteristic.

[0050] In some embodiments, the four n-type silicon carbide voltage-dependent resistors 10 are connected in sequence through four resistance strip leads 11, and the patterns of the four resistance strip leads 11 are completely the same and symmetrically distributed outside the stress area to form a closed bridge Wheatstone bridge.

[0051] By connecting the four voltage-dependent resistors in sequence through the same resistance strip leads 11 and symmetrically distributing them outside the stress area, the consistency and positional symmetry of the lead patterns can be achieved, thereby reducing the influence of process deviation and uneven stress distribution on the balance of the bridge. The closed bridge Wheatstone bridge can improve the stability of the output signal, improve the common mode noise rejection capability, and thus improve the accuracy and reliability of the pressure measurement.

[0052] In some embodiments, the thickness of the silicon dioxide layer 12 is 50 nanometers to 200 nanometers; and the metal electrode layer 14 includes at least one metal combination of titanium, platinum, tungsten, titanium nitride and gold.

[0053] It should be understood that the oxidation rate of the silicon carbide material is low, the dielectric constant is large, the thickness of the 50-200 nm silicon dioxide layer 12 can realize the electrical insulation of the metal electrode layer 14 and the p-type silicon carbide bonding layer 5, reduce the processing cost, and at the same time, can fix the movable ions and interface defects of the silicon carbide and silicon dioxide interface, resist micro-mechanical scratches and particle impact, enhance the protection of the device layer, block the penetration of corrosive media such as water and chloride ions, enhance the insulation barrier, and reduce the leakage current.

[0054] The thickness range of the silicon dioxide layer 12 helps to reduce the stress of the dielectric layer while providing sufficient electrical insulation capability, thereby optimizing the reliability of the device during long-term operation; the selected material combination of the metal electrode layer 14 can take into account good ohmic contact, adhesion and anti-electromigration performance, which helps to improve the stability of the electrode structure and the quality of signal transmission.

[0055] In some embodiments, the inner wall and / or the outer wall of the annular stepped pressure cavity 15 are annular stepped structures; the annular stepped structure has one or more annular steps, and when there are multiple annular steps, the multiple annular steps are concentric annular steps.

[0056] It should be understood that due to the uneven distribution of energy within the laser spot, the energy at the center of the spot is strong and the energy at the edge is weak, as the laser processing depth increases, the verticality of the sidewall decreases, the pressure cavity pattern deforms, and then the stress distribution of the pressure sensitive diaphragm is uneven, which affects the measurement accuracy. The annular step is set to one or more, which avoids the problem of poor bottom corner verticality caused by excessive depth, helps to improve the verticality of the sidewall of the pressure cavity, and ensures the pattern fidelity of the cavity; when there are multiple concentric annular steps, the uniformity of the stress distribution can be further optimized, thereby improving the structural stability and measurement consistency of the pressure sensor under high pressure or cyclic load conditions.

[0057] In some embodiments, the depth of the annular stepped pressure cavity 15 is 250-480 microns, the annular step can be set to multiple, and the height of each step can be 50-200 microns, and the depth of the dry etching is 5-10 microns.

[0058] It should be understood that the processing depth of 250-480 microns can cover the low, medium and high range of the measurement range of the pressure sensor chip, meeting the measurement needs of different pressure environments. Setting multiple annular steps and 50-200 micron step heights can fully ensure the verticality of the sidewall of the pressure cavity and the pattern fidelity of the cavity. The dry etching depth of 5-10 microns can effectively remove the damage layer caused by laser processing, significantly improving the surface quality and mechanical strength of the pressure cavity.

[0059] In some embodiments, the wedge-shaped via hole 17 is formed on the silicon carbide sealing cover plate near the metal electrode layer 14; the blind groove 16 is formed on the silicon carbide sealing cover plate near the annular stepped pressure cavity 15; the silicon carbide sealing cover plate and the p-type silicon carbide bonding layer 5 are homogeneously bonded by surface activation bonding technology, and the bonding strength is greater than 32 MPa.

[0060] By arranging the wedge-shaped via hole 17 near the metal electrode layer 14, the difficulty of electrode lead connection is reduced and the parasitic effect of signal transmission path is reduced; the blind groove 16 is located above the annular stepped pressure cavity 15, which can optimize the uniformity of pressure transmission and improve the consistency of sensor response; the silicon carbide sealing cover plate and the bonding layer are homogeneously bonded by surface activation bonding technology, and the bonding strength helps to improve the packaging air tightness and interface stability, thereby enhancing the long-term working reliability of the device in harsh environment.

[0061] Part of the embodiments of the present application also provide a pressure sensor chip preparation method for processing the pressure sensor chip of the above embodiments, the method comprising: S100: Select a five-layer structure double-polished silicon carbide epitaxial wafer as a processing substrate, and the silicon carbide epitaxial wafer comprises, from top to bottom, a p-type silicon carbide bonding layer 5, an n-type silicon carbide device layer 4, a p-type silicon carbide isolation layer 3, an n-type silicon carbide buffer layer 2 and an n-type silicon carbide substrate 1.

[0062] S200: Etching the p-type silicon carbide bonding layer 5 by dry etching process to form a metal electrode opening area 6, a p-type isolation channel 7 and a bonding area 8.

[0063] S300: Etching the n-type silicon carbide device layer 4 by dry etching process to form an n-type isolation channel 9, four resistance strip leads 11 and four n-type silicon carbide pressure sensitive resistors 10.

[0064] S400: Growing a layer of silicon dioxide 12 on the upper surface of the silicon carbide epitaxial wafer by thermal oxidation process.

[0065] S500: Etching the silicon dioxide layer 12 by dry etching process to retain the sidewalls of the p-type isolation channel 7, the sidewalls of the n-type isolation channel 9 and the oxide layer of the passivation area 13.

[0066] S600: Forming a metal electrode layer 14 on the metal electrode opening area 6 by peeling process combined with electron beam evaporation method, and performing annealing treatment to form ohmic contact.

[0067] S700: Etching the bottom of the n-type silicon carbide substrate 1 by multiple laser processing processes to form an annular stepped pressure cavity 15, and removing the laser damage layer by deep dry etching technology.

[0068] Referring to Figure 2Wherein (a) is a schematic diagram of the structure of step S100; (b) is a schematic diagram of the structure of step S200; (c) is a schematic diagram of the structure of step S300; (d) is a schematic diagram of the structure of step S400; (e) is a schematic diagram of the structure of step S500; (f) is a schematic diagram of the structure of step S600; (g) is a schematic diagram of the structure of step S700; (h) is a schematic diagram of the structure of step S800; (i) is a schematic diagram of the structure of step S900.

[0069] It should be understood that the laser processing process can select a femtosecond laser with a pulse width controlled at 190 femtoseconds to 350 femtoseconds, which can effectively reduce the heat affected zone and improve the processing precision. The single pulse energy is 5 microjoules to 57 microjoules to avoid edge collapse defects. The average power is set at 0.75 watts to 1.5 watts, the scanning speed is 15 mm / s to 50 mm / s, the spacing between adjacent processing lines is kept at 20 microns to 50 microns, and the spot diameter is 1 micron to 20 microns. Deep dry etching technology uses inductively coupled plasma etching or reactive ion etching process, the etching power can be selected at 1000 watts to 1500 watts, the radio frequency bias can be selected at 100 watts to 300 watts, and the working pressure can be selected at 0.34 Pa to 1 Pa. The gas flow used is as follows: sulfur hexafluoride flow: 100 to 120 standard cubic centimeters per minute; oxygen flow: 5 to 15 standard cubic centimeters per minute (or 5% to 50% of the volume fraction of the mixed gas); if carbon tetrafluoride and oxygen are used in combination, the carbon tetrafluoride flow is 100 to 120 standard cubic centimeters per minute, and the oxygen flow is 5 to 15 standard cubic centimeters per minute. A sidewall protection layer is formed during etching to reduce lateral etching, improve the aspect ratio, and the deep dry etching depth is 5 to 10 microns, effectively removing the damage layer caused by laser processing, significantly improving the surface quality and mechanical strength of the pressure cavity.

[0070] S800: Etching the silicon carbide material using a first etching process to form the blind groove 16 and the wedge-shaped through hole 17, and obtain the silicon carbide sealing cover plate.

[0071] It should be understood that the deep silicon carbide etching process uses sulfur hexafluoride as the main etching gas, which generates fluorine radicals through plasma decomposition and reacts with silicon carbide to generate volatile silicon tetrafluoride and carbon (which requires auxiliary gas removal), with an etching rate of about 0.5 microns / minute to 2 microns / minute. The auxiliary gas is oxygen and argon, wherein the oxygen is used to oxidize the carbon impurities on the surface of the silicon carbide to improve the etching rate; the argon is used to dilute the plasma concentration to reduce excessive bombardment on the surface of the silicon carbide and prevent lattice damage; at the same time, argon ions can clean the deposits (such as carbon particles) in the groove to avoid blockage. The etching power is 1000 watts to 3000 watts, the bias power is 300 to 400 watts, the sulfur hexafluoride flow is 50 to 200 standard cubic centimeters per minute, and the reaction chamber pressure is controlled at 5 mTorr to 20 mTorr. By precisely controlling these parameters, a high-quality etching with an aspect ratio >20, a sidewall perpendicularity <5°, and a surface damage <10 nanometers can be achieved.

[0072] S900: Homogeneous bonding of the silicon carbide sealing cover plate to the p-type silicon carbide bonding layer 5 is performed using surface activated bonding technology.

[0073] It should be understood that surface activated bonding (SAB) is a key technology for realizing high-strength bonding of silicon carbide homogeneous materials at low temperature / room temperature. The core is to activate the surface of silicon carbide, remove contaminants and oxide layers, and form a firm covalent bond under low-energy conditions. The surface activated bonding technology does not require chemical cleaning and annealing. By ionically activating the surface of silicon carbide, the silicon carbide sealing cover plate can be bonded to the p-type silicon carbide bonding layer 5 in the atmosphere, and the bonding strength is >32 MPa, which is suitable for large-scale industrial production.

[0074] In some embodiments, argon ion / atom beam bombardment is used: 10 -4 to 10 -7 MPa ultra-high vacuum, high-energy argon ions are used to bombard the surface of silicon carbide. This process can effectively remove the surface oxide layer and physically adsorbed organic / inorganic impurities, break the silicon-carbon bond to form a dangling bond, and significantly enhance the surface reactivity. The ultra-high vacuum can prevent the recontamination of the activated silicon carbide surface by oxygen and moisture in the air, ensuring the bonding quality. The temperature is room temperature (25°C) or <200°C, and room temperature bonding can completely avoid thermal stress (the thermal expansion coefficient of silicon carbide is only 4.5x10 -6 / ℃), which is suitable for homogeneous bonding. A vertical uniform pressure of 4 MPa to 5 MPa is applied, and the pressure needs to be uniformly transmitted through a custom graphite clamp to avoid local pressure that is too large causing wafer cracking. The bonding time is 300 seconds, and a short time will result in insufficient surface contact and low bonding strength, while a long time may introduce unnecessary heat accumulation.

[0075] The above preparation method uses a five-layer structure silicon carbide epitaxial wafer as a substrate, which helps to ensure material consistency and process compatibility; uses a dry etching process to form an isolation channel and a resistance pattern, which can improve etching precision and pattern uniformity and reduce size deviation; grows a silicon dioxide layer 12 by thermal oxidation and combines selective etching, which can optimize insulation layer coverage quality and passivation effect; uses a stripping process and electron beam evaporation to prepare a metal electrode and perform annealing, which helps to form stable ohmic contact and reduce contact resistance; uses multiple laser processing and deep dry etching to form a ring-shaped stepped pressure cavity 15 and remove a damage layer, which can reduce stress concentration introduced by processing and improve cavity structure integrity; uses surface activated bonding technology to realize homogeneous bonding, which helps to improve packaging interface bonding strength and air tightness, thereby enhancing the overall reliability and measurement stability of the device.

[0076] In some embodiments, the first etching process adopts one or more of a dry etching process, a laser processing process, and a mechanical grinding processing process; the dry etching process and the deep dry etching process both adopt an inductively coupled plasma etching process or a reactive ion etching process.

[0077] By adopting a combination of multiple processing processes in the first etching process, process selection flexibility is provided, which helps to adapt to different structural feature processing needs; the dry etching process and the deep dry etching process both adopt inductively coupled plasma etching or reactive ion etching, which can improve etching pattern precision and uniformity, reduce sidewall roughness and material damage during etching, and thus improve device structure integrity and electrical performance stability.

[0078] In some embodiments, the deep dry etching process has an etching power of 1000-1500 W, a radio frequency bias of 100-300 W, a working pressure of 0.34-1 Pa, and a depth of 5-10 microns; the deep dry etching process adopts a mixture of sulfur hexafluoride and oxygen gas or a mixture of carbon tetrafluoride and oxygen gas; if the deep dry etching process adopts a mixture of sulfur hexafluoride and oxygen gas, the sulfur hexafluoride flow rate is 100-120 standard cubic centimeters per minute, and the oxygen flow rate is 5-15 standard cubic centimeters per minute; if the deep dry etching process adopts a mixture of carbon tetrafluoride and oxygen gas, the carbon tetrafluoride flow rate is 100-120 standard cubic centimeters per minute, and the oxygen flow rate is 5-15 standard cubic centimeters per minute.

[0079] The deep dry etching process helps to optimize etching rate and directionality, reduce sidewall roughness and lattice damage during etching, and thus improve etching pattern precision and structure integrity, and enhance device performance consistency and stability by setting specific etching power, radio frequency bias, working pressure, and depth ranges, and combining sulfur hexafluoride and oxygen or carbon tetrafluoride and oxygen mixture gas and flow rate control.

[0080] In some embodiments, during the deep dry etching process, an oxide layer is formed on the sidewall by controlling gas composition and etching parameters to reduce lateral etching and improve aspect ratio.

[0081] By controlling gas composition and etching parameters to form an oxide layer on the sidewall, lateral etching is inhibited, etching structure perpendicularity and aspect ratio are improved, pattern transfer precision and structure size consistency are improved, and device performance stability at a microscopic scale is enhanced.

[0082] According to the technical scheme, the application provides a pressure sensor chip and a preparation method. The five-layer structure double-etched silicon carbide epitaxial wafer is selected as a processing substrate, a dry etching process is used to etch the p-type silicon carbide bonding layer 5, so as to form a metal electrode opening area 6, a p-type isolation channel 7 and a bonding area 8; a dry etching process is used to etch the n-type silicon carbide device layer 4, so as to form an n-type isolation channel 9, four resistance strip leads 11 and four n-type silicon carbide pressure-sensitive resistors 10; a thermal oxidation process is used to grow a silicon dioxide layer 12 on the upper surface of the silicon carbide epitaxial wafer; a dry etching process is used to etch the silicon dioxide layer 12, so as to retain the sidewall of the p-type isolation channel 7, the sidewall of the n-type isolation channel 9 and the oxidation layer of the passivation area 13; a stripping process is combined with an electron beam evaporation method to form a metal electrode layer 14 on the metal electrode opening area 6, and annealing treatment is performed to form an ohmic contact; a multiple laser processing process is used to etch the bottom of the n-type silicon carbide substrate 1, so as to form a ring-shaped stepped pressure cavity 15, and a deep dry etching technology is used to remove the laser damage layer; a first etching process is used to etch the silicon carbide material, so as to form a blind groove 16 and a wedge-shaped through hole 17, and a silicon carbide sealing cover plate is obtained; a surface activation bonding technology is used to homogeneously bond the silicon carbide sealing cover plate and the p-type silicon carbide bonding layer 5, so as to solve the problem that the silicon carbide pressure sensor chip is difficult to meet the high-precision pressure measurement requirement.

[0083] The similar parts among the embodiments provided in the application can be referred to each other, the specific embodiments provided above are only several examples under the general concept of the application, and do not limit the protection scope of the application. Any other embodiments extended according to the application scheme without creative labor belong to the protection scope of the application.

Claims

1. A pressure sensor chip, characterized by The pressure sensor chip comprises a silicon carbide epitaxial wafer, a silicon dioxide layer (12), a metal electrode layer (14) and a silicon carbide sealing cover plate. The silicon carbide epitaxial wafer comprises, from top to bottom, a p-type silicon carbide bonding layer (5), an n-type silicon carbide device layer (4), a p-type silicon carbide isolation layer (3), an n-type silicon carbide buffer layer (2) and an n-type silicon carbide substrate (1). The p-type silicon carbide bonding layer (5) is etched to form a metal electrode opening area (6), a p-type isolation channel (7) and a bonding area (8). The n-type silicon carbide device layer (4) is etched to form an n-type isolation channel (9), a resistance strip lead (11) and four n-type silicon carbide varistors (10); the n-type isolation channel (9) is arranged at the bottom of the p-type isolation channel (7), and the n-type silicon carbide varistor (10) is provided with the p-type silicon carbide bonding layer (5) at the top. The silicon dioxide layer (12) is arranged on the sidewalls of the p-type isolation channel (7) and the n-type isolation channel (9), and a wedge-shaped through hole (17) and a passivation area (13) not in contact with the p-type silicon carbide bonding layer (5). The metal electrode layer (14) is arranged in the metal electrode opening area (6) and is in contact with the n-type silicon carbide device layer (4). The bottom of the n-type silicon carbide substrate (1) is etched to form an annular stepped pressure cavity (15). The silicon carbide sealing cover plate is centrally provided with a blind groove (16) and peripherally provided with four wedge-shaped through holes (17), and the silicon carbide sealing cover plate is bonded to the top of the silicon carbide epitaxial wafer. The n-type isolation channel (9) and the p-type isolation channel (7) have the same width; the four n-type silicon carbide varistors (10) have the same resistance and are distributed around the annular stepped pressure cavity (15); the n-type silicon carbide varistor (10) has a π-shaped structure for improving the pressure sensing capability and the measurement accuracy.

2. The pressure sensor chip of claim 1, wherein, The four n-type silicon carbide varistors (10) are sequentially connected through the four resistance strip leads (11), and the four resistance strip leads (11) have the same pattern and are symmetrically distributed outside the stress area to form a Wheatstone bridge in a closed bridge form.

3. The pressure sensor chip of claim 2, wherein, The thickness of the silicon dioxide layer (12) is 50-200 nm; the metal electrode layer (14) comprises at least one metal combination of titanium, platinum, tungsten, titanium nitride and gold.

4. The pressure sensor chip of claim 1, wherein, The inner wall and / or the outer wall of the annular stepped pressure cavity (15) has an annular stepped structure.

5. The pressure sensor chip of claim 1, wherein, The annular stepped structure has one or more annular steps, and when there are multiple annular steps, the multiple annular steps are concentric annular steps. The wedge-shaped through hole (17) is arranged at a position close to the metal electrode layer (14) of the silicon carbide sealing cover plate; and the blind groove (16) is arranged at a position close to the annular stepped pressure cavity (15) of the silicon carbide sealing cover plate.

6. The pressure sensor chip of claim 1, wherein, The silicon carbide sealing cover plate and the p-type silicon carbide bonding layer (5) are homogeneously bonded by a surface activated bonding (SAB) technology, and the bonding strength is greater than 32 MPa. A method for processing the pressure sensor chip of any one of claims 1-6, the method comprising:

7. A method of fabricating a pressure sensor chip, characterized by, ​ Select a five-layer structure of double-polished silicon carbide epitaxial wafer as a processing substrate, the silicon carbide epitaxial wafer includes, from top to bottom, a p-type silicon carbide bonding layer (5), an n-type silicon carbide device layer (4), a p-type silicon carbide isolation layer (3), an n-type silicon carbide buffer layer (2), and an n-type silicon carbide substrate (1); The p-type silicon carbide bonding layer (5) is etched by using a dry etching process to form a metal electrode opening area (6), a p-type isolation channel (7), and a bonding area (8); The n-type silicon carbide device layer (4) is etched by using a dry etching process to form an n-type isolation channel (9), four resistance strip leads (11), and four n-type silicon carbide varistors (10); A silicon dioxide layer (12) is grown on the upper surface of the silicon carbide epitaxial wafer by using a thermal oxidation process; The silicon dioxide layer (12) is etched by using a dry etching process to retain the sidewall of the p-type isolation channel (7), the sidewall of the n-type isolation channel (9), and the oxide layer of the passivation area (13); A metal electrode layer (14) is formed on the metal electrode opening area (6) by using a stripping process combined with an electron beam evaporation method, and annealing treatment is performed to form an ohmic contact; The bottom of the n-type silicon carbide substrate (1) is etched by using a multiple laser processing process to form a ring-shaped stepped pressure cavity (15), and a laser damage layer is removed by deep dry etching technology; A first etching process is used to etch the silicon carbide material to form a blind groove (16) and a wedge-shaped via (17), and a silicon carbide sealing cover plate is obtained; The silicon carbide sealing cover plate is homogeneously bonded to the p-type silicon carbide bonding layer (5) by using a surface activation bonding technology.

8. The method of claim 7, wherein the pressure sensor chip is prepared by, The first etching process uses one or more of a deep dry etching process, a laser processing process, and a mechanical grinding processing process; the dry etching process and the deep dry etching process both use an inductively coupled plasma etching process or a reactive ion etching process.

9. The method of claim 8, wherein the pressure sensor chip is prepared by a method comprising: The deep dry etching process has an etching power of 1000-1500 W, an RF bias of 100-300 W, a working pressure of 0.34-1 Pa, and a depth of 5-10 μm; the deep dry etching process uses a mixture of sulfur hexafluoride and oxygen or a mixture of carbon tetrafluoride and oxygen; If the deep dry etching process uses a mixture of sulfur hexafluoride and oxygen, the sulfur hexafluoride flow rate is 100-120 standard milliliters per minute, and the oxygen flow rate is 5-15 standard milliliters per minute; If the deep dry etching process uses a mixture of carbon tetrafluoride and oxygen, the carbon tetrafluoride flow rate is 100-120 standard milliliters per minute, and the oxygen flow rate is 5-15 standard milliliters per minute.

10. The method of claim 9, wherein the pressure sensor chip is prepared by a method comprising: During the deep dry etching process, an oxide layer is formed on the sidewall by controlling the gas composition and etching parameters to reduce lateral etching and improve the aspect ratio.

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