Vector data processor, instruction processing method and system on chip

Abstract

The embodiment of the invention provides a vector data processor, an instruction processing method and a system on chip, and the method comprises the steps: determining an instruction calculation mode of a vector instruction according to vector mode configuration information after obtaining the vector instruction needing to be subjected to vector operation; the vector configuration information comprises configuration information for adjusting a data path executed by the current vector through the size of the data block. According to an instruction calculation mode, determining one or more execution assembly lines in the N execution assembly lines for the vector instruction; and executing vector operations corresponding to the vector instructions by execution assembly lines in the vector floating point execution unit respectively. The scheme provided by the invention supports a mixed width calculation mode, so that the vector data processor has the capability of adjusting the data path mode executed by the current vector through the size of the data block, and the throughput of processing small block data is improved; the performance of a large bit width vector register architecture processor when processing software loads with mixed size data block characteristics is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic information technology, and in particular to a vector data processor, an instruction processing method and a system on chip. BACKGROUND

[0002] With the development of semiconductor technology and processor architecture technology, vector data processors are widely used in different fields such as high-performance computing, artificial intelligence, edge computing, etc. due to their high performance and low power consumption. Vector data processors are also known as vector accelerators.

[0003] In the application scenarios of vector data processors, data centers are a typical application scenario. The core tasks of data centers include AI inference and training, media processing and transcoding, encryption and decryption operations, etc. The related software load has high data parallelism, i.e. the same or highly similar operations need to be performed on a large amount of different data. The characteristics of data center software load determine that server-level high-performance processors not only need to have the ability to efficiently process scalar operations, but also need to have efficient vector operation capabilities.

[0004] To adapt to the increasing demand for parallel computing capabilities of software loads with the rapid development of artificial intelligence and large language models, there is an increasing demand for parallel computing capabilities of server-level high-performance processors, which also poses greater challenges to processor design companies to design high-performance vector operation architectures. SUMMARY

[0005] Therefore, the embodiments of the present application provide an instruction processing method to solve some or all of the above problems.

[0006] According to a first aspect of the embodiments of the present application, an instruction processing method is provided for a vector data processor, the vector data processor comprising a vector register, a vector floating point unit, a launch unit, the vector register having a first bit width, the vector floating point unit storing N execution pipelines, each of the execution pipelines supporting a maximum data bit width of an operation being a second bit width, the first bit width being greater than the second bit width, and the sum of N second bit widths being greater than the first bit width, wherein N is a multiple of 2, the method comprising: obtaining a vector instruction requiring vector operation; determining an instruction calculation mode of the vector instruction according to vector mode configuration information, the vector configuration information including configuration information of a data path of the current vector execution adjusted by a data block size; determining one pipeline or multiple execution pipelines in the N execution pipelines for the vector instruction according to the instruction calculation mode; the execution pipelines in the vector floating point execution unit respectively perform vector operations corresponding to the vector instruction.

[0007] According to a second aspect of the embodiments of the present application, a vector data processor is provided, which comprises a vector register, a vector floating point unit, a launch unit, the vector register has a first bit width, the vector floating point unit stores N execution pipelines, each of the execution pipelines supports a maximum data bit width of an operation as a second bit width, the first bit width is greater than the second bit width, and the sum of N second bit widths is greater than the first bit width, wherein N is a multiple of 2, and the method comprises: an instruction fetch unit configured to acquire a vector instruction requiring a vector operation; a mode configuration unit configured to determine an instruction calculation mode of the vector instruction according to vector mode configuration information, wherein the vector mode configuration information comprises configuration information of adjusting a data path of a current vector execution by a data block size; an instruction distribution unit configured to determine one pipeline or multiple execution pipelines of the N execution pipelines for the vector instruction according to the instruction calculation mode; a vector floating point unit configured to control the execution pipelines to respectively perform a vector operation corresponding to the vector instruction.

[0008] According to a third aspect of the embodiments of the present application, a system on chip is provided, which comprises: a control unit and a plurality of on-chip components, wherein the plurality of on-chip components comprises a vector data processor; the control unit is configured to control and manage the plurality of on-chip components, and the vector data processor is configured to execute a computer program / instruction, which, when executed by the vector data processor, implements the method of the first aspect of the present application.

[0009] The vector data processor and the instruction processing method provided by the embodiments of the present application, after acquiring a vector instruction requiring a vector operation, determine an instruction calculation mode of the vector instruction according to vector mode configuration information, and adjust the configuration information of a data path of a current vector execution by a data block size; determine one pipeline or multiple execution pipelines of the N execution pipelines for the vector instruction according to the instruction calculation mode, and the execution pipelines in the vector floating point execution unit respectively perform a vector operation corresponding to the vector instruction. The scheme provided by the present application supports a mixed width calculation mode, so that the vector data processor has the ability to adjust the data path mode of a current vector execution by a data block size, improves the throughput of processing small data blocks, and improves the performance of a large bit width vector register architecture processor when processing a software load with a mixed size data block characteristic. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. All other drawings obtained by those of ordinary skill in the art based on these drawings should belong to the protection scope of the present application.

[0011] Figure 1 is a schematic diagram of an architecture of a vector data processor provided by an embodiment of the present application; Figure 2 is a flowchart of an embodiment of an instruction processing method provided by the present application; Figure 3 is a flowchart of an embodiment of an instruction processing method provided by the present application; Figure 4 is a data processing schematic diagram of an embodiment of an instruction processing method provided by the present application; Figure 5 is another data processing schematic diagram of an embodiment of an instruction processing method provided by the present application; Figure 6 is still another data processing schematic diagram of an embodiment of an instruction processing method provided by the present application; Figure 7 is a schematic diagram of a structure of a system on chip provided by an embodiment of the present application. DETAILED DESCRIPTION

[0012] In order to make those skilled in the art better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art should belong to the protection scope of the present application.

[0013] The following explains some technologies in the present application file.

[0014] Vector data processor: a vector data processor is a special hardware capable of simultaneously executing the same operation on multiple data elements, which drives multiple parallel computing units by a single instruction to efficiently process large-scale data.

[0015] Vector operation: the vector operation in a processor refers to simultaneously executing the same operation on a group of data (referred to as a vector or a vector) by a single instruction, thereby greatly improving the data processing throughput, and being especially suitable for processing intensive tasks such as scientific computing, graphics images, etc.

[0016] Floating point: floating point is a method of approximating real numbers in computers using scientific notation, which encodes a value through the combination of a sign bit, an exponent bit and a mantissa bit, so as to balance the representation range and precision in a fixed length of storage space.

[0017] PPA: PPA is a core trade-off index of chip design, which refers to performance, power consumption and area. When improving one index (such as performance), the other indexes (such as power consumption and area) will be deteriorated. Therefore, the design goal of the vector data processor is to achieve the best balance among the three.

[0018] In the related art, the vector register width represents the maximum data bit width allowed to be stored in the vector register, and also reflects the data width that can be processed by the vector processor in one instruction, which also means higher throughput and energy efficiency. For example, the efficiency of a single instruction execution of a processor with a 256-bit wide vector register architecture is twice that of a 128-bit wide architecture, which means that the processor with a 128-bit wide architecture needs to use two instructions to complete the same calculation as the processor with a 256-bit wide architecture. At the same time, the large bit width vector can more efficiently utilize the memory bandwidth and more fully utilize the data bus width between the processor and the memory, reducing the number of memory accesses and the pressure on the memory subsystem compared with the scalar processor.

[0019] The server-level high-performance processor adopts a large bit width vector register as the mainstream trend. The bit width of the vector register cannot be increased indefinitely, and the excessively large vector register width is a huge challenge to the timing, control area and power consumption of the processor. The products in the related art have encountered the problem that the power consumption cannot be controlled, and the processor temperature is too high, which leads to the need to run at a reduced frequency, thereby affecting the performance. Therefore, the current mainstream vector data processor is almost 256-bit wide or 128-bit wide.

[0020] However, in the program compiled by the vectorizer, not all data blocks in the to-be-processed vector are integer multiples of 256 bits, and many software loads also inevitably process small block data while processing large block data. Due to the PPA limitation, the vector instruction throughput of the processor with a 256-bit wide vector register architecture is usually less than that of the processor with a 128-bit wide vector register architecture. The performance of the processor with a 256-bit wide vector register architecture is weaker than that of the processor with a 128-bit wide vector register architecture when processing small block data, i.e., the vector with a data width less than 256 bits.

[0021] As shown in FIG. 1, Figure 1 the embodiment of the present application provides a vector data processor, which can also be called a vector accelerator, Figure 1A logic architecture diagram of a vector data processor is provided for embodiments of the present application. As shown in Figure 1 As can be seen, the vector data processor 100 provided by the embodiments of the present application can include a vector floating-point unit 105, a vector register 106, a vector floating-point execution unit 107, and further include a fetch unit 101, a mode configuration unit 102, an instruction dispatch unit 103, a launch queue unit 104, and miscellaneous registers 108 that need to be configured.

[0022] Generally, the instruction dispatch unit (Dispatch) can dispatch the decoded instructions to different execution pipelines to ensure that the instructions can be correctly processed and executed by hardware resources.

[0023] The vector floating-point unit (Vector & Floating-Point Execution Unit, VFPU) can be used to perform vector and floating-point operations, including vector addition, vector multiplication, floating-point addition, floating-point multiplication, etc. The VFPU supports efficient parallel computing, and is particularly suitable for scientific computing, image processing, machine learning, and other applications.

[0024] The vector register (Vector Processing Register, VPR for short) can store vector data and intermediate results, and supports vector operations. The vector register usually has a large capacity and can accommodate multiple data elements to support efficient parallel processing.

[0025] In the embodiments of the present application, the vector register 106 has a first bit width VLEN, the vector floating-point unit stores N execution pipelines, each of the execution pipelines supports a maximum data bit width of DPLEN for operations, the first bit width VLEN is greater than the second bit width DPLEN, and the sum of N second bit widths is greater than the first bit width, that is, DPLEN*N is greater than VLEN, where N is a multiple of 2.

[0026] According to the architecture of the vector data processor shown in Figure 1 The fetch unit 101 first acquires a vector instruction that needs to be subjected to vector operations, and then the mode configuration unit 102 determines an instruction calculation mode of the vector instruction according to vector mode configuration information, which includes configuration information for adjusting the data path of the current vector execution through a data block size.

[0027] The instruction dispatch unit 103 can determine one pipeline or multiple execution pipelines in the N execution pipelines for the vector instruction according to the instruction calculation mode. The execution pipelines in the vector floating point execution units 107 in the vector floating point units 105 respectively perform vector operations corresponding to the vector instructions. Finally, the vector operation results are written back to the vector registers 106.

[0028] In the above embodiment, the mode configuration unit 102 can read the pre-stored vector mode configuration information from the miscellaneous registers 108. For example, the vector mode configuration information can be vector element width, vector length, predicate processing mode, etc., and rules for configuring instruction processing modes according to these information, etc.

[0029] The vector data processor in this embodiment is a vector data processor capable of mixing width calculation modes, which can process large blocks of data with a data width of VLEN at a low throughput, and can process small blocks of data with a data width of DPLEN at a high throughput. The vector data processor can adjust the data path mode of the current vector execution according to the data block size, improve the throughput of processing small blocks of data, and improve the performance of the large width vector register architecture processor when processing software loads with mixed size data block characteristics.

[0030] It should be noted that the names of the different units in the above architecture are only for logical differentiation, and do not represent strict differentiation restrictions between each unit.

[0031] Figure 2 is a flowchart of an instruction processing method according to the above vector data processor architecture, which comprises Figure 2 It can be seen that the instruction processing method provided in this embodiment can comprise: S201: obtaining a vector instruction requiring vector operation; Exemplarily, the instruction fetch unit or other data access unit with similar functions can be responsible for reading the vector instruction requiring vector operation in the cache.

[0032] In different embodiments, after obtaining the vector instruction, decoding also needs to be performed, which will not be described in detail.

[0033] S202: determining the instruction calculation mode of the vector instruction according to the vector mode configuration information, wherein the vector mode configuration information comprises configuration information for adjusting the data path of the current vector execution according to the data block size.

[0034] Exemplarily, the vector mode configuration information can be written in the setting registers of the vector data processor, and the logical mode configuration unit can read the vector mode configuration information in the registers, and then determine the instruction calculation mode for the vector instruction requiring vector operation.

[0035] According to the vector length configuration information in the vector mode configuration information, and at least one of the information in the predicate processing mode, the instruction calculation mode of the vector instruction is determined.

[0036] For example, the vector mode configuration information indicates that the vector length processed by the current processor is A, and A mode is configured; The vector length processed by the current processor is B, and B mode is configured; The predicate processing mode of the current processor is C, the vector length is D, and D mode is configured.

[0037] Different modes can correspond to different launch queues, and different launch queues correspond to different execution pipelines.

[0038] Exemplarily, the vector configuration mode information can include vector length, element bit width, predicate processing mode and the like in the processor of the variable-length vector architecture, for example, Selected Element Width (SEW) and Vector Register Group Multiplication (LMUL) and the like in the processor of the RISC-V architecture.

[0039] According to the vector mode configuration information, the vector instruction requiring vector operation is labeled, and the instruction calculation mode is represented by the label.

[0040] Exemplarily, according to the vector mode configuration information, the instruction calculation mode of the vector instruction is determined; and the vector instruction requiring vector operation can be labeled according to the vector mode configuration information, and the instruction calculation mode is represented by the label.

[0041] In this scheme, the instruction can be labeled according to these information, and the label represents the instruction calculation mode. The label will be recognized by the vector processor to determine the launch mode and execution mode of the instruction. In this scheme, the calculation mode of the instruction is set, and the label of the instruction can be labeled as follows: The HINT mode is set by software to explicitly configure or automatically assigned by hardware to record configuration information; According to the stage of the instruction in the vector processor, the behavior of the labeled instruction can occur before the instruction is launched, for example, the label is labeled when the instruction is decoded; that is, when the vector instruction requiring vector operation is decoded, the vector instruction requiring vector operation is labeled. It can also occur after the instruction occurs, and the vector instruction requiring vector operation is labeled according to the vector mode configuration information after the vector instruction enters the launch queue through the instruction distribution unit; the vector floating point unit selects the corresponding execution pipeline for execution according to the label.

[0042] The specific timing of the tagging of the instructions can be determined according to the specific micro-architecture design of the vector data processor.

[0043] S203: determining one or more execution pipelines of the N execution pipelines for the vector instruction according to the instruction computing mode. According to the foregoing example, this step can include assigning a launch queue for the vector instruction according to the instruction computing mode; and then launching the vector instruction in the launch queue to one or more execution pipelines of the N execution pipelines in the vector floating point unit according to the instruction computing mode corresponding to each launch queue. According to the foregoing description, in this mode, the tagging of the vector instruction occurs before the launching of the instruction, that is, first assigning a tag for the vector instruction according to the instruction computing mode; then the launch queue unit identifies the tag; the launch queue unit determines the launching mode and the execution mode of the vector instruction according to the tag indication; finally, the launch queue unit launches the vector instruction in the launch queue to one or more execution pipelines of the N execution pipelines in the vector floating point unit according to the tag indication.

[0044] In another implementation mode, the tagging occurs after the launching of the instruction, in which mode, the instruction distribution unit tags the vector instruction requiring vector operation according to the vector mode configuration information after the vector instruction enters the launch queue; and the vector floating point unit executes according to the tag indication.

[0045] S204: the execution pipelines in the vector floating point execution unit respectively execute the vector operation corresponding to the vector instruction.

[0046] Exemplarily, the execution pipelines of the vector floating point operation unit in the vector floating point unit respectively execute the vector operation corresponding to the vector instruction.

[0047] More specifically, this step can further include the vector floating point operation unit executing the vector operation instruction, sending the vector instruction to a corresponding operator engine, which executes the corresponding vector operation on the vector instruction; and the operator engine writes the vector operation result of the vector instruction back to the vector register.

[0048] The instruction processing method provided by the above embodiment, the vector data processor of the mixed width calculation mode in the embodiment can process large block data with a data width of VLEN at a low throughput, and the calculation mode is referred to as a long bit width calculation mode; and can also process small block data with a data bit width of DPLEN at a high throughput. The vector data processor can adjust the data path mode of the current vector execution according to the data block size, improve the throughput of processing small block data, and improve the performance of the large bit width vector register architecture processor when processing software loads with mixed size data block characteristics.

[0049] Figure 3 is a data flow mode diagram for metering data processing according to the instruction processing method provided by the embodiment of the application. It is assumed that according to steps S201-S204, the vector data processor has transmitted the vector instruction to the transmission queue according to the instruction calculation mode tag. After transmission from the transmission queue to the execution mode of the execution pipeline, the vector instruction can be transmitted to 1 to X execution pipelines for execution in different calculation modes. As shown in Figure 3 three possible transmission modes are described: the instruction in the transmission queue 0 is transmitted to the execution pipeline 0 for execution; the instruction in the transmission queue 1 is transmitted to the execution pipeline 0 and the execution pipeline M for execution; the instruction in the transmission queue N is transmitted to the execution pipeline 0, the execution pipeline M, and the execution pipeline M+L for execution; wherein the operation resources occupied by the instruction comply with the following principles: the instruction in the smaller calculation bit width mode uses fewer execution pipelines to complete the operation; the instruction in the larger calculation bit width mode uses more execution pipelines to complete the operation; assuming that the maximum data bit width that can be processed by each execution pipeline is DPLEN, it is easy to know Figure 3 as shown in the execution mode, the maximum calculation bit width supported by the instruction calculation mode in the transmission queue 0 is DPLEN, so only one execution pipeline is needed to complete the corresponding operation; the instruction in the transmission queue 1 is transmitted to the execution pipeline 0 and the execution pipeline M for execution, the maximum calculation bit width supported by the instruction calculation mode in the transmission queue 1 is 2*DPLEN, so two execution pipelines are needed to complete the operation; the instruction in the transmission queue 2 is transmitted to the execution pipeline 0, the execution pipeline M, and the execution pipeline M+L for execution, the maximum calculation bit width supported by the instruction calculation mode in the transmission queue 1 is 3*DPLEN, so three execution pipelines are needed to complete the operation.

[0050] In another embodiment, due to area and timing constraints, there is a certain limit on the distance between the issue queue and the corresponding execution pipeline, and usually it is not possible to have instructions in multiple compute modes in one issue queue, so the compute mode tag of the instruction not only determines the execution manner of the execution pipeline, but also determines the way of entering the issue queue.

[0051] Taking the number of issue queues as 4, the number of execution pipelines as 4, and the instruction supporting long bit-width compute mode and short bit-width compute mode as an example, a possible micro-architecture implementation of the vector processor architecture of the mixed width compute mode is shown in FIG. 3. Figures 3-5 The maximum compute bit-width supported by the long bit-width compute mode is the vector processor bit-width VLEN, and the maximum compute bit-width supported by the short bit-width compute mode is DPLEN, where VLEN = 2 * DPLEN.

[0052] According to the vector configuration mode, if the currently configured vector length is DPLEN, it is the short bit-width compute mode, and if the currently configured vector length is VLEN, it is the long bit-width compute mode. The vector length in the configuration mode determines the width of the vector data that can be processed at one time by the processor, and the distinction between the two compute modes can allocate different execution pipeline resources to execute the corresponding instructions according to the compute data width requirement, thereby improving the utilization efficiency of the execution pipeline.

[0053] The issue queue 301, the issue queue 302, the issue queue 303, and the issue queue 304 all support issuing vector instructions to the corresponding execution pipeline.

[0054] As shown in FIG. 3, Figure 4 In the short bit-width compute mode, the instruction can enter any one of the four issue queues. The instructions in the corresponding issue queue will be issued to the corresponding execution pipeline for operation, and the corresponding relationship is as follows: The instructions in the issue queue 301 are issued to the execution pipeline 300 for execution; The instructions in the issue queue 302 are issued to the execution pipeline 310 for execution; The instructions in the issue queue 303 are issued to the execution pipeline 320 for execution; The instructions in the issue queue 304 are issued to the execution pipeline 330 for execution; As shown in FIG. 3, Figure 5 and Figure 6 In the long bit-width compute mode, the vector instruction can enter any two of the issue queue 301 and the issue queue 302. The instructions in the corresponding issue queue will be issued to the corresponding execution pipeline for operation, and in the long bit-width compute mode, the corresponding relationship is as follows: The instructions in the issue queue 301 are dispatched to the execution pipeline 300 for execution, or to the execution pipeline group 340 for execution; The instructions in the issue queue 302 are dispatched to the execution pipeline 310 for execution, or to the execution pipeline group 350 for execution; As can be seen from the correspondence between the issue queues and the respective execution pipelines of the vector floating point unit, in this architecture, the short bit width calculation mode can support parallel execution of up to 4 vector instructions, and the long bit width calculation mode can support parallel execution of up to 2 vector instructions, so as to better exert the performance of the vector processor in the short bit width vector configuration mode.

[0055] To support the long bit width calculation mode and the short bit width calculation mode, the execution pipeline is designed such that most of the operator engines can process DPLEN bit width data per clock cycle. Such a design can meet the calculation bit width requirement of the short bit width calculation mode. A small number of operator engines are implemented to process VLEN bit width data per clock cycle.

[0056] In an embodiment of the present application, the operators in the execution pipeline are divided into symmetric operation operators and asymmetric operation operators. The symmetric operation operators complete symmetric operations, and the asymmetric operation operators complete asymmetric operations.

[0057] For the case of the first bit width VLEN=2*DPLEN (the second bit width), when the symmetric operation operators perform vector operations with a data bit width of the first bit width VLEN, the high bit (high DPLEN bit) and the low bit (low DPLEN bit) data in the first bit width VLEN bits complete the same operation process, and the two operation processes are not dependent on each other. For example, floating point or integer vector addition and floating point or integer vector multiplication belong to symmetric operations. The high bit data refers to the second bit width DPLEN data of the high bit in the calculation of the first bit width VLEN width data, and the low bit data refers to the second bit width DPLEN data of the low bit in the calculation of the first bit width VLEN width data.

[0058] When the asymmetric operation operators process vector operations with a bit width of VLEN, the high DPLEN bit and the low DPLEN bit data in the VLEN bits have different operation processes, and the two operations are dependent on each other. The operation result of the low DPLEN bit source data can depend on the operation of the high DPLEN bit data. For example, the operation performed by the vector permutation instruction reorders the vector data, and such an operation belongs to asymmetric operation.

[0059] The second bit width DPLEN is a computation width supported by the execution pipeline, the first bit width VLEN is a width of a vector register, the high bit data refers to second bit width DPLEN data of high bits in computation of first bit width VLEN width data, and the low bit data refers to second bit width DPLEN data of low bits in computation of first bit width VLEN width data.

[0060] For the long bit width computation mode, the vector instruction performing the symmetric operation will be split into high and low parts when being issued, and is sent to two execution pipelines to perform operations. For example, as shown in the data flow mode 370, the vector instruction performing the symmetric operation in the issue queue 301 will be simultaneously issued to the execution pipeline 310 and the execution pipeline 320, that is, the execution pipeline group 340 performs. If the vector instruction performs the asymmetric operation, in order to accelerate such operation, the asymmetric operation operator engine specially designed for performing the asymmetric operation is arranged in the execution pipeline 300 and the execution pipeline 310, as shown in the data flow mode 360, and the instruction is directly sent to the execution pipeline 300 or the execution pipeline 310 to perform.

[0061] The vector data processor in the embodiment can process large block data with a data width of VLEN at a low throughput, and the computation mode is referred to as a long bit width computation mode; and can also process small block data with a data bit width of DPLEN at a high throughput. The vector data processor can adjust the data path mode of the current vector execution according to the data block size, improve the throughput of processing small block data, and improve the performance of the large bit width vector register architecture processor when processing software loads with mixed size data block characteristics.

[0062] In the embodiment of the application, the two computation modes are distinguished, different execution pipeline resources are allocated according to the computation data width requirement to execute corresponding instructions, and the utilization efficiency of the execution pipeline is improved.

[0063] For the symmetric operation, the long bit width computation mode needs to use two execution pipelines to complete the operation, and the short bit width computation mode only needs one execution pipeline; for the asymmetric operation, considering the area overhead, only two VLEN width computation resources are implemented in two execution pipelines.

[0064] Corresponding to the embodiment of the instruction processing method, the specification also provides an embodiment of a system on chip, Figure 7 A structure schematic diagram of a system on chip provided by one embodiment of the specification is shown, the system on chip 700 includes but is not limited to a control unit 710 and a plurality of on-chip components 720, and the plurality of on-chip components 720 includes the vector data processor 100.

[0065] The control unit 710 is configured to control and manage the plurality of on-chip components 720.

[0066] The vector data processor 100 is configured to execute computer programs / instructions, which, when executed by the vector data processor 100, implement the steps of the instruction processing method described above.

[0067] The system on chip 700 is a system on chip level hardware device integrating a control unit 710 and a plurality of on-chip components 720, and is usually integrated with the control unit 710, and a plurality of on-chip components 720 such as a central processor, a digital signal processor, a vector data processor and an input / output interface (I / O). The system on chip 700 can improve performance, reduce power consumption and reduce physical size, and can be suitable for mobile devices, Internet of Things devices, embedded systems and other scenarios. The specific embodiments of the present application do not limit the specific implementation of the system on chip.

[0068] The control unit 710 is a core component in the system on chip 700, responsible for decoding instructions, controlling execution flow and coordinating work with the plurality of on-chip components 720. The control unit 710 controls and manages the work flow of the plurality of on-chip components 720 by sending control signals, and ensures that each on-chip component can correctly complete the task according to the predetermined order and logic.

[0069] The plurality of on-chip components 720 are various functional hardware components in the system on chip 700, which work together to complete specific tasks or functions. The plurality of on-chip components 720 can include but are not limited to a central processor, a digital signal processor, a vector data processor and an input / output interface.

[0070] The above is a schematic scheme of a system on chip according to the embodiment. It should be noted that the technical scheme of the system on chip belongs to the same concept as the technical scheme of the instruction processing method described above, and the details of the technical scheme of the system on chip that are not described in detail can be referred to the description of the technical scheme of the instruction processing method.

[0071] It should be noted that according to the needs of implementation, each component / step described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or part of the operations of the components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.

[0072] The above-described methods according to embodiments of the present application can be implemented in hardware, firmware, or software, or any combination thereof, and can be stored in a recording medium such as CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk, or be downloaded by network from a remote recording medium or non-transitory machine-readable medium originally stored in a remote recording medium or non-transitory machine-readable medium and to be stored in a local recording medium, so that such software implementing the methods described herein can be stored in a recording medium on a general-use computer, a special-purpose processor, or programmable or special-purpose hardware (such as ASIC or FPGA). It can be understood that the computer, processor, microprocessor controller, or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, processor, or hardware, the business object switching method described herein is implemented. Furthermore, when a general-purpose computer accesses the code for implementing the business object switching method shown herein, the execution of the code will convert the general-purpose computer into a special-purpose computer for executing the business object switching method shown herein.

[0073] Those skilled in the art can understand that the units and method steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0074] The above embodiments are only used to illustrate but not limit the embodiments of the present application, and a person of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, therefore all equivalent technical solutions belong to the scope of the embodiments of the present application, and the patent protection scope of the embodiments of the present application should be defined by the claims.

Claims

1. A method of processing instructions, applied to a vector data processor, characterized by, The vector data processor includes a vector register, a vector floating point unit, an instruction distribution unit, and a launch queue unit, the vector register has a first bit width, the vector floating point unit stores N execution pipelines, each of the execution pipelines supports a maximum data bit width of an operation, the maximum data bit width is a second bit width, the first bit width is greater than the second bit width, and the sum of N second bit widths is greater than the first bit width, wherein N is a multiple of 2, and the method includes: Obtaining a vector instruction requiring vector operation; According to the vector mode configuration information, determining the instruction calculation mode of the vector instruction, the vector mode configuration information including configuration information of adjusting the data path of the current vector execution by a data block size; According to the instruction calculation mode, determining one pipeline or multiple execution pipelines of the N execution pipelines for the vector instruction; The execution pipelines in the vector floating point unit respectively perform vector operations corresponding to the vector instruction.

2. The method of claim 1, wherein, Before the vector mode configuration information is determined according to the vector mode configuration information, the vector instruction calculation mode is determined, including: Reading the vector mode configuration information in the configuration information register.

3. The method of claim 1 or 2, wherein, According to the vector mode configuration information, determining the instruction calculation mode of the vector instruction, including: According to the vector mode configuration information, tagging the vector instruction requiring vector operation, and representing the instruction calculation mode through the tag.

4. The method of claim 3, wherein, According to the instruction calculation mode, assigning a launch queue for the vector instruction; According to the instruction calculation mode of each launch queue, launching the vector instruction in the launch queue to one pipeline or multiple execution pipelines of the N execution pipelines in the vector floating point unit. According to the instruction calculation mode, assigning a tag for the vector instruction; 5. The method of claim 4, wherein, The launch queue unit identifies the tag; According to the tag indication, determining the launch mode and execution mode of the vector instruction. According to the instruction calculation mode, assigning a launch queue for the vector instruction; According to the tag indication, launching the vector instruction in the launch queue to one pipeline or multiple execution pipelines of the N execution pipelines in the vector floating point unit.

6. The method of claim 5, wherein, According to the tag indication, launching the vector instruction in the launch queue to one pipeline or multiple execution pipelines of the N execution pipelines in the vector floating point unit. After the vector instruction requiring vector operation is obtained, the vector instruction requiring vector operation is further decoded. According to the vector mode configuration information, the vector instruction requiring vector operation is tagged, including:

7. The method of claim 1, wherein, When the vector instruction requiring vector operation is decoded, the vector instruction requiring vector operation is tagged. According to the instruction calculation mode, determining one pipeline or multiple execution pipelines of the N execution pipelines for the vector instruction; ​ 8. The method of claim 3, wherein, ​ After the vector instruction enters the dispatch queue, the vector instruction requiring vector operation is tagged according to vector mode configuration information; The corresponding execution pipeline is selected according to the tag to execute.

9. The method of claim 1, wherein, The execution pipeline in the vector floating point unit respectively executes the vector operation corresponding to the vector instruction; further comprising: The vector floating point execution unit executes the vector operation instruction, and sends the vector instruction to the corresponding operator engine, which executes the corresponding vector operation on the vector instruction; The operator engine writes the vector operation result of the vector instruction back to the vector register.

10. The method of claim 9, wherein, The operators in the execution pipeline include symmetric operation operators and asymmetric operation operators, the symmetric operation operators complete symmetric operations, and the asymmetric operation operators complete asymmetric operations.

11. The method of claim 10, wherein, When the symmetric operation operator executes the vector operation with a first bit width, the high bit data and the low bit data in the first bit width complete the same operation process, and the two operation processes are not dependent on each other; the high bit data refers to the second bit width data of the high bit in the data of the first bit width, and the low bit data refers to the second bit width data of the low bit in the data of the first bit width; When the asymmetric operation operator processes the vector operation of the first bit width, the high bit and the low bit data in the first bit width have different operation processes, and the two operations are dependent on each other, and the operation result of the low bit bit source data depends on the operation of the high bit data.

12. The method of claim 1, wherein, According to the vector mode configuration information, the instruction calculation mode of the vector instruction is determined, and the vector mode configuration information includes configuration information for adjusting the data path of the current vector execution through the data block size, and further comprising: According to at least one of the vector length configuration information in the vector mode configuration information and the predicate processing mode, the instruction calculation mode of the vector instruction is determined.

13. A vector data processor, characterized by The vector data processor includes a vector register, a vector floating point unit, an instruction distribution unit, and a dispatch queue unit, the vector register has a first bit width, the vector floating point unit stores N execution pipelines, each execution pipeline supports a maximum data bit width of second bit width for operation, the first bit width is greater than the second bit width, and the sum of N second bit widths is greater than the first bit width, wherein N is a multiple of 2, wherein the vector data processor further comprises: An instruction fetching unit is configured to obtain a vector instruction requiring vector operation; A mode configuration unit is configured to determine an instruction calculation mode of the vector instruction according to vector mode configuration information, wherein the vector mode configuration information includes configuration information for adjusting a data path of a current vector execution through a data block size; An instruction distribution unit is configured to determine one pipeline or multiple execution pipelines in N execution pipelines for the vector instruction according to the instruction calculation mode; A vector floating point unit is configured to control execution pipelines to respectively execute vector operations corresponding to the vector instruction.

14. A system on chip, characterized by Comprising: A control unit and a plurality of on-chip components, the plurality of on-chip components including a vector data processor; The control unit is configured to control the plurality of on-chip components, and the vector data processor is configured to execute a computer program / instructions that, when executed by the vector data processor, implement the method of any one of claims 1-12.

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