Access management device and method for storage device

Abstract

The invention provides an access management device and method for storage equipment. The apparatus and method utilize a task wait linked list to maintain an execution order of commands with overlapping logical block address ranges. The task waiting linked list is essentially a modified one-way linked list, the hardware resource overhead is relatively low, and when the number of received host commands is relatively large, the hardware resource overhead cannot be increased along with the increase of the number of the commands processed in parallel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of storage, and more particularly, to an access management device and method for a storage device. BACKGROUND

[0002] A storage system generally includes a host and one or more storage devices. The host device can issue various logical block related host commands to the storage device to manage data in the storage device. The logical block related host commands use LBA (Logic Block Address) and NLB (number of logic blocks) to describe a continuous LBA range, and perform read operations on data in the continuous LBA range. In some specific scenarios, there may be overlaps between the LBA ranges in these commands.

[0003] To meet the atomicity of the execution of the logical block related host commands, for the three command combinations of read & write, write & read, and write & write, the execution of the command with an overlapping LBA range needs to be prevented during the execution of the previous command, so that the command is in a waiting execution state. After the execution of the previous command ends, the command is allowed to continue execution. If there are multiple blocked read and write commands, these blocked read and write commands should be guaranteed to be executed in a certain order. SUMMARY

[0004] Therefore, embodiments of the present disclosure provide an access management device and method for a storage device to solve the technical problems in the prior art.

[0005] According to a first aspect of the present disclosure, an access management device for a storage device is provided, comprising:

[0006] A task scheduling management module configured to receive a logical block address associated host command, and invoke an LRT controller to check the host command, and add an identifier of the host command with an overlapping logical block address to the tail of a task waiting linked list according to a feedback result;

[0007] An LRT controller configured to compare whether a logical block address range associated with the host command overlaps with an existing logical block address range in a logical block address range table, and provide the feedback result, while adding related information of the host command in the logical block address range, the related information including a logical block address range of the host command, whether a state of the host command is valid, and whether the host command has an overlapping logical block address range;

[0008] The task scheduling management module assigns host commands without overlapping logical block address ranges to other components for execution, and modifies the status of the executed host commands from valid to invalid.

[0009] The task scheduling management module also periodically scans the task waiting chain table from the head to the tail using a scan pointer, and for each scanned host command, calls the LRT controller to compare the logical block address range of the host command with the logical block address range of the host command before the host command and the logical block address range of the host command without overlapping logical block address range and being executed, and updates whether the host command has overlapping logical block address range according to the comparison result, and deletes the identification of the host command without overlapping logical block address range from the task waiting chain table, wherein the task scheduling management module determines the host command before the host command using the time sequence relationship reflected by the task waiting chain table.

[0010] In some embodiments, the task scheduling management module also updates one or more of the head pointer, the tail pointer and the scan pointer of the task waiting chain table according to the operation on the task waiting chain table, and the host command before the host command is the host command defined by the range between the head pointer and the scan pointer.

[0011] In some embodiments, the related information of the host command further includes a flip flag, and the task scheduling management module further maintains a scan flag, and the scan flag and the flip flag both take values from a first value and a second value.

[0012] In some embodiments, when a new operation is added, the task scheduling management module sets the flip flag in the related information of the host command with overlapping logical block address range to the current value of the scan flag, and sets the flip flag in the related information of the host command without overlapping logical block address range to the first value.

[0013] The task scheduling management module also flips the flip flag in the related information of the host command indicated by the scan pointer from the current value to another value other than the current value as the scan pointer moves, and flips the scan flag from the current value to another value other than the current value when the scan pointer jumps from the tail pointer to the head pointer.

[0014] In some embodiments, the logical block address range table is obtained by the following steps:

[0015] retrieving the LRT to obtain a corresponding host command according to the identification of each host command.

[0016] In some embodiments, the task scheduling management module obtains the host command defined by the range between the head pointer and the scan pointer in the LRT by the following steps:

[0017] reading the identification of each host command between the head pointer and the scan pointer; and

[0018] retrieving the LRT to obtain a corresponding host command according to the identification of each host command.

[0019] In some embodiments, the LRT controller performs the operation of comparing whether the logical block address range associated with the comparison host command overlaps with the existing logical block address range in the LRT in parallel.

[0020] In some embodiments, when the task scheduling management module invokes the LRT controller to compare, if there is an overlap between the current host command and the existing logical block address range in the LRT, the comparison is stopped.

[0021] In some embodiments, the task waiting linked list is implemented by a fixed number of hardware storage units, including: allocating an index address of a free hardware storage unit to a host command to be stored as its identification, and storing an index address of a next host command linked with the host command in the free hardware storage unit.

[0022] According to a second aspect of the present disclosure, a memory controller is provided, including the above-mentioned access management device.

[0023] According to a third aspect of the present disclosure, a storage device is provided, including a storage medium and the above-mentioned memory controller.

[0024] According to a fourth aspect of the present disclosure, a method for checking whether a host command has an overlapping logical block address range is provided, in which a host device sends a host command to a storage device, and the method includes:

[0025] storing relevant information of the received host command into the LRT, the relevant information including a logical block address range of the host command, whether a state of the host command is valid, and whether the host command has an overlapping logical block address range;

[0026] store the received identification of the host command with overlapping logical block address range into a task waiting linked list, wherein the link relationship of each node of the task waiting linked list reflects the time sequence relationship of the corresponding host command;

[0027] periodically scan the task waiting linked list from head to tail, for each scanned host command, compare the logical block address range of the host command with the logical block address range of the host command before the host command and the logical block address range of the host command which does not have overlapping logical block address range and is being executed, and update the related information of the host command according to the comparison result, and delete the identification of the host command which does not have overlapping logical block address range from the task waiting linked list, wherein the host command before the host command is determined by using the time sequence relationship reflected by the task waiting linked list.

[0028] In some embodiments, further comprising: updating one or more of a head pointer, a tail pointer and a scan pointer of the task waiting linked list according to the operation on the task waiting linked list, wherein the host command before the host command is the host command defined by the range between the head pointer and the scan pointer.

[0029] In some embodiments, the related information further comprises a flip flag, and the method further comprises: maintaining a scan flag, wherein the scan flag and the flip flag both take values from a first value and a second value.

[0030] In some embodiments, further comprising: setting the flip flag of the related information of the host command with overlapping logical block address range equal to the current value of the scan flag, and setting the flip flag of the related information of the host command which does not have overlapping logical block address range as the first value.

[0031] As the scan pointer moves, the flip flag in the related information of the host command indicated by the scan pointer is flipped from the current value to another value other than the current value, and when the scan pointer jumps from the tail pointer to the head pointer, the scan flag is flipped from the current value to another value other than the current value.

[0032] The access management device provided by the embodiments of the present disclosure uses a task waiting linked list to maintain the execution order of the commands with overlapping logical block address range. The task waiting linked table is essentially a modified single-direction linked list, and the hardware resource overhead is relatively small. When the number of received host commands is large, the hardware resource overhead will not increase with the increase of the number of parallel processed commands. In addition, when the embodiments of the present disclosure check that the current host command and the existing logical block address range in the logical block address range table have overlapping logical block address range, the checking can be stopped, the checking task can be ended in advance, and the execution efficiency is relatively high. BRIEF DESCRIPTION OF DRAWINGS

[0033] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 A schematic block diagram of a storage system is shown;

[0035] Figure 2 is a structural schematic diagram of an access management device for a storage device provided by an embodiment of the present disclosure;

[0036] Figure 3 A schematic diagram of an exemplary task waiting linked list is provided;

[0037] Figure 4 is an exemplary diagram of a linked list design provided by an embodiment of the present disclosure;

[0038] Figure 5 is a flowchart of an access management method for a storage device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The present disclosure is described below based on embodiments. In the following, many specific details of the present disclosure are described in order to more clearly understand the present disclosure. But as those skilled in the art can understand, the present disclosure can be implemented without these specific details, that is, the present disclosure is not limited to only these embodiments. In order to avoid confusion of the essence of the present disclosure, well-known methods, processes, flows, chip devices, and chip circuits are not described in detail.

[0040] Similar reference signs are used in the various drawings to represent. In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0041] Figure 1A schematic block diagram of a storage system is shown. The storage system 100 can include a host device 110 (e.g., a host computer) 110 and a storage device 120. The host device 110 can issue host commands related to logical block addresses to the storage device 120, causing the storage device 120 to manage host data stored therein according to the commands. For example, the host device 110 can be communicably connected to the storage device 120 (e.g., over a storage interface) and can issue various commands (e.g., READ, WRITE, UNMAP, REASSIGN BLOCK, TRIM, etc.) to the storage device 120 along with one or more LBAs or LBA ranges associated therewith. The storage device 120 can store, update, and / or otherwise manage host data in one or more logical blocks associated with the one or more LBAs or LBA ranges. Once the commands are executed, the storage device 120 can transmit a response to the host device 110, indicating that the commands were successfully completed.

[0042] The host device 110 can include a processor 111 and a memory 112. The processor 111 can be a general purpose processor, such as a central processing unit (CPU) core of the host device 110. The memory 112 can be considered a high performance main memory of the host device 110. For example, in some embodiments, the memory 112 can be a volatile memory, such as a dynamic random access memory (DRAM), although the present disclosure is not so limited, the memory 112 can also be or include any suitable high performance main memory. For example, in other embodiments, the memory 112 can be a relatively higher performance non-volatile memory, such as a NAND flash memory, phase change memory (PCM), resistive RAM, spin transfer torque RAM (STTRAM), any suitable memory based on PCM technology, memristor technology, and / or resistive random access memory (ReRAM).

[0043] The storage device 120 is a secondary storage that can persistently store data accessible to the host device 110. In this case, the storage device 120 can be a relatively slower memory when compared to the memory 112. For example, in some embodiments, the storage device 120 is a secondary storage of the host device 110, such as a solid state drive (SSD), although the present disclosure is not so limited, in other embodiments, the storage device 120 can include (or can be) any suitable storage device, such as a magnetic storage device (e.g., a hard disk drive (HDD), etc.), an optical storage device (e.g., a Blu-ray disc drive, a compact disc (CD) drive, a digital versatile disc (DVD) drive, etc.), other kinds of flash memory devices (e.g., a USB flash drive, etc.), etc.

[0044] The host device 110 and the storage device 120 can communicate through a storage interface 130. For example, the host device 110 issues a command to the storage device 120 through the storage interface 130, and the storage device 120 provides feedback of the execution of the command through the storage interface 130. The type of the storage interface 130 is not limited in the present disclosure. For example, it can be one of Small Computer System Interface (SCSI), Non-Volatile Memory Express (NVMe), Peripheral Component Interconnect Express (PCIe), Remote Direct Memory Access over Ethernet (RDMA), Serial Advanced Technology Attachment (SATA), Fibre Channel, Serial Attached SCSI (SAS), and NVMe over Fabrics (NVMe-oF).

[0045] The storage device 120 can include a storage controller 121 and a storage medium 122. The storage controller 121 can be connected to the storage interface 130 and receive host commands from the host device 110 through the storage interface 130 and feed back the execution results of the commands to the host device 110. Each command has a continuous logical block address range (LBA range), which is represented by a start logical block address (SLBA) and a number of logical blocks (NLB).

[0046] Referring to the background art, during the execution of the previous host command, the execution of the current command with overlapping logical address range needs to be blocked, and the execution of the current command is allowed after the execution of the previous command ends. If there are multiple blocked host commands, these blocked host commands should be guaranteed to be executed in their original time sequence. To this end, the present disclosure provides an access management device arranged in a storage controller, which is used to complete the above functions.

[0047] As shown in FIG. 2, Figure 2 The access management device 200 includes a host command pipeline 203, a task scheduling management module 201, a task waiting linked list 202, an LRT controller 205, and a logical block address range table 206.

[0048] The host command pipeline 203 receives host commands issued by the host in the form of a pipeline, parses and processes these commands, and forwards the host commands associated with logical block addresses to the task scheduling management module 201.

[0049] The task scheduling management module 201 receives host commands associated with logical block addresses from the host command pipeline 203, calls the LRT controller 205 to check the host commands, and adds the identifiers of the host commands with overlapping logical block addresses to the tail of the task waiting linked list 202 according to the feedback results.

[0050] The LRT controller 205 includes a logical block address overlap checking module 2052 configured to check the logical block address range of a host command, check whether the logical block address range overlaps with an existing logical block address range in the logical block address range table 206, and provide a feedback result to the task scheduling management module 201. Meanwhile, the logical block address range table 206 is updated with information about the host command, including the logical block address range of the host command, whether the state of the host command is valid, and whether the host command has an overlapping logical block address range. The logical block address range of the host command can be represented by a start logical block address and a logical block quantity. When the host command has an overlapping logical block address range, the host command needs to wait until all host commands in front of it that overlap with it are executed. When the host command is added to the logical block address range table 206, the state of the host command is valid. When the host command is executed, the state of the host command becomes invalid.

[0051] The logical block address overlap checking module 2052 can be implemented by hardware resources, and the efficiency can be improved by pipeline grouping and parallel checking. For example, a plurality of logical address ranges in the logical block address range table 206 are divided into a plurality of groups, and a pipeline grouping and parallel checking manner is used to compare a to-be-checked logical block address range with one or more logical address ranges in the plurality of groups, so as to improve the checking speed. The number of groups is determined according to specific design requirements and design constraints, such as the maximum number of commands that can be executed in parallel in a storage device, hardware resource limitations, and the like. During the parallel comparison process, if the previous check has found an overlap, the checking task can be ended in advance, and it is not necessary to execute all checking pipelines.

[0052] The LRT controller 205 releases (or allows execution of) the host command that does not have an overlapping logical block address range (i.e., 2051 in the figure), so that the task scheduling management module 201 assigns the host command that does not have an overlapping logical block address range to other components for execution, and changes the state of the executed host command from valid to invalid.

[0053] The task scheduling management module 201 also periodically scans the task waiting list 202 from the head to the tail using a scan pointer. For each host command scanned, the LRT controller 205 is called to compare the host command with the host commands in the logical block address range table 206 that satisfy the first condition. If there is no overlap, the relevant information of the host command in the logical block address range table 206 is modified to be a logical block address range without overlap, and at the same time, the identification of the corresponding host command in the task waiting list 202 is deleted. In order to manage the task waiting list 202, the task scheduling management module 201 can maintain three pointers: a head pointer, a tail pointer and a scan pointer, and one or more of the three pointers are updated according to the operation on the task waiting list 202. In addition, the host commands in the logical block address range table 206 that satisfy the first condition include: the host commands in the logical block address range table 206 that are within the range defined by the head pointer and the scan pointer in the task waiting list, and the host commands without overlap and with a valid state.

[0054] In some embodiments, the task scheduling management module 201 includes an arbitration circuit for determining the command processing timing of the host command pipeline 203 and the task waiting list 202.

[0055] In some embodiments, the LRT controller 205 also obtains logical block address range related tasks from the software task queue (SWTQ) 204, performs tasks such as writing logical block address ranges to the logical block address range table 206, releasing logical block address ranges, checking logical block address range overlaps, rewriting the attributes of logical block address ranges, and returns the task execution results to the software task queue. For example, if the software expects to prevent the execution of host commands issued by the host that overlap with a certain or several logical block address ranges, the software can issue a write logical block address range task through the software task queue to write a certain or several logical block address ranges to the logical block address range table. When the task scheduling management module 201 calls the LRT controller 205 to check the logical block address ranges in the commands, the certain or several logical block address ranges written by the software can be compared with the logical block address ranges in the commands. This function can be used to implement the TRIM function in the storage system.

[0056] In some embodiments, the table design of the logical block address range table 206 is shown in Table 1.

[0057] Table 1

[0058]

[0059] Based on Table 1, when a record of a host command is added to the logical block address range table 206, the VLD of the record is set to 1 (valid), and if the host command and other host commands have overlapping logical block address ranges, the ACTIVE of the record is set to 0 (waiting), and if the host command and other host commands do not have overlapping logical block address ranges, the ACTIVE of the record is set to 1 (active); when the host command is executed, the VLD of the record is set to 0 (invalid); if the host command and other host commands change from having overlapping logical block address ranges to not having overlapping logical block address ranges as the host commands before the host command are executed one by one, the ACTIVE of the record is modified to 1 (active).

[0060] In combination with Table 1, Figure 3 An exemplary task waiting chain table is provided. As shown in the figure, each node includes an ID for identifying a host command and a NEXT for pointing to the next node. The HEAD and TAIL point to the head and tail of the chain table respectively, and the SCAN points to the current node. According to the chain table design of Figure 3 , the "comparing the current host command with the host commands in the task waiting chain table corresponding to the range defined by the head pointer and the scan pointer in the logical block address range table" in the above is: reading the ID in each node between the HEAD and the SCAN (including the SCAN and the HEAD), and then obtaining the logical block address range of each command in the logical block address range table 206 in Figure 2 , and comparing the logical block address range of the command corresponding to the SCAN with the logical block address ranges of the rest of the commands.

[0061] However, in order to save the hardware storage space required by the task waiting chain table 202, in some other embodiments, the task waiting chain table is implemented by a fixed number of hardware storage units, each of which has a unique index address, and for each received host command, the system allocates an index address of a free hardware storage unit to it, and stores the index address of the next host command linked to the host command in the free hardware storage unit. Figure 4 is an example of the present embodiment, the left side is the index address of each hardware storage unit, and the right side represents the index address of the next node stored in the corresponding hardware storage unit.

[0062] Further, the index address of the same host command in the task waiting chain table 202 is the same as its index address in the logical block address range table 206, so that the relevant information of the host command can be obtained from the logical block address range table 206 according to the current position of the scan pointer, and thus the hardware storage space required by the logical block address range table 206 can be saved.

[0063] In other embodiments, the table design of the logical block address range table 206 is shown in Table 2.

[0064] Table 2

[0065]

[0066] Table 2 adds a field ROLL to Table 1. This field is to simplify the comparison operation of the LRT controller 205. Meanwhile, the task scheduling management module 201 also needs to maintain a scan flag SCANFLAG, which can be stored in a register. Both the field ROLL and the scan flag SCANFLAG take values from a first value PI (e.g., 1) and a second value P0 (e.g., 0). The initial value of the scan flag SCANFLAG can be set to PI or P0. Now, the initial value of the scan flag SCANFLAG is set to PI for explanation. In addition, the processing of other fields in Table 2 can refer to the description of Table 1 above.

[0067] Whenever a record of a host command is added to the logical block address range table 206, the toggle flag ROLL of the related information of the host command with overlapping logical block address ranges is set to the current value of the scan flag SCANFLAG, and the toggle flag of the related information of the host command without overlapping logical block address ranges is set to PI.

[0068] When the scan pointer moves on the linked list, every time a new node is reached, the logical block address range of the host command in the logical block address range table 206 corresponding to the new node is compared with the logical block address range of the host command in the logical block address range table 206 defined by the head pointer and the scan pointer. The host command defined by the head pointer and the scan pointer satisfies the following condition (1):

[0069] ACTIVE == 0 && ROLL!= SCANFLAG (1)

[0070] Among them, condition (1) is that the current value of the toggle flag ROLL is opposite to the current value of the scan flag SCANFLAG and is a host command with overlapping addresses.

[0071] Meanwhile, the logical block address range of the host command in the logical block address range table 206 corresponding to the new node is compared with the logical block address range of the host command in the logical block address range table 206 satisfying the following condition (2):

[0072] ACTIVE == 1 && ROLL == PI && VLD == 1 (2)

[0073] The host command satisfying condition (2) is a host command currently being executed.

[0074] When the logical block address range of the host command in the logical block address range table 206 corresponding to the new node and the host command of condition (1) and (2) do not have an overlapping logical block address range, the host command is deleted from the task waiting chain table 202, and the ACTIVE of the host command in the logical block address range table 206 is changed to 1; each time a node is scanned, whether or not there is an overlapping logical block address range, the roll-over flag ROLL of each host command in the logical block address range table 206 defined by the head pointer and the scan pointer is flipped to the other value from the current value (i.e., P0 is flipped to P1, and P1 is flipped to P0), and when the scan pointer jumps from the tail pointer to the head pointer, the current value of the scan flag SCANFLAG is flipped to the other value (i.e., P0 is flipped to P1, and P1 is flipped to P0). This design is conducive to the hardware execution unit performing a batch comparison operation.

[0075] In an alternative, the task waiting chain table of the embodiments of the present disclosure can be implemented as two single-directional linked lists, specifically, two single-directional linked lists SLL1 and SLL2 are used to store all commands before the current command and other commands, respectively. Overall, SLL1 and SLL2 perform a ping-pong operation to realize the function of the single-directional linked list after modification in the above embodiment. Figure 2 In the initial state, SCANFLAG1 is P0, and the identification of the host command is inserted from the tail of SLL1. When it is detected that the command pointed to by the head pointer of SLL1 and the existing logical block address range in the logical block address range table have an overlapping logical block address range, the task scheduling management module removes the command from SLL1 and then inserts it into the tail of SLL2. At the same time, the roll-over flag ROLL of the command pointed to by the head pointer is flipped (P0 is flipped to P1, and P1 is flipped to P0). If it is detected that the command pointed to by the head pointer of SLL1 and the existing logical block address range in the logical block address range table do not have an overlapping logical block address range, the task scheduling management module removes the command from SLL1, then marks the command as P1 and changes it to the active state so that it can continue to be normally executed. After the commands in SLL1 are all removed, SCANFLAG1 is also flipped to 1. Then the functions of SLL1 and SLL2 are exchanged, the identification of the host command is inserted from the tail of SLL2, and the task scheduling management module also detects whether the command pointed to by the head pointer of SLL2 has an overlapping logical block address range with the existing logical block address range in the logical block address range table. In this way, the execution order of the commands having an overlapping logical block address range is maintained through the two single-directional linked lists.

[0076] Correspondingly, the embodiments of the present disclosure also provide an access management method for a storage device, as shown in Figure 5 the accompanying drawings.

[0077] In step S510, the relevant information of the received host command is stored into the logical block address range table, the relevant information including the logical block address range of the host command, whether the status of the host command is valid, and whether the host command has overlapping logical block address range.

[0078] In step S520, the identification of the received host command having overlapping logical block address range is stored into the task waiting chain table, wherein the link relationship of each node of the task waiting chain table reflects the time sequence relationship of the corresponding host command.

[0079] In step S530, the task waiting chain table is scanned periodically from head to tail, for each scanned host command, the logical block address range of the host command is compared with the logical block address range of the host command before the host command having overlapping logical block address, the logical block address range of the host command not having overlapping logical block address range and being executed, and the relevant information of the host command is updated according to the comparison result, and the identification of the host command not having overlapping logical block address range is deleted from the task waiting chain table, wherein the host command before the host command is determined by the time sequence relationship reflected by the task waiting chain table.

[0080] In further embodiments, when the operation on the task waiting chain table correspondingly updates one or more of the head pointer, the tail pointer and the scan pointer of the task waiting chain table, the host command before the host command defined by the scan pointer is located by the range between the head pointer and the scan pointer.

[0081] In further embodiments, the relevant information of the host command stored by the table structure further includes a flip flag, and the system further maintains a scan flag SCANFLAG, both the scan flag SCANFLAG and the flip flag taking values from a first value and a second value, when data is incorporated into the table structure, the flip flag of the relevant information of the host command having overlapping logical block address range is set equal to the current value of the scan flag, and the flip flag of the relevant information of the host command not having overlapping logical block address range is set to the first value, and when the task waiting chain table is scanned, as the scan pointer moves, the flip flag in the relevant information of the host command indicated by the scan pointer is flipped from the current value to another value other than the current value, and when the scan pointer jumps from the tail pointer to the head pointer, the scan flag is flipped from the current value to another value other than the current value.

[0082] It should be understood that embodiments of the method correspond to the above embodiments of the apparatus, and are therefore described in a relatively brief manner here.

[0083] In summary, the device and method provided by the embodiments of the present disclosure have the beneficial effects that using a wait queue in the form of a linked list to maintain the execution order of commands with overlapping logical block address ranges can reduce hardware resource overhead and lower product cost.

[0084] In accordance with the embodiments of the present disclosure as described above, these embodiments do not describe all the details of the application, nor limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. The description of the embodiments is chosen and described in order to provide the best and most clear implementation of the principles of the present disclosure and its practical application, so that those skilled in the art can well utilize the present disclosure and make modifications based on the present disclosure.

Claims

1. An access management apparatus for a storage device, comprising: a task scheduling management module configured to receive host commands associated with logical block addresses, and invoke a LRT controller to check the host commands and add an identifier of a host command having an overlapping logical block address to a tail of a task waiting linked list according to a feedback result; a LRT controller configured to compare a logical block address range associated with a host command with an existing logical block address range in a logical block address range table, and provide the feedback result, while adding relevant information of a new host command in the logical block address range, the relevant information including a logical block address range of the host command, whether a status of the host command is valid, and whether the host command has an overlapping logical block address range; wherein the task scheduling management module assigns a host command not having an overlapping logical block address range to other components for execution, and modifies a status of an executed host command from valid to invalid; the task scheduling management module is further configured to periodically scan the task waiting linked list from a head to a tail using a scan pointer, and for each scanned host command, invoke the LRT controller to compare a logical block address range of the host command with a logical block address range of a host command before the host command having an overlapping logical block address and a logical block address range of a host command before the host command not having an overlapping logical block address and being executed, update whether the host command has an overlapping logical block address range according to a comparison result, and delete an identifier of a host command not having an overlapping logical block address range from the task waiting linked list, wherein the task scheduling management module determines the host command before the host command using a time sequence relationship reflected by the task waiting linked list.

2. The access management apparatus according to claim 1, wherein the task scheduling management module further updates one or more of a head pointer, a tail pointer and a scan pointer of the task waiting linked list according to an operation on the task waiting linked list, and the host command before the host command is a host command defined by a range between the head pointer and the scan pointer.

3. The access management apparatus according to claim 2, wherein the relevant information of the host command further includes a flip flag, and the task scheduling management module further maintains a scan flag, and the scan flag and the flip flag both take a value from a first value and a second value. 4.The access management apparatus of claim 3, wherein the task scheduling management module sets the flip flag in the relevant information of a host command having an overlapping logical block address range to a current value of the scan flag and sets the flip flag in the relevant information of a host command not having an overlapping logical block address range to the first value when adding a new operation; the task scheduling management module further flips the flip flag in the relevant information of a host command indicated by the scan pointer from a current value to another value other than the current value as the scan pointer moves, and flips the scan flag from a current value to another value other than the current value when the scan pointer jumps from the tail pointer to the head pointer.

5. The access management apparatus according to claim 3 or 4, wherein The task scheduling management module obtains the host commands in the range between the head pointer and the scan pointer in the logical block address range table by the following steps: Retrieving the logical block address range table to obtain the host commands with the overlapping logical block address range whose current value of the flip flag is opposite to the current value of the scan flag as the corresponding host commands.

6. The access management device of claim 2, wherein, The task scheduling management module obtains the host commands in the range between the head pointer and the scan pointer in the logical block address range table by the following steps: Reading the identification of each host command between the head pointer and the scan pointer; and Retrieving the logical block address range table according to the identification of each host command to obtain the corresponding host command.

7. The access management apparatus according to claim 1, wherein The LRT controller performs the operation of comparing whether the logical block address range associated with the comparison host command overlaps with the existing logical block address range in the logical block address range table in parallel.

8. The access management device of claim 1, wherein, When the task scheduling management module calls the LRT controller to compare, if there is an overlap between the host command and a logical block address range in the logical block address range table, the comparison is stopped.

9. The access management apparatus according to any one of claims 1 to 4, wherein The task waiting linked list is implemented by a fixed number of hardware storage units, including: allocating the index address of a free hardware storage unit to the host command to be stored as its identification, and storing the index address of the next host command linked with the host command in the free hardware storage unit.

10. A memory controller comprising the access management device of any one of claims 1 to 9.

11. A storage device comprising a storage medium and the memory controller of claim 10.

12. An access management method for a storage device, wherein a host device sends a host command to the storage device, the method comprising: storing the relevant information of the received host command into a logical block address range table, the relevant information including the logical block address range of the host command, whether the status of the host command is valid, and whether the host command has an overlapping logical block address range; storing the identification of the received host command with the overlapping logical block address range into a task waiting linked list, wherein the link relationship of each node of the task waiting linked list reflects the time sequence relationship of the corresponding host command; periodically scanning the task waiting linked list from the head to the tail, for each scanned host command, comparing the logical block address range of the host command with the logical block address range of the host command before the host command with the overlapping logical block address, the logical block address range of the host command without the overlapping logical block address range and the logical block address range of the host command being executed, and updating the relevant information of the host command according to the comparison result, and deleting the identification of the host command without the overlapping logical block address range from the task waiting linked list, wherein the host command before the host command is determined by using the time sequence relationship reflected by the task waiting linked list.

13. The access management method of claim 12, further comprising: The head pointer, the tail pointer and the scan pointer of the task wait list are updated according to the operation on the task wait list, and a host command before the host command is a host command defined by a range between the head pointer and the scan pointer.

14. The access management method according to claim 13, wherein, The related information further includes a flip flag, and the method further includes: maintaining a scan flag, the scan flag and the flip flag each taking a value from a first value and a second value.

15. The access management method of claim 14, further comprising: setting the flip flag of the related information of the host command with the overlapping logical block address range equal to the current value of the scan flag, and setting the flip flag of the related information of the host command without the overlapping logical block address range to the first value; as the scan pointer moves, flipping the flip flag in the related information of the host command indicated by the scan pointer from the current value to another value other than the current value, and flipping the scan flag from the current value to another value other than the current value when the scan pointer jumps from the tail pointer to the head pointer.

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