Heterogeneous multi-core inter-core communication method and system, terminal equipment and storage medium

Abstract

The invention provides a heterogeneous multi-core inter-core communication method and system, terminal equipment, a storage medium and a program product. The heterogeneous multi-core inter-core communication method is applied to a heterogeneous multi-core inter-core communication system, the heterogeneous multi-core inter-core communication system comprises a plurality of communication sending cores and a plurality of communication receiving cores, and the method comprises the following steps: the plurality of communication sending cores sequentially obtain hardware locks according to communication needs; the plurality of communication sending cores sequentially apply for communication areas from the shared memory pool according to the sequence of obtaining the hardware locks; the plurality of communication sending cores write data into the communication area and send the data; and the plurality of communication sending cores notify the communication receiving core in a triggering interruption mode. According to the application, the data is written into the shared memory pool through the plurality of communication sending cores at the same time and sent, the application is suitable for a communication system of multiple producers and multiple consumers, the concurrency and high efficiency of data receiving and sending are supported at the same time, and multi-thread and multi-task simultaneous inter-system communication is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of shared memory communication, and in particular to a heterogeneous multi-core inter-core communication method and system, a terminal device, a storage medium and a program product. BACKGROUND

[0002] Multi-system communication, multi-machine system intercommunication, and multi-thread communication in a system commonly use shared memory communication. The application scenarios of existing shared memory communication patents are mainly between multi-threads and multi-machine systems.

[0003] In the process of conceiving and implementing the present application, the inventors found that at least the following problems exist: the intercommunication function between multi-core systems needs to ensure the reliability of communication while taking into account the real-time performance of each system and the simultaneous multi-thread and multi-task system intercommunication, etc. However, in some solutions, multi-core intercommunication requires complex protocol specifications or relies on special hardware or only supports one-to-one communication function. Moreover, complex communication protocols are not conducive to porting to processors with limited resources (memory resources) and do not have enough flexibility to meet different application scenarios.

[0004] The foregoing description is intended for general background information and does not necessarily constitute the prior art. SUMMARY

[0005] The embodiments of the present application provide a heterogeneous multi-core inter-core communication method, system, terminal device, storage medium and program product to solve the problem of simultaneous multi-thread and multi-task system intercommunication.

[0006] In a first aspect, the embodiments of the present application provide a heterogeneous multi-core inter-core communication method. The method is applied to a heterogeneous multi-core inter-core communication system, which includes a plurality of communication sending cores and a plurality of communication receiving cores. The method includes the following steps:

[0007] The plurality of communication sending cores sequentially acquire hardware locks according to communication needs;

[0008] The plurality of communication sending cores sequentially apply for communication areas from a shared memory pool according to the order of acquiring the hardware locks;

[0009] The plurality of communication sending cores write data into the communication areas and send the data;

[0010] The plurality of communication sending cores notify the communication receiving cores by triggering an interrupt.

[0011] In one embodiment, the communication sending core includes a memory for managing the shared memory pool. The plurality of communication sending cores write data into the communication areas and send the data, specifically including the following steps:

[0012] The communication sending core configures attribute information of the communication region in the memory, the attribute information of the communication region including a start address offset and memory of the shared memory pool, and updates a free space head offset;

[0013] The plurality of communication sending cores release the hardware lock;

[0014] The communication sending core reacquires the hardware lock after writing data into the communication region;

[0015] The communication sending core configures a valid data tail offset at a tail of the communication region, and re-releases the hardware lock after completing data sending.

[0016] In one of the embodiments, the first communication sending core acquires the hardware lock according to communication needs, and applies for a communication region from the shared memory pool;

[0017] The first communication sending core configures attribute information of the communication region in the memory, and updates the free space head offset, and releases the hardware lock after completion;

[0018] The i-th communication sending core acquires the hardware lock according to communication needs, and applies for a communication region from the shared memory pool;

[0019] The i-th communication sending core configures attribute information of the communication region in the memory, and updates the free space head offset, and releases the hardware lock after completion, wherein i>1.

[0020] In one of the embodiments, the order in which the communication sending core reacquires the hardware lock is consistent with the order in which the communication sending core acquires the hardware lock for the first time.

[0021] In one of the embodiments, before the plurality of communication sending cores acquire the hardware lock in sequence according to communication needs, the method further comprises:

[0022] The plurality of communication sending cores perform a memory initialization process.

[0023] In one of the embodiments, the plurality of communication sending cores perform a memory initialization process, specifically comprising:

[0024] The plurality of communication sending cores initialize the memory;

[0025] The plurality of communication sending cores acquire the hardware lock from system resources, and the hardware lock is used for mutual exclusion access of the shared memory pool;

[0026] The plurality of communication sending cores configure a local interrupt, and the local interrupt is used for responding to a notification of other cores.

[0027] In one of the embodiments, before the plurality of communication sending cores acquire the hardware lock in sequence according to communication needs, the method further comprises:

[0028] determining whether the memory size in the memory is greater than or equal to a first preset value;

[0029] if the memory size in the memory is less than the first preset value;

[0030] The plurality of communication sending cores notify the communication receiving cores to unblock by triggering an interrupt.

[0031] In a second aspect, the application provides a heterogeneous multi-core inter-core communication method, which is applied to a heterogeneous multi-core inter-core communication system including a plurality of communication sending cores and a plurality of communication receiving cores. The method includes the following steps:

[0032] The plurality of communication receiving cores acquire hardware locks in sequence according to communication needs.

[0033] The plurality of communication receiving cores apply for communication areas from the shared memory pool in sequence according to the order of acquiring the hardware locks.

[0034] The plurality of communication receiving cores read data from the communication areas.

[0035] The plurality of communication receiving cores notify the communication sending cores by triggering an interrupt.

[0036] In one embodiment, the communication sending core includes a memory for managing the shared memory pool. The plurality of communication receiving cores read data from the communication areas, and the reading specifically includes the following steps:

[0037] The plurality of communication receiving cores configure attribute information of the communication areas in the memory, the attribute information of the communication areas including a start address offset and a memory of the shared memory pool, and update a valid data header offset.

[0038] The plurality of communication receiving cores release the hardware locks.

[0039] The communication receiving cores acquire the hardware locks again after reading data from the communication areas.

[0040] The communication receiving cores update an idle space tail offset at the tail of the communication areas, and release the hardware locks again after completing data reception.

[0041] The communication receiving cores notify the communication sending cores by triggering an interrupt.

[0042] In one embodiment, before the plurality of communication receiving cores acquire the hardware locks in sequence according to the communication needs, the method further includes the following steps:

[0043] The plurality of communication receiving cores perform a memory initialization process.

[0044] In a third aspect, the application further provides a heterogeneous multi-core inter-core communication system including a plurality of communication sending cores, a plurality of communication receiving cores, a hardware lock module, and a shared memory pool. The plurality of communication sending cores are configured to perform the following steps:

[0045] The plurality of communication sending cores acquire the hardware lock in sequence according to communication needs;

[0046] The plurality of communication sending cores apply for a communication area to the shared memory pool in sequence according to the sequence of acquiring the hardware lock;

[0047] The plurality of communication sending cores write data into the communication area and send simultaneously;

[0048] The plurality of communication sending cores notify the communication receiving core by triggering an interrupt.

[0049] In one embodiment, the communication sending core and the communication receiving core include an application module, an intermediate module and a porting layer module;

[0050] The hardware lock module is used to limit access of one of the communication sending core and the communication receiving core to the shared memory pool.

[0051] In one embodiment, the intermediate module includes a memory, and the memory includes a data interface;

[0052] The communication sending core writes data into the shared memory pool through the data interface, and the communication receiving core reads data from the shared memory pool through the data interface.

[0053] In a fourth aspect, the application further provides a terminal device, including: a heterogeneous multi-core inter-core communication system, the heterogeneous multi-core inter-core communication system including a plurality of communication sending cores, a plurality of communication receiving cores and a shared memory pool, each core being configured with a memory;

[0054] The memory stores computer execution instructions;

[0055] The processor executes the computer execution instructions stored in the memory, so that the processor executes the heterogeneous multi-core inter-core communication method as any of the above.

[0056] In a fifth aspect, the application further provides a computer readable storage medium, the computer readable storage medium storing computer execution instructions, the computer execution instructions being executed by a processor to implement the heterogeneous multi-core inter-core communication method as any of the above.

[0057] In a sixth aspect, the application further provides a computer program product, including a computer program, the computer program being executed by a processor to implement the heterogeneous multi-core inter-core communication method as any of the above.

[0058] The application provides a heterogeneous multi-core inter-core communication method, system, terminal equipment, storage medium and program product. The method is applied to a heterogeneous multi-core inter-core communication system. The heterogeneous multi-core inter-core communication system comprises a plurality of communication sending cores and a plurality of communication receiving cores. The method comprises the following steps: the plurality of communication sending cores sequentially acquire hardware locks according to communication needs; the plurality of communication sending cores sequentially apply for communication areas to a shared memory pool according to the order of acquiring the hardware locks; the plurality of communication sending cores write data into the communication areas and send the data; and the plurality of communication sending cores notify the communication receiving cores by triggering an interrupt. The plurality of communication sending cores simultaneously write data into the shared memory pool and send the data, which is suitable for a multi-producer and multi-consumer communication system, supports the concurrency and high efficiency of data transmission, and realizes the inter-system communication of multiple threads and multiple tasks at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0059] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0060] Figure 1 A structure schematic diagram of a heterogeneous multi-core inter-core communication system according to an embodiment of the application is provided.

[0061] Figure 2 A flowchart of a heterogeneous multi-core inter-core communication method according to an embodiment of the application is provided.

[0062] Figure 3 A flowchart of a heterogeneous multi-core inter-core communication (IPC) initialization method according to an embodiment of the application is provided.

[0063] Figure 4 A structure schematic diagram of a ring buffer according to an embodiment of the application is provided.

[0064] Figure 5 A flowchart of a data sending method of a communication sending core according to an embodiment of the application is provided.

[0065] Figure 6 A data format diagram according to an embodiment of the application is provided.

[0066] Figure 7 A flowchart of a data receiving method of a communication receiving core according to an embodiment of the application is provided.

[0067] Figure 8 A flowchart of a data receiving method of a communication receiving core according to an embodiment of the application is provided.

[0068] Figure 9 A structure schematic diagram of a heterogeneous multi-core inter-core communication system according to an embodiment of the application is provided.

[0069] The specific embodiments of the application have been shown and described in considerable detail in order to explain the application clearly and to enable one skilled in the art to practice the application. These exemplary embodiments are not intended to limit the scope of the application in any way, but rather to illustrate the principles of the application. DETAILED DESCRIPTION

[0070] The exemplary embodiments will be described in relation to the drawings. When the description below refers to portions, areas, and regions, these are meant to be examples only and are not meant to be limiting in any way. These exemplary embodiments are not meant to limit the scope of the application in any way, but rather to illustrate the principles of the application.

[0071] First, the terms involved in the present application are explained:

[0072] Spinlock: Spinlock is a synchronization mechanism used in multi-threaded programming to protect shared resources from being accessed by multiple threads simultaneously. The characteristic of spinlock is that when a thread tries to acquire the lock, if the lock is already held by another thread, the thread will keep looping (spinning) until the lock is released.

[0073] Heterogeneous multi-core: Heterogeneous multi-core refers to a processor chip that integrates multiple processing cores with different architectures, performance characteristics, or power consumption characteristics. Heterogeneous multi-core processors are usually composed of multiple cores of different types, such as high-performance cores, low-power cores, and graphics processing cores, to perform different types of tasks or workloads on the processor simultaneously.

[0074] Shared memory pool: Shared memory pool refers to a mechanism for sharing memory resources between multiple processes or threads. In a shared memory pool, multiple processes or threads can access the same memory area to achieve data sharing, communication, and collaboration.

[0075] IPC: Inter-Process Communication (IPC) refers to a mechanism for different processes to exchange data and communicate with each other. Through IPC, different processes can pass data, share resources, and work together.

[0076] FIFO: FIFO (First In, First Out) is a data structure also known as a first-in, first-out queue. In a FIFO queue, the elements that enter the queue first will be removed first.

[0077] Ring buffer: A data structure also known as a circular buffer or circular queue. It is a fixed-size buffer that can store a certain amount of data and supports efficient read and write operations. The characteristic of a ring buffer is that data is stored in a circular memory area, when writing data exceeds the end of the buffer, data will be stored from the beginning of the buffer, forming a circular storage structure.

[0078] The intercommunication function between multi-core systems not only guarantees the reliability of communication, but also takes into account the real-time performance of each system and the simultaneous communication between multi-thread and multi-task systems. There are three existing solutions to solve the problem of heterogeneous multi-core intercommunication, the first is based on complex protocol specifications, such as using the RPMsg protocol specification and the corresponding underlying hardware to realize data communication between heterogeneous platforms, which may be different systems or application codes on RPMsg, but this solution is not suitable for porting to resource-constrained processors, and its flexibility is not enough to adapt to different application scenarios. The second solution is to use special hardware support, but it will increase the complexity and cost of hardware design, and the third solution is one-to-one communication, which only requires a sender and a supporter to complete, which cannot meet the concurrency and efficiency requirements of multi-core intercommunication data transmission.

[0079] Figure 1 The structure diagram of the heterogeneous multi-core intercommunication system provided by an embodiment of the present application is shown in FIG. 1, and the specific application scenario of the present application is to support a complex scenario of multiple producers and multiple consumers. The cores where the producers and consumers are located can be completely different hardware architectures, or the same architecture but different systems. The present application also provides a heterogeneous multi-core intercommunication system, which includes multiple communication sending cores (producers), multiple communication receiving cores (consumers), a hardware lock module, and a shared memory pool. The communication sending core and the communication receiving core include an application module, an intermediate module, and a transplantation layer module. Figure 1

[0080] The hardware lock module is used to limit access to the shared memory pool by one of the communication sending core and the communication receiving core.

[0081] In one embodiment, the intermediate module includes a memory, and the memory includes a data interface.

[0082] The communication sending core writes data to the shared memory pool through the data interface, and the communication receiving core reads data from the shared memory pool through the data interface.

[0083] ​In one of the embodiments, the memory is a fifo memory. In one of the embodiments, the heterogeneous multi-core inter-core communication system includes a plurality of consumer cores, a plurality of producer cores, a spin lock module, and a shared memory pool, the plurality of producer cores include producer0, producer1, …, producerM, the plurality of consumer cores include consumer0, consumer1, …, consumerN, each core is divided into an application module, a middleware module, and a porting layer module, wherein the code or implementation logic of the application module and the middleware module of each core is the same, the porting layer module of each core allows differences, the code or implementation logic of the application module and the middleware module of each core is the same, the software data interface consistency of each core is high, and the ipc functions on different cores can be maximally guaranteed to be consistent.

[0084] The middleware module of each core includes a memory, and the memory includes a data interface, the producer and the consumer transmit and receive data from the shared memory pool through the data interface, and it can be understood that the producer and the consumer manage a shared memory through the data interface. On different heterogeneous cores or different systems, the underlying hardware interface may differ, and the same interface needs to be adapted to support the related functions of the middleware module, for example, a hardware lock acquisition core release interface for implementing mutual exclusion, an inter-core interrupt triggering core response interface, and the like.

[0085] On the basis of the fifo, the data can be encapsulated in a certain format, such as a fixed number of data blocks transmission and reception. An inter-core interaction protocol can also be designed, such as information transmission and processing, remote process scheduling (rpc), and the like.

[0086] The heterogeneous multi-core inter-core communication method provided in the application is applied to a heterogeneous multi-core inter-core communication system including a plurality of communication sending cores and a plurality of communication receiving cores, and includes the following steps: the plurality of communication sending cores simultaneously write data into a shared memory pool and send; and the plurality of communication receiving cores simultaneously receive data from the shared memory pool. The application simultaneously writes or receives data into or from the shared memory pool through the plurality of communication sending cores and the plurality of communication receiving cores, adapts to a multi-producer and multi-consumer communication system, simultaneously supports the concurrency and efficiency of data transmission and reception, achieves multi-thread and multi-task simultaneous system communication, adapts to different application scenarios, and meets the concurrency and efficiency requirements of multi-core inter-core communication data transmission and reception.

[0087] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0088] See Figure 1 Each core's intermediate module provides a basic set of inter-core data transmission and reception interfaces. For both the sending and receiving cores, data writing and reading are accomplished by calling these data interfaces. Each core manages a shared memory segment through these interfaces. Multiple sending cores can simultaneously write and send data to the shared memory pool, and multiple receiving cores can simultaneously read data from the shared memory pool, ensuring concurrency and efficiency for data transmission and reception in multi-core application scenarios.

[0089] Both the communication sending core and the communication receiving core can send and receive data. In order to make a distinction, the principles of the communication sending core reading data from the shared memory pool and the communication receiving core sending data to the shared memory pool will not be described in detail in this application. Please refer to the cases of the communication sending core writing data to the shared memory pool and the communication receiving core reading data from the shared memory pool.

[0090] This application also provides a method for inter-core communication in heterogeneous multi-core systems, such as... Figure 2 As shown, Figure 2 This is a flowchart of a heterogeneous multi-core inter-core communication method according to an embodiment of this application. The method is applied to a heterogeneous multi-core inter-core communication system, which includes multiple communication transmitting cores and multiple communication receiving cores. The method includes:

[0091] Step S202: Multiple communication sending cores acquire hardware locks sequentially according to communication needs;

[0092] Specifically, multiple communication sending cores need to mutually exclude each other when accessing the shared memory pool simultaneously to avoid data corruption. Therefore, the communication sending core requests a hardware lock from the hardware lock module before communication. The hardware lock module can only allow one core to hold the hardware lock at a time, which can ensure mutual exclusion of shared memory pool access and prevent data corruption caused by multiple cores accessing the shared memory pool simultaneously.

[0093] Step S204: Multiple communication sending cores apply for communication areas from the shared memory pool in the order in which they acquire hardware locks;

[0094] Specifically, taking two communication sending cores as an example, the first communication sending core acquires a hardware lock first, then applies for a communication region to the shared memory pool, and releases the hardware lock after completion, and then the second communication sending core acquires the hardware lock, then applies for a communication region to the shared memory pool, and releases the hardware lock after completion. When the first communication sending core holds the hardware lock, the second communication sending core is in a blocking state, so that only one core can access the shared memory pool, and data disorder is avoided.

[0095] In step S206, the plurality of communication sending cores write data into the communication region and send the data.

[0096] In step S208, the plurality of communication sending cores notify the communication receiving core by triggering an interrupt.

[0097] Specifically, the application needs to notify the communication receiving core when new data is written into the shared memory pool, and also needs to notify the communication sending core when new space is released, and the notification operation is completed by triggering an interrupt between cores.

[0098] In one embodiment, the hardware lock is a spin lock.

[0099] In one embodiment, the communication sending core includes a memory for managing the shared memory pool; the plurality of communication sending cores write data into the communication region and send the data, specifically including the following steps:

[0100] The communication sending core configures attribute information of the communication region in the memory, and the attribute information of the communication region includes a start address offset and a memory of the shared memory pool, and updates a free space header offset;

[0101] The plurality of communication sending cores release the hardware lock;

[0102] Specifically, in order to avoid congestion, the communication sending core and the communication receiving core release the hardware lock after performing the corresponding operation, and the blocking state is released.

[0103] The communication sending core acquires the hardware lock again after writing data into the communication region;

[0104] Specifically, the order of the communication sending core acquiring the hardware lock again after writing data into the communication region is consistent with the order of acquiring the hardware lock for the first time.

[0105] The communication sending core configures a valid data tail offset at the tail of the communication region, and releases the hardware lock again after completing the data sending.

[0106] Specifically, the order of the communication sending core releasing the hardware lock is consistent with the order of acquiring the hardware lock for the first time.

[0107] In one embodiment, the first communication sending core acquires a hardware lock according to communication needs and requests a communication area from the shared memory pool;

[0108] The first communication sending core configures the attribute information of the communication region in memory, updates the free space header offset, and releases the hardware lock after completion;

[0109] The i-th communication sending core acquires a hardware lock according to communication needs and requests a communication area from the shared memory pool;

[0110] The i-th communication sending core configures the attribute information of the communication region in memory and updates the free space header offset. After completion, it releases the hardware lock, where i > 1.

[0111] In one embodiment, the order in which the communication sending core acquires the hardware lock again is the same as the order in which the communication sending core first acquires the hardware lock.

[0112] In one embodiment, the hardware lock is a spinlock.

[0113] In one embodiment, prior to step S202, the method further includes:

[0114] Multiple communication cores perform the memory initialization process.

[0115] In one embodiment, multiple communication sending cores perform a memory initialization process, specifically including:

[0116] Multiple communication sending cores initialize memory;

[0117] Multiple communication sending cores acquire hardware locks from system resources; these hardware locks are used for mutual exclusion access to the shared memory pool.

[0118] Multiple communication sending cores are configured with local interrupts, and local terminals are used to respond to notifications from other cores.

[0119] like Figure 3 As shown, Figure 3 A flowchart of a heterogeneous multi-core inter-core communication (IPC) initialization method provided in an embodiment of this application includes the following steps:

[0120] Step S1: Check if the FIFO memory is initialized. The FIFO memory is used to manage shared memory;

[0121] Step S2, if the fifo memory is not initialized, initialize the fifo memory; specifically, the fifo is a data structure, through the initialization of the fifo memory, it can be ensured that the data items entering the data structure first will be processed and retrieved first, and the data items entering later will be kept in the data structure waiting for processing. Therefore, initializing the fifo memory before inter-core communication is to maintain the order of data storage and retrieval, which helps to ensure the correctness and consistency of the data, and can be processed in a specific order when needed.

[0122] Step S3, check whether the hardware lock is completed for allocation, the hardware lock is used for mutual exclusion operation of the fifo memory;

[0123] Step S4, if the hardware lock is not allocated, allocate a hardware lock from the system resources;

[0124] Step S5, check whether the local interrupt is completed for initialization, the local interrupt is used for responding to the notification of other heterogeneous cores;

[0125] S6: if the interrupt is not configured, configure the interrupt.

[0126] Specifically, the local interrupt refers to an interrupt signal generated by the processor internally, which is used to notify the processor to execute a specific interrupt service program. The local interrupt is usually issued by some modules or peripherals inside the processor, and is used to handle various events or abnormal situations inside the processor. The purpose of local interrupt initialization is to ensure that the processor can correctly respond to and handle the interrupt signals generated internally. By initializing the local interrupt, the system can set the interrupt vector table, interrupt service program, interrupt controller and other related parameters to ensure that the processor can correctly execute the corresponding interrupt processing logic when receiving the interrupt signal. After receiving the local interrupt signal, the processor will find the corresponding interrupt service program according to the interrupt vector table and execute the corresponding processing logic. The processing process of the local interrupt can help the processor respond to internal events in time, ensuring the normal operation and stability of the system.

[0127] In one embodiment, before the plurality of communication sending cores acquire the hardware lock in turn according to the communication needs, the method further comprises:

[0128] Confirm whether the memory size in the memory is greater than or equal to a first preset value;

[0129] If the memory in the memory is less than the first preset value;

[0130] The plurality of communication sending cores notify the communication receiving core to release the blocking state by triggering the interrupt.

[0131] Specifically, if the memory available in the memory is less than a first preset value, the system enters a blocked state, indicating that another core (or communication receiving core) is currently occupying memory. An interrupt is triggered to notify the other core to release the blocked state. The first preset value can be set based on the data size sent by the communication sending core and is not limited here. For example, if the communication sending core wants to send n bytes of data, then the first preset value is n bytes.

[0132] like Figure 4 As shown, Figure 4 This is a schematic diagram of the ring buffer structure provided in one embodiment of this application. Data transmission and reception between heterogeneous multi-core processors can be represented by a ring buffer, supporting multiple producers sending data simultaneously. Each core requests a communication region from the shared memory pool, records the attribute information of the requested communication region, including the starting address offset and memory size of the shared memory pool, and then updates the free space header offset (free_head). Each update is based on the memory size of the requested communication region. Taking three heterogeneous cores sending data simultaneously as an example, the three cores request communication regions (pkt0, pkt1, pkt2) respectively according to the order in which they acquire the hardware lock, and then update the free space header offset (free_head) sequentially. After each core writes data to the requested communication region, it needs to acquire the hardware lock again, and update the valid data tail offset (ready_tail) sequentially according to the order in which the hardware lock was acquired. The write operations of the three heterogeneous cores are independent and can be performed synchronously.

[0133] Similarly, this application also supports multiple producers receiving data simultaneously. Each core requests a communication region from the shared memory pool, records the attribute information of the requested communication region, including the starting address offset and memory size of the shared memory pool, and updates the valid data header offset (ready_head). Taking three heterogeneous cores receiving data simultaneously as an example, the three cores request communication regions (pkt0, pkt1, pkt2) respectively according to the order in which they acquired the hardware lock, and then update the valid data header offset (ready_head) sequentially, with each update based on the memory size of the requested communication region. After each core reads data from the requested communication region, it needs to update the free space tail offset (free_tail), and the order of updating the free space tail offset must be consistent with the order in which the communication regions were requested.

[0134] like Figure 5 As shown, Figure 5 This is a flowchart of a method for one communication sending core to send data according to an embodiment of this application. The method includes the following steps: When multiple communication sending cores send data simultaneously, the method for one communication sending core to send data includes the following steps:

[0135] Step S1, the communication sender core needs to confirm whether the heterogeneous multi-core inter-process communication (ipc) is initialized before sending data (n bytes);

[0136] Step S2, if the heterogeneous multi-core inter-process communication (ipc) is not initialized, initialize the heterogeneous multi-core inter-process communication (ipc);

[0137] Step S3, check whether the free space is greater than or equal to the first preset value (n bytes);

[0138] Step S4, if the free space is less than the first preset value, enter the blocked state;

[0139] Step S5, after the communication sender receives the data, the communication receiver is notified by interrupt, and after the communication receiver is unblocked, step S3 is entered;

[0140] Step S6, if the free space satisfies n bytes, acquire the hardware lock;

[0141] Step S7, apply for n bytes of free space from the shared memory pool, and update the free space header offset free_head;

[0142] Step S8, release the hardware lock;

[0143] After completing the corresponding operation, release the hardware lock to avoid blocking.

[0144] Step S9, the communication sender core writes data into the applied space;

[0145] Step S10, acquire the hardware lock again;

[0146] Step S11, update the valid data tail offset ready_tail;

[0147] Step S12, after updating, release the spinlock;

[0148] Step S13, remind all cores that new data has been written into the fifo memory by triggering an interrupt.

[0149] As Figure 4As shown, if the size of the shared memory managed by each core through the data interface is size, and the address thereof is called base address addr_base. The offset of the read / write operation relative to the base address jumps to 0 after reaching size. The head offset of the free space, i.e., the head of the free space segment, is called free_head, the tail offset of the free space, i.e., the tail of the free space segment, is called free_tail, and the write direction of the shared memory is from the head to the tail. The head offset of the valid data, i.e., the head of the valid data segment, is called ready_head, the tail offset of the valid data, i.e., the tail of the valid data segment, is called ready_tail, and the read direction of the shared memory is from the head to the tail.

[0150] A piece of data sent or received is called a packet, and the information of the packet includes buf0: the start address of the data / space segment, size0, the length of the data / space segment. If there is offset flipping, buf1: the start address of the second data / space segment, size1, the length of the second data / space segment are needed. Writing a piece of data into the memory includes three processes: allocating memory space; writing data into the allocated memory; sending data, adding the data to the valid data segment, and broadcasting to all consumers that new data is written.

[0151] As shown in FIG. 1, Figure 4 The interval between the head offset of the free space free_head and the tail offset of the valid data ready_tail is the part that has been allocated but not sent, which has been occupied for the communication sending core, but is not valid data for the communication receiving core.

[0152] The heterogeneous multi-core inter-core communication method provided in the application supports concurrent writing, i.e., multiple cores continuously allocate multiple communication regions, then write data into the obtained communication regions at the same time, and then send the data according to the order of obtaining the hardware lock. The longest process in the three processes of writing data into the fifo memory is writing data, and the application can realize multi-core parallel writing of data, which can greatly improve the writing efficiency and improve the communication efficiency.

[0153] The application supports various copying modes when writing data, and the copying mode in the sending or receiving process can be a mode defined by the caller, such as DMA (Direct Memory Access), which can shorten the time to the greatest extent.

[0154] As shown in FIG. 1, Figure 6 Figure 6 ​A data format diagram is provided for an embodiment of the present application. Information interaction based on a FIFO memory needs to define a set of information formats: a message is a variable-length data packet, which is composed of a header and a payload. The length of the payload is specified in the header, and is at least 0. The payload refers to the actual data part of the transmission, and does not include the header, tail or other control information of the transmission protocol. The fields of the data message are defined as follows: size, the length of the payload carried by the message; msg_id, the message id, representing the information type carried by the message, such as a specific configuration command, an event, or an ack, etc.; src_core, the core id of the message producer, representing the global and unique id value corresponding to the producer; dst_core, the core id of the message consumer, representing the global and unique id value corresponding to the consumer; and payload, the data carried by the message, such as the parameters carried by the configuration command.

[0155] The communication sending core is responsible for encapsulating a complete and accurate data packet, and then sending the data packet; and the communication receiving core is responsible for receiving the data packet, and analyzing and processing the data packet.

[0156] The present application also provides a heterogeneous multi-core inter-core communication method, as shown in Figure 7 , and the method comprises the steps of: Figure 7 A method flowchart for receiving data by a communication receiving core according to an embodiment of the present application is provided, comprising the following steps:

[0157] In step S702, a plurality of communication receiving cores acquire hardware locks in sequence according to communication needs.

[0158] In step S704, the plurality of communication receiving cores apply for communication areas from the shared memory pool in sequence according to the order of acquiring the hardware locks.

[0159] In step S706, the plurality of communication receiving cores read out data from the communication areas.

[0160] Specifically, after receiving the data, the communication receiving core needs to analyze and process the data packet.

[0161] In step S708, the plurality of communication receiving cores notify the communication sending core by triggering an interrupt.

[0162] The logic of receiving data by the communication receiving core is similar to the logic of sending data by the communication sending core.

[0163] In one embodiment, the communication sending core comprises a memory, and the memory is used for managing the shared memory pool; and step S706 specifically comprises:

[0164] Multiple communication receiving cores configure the attribute information of the communication region in memory. The attribute information of the communication region includes the starting address offset of the shared memory pool and the memory, and update the offset of the valid data header.

[0165] Multiple communication receiving cores release hardware locks;

[0166] After reading data from the communication area, the communication receiving core acquires the hardware lock again;

[0167] The communication receiving core updates the tail offset of the free space at the end of the communication area, and releases the hardware lock again after completing the data reception.

[0168] The communication receiving core notifies the communication sending core by triggering an interrupt.

[0169] In one embodiment, the step S802 is preceded by the following step:

[0170] Multiple communication receiving cores perform the FIFO memory initialization process.

[0171] like Figure 4 As shown, if the size of the shared memory managed by each core through the FIFO data interface is 'size', its address is called the base address 'addr_base'. Read / write operations jump to 0 after the offset relative to the base address reaches 'size'. The free space head offset, i.e., the head of the free space segment, is called 'free_head', and the free space tail offset, i.e., the tail of the free space segment, is called 'free_tail'. Shared memory is written from head to tail. The valid data head offset, i.e., the head of the valid data segment, is called 'ready_head', and the valid data tail offset, i.e., the tail of the valid data segment, is called 'ready_tail'. Shared memory is read from head to tail.

[0172] A segment of data sent or received is called a packet. The packet information includes buf0: the starting address of the data / space segment, size0, and the length of the data / space segment. If an offset flip exists, buf1 is needed: the starting address of the second data / space segment, size1, and the length of the second data / space segment. Reading data from memory involves three processes: allocating a data space; reading the data from the allocated memory; and releasing the data space back to a free space segment in memory, broadcasting this information to all communication sending cores.

[0173] The interval between the effective data header offset `ready_head` and the free space tail offset `free_tail` represents the portion that has been received but not yet released. For the communication receiving core, the data in this interval has been received, but for the communication sending core, this interval is not considered free space.

[0174] The present application supports multi-core concurrent readout, that is, supports multiple cores to continuously allocate free space, then simultaneously read data from the applied memory, and then release the hardware lock according to the order of the applied communication area. The longest time-consuming process in the three processes of reading data from the fifo memory is reading data, and if multi-core parallel reading can be achieved, the communication efficiency can be greatly improved.

[0175] As shown in Figure 8 , a flow chart of a method for receiving data by a communication receiving core provided by an embodiment of the present application is shown. Figure 8 A process of receiving n bytes of data by a communication receiving core is shown.

[0176] Step S1, before receiving data, the communication receiving core needs to confirm whether the multi-core inter-process communication ipc is initialized;

[0177] Step S2, if the multi-core inter-process communication ipc is not initialized, initialize the multi-core inter-process communication ipc;

[0178] Step S3, check whether the valid data in the memory is greater than or equal to n bytes;

[0179] Step S4, if the valid data in the memory is less than n bytes, enter the blocked state;

[0180] Step S5, after the communication sending core sends data, notify the communication receiving core through an interrupt; the communication receiving core unblocks, and then enters step S3.

[0181] Step S6, if the valid data satisfies not less than n bytes, acquire the hardware lock spinlock.

[0182] Step S7, apply n bytes of valid data from the shared memory, and update the valid data header offset ready_head.

[0183] Step S8, release the hardware lock spinlock.

[0184] Step S9, the consumer reads data from the applied space.

[0185] Step S10, acquire the hardware lock spinlock again.

[0186] Step S11, update the free space tail offset free_tail.

[0187] Step S12, after the update is completed, release the hardware lock spinlock.

[0188] Step S13, remind all cores that new space has been released by triggering an interrupt.

[0189] Data interface data interface data interface data interface data interface such as Figure 9 As shown, Figure 9 This is a schematic diagram of a heterogeneous multi-core inter-core communication system provided in one embodiment of this application. The system consists of five different cores, each responsible for a different task. The core responsible for overall system scheduling is the master device. The other four cores are slave device 1, slave device 2, slave device 3, and slave device 4, hereinafter referred to as slave devices. The master device can receive data from all slave devices and can also send data to each slave device. Conversely, each slave device can send data to the master device and also receive data from the master device.

[0190] Each core has a segment of shared memory managed by the memory manager for receiving data. When sending data, the data needs to be written into the shared memory of the other core. This application establishes a one-to-four bidirectional data exchange channel using the above method.

[0191] This application supports multi-producer, multi-consumer application scenarios, satisfying various practical application needs. Secondly, it supports different processor architectures and operating systems. Regarding concurrency, for producers, the process involves allocating memory, writing data, and then updating the write pointer. Allocating memory and updating the pointer require acquiring hardware locks, but these operations are short-lived; the longer data writing operations do not require prolonged hardware lock occupation. Therefore, it can support multiple producers simultaneously writing data to shared memory. Similarly, it can also support multiple consumers simultaneously reading data, and multiple consumers and multiple producers simultaneously sending and receiving data.

[0192] The software framework of this application is simple and suitable for porting to various heterogeneous processors; secondly, the software framework does not limit the data format and can simultaneously handle scenarios such as data interaction, large-block data transmission and reception, and remote procedure calls; it also supports multiple data migration methods.

[0193] The hardware dependencies of this application are simple, requiring only a shared memory pool, a hardware lock module, and inter-core interrupts, which are easy to implement in heterogeneous multi-core systems.

[0194] This application also provides a heterogeneous multi-core inter-core communication system, including multiple communication sending cores, multiple communication receiving cores, a hardware lock module, and a shared memory pool, wherein the multiple communication sending cores are used to execute:

[0195] Multiple communication sending cores acquire hardware locks sequentially according to communication needs;

[0196] Multiple communication sending cores request communication regions from the shared memory pool in the order in which they acquire hardware locks;

[0197] Multiple communication sending cores simultaneously write and send data to the communication area;

[0198] The plurality of communication sending cores notify the communication receiving core by triggering an interrupt.

[0199] In one of the embodiments, the communication sending core and the communication receiving core include an application module, an intermediate module and a porting layer module.

[0200] The hardware lock module is used to limit access of one of the communication sending core and the communication receiving core to the shared memory pool.

[0201] In one of the embodiments, the intermediate module includes a memory, and the memory includes a data interface.

[0202] The communication sending core writes data to the shared memory pool through the data interface, and the communication receiving core reads data from the shared memory pool through the data interface.

[0203] The application also provides a terminal device, including: a heterogeneous multi-core inter-core communication system, the heterogeneous multi-core inter-core communication system including a plurality of communication sending cores, a plurality of communication receiving cores and a shared memory pool, each core being configured with a memory.

[0204] The memory stores computer execution instructions.

[0205] The processor executes the computer execution instructions stored in the memory, so that the processor executes the heterogeneous multi-core inter-core communication method as described above.

[0206] The application also provides a computer readable storage medium, the computer readable storage medium storing computer execution instructions, the computer execution instructions being executed by the processor to implement the heterogeneous multi-core inter-core communication method as described above.

[0207] The application embodiment provides a computer program product, including a computer program, the computer program being executed by the processor to implement the heterogeneous multi-core inter-core communication method as described above.

[0208] In the above embodiments, it should be understood that the processor can be a central processing unit (English: Central Processing Unit, for short: CPU), and can also be other general-purpose processors, digital signal processors (English: Digital Signal Processor, for short: DSP), application specific integrated circuits (English: Application Specific Integrated Circuit, for short: ASIC) and the like. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor and the like. The steps of the method disclosed in combination with the application can be directly embodied as hardware processor execution, or executed by hardware and software modules in the processor.

[0209] The memory can include a Random Access Memory (RAM) and can also include a Non-volatile Memory (NVM), such as at least one disk memory.

[0210] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0211] The present application also provides a computer program product, comprising a computer program, which, when executed by a processor, implements the above method.

[0212] The present application also provides a computer readable storage medium, which stores computer execution instructions, and when a processor executes the computer execution instructions, the above method is implemented.

[0213] The above readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0214] An exemplary readable storage medium is coupled to the processor, so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be an integral part of the processor. The processor and the readable storage medium can be located in an Application Specific Integrated Circuit (ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in the device.

[0215] The division of units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some data interface, device or unit, which can be electrical, mechanical or other forms.

[0216] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0217] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0218] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0219] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware. The aforementioned program can be stored in a computer readable storage medium. The program executes the steps including the above-mentioned method embodiments when executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, and various program code storage media.

[0220] It should be understood that many of the materials and devices exemplified in this disclosure are articles of manufacture (i.e., articles of manufacture) according to this disclosure. The articles of manufacture can be manufactured as such or can be manufactured by combining the materials and devices exemplified in this disclosure. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. It should be understood that, in some embodiments, equivalents to the specific electrode structures and / or methods described herein can be employed without departing from the scope of the application. Accordingly, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "containing," "involving," "characterized by," "characterized into," and variations thereof herein, is meant to encompass the items listed thereafter, and equivalents thereof as well as additional items. Although the foregoing application has been described in some detail by way of illustration and example, it is not to be limited thereby, but rather, only by the scope of the appended claims.

Claims

1. A heterogeneous multi-core inter-core communication method, characterized in that, The method is applied to a heterogeneous multi-core inter-core communication system, which includes multiple communication transmitting cores and multiple communication receiving cores. The method includes: The multiple communication sending cores acquire hardware locks sequentially according to communication needs; The multiple communication sending cores sequentially request communication areas from the shared memory pool according to the order in which they acquire the hardware lock; The multiple communication sending cores simultaneously write and send data to the communication area; The multiple communication sending cores notify the communication receiving core by triggering an interrupt.

2. The heterogeneous multi-core inter-core communication method according to claim 1, characterized in that, The communication sending core includes a memory used to manage the shared memory pool; the plurality of communication sending cores write data to and send it to the communication area, specifically including: The communication sending core configures the attribute information of the communication region in the memory. The attribute information of the communication region includes the starting address offset of the shared memory pool and the memory, and updates the free space header offset. The plurality of communication sending cores release the hardware lock; After the communication sending core writes data to the communication area, it acquires the hardware lock again. The communication sending core configures a valid data tail offset at the end of the communication area, and releases the hardware lock again after the data transmission is completed.

3. The heterogeneous multi-core inter-core communication method according to claim 2, characterized in that, Specifically, it includes: The first communication sending core acquires a hardware lock according to communication needs and requests a communication area from the shared memory pool; The first communication sending core configures the attribute information of the communication region in the memory, updates the free space header offset, and releases the hardware lock after completion; The i-th communication sending core acquires the hardware lock according to communication needs and requests a communication area from the shared memory pool; The i-th communication sending core configures the attribute information of the communication region in the memory, updates the free space header offset, and releases the hardware lock after completion, where i>1.

4. The heterogeneous multi-core inter-core communication method according to claim 2, characterized in that, Before the plurality of communication sending cores acquire the hardware lock sequentially according to communication needs, the method further includes: The plurality of communication sending cores perform the memory initialization process; The plurality of communication transmitting cores initialize the memory; The plurality of communication sending cores acquire hardware locks from system resources, and the hardware locks are used for mutual exclusion access to the shared memory pool; The multiple communication sending cores are configured with local interrupts, which are used to respond to notifications from other cores.

5. The heterogeneous multi-core inter-core communication method according to claim 2, characterized in that, Before the plurality of communication sending cores acquire the hardware lock sequentially according to communication needs, the method further includes: Confirm whether the memory size in the storage device is greater than or equal to a first preset value; If the memory in the storage is less than a first preset value; The multiple communication sending cores notify the communication receiving core to unblock by triggering an interrupt.

6. The heterogeneous multi-core inter-core communication method according to claim 2, characterized in that, The order in which the communication sending core acquires the hardware lock again is the same as the order in which the communication sending core first acquires the hardware lock.

7. A heterogeneous multi-core inter-core communication method, characterized in that, The method is applied to a heterogeneous multi-core inter-core communication system, which includes multiple communication transmitting cores and multiple communication receiving cores. The method includes: The multiple communication receiving cores acquire hardware locks sequentially according to communication needs; The multiple communication receiving cores sequentially request communication areas from the shared memory pool according to the order in which they acquire the hardware lock; The plurality of communication receiving cores read data from the communication area; The multiple communication receiving cores notify the communication sending core by triggering an interrupt.

8. A heterogeneous multi-core inter-core communication system, characterized in that, It includes multiple communication sending cores, multiple communication receiving cores, a hardware lock module, and a shared memory pool. The multiple communication sending cores are used to perform: The multiple communication sending cores acquire hardware locks sequentially according to communication needs; The multiple communication sending cores sequentially request communication areas from the shared memory pool according to the order in which they acquire the hardware lock; The multiple communication sending cores simultaneously write and send data to the communication area; The multiple communication sending cores notify the communication receiving core by triggering an interrupt.

9. The heterogeneous multi-core inter-core communication system according to claim 8, characterized in that, The communication sending core and the communication receiving core include an application module, an intermediate module, and a porting layer module; The hardware lock module is used to restrict either the communication sending core or the communication receiving core from accessing the shared memory pool.

10. The heterogeneous multi-core inter-core communication system according to claim 9, characterized in that, The intermediate module includes a memory, and the memory includes a data interface; The communication sending core writes data to the shared memory pool through the data interface, and the communication receiving core reads data from the shared memory pool through the data interface.

11. A terminal device, characterized in that, include: A heterogeneous multi-core inter-core communication system, comprising multiple communication sending cores, multiple communication receiving cores, and a shared memory pool, wherein each core is equipped with a memory; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the heterogeneous multi-core inter-core communication method as described in any one of claims 1-6, or Perform the heterogeneous multi-core inter-core communication method as described in claim 7.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the heterogeneous multi-core inter-core communication method as described in any one of claims 1-6, or Perform the heterogeneous multi-core inter-core communication method as described in claim 7.

13. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the heterogeneous multi-core inter-core communication method as described in any one of claims 1-6, or Implement the heterogeneous multi-core inter-core communication method as described in claim 7.

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