SiC MOSFET modeling method and system
By constructing the parasitic junction capacitance relationship of SiC MOSFET devices and segmenting the input, output, and reverse transmission capacitance, obtaining the inductance and driving resistance, and building a dual-pulse test circuit, the problem of insufficient accuracy and efficiency in SiC MOSFET modeling is solved, and high-precision and efficient simulation analysis is achieved.
Patent Information
- Application Number
- CN202511522590.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-23
- Publication Date
- 2026-01-20
AI Technical Summary
Existing SiC MOSFET modeling methods have shortcomings in terms of accuracy and efficiency, especially in the simulation deviation caused by neglecting key parasitic parameters and nonlinear behavior during high-frequency switching.
The parasitic junction capacitance relationship of SiC MOSFET devices is constructed. The input capacitance Ciss, output capacitance Coss, and reverse transmission capacitance Crss are modeled in segments. The drain inductance Ld, source inductance Ls, gate inductance Lg, and gate drive resistance Rg are obtained. A dual-pulse test circuit for SiC MOSFET devices is built, taking into account a variety of parasitic parameters.
While ensuring high simulation accuracy, the simulation time is shortened, which facilitates the simulation of system-level control algorithms. The model can be built using information from the SiC MOSFET module datasheet without needing to obtain detailed device material and geometric parameters.
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Figure CN121365635A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of SiC MOSFET device modeling, and particularly relates to a SiC MOSFET modeling method and system considering multiple parasitic parameters. BACKGROUND
[0002] In recent years, with the development of material science and new type of semiconductor device manufacturing technology, due to the excellent physical properties of new wide-bandgap (Wide-Bandgap, WBG) semiconductor materials such as silicon carbide (Silicon Carbide, SiC) and gallium nitride (Gallium Nitride, GaN), power semiconductor devices based on silicon carbide and gallium nitride, such as SiC MOSFET, have been widely studied in motor drive system applications. However, the high-frequency oscillation harmonics caused by the parasitic parameters of SiC MOSFET devices have also worsened the system electromagnetic interference (Electromagnetic Interference, EMI) problem. In summary, in order to better apply SiC MOSFET wide-bandgap power semiconductor devices to motor drive systems, it is of great significance to study SiC MOSFET device modeling.
[0003] Due to the differences in material properties between silicon carbide and silicon, SiC MOSFET has great differences in switching characteristics compared with traditional silicon-based power switching devices. In order to accurately evaluate the switching characteristics of SiC MOSFET, such as switching time and switching oscillation, accurate modeling of its switching process is required. At present, the models describing the switching process of SiC MOSFET mainly include finite element models and equivalent circuit models. The existing technology uses finite element analysis tools to establish a simulation model of SiC MOSFET. This kind of finite element model has high precision but the model simulation solving process is time-consuming and difficult to be used for system-level simulation analysis, and the model establishment needs to obtain detailed semiconductor device material and geometric size parameters, which are usually confidential and difficult to obtain. The equivalent circuit model can accurately reflect the switching characteristics of SiC MOSFET, and the simulation speed is very fast. The existing technology has also established an equivalent circuit model of SiC MOSFET, but only considers the influence of nonlinear gate-drain junction capacitance C gd , but does not consider the influence of parasitic inductance of the source end (S) and the drain end (D) of SiC MOSFET device. The model in the prior art considers the nonlinear characteristics of most SiC MOSFET junction capacitances C ds , but considers the junction capacitance Cds The capacitance value decreases with the increase of the drain voltage. Therefore, in order to carry out accurate and efficient simulation analysis, it is necessary to establish a more suitable SiC MOSFET model to describe the dynamic change characteristics of SiC MOSFET in high-frequency switching process. SUMMARY
[0004] In view of the above problems in the prior art, the SiC MOSFET modeling method and system considering multiple parasitic parameters provided by the application solve the problems of the existing SiC MOSFET modeling method in terms of precision and efficiency, and especially solve the simulation deviation problem caused by ignoring key parasitic parameters and nonlinear behavior in the high-frequency switching process.
[0005] In order to achieve the above purpose, the technical scheme adopted by the application is as follows: a SiC MOSFET modeling method considering multiple parasitic parameters, comprising the following steps: S1, constructing a parasitic junction capacitance relationship of the SiC MOSFET device; S2, based on the relationship constructed in S1, modeling the input capacitance of the SiC MOSFET device C iss in a segmented manner; S3, based on the relationship constructed in S1, modeling the output capacitance of the SiC MOSFET device C oss ; S4, based on the relationship constructed in S1, modeling the reverse transmission capacitance of the SiC MOSFET device C rss ; S5, obtaining the drain inductance of the SiC MOSFET device L d , the source inductance L s , the gate inductance L g and the gate drive resistance R g ; S6, constructing a diode model; S7, based on the modeling result, the parameters obtained in S5 and the constructed diode model, building a double-pulse test circuit of the SiC MOSFET device, and completing the modeling of the SiC MOSFET.
[0006] The beneficial effects of this invention are: The modeling of SiC MOSFETs in this invention comprehensively considers simulation time and accuracy, shortening simulation time while ensuring high simulation accuracy, thus facilitating its use in system-level control algorithm simulation. The modeling of SiC MOSFETs in this invention can be established using only relevant information from the corresponding SiC MOSFET module datasheet, without requiring detailed SiC MOSFET device material and geometric parameters.
[0007] Furthermore, the parasitic junction capacitance relationship of the SiC MOSFET device is as follows: ; in, This represents the junction capacitance between the gate and the source. This represents the junction capacitance between the gate and drain. This represents the junction capacitance between the drain and source.
[0008] The technical effect of the above further solution is to obtain the relationship expression between the parasitic junction capacitance of the SiC MOSFET device and the input capacitance, output capacitance and reverse transfer capacitance.
[0009] Furthermore, regarding the input capacitance of SiC MOSFET devices... C iss The model is performed in segments, specifically as follows: The input capacitance of the SiC MOSFET device is calculated using the following formula. C iss Perform segmented modeling: ; in, This indicates the SiC MOSFET device at different drain-source voltages. v ds The input capacitor below C iss , , and All represent coefficients to be determined. This represents the drain-source voltage of a SiC MOSFET device. Indicates the input capacitance of a SiC MOSFET device. C iss steady-state value The corresponding drain-source voltage, Indicates the input capacitance of a SiC MOSFET device. C iss The steady-state value.
[0010] The technical effect of the above further solution is: to obtain SiC MOSFET devices at different drain-source voltagesv ds input capacitance C iss model.
[0011] Further, the output capacitance of the SiC MOSFET device under different drain-source voltages C oss is modeled by using the following formula: C oss ; wherein, Cout represents the output capacitance of the SiC MOSFET device under different drain-source voltages v ds C oss , VDS represents the drain-source voltage of the SiC MOSFET device, , and all represent coefficients to be solved.
[0012] The technical effect brought by the above further scheme is that the output capacitance of the SiC MOSFET device under different drain-source voltages v ds C oss model.
[0013] Further, the reverse transmission capacitance of the SiC MOSFET device under different drain-source voltages C rss is modeled by using the following formula: C rss ; wherein, Crr represents the reverse transmission capacitance of the SiC MOSFET device under different drain-source voltages v ds C rss , VDS represents the drain-source voltage of the SiC MOSFET device, , and all represent coefficients to be solved.
[0014] The technical effect brought by the above further scheme is that the reverse transmission capacitance of the SiC MOSFET device under different drain-source voltages v ds reverse transmission capacitance C rss model.
[0015] Further, a diode model is constructed, which is specifically: obtaining diode parameters and volt-ampere characteristic curve data; constructing a diode model based on the diode parameters and the volt-ampere characteristic curve data.
[0016] The technical effects brought by the above further scheme are: obtaining a SiC MOSFET device diode model.
[0017] Further, the circuit elements of the SiC MOSFET device double-pulse test circuit include a SiC MOSFET power device Q 1, a Schottky barrier diode D 1, an inductive load element L load , a bus filter capacitor C dc , and a gate drive power supply voltage v gg ; The gate drive power supply voltage v gg is connected to one end of a gate drive resistor R g , and the other end of the gate drive resistor R g is connected to one end of a gate inductor L g , and the other end of the gate inductor L g is connected to the gate of the SiC MOSFET power device Q 1, one end of a gate-drain capacitor C gd , and one end of a gate-source capacitor C gs , respectively. The other end of the gate-drain capacitor C gd is connected to the drain of the SiC MOSFET power device Q 1, one end of a drain-source capacitor C ds , and one end of a drain inductor L d , respectively. The other end of the drain inductor L d is connected to the anode of the Schottky barrier diode D 1, one end of a diode junction capacitor C J , and the inductive load elementL load one end of the diode junction capacitor C J the other end of the Schottky barrier diode D 1, the inductive load element L load the other end of the bus filter capacitor C dc one end of the power supply V dc the positive electrode of the power supply V dc the negative electrode of the bus filter capacitor C dc the other end of the source inductor L s one end of the gate drive power supply voltage v gg the negative electrode of the source inductor L s the other end of the gate-source capacitor C gs the other end of the drain-source capacitor C ds the other end of the drain-source capacitor.
[0018] The technical effect brought by the above further scheme is that a complete SiC MOSFET device double-pulse test circuit is established, which can be used to test the switching dynamic performance of the SiC MOSFET device.
[0019] The application further provides a SiC MOSFET modeling system considering multiple parasitic parameters, comprising: a first processing module configured to construct a SiC MOSFET device parasitic junction capacitor relationship; a second processing module configured to perform segmented modeling on SiC MOSFET device input capacitance C iss based on the constructed SiC MOSFET device parasitic junction capacitor relationship; a third processing module configured to perform modeling on SiC MOSFET device output capacitance C oss based on the constructed SiC MOSFET device parasitic junction capacitor relationship; a fourth processing module configured to perform modeling on SiC MOSFET device reverse transmission capacitance C rss based on the constructed SiC MOSFET device parasitic junction capacitor relationship; The fifth processing module is used for acquiring the drain inductance of the SiC MOSFET device L d , the source inductance L s , the gate inductance L g and the gate drive resistance R g ; The sixth processing module is used for constructing a diode model. The seventh processing module is used for building a SiC MOSFET double-pulse test circuit based on the modeling result, the acquired parameters and the constructed diode model, and completing the modeling of the SiC MOSFET.
[0020] The modeling of the SiC MOSFET in the application considers the simulation time and the simulation accuracy comprehensively, shortens the simulation time while ensuring high simulation accuracy, and is convenient for system-level control algorithm simulation. The modeling of the SiC MOSFET in the application can be established only by using the relevant information in the SiC MOSFET module data manual, without the need of acquiring detailed SiC MOSFET device material and geometric size parameters BRIEF DESCRIPTION OF DRAWINGS Figure 1 The SiC MOSFET device input capacitance value in the application changes with the drain-source voltage. C iss The SiC MOSFET device output capacitance value in the application changes with the drain-source voltage.
[0021] Figure 2 The SiC MOSFET device reverse transmission capacitance value in the application changes with the drain-source voltage. C oss The SiC MOSFET device reverse transmission capacitance value in the application changes with the drain-source voltage.
[0022] Figure 3 The SiC MOSFET device reverse transmission capacitance value in the application changes with the drain-source voltage. C rss The SiC MOSFET device reverse transmission capacitance value in the application changes with the drain-source voltage.
[0023] Figure 4 The SiC MOSFET device double-pulse test circuit in the application is shown in the figure.
[0024] Figure 5(a) is a SiC MOSFET switching characteristic drain-source voltage double-pulse test simulation waveform diagram without considering the parasitic inductance and junction capacitance resonance influence in the application.
[0025] Figure 5(b) is a SiC MOSFET switching characteristic drain-source voltage double-pulse test simulation waveform diagram considering the parasitic inductance and junction capacitance resonance influence in the application.
[0026] Figure 6 Drain-source voltage for SiC MOSFET switching characteristics considering the influence of parasitic inductance and junction capacitance resonance in the application v ds Double pulse test experimental waveform diagram.
[0027] Figure 7 Comparison chart of double pulse test simulation waveforms before and after the junction capacitance of the SiC MOSFET device in the application is constant and changes.
[0028] Figure 8 Flowchart of the method of the application.
[0029] Figure 9 System structure schematic diagram of the application. DETAILED DESCRIPTION
[0030] The specific embodiments of the application are described below to facilitate the understanding of the application by those skilled in the art, but it should be clear that the application is not limited to the scope of the specific embodiments, and for those skilled in the art, it is obvious that various changes are within the spirit and scope of the application defined and determined by the appended claims, and all applications utilizing the concept of the application are within the scope of protection.
[0031] Example 1 To improve the deficiencies of the SiC MOSFET modeling method in the background art, considering the simulation time and simulation accuracy, a SiC MOSFET equivalent circuit modeling method considering multiple parasitic inductances and nonlinear junction capacitances is provided, the basic idea of which is to consider the model simulation time and simulation accuracy, and to provide an equivalent circuit modeling method considering multiple SiC MOSFET device parasitic parameters: drain inductance ( L d ), source inductance ( L s ), gate inductance ( L g ), gate-source capacitance ( C gs ), gate-drain capacitance ( C gd ), drain-source capacitance ( C ds ), as shown in Figure 8 , the application provides a SiC MOSFET modeling method considering multiple parasitic parameters, the implementation method of which is as follows: S1, construct the parasitic junction capacitance relationship of the SiC MOSFET device; In this embodiment, the parasitic capacitance of the SiC MOSFET device mainly includes the junction capacitance between the gate and the sourceC gs Junction capacitance between gate and drain C gd Junction capacitance between drain and source C ds The turn-on and turn-off processes of a SiC MOSFET are essentially the charging and discharging processes of its input and output capacitors. Therefore, in SiC MOSFET datasheets, the input capacitor is usually used as the reference. C iss Output capacitor C oss and reverse transfer capacitor C rss The parasitic junction capacitance is used to represent the capacitance, and the specific relationship between the two can be expressed by the following formula: (1) S2, Based on the relationship constructed in S1, the input capacitance of the SiC MOSFET device is... C iss Perform segmented modeling; In this embodiment, the input capacitance of the SiC MOSFET device is determined using formula (2). C iss Modeling is performed, taking into account the input capacitance of SiC MOSFET devices. C iss It exhibits strong nonlinear characteristics, affecting the input capacitance of SiC MOSFET devices. C iss Segmented modeling is used to ensure high modeling accuracy: (2) in, This indicates the SiC MOSFET device at different drain-source voltages. v ds The input capacitor below C iss , , and All represent coefficients to be determined. This represents the drain-source voltage of a SiC MOSFET device. Indicates the input capacitance of a SiC MOSFET device. C iss steady-state value The corresponding drain-source voltage, Indicates the input capacitance of a SiC MOSFET device. C iss The steady-state value.
[0032] Input capacitance from SiC MOSFET device datasheet Ciss Curve data to solve the coefficient a 1、 b 1、 c 1. SiC MOSFET device input capacitance C iss The fitting value and actual value comparison results are shown in Figure 1 .
[0033] S3, based on the relationship of S1, the output capacitance of SiC MOSFET device C oss Modeling; In this embodiment, the output capacitance of SiC MOSFET device is modeled by formula (3) C oss : (3) Wherein, The output capacitance of SiC MOSFET device under different drain-source voltage v ds C oss , The drain-source voltage of SiC MOSFET device, , And All represent the coefficient to be solved.
[0034] The output capacitance of SiC MOSFET device data manual C oss Curve data to solve the coefficient a 2、 b 2、 c 2. The output capacitance of SiC MOSFET device C oss The fitting value and actual value comparison results are shown in Figure 3 .
[0035] S4, based on the relationship of S1, the reverse transmission capacitance of SiC MOSFET device C rss Modeling; In this embodiment, the reverse transmission capacitance of SiC MOSFET device is modeled by formula (4) C rss : (4) Wherein, The reverse transmission capacitance of SiC MOSFET device under different drain-source voltage v ds underC rss , denotes the SiC MOSFET device drain-source voltage, , and all denote the coefficient to be determined.
[0036] Reverse transfer capacitance of SiC MOSFET device from data sheet C rss Curve data to solve the coefficient a 3、 b 3、 c 3. Reverse transfer capacitance of SiC MOSFET device C rss The comparison results of the fitted values and the actual values are shown in Figure 4 .
[0037] S5, obtaining the drain inductance of SiC MOSFET device L d , source inductance L s , gate inductance L g and gate drive resistance R g ; In this embodiment, the drain inductance L d , source inductance L s , gate inductance L g and gate drive resistance R g of SiC MOSFET device are obtained from the data sheet of SiC MOSFET device.
[0038] S6, constructing a diode model, which specifically comprises: obtaining diode parameters and volt-ampere characteristic curve data; constructing a diode model based on the diode parameters and the volt-ampere characteristic curve data.
[0039] In this embodiment, the diode model is established based on the diode parameters and the volt-ampere characteristic curve data from the data sheet of SiC MOSFET device.
[0040] S7, based on the modeling results, the parameters obtained in S5 and the constructed diode model, a SiC MOSFET device double-pulse test circuit is built, and the modeling of SiC MOSFET is completed.
[0041] The circuit elements of the SiC MOSFET device double-pulse test circuit comprise a SiC MOSFET power deviceQ 1. A Schottky barrier diode D 1. An inductive load element L load , a bus filter capacitor C dc , and a gate drive supply voltage v gg ; The gate drive supply voltage v gg is connected to one end of a gate drive resistor R g , the other end of the gate drive resistor R g is connected to one end of a gate inductor L g , the other end of the gate inductor L g is connected to the gate of a SiC MOSFET power device Q 1, one end of a gate-drain capacitor C gd , and one end of a gate-source capacitor C gs , the other end of the gate-drain capacitor C gd is connected to the drain of the SiC MOSFET power device Q 1, one end of a drain-source capacitor C ds , and one end of a drain inductor L d , the other end of the drain inductor L d is connected to the anode of a Schottky barrier diode D 1, one end of a diode junction capacitor C J , and one end of an inductive load element L load , the other end of the diode junction capacitor C J is connected to the cathode of the Schottky barrier diode D 1, the other end of the inductive load element L load , one end of a bus filter capacitor C dc , and the positive terminal of a power supply V dc , the negative terminal of the power supply V dc is connected to the other end of the bus filter capacitor C dc , and the source inductor Ls One end and gate drive power supply voltage v gg The negative terminal is connected to the source inductor. L s The other end is connected to the gate-source capacitor respectively. C gs The other end and the drain-source capacitance C ds The other end is connected.
[0042] In this embodiment, a dual-pulse test circuit for SiC MOSFET devices is constructed, as shown in Figure 5. The effectiveness of the established model is verified by comparing the results of dual-pulse simulation and experimental testing. The core components of the circuit include: Q 1 (SiC MOSFET power device) D 1 (Schottky barrier diode) L load (Inductive load element) C dc (Bus filter capacitor) and v gg (Gate drive power supply voltage). The parasitic parameters in Figure 4 are as follows: drain inductance ( L d ), source inductor ( L s ), gate inductor ( L g ), gate-source capacitance ( C gs ), gate-drain capacitance ( C gd ), drain-source capacitance ( C ds ), diode junction capacitance ( C J ), gate drive resistor ( R g ).
[0043] Taking the turn-off waveform of a SiC MOSFET as an example, it can be seen from Figure 5 that the drain-source voltage V ds The rising edge of the waveform exhibits a distinct sloping trend, rather than an ideal linear rising curve. This is due to the charging and discharging time of the parasitic junction capacitance in the SiC MOSFET device, with a rise time of approximately 33 ns. By simulating the turn-off delay waveform of an actual SiC MOSFET device, the turn-off time of the SiC MOSFET device can be obtained, which can then be used to calculate the turn-off loss of the power device. Simultaneously, from Figure 5(b), the drain-source voltage... V dsThe waveform can be seen, considering the effect of power device parasitic inductance and junction capacitance, there is a significant high-frequency switching oscillation phenomenon at the end of the power device turn-off waveform, which is caused by the resonance of device parasitic inductance and junction capacitance, the resonance period is 32 ns, and the resonance frequency is as high as 31.2 MHz, which is used to simulate the actual power device turn-off voltage oscillation, and then can be used to evaluate the EMI problem caused by high-frequency harmonics generated in the high-speed switching process of SiC MOSFET device. The experimental SiC MOSFET device turn-off drain-source voltage V ds The waveform is shown in Figure 6 From the figure, it can be seen that the SiC MOSFET device is affected by the parasitic inductance and junction capacitance, and the drain-source voltage V ds The rising edge of the waveform shows a clear tilt trend, and the rise time of the drain-source voltage is about 41 ns, the resonance period is 35.3 ns, and the resonance frequency is as high as 28.3 MHz. Figure 5 (a) does not consider the influence of parasitic inductance and capacitance resonance, and Figure 5 (b) considers the influence of parasitic inductance and capacitance resonance.
[0044] The main reason for the deviation between the simulation results and the experimental results is that the parasitic junction capacitance of the SiC MOSFET device is considered as a constant value in the simulation modeling. The actual parasitic junction capacitance of the SiC MOSFET device will change nonlinearly with the change of the drain-source voltage across the device. Therefore, the influence of the change of the parasitic junction capacitance of the SiC MOSFET device on its switching dynamic performance will be considered in the following, and the nonlinear parasitic junction capacitance of the SiC MOSFET device will be modeled to improve the accuracy of the simulation model. Considering the influence of the change of the parasitic junction capacitance of the SiC MOSFET device with the drain-source voltage, the device input capacitance C iss , output capacitance C oss and reverse transmission capacitance C rss are modeled according to formulas (2)-(4). The SiC MOSFET drain-source voltage waveform after the model is corrected is shown in Figure 7
[0045] From Figure 7 , considering the influence of the change of the parasitic junction capacitance of the SiC MOSFET device with the drain-source voltage V ds , the response speed is slower than that of the drain-source voltage waveform when the junction capacitance is considered as a constant value, and the rise time increases to 43 ns, and the drain-source voltage V ds oscillates at a frequency of 30.8 MHz, which is Figure 6 The experimental results are closer to the actual values, improving the accuracy of the model. In summary, the simulation model waveform of the SiC MOSFET drain-source voltage can better reproduce the overall trend of the experimental waveform, verifying the effectiveness of the simulation model.
[0046] Example 2 like Figure 9 As shown, this invention provides a SiC MOSFET modeling system that considers multiple parasitic parameters, including: The first processing module is used to construct the parasitic junction capacitance relationship of SiC MOSFET devices; The second processing module is used to process the input capacitance of the SiC MOSFET device based on the constructed parasitic junction capacitance relationship. C iss Perform segmented modeling; The third processing module is used to process the output capacitance of the SiC MOSFET device based on the constructed parasitic junction capacitance relationship. C oss Perform modeling; The fourth processing module is used to process the reverse transfer capacitance of the SiC MOSFET device based on the constructed parasitic junction capacitance relationship. C rss Perform modeling; The fifth processing module is used to obtain the drain inductance of the SiC MOSFET device. L d Source inductor L s Gate inductor L g and gate drive resistor R g ; The sixth processing module is used to build the diode model; The seventh processing module is used to build a double-pulse test circuit for SiC MOSFET devices based on the modeling results, the acquired parameters, and the constructed diode model, thus completing the modeling of SiC MOSFETs.
[0047] like Figure 9 The SiC MOSFET modeling system provided in the illustrated embodiment can execute the technical solution shown in the SiC MOSFET modeling system method of the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be repeated here.
[0048] In this embodiment, the SiC MOSFET modeling system can divide the functional units according to the SiC MOSFET modeling method. For example, each function can be divided into a functional unit, or two or more functions can be integrated into a processing unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit. It should be noted that the division of the units in the present application is illustrative and is only a logical division. In actual implementation, there can be another division method.
[0049] In this embodiment, the SiC MOSFET modeling system includes hardware structures and / or software modules corresponding to each function in order to realize the principles and beneficial effects of the SiC MOSFET modeling method. Those skilled in the art should easily realize that, in combination with the description of each schematic unit and algorithm step of the embodiments disclosed in the present application, the present application can be realized in the form of hardware and / or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software depends on the specific application and design constraints of the technical solution. Different methods can be used to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.
Claims
1. A SiC MOSFET modeling method, characterized by, The method comprises the following steps: S1, constructing a SiC MOSFET device parasitic junction capacitance relationship; S2, a relationship based on S1, input capacitance of SiC MOSFET device C iss Segmented modeling is performed; S3, the relationship formula based on S1, the output capacitance of SiC MOSFET device C oss modeling; S4, the relationship constructed based on S1, reverse transmission capacitance of SiC MOSFET device C rss modeling; S5, obtaining a drain inductance of the SiC MOSFET device L d , a source inductance L s , a gate inductance L g and a gate drive resistance R g ; S6, constructing a diode model; S7, based on the modeling result, the obtained parameter and the constructed diode model, building a SiC MOSFET device double pulse test circuit to complete the modeling of the SiC MOSFET.
2. The SiC MOSFET modeling method of claim 1, wherein, The SiC MOSFET device parasitic junction capacitance relationship is as follows: ； wherein Cgd represents a junction capacitance between the gate and the drain, Cgd represents a junction capacitance between the gate and the drain, Cgd represents a junction capacitance between the gate and the drain.
3. The SiC MOSFET modeling method of claim 1, wherein, Segmented modeling of SiC MOSFET device input capacitance C iss Segmented modeling of SiC MOSFET device input capacitance is performed by utilizing the following equation: C iss Segmented modeling of SiC MOSFET device input capacitance is performed by utilizing the following equation: ； in, This indicates the SiC MOSFET device at different drain-source voltages. v ds The input capacitor below C iss , , and All represent coefficients to be determined. This represents the drain-source voltage of a SiC MOSFET device. Indicates the input capacitance of a SiC MOSFET device. C iss steady-state value The corresponding drain-source voltage, Indicates the input capacitance of a SiC MOSFET device. C iss The steady-state value.
4. The SiC MOSFET modeling method of claim 1, wherein, Modeling the output capacitance of SiC MOSFET devices C oss Modeling the output capacitance of SiC MOSFET devices C oss Modeling the output capacitance of SiC MOSFET devices ； wherein represents the output capacitance of a SiC MOSFET device at different drain-source voltages v ds C oss , represents the drain-source voltage of a SiC MOSFET device, , and all represent coefficients to be determined. 5. The SiC MOSFET modeling method of claim 1, wherein, Modeling reverse transfer capacitance of SiC MOSFET devices C rss Modeling reverse transfer capacitance of SiC MOSFET devices C rss Modeling reverse transfer capacitance of SiC MOSFET devices ； wherein represents the reverse transfer capacitance of a SiC MOSFET device at different drain-source voltages v ds C rss , represents the drain-source voltage of a SiC MOSFET device, , and all represent coefficients to be determined. 6. The SiC MOSFET modeling method of claim 1, wherein, The diode model is constructed, and specifically: Obtaining diode parameters and volt-ampere characteristic curve data; Based on the diode parameters and the volt-ampere characteristic curve data, the diode model is constructed.
7. The SiC MOSFET modeling method of claim 1, wherein, The circuit elements of the SiC MOSFET device double pulse test circuit include a SiC MOSFET power device Q 1. A Schottky barrier diode D 1. An inductive load element L load , a bus filter capacitor C dc and a gate drive supply voltage v gg ; The gate drive power voltage v gg The positive electrode of the gate drive resistor R g The other end of the gate drive resistor R g The other end of the gate inductor L g The other end of the gate inductor L g The other end of the gate inductor Q The other end of the gate inductor C gd The other end of the gate inductor C gs The other end of the gate inductor C gd The other end of the gate inductor Q The other end of the gate inductor C ds The other end of the gate inductor L d The other end of the gate inductor L d The other end of the gate inductor D The other end of the gate inductor C J The other end of the gate inductor L load The other end of the gate inductor C J The other end of the gate inductor D The other end of the gate inductor L load The other end of the gate inductor C dc The other end of the gate inductor V dc The other end of the gate inductor V dc The other end of the gate inductor C dc The other end of the gate inductor L s The other end of the gate inductor v gg The other end of the gate inductor L s The other end of the gate inductor C gs The other end of the gate inductor C ds The other end is connected.
8. A SiC MOSFET modeling system for performing the SiC MOSFET modeling method of any one of claims 1-7, wherein, It comprises: A first processing module for constructing a SiC MOSFET device parasitic junction capacitance relationship; The second processing module is configured to obtain the input capacitance of the SiC MOSFET device based on the constructed parasitic junction capacitance relationship of the SiC MOSFET device. C iss Segmented modeling is performed. The third processing module is configured to obtain the output capacitance of the SiC MOSFET device based on the constructed parasitic junction capacitance relationship of the SiC MOSFET device. C oss modeling; The fourth processing module is configured to obtain the reverse transmission capacitance of the SiC MOSFET device based on the constructed relationship of the parasitic junction capacitance of the SiC MOSFET device. C rss modeling; a fifth processing module configured to acquire a drain inductance of the SiC MOSFET device L d , a source inductance L s , a gate inductance L g , and a gate drive resistance R g ; A sixth processing module for constructing a diode model; A seventh processing module for building a SiC MOSFET device double pulse test circuit based on the modeling result, the obtained parameter and the constructed diode model to complete the modeling of the SiC MOSFET.