Buck-boost DC conversion circuit with same-phase input and output

Abstract

The invention provides a buck-boost DC conversion circuit with same-phase input and output. The buck-boost DC conversion circuit comprises a PWM comparator, an error amplifier, a voltage comparator, a first electronic selection switch, a first diode, a third diode, a first inductor, a second inductor, a first MOS tube, a second MOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor. The buck-boost DC conversion circuit with the same-phase input and output is simple, controllable and practical, DC voltage can be boosted and reduced, the input voltage and the output voltage are the same in phase, and the buck-boost DC conversion circuit is suitable for being used in a bidirectional converter with wide voltage input.

Description

TECHNICAL FIELD

[0001] The application relates to an input and output in-phase step-up and step-down DC conversion circuit. BACKGROUND

[0002] With the vigorous development of the new energy industry, especially the new energy vehicles and large energy storage technology, the DC switching conversion technology has also developed rapidly. Various DC conversion circuits, especially the step-down Bulk circuit and the step-up Boost circuit, are more prominent in practical applications. However, in some actual circuit designs, in order to widen the input voltage range, the output voltage needs to be both step-up and step-down. The use of the step-down Bulk circuit or the step-up Boost circuit alone cannot meet the demand of both step-up and step-down, and the power supply voltage adaptability is poor. Moreover, because the energy storage inductor in the traditional Bulk-Boost circuit is across the positive and negative poles of the power supply, the input voltage and the output voltage are in opposite phases, which cannot be directly used in some new energy vehicles and energy storage projects for bidirectional conversion design. The bidirectional conversion technology is a relatively efficient and lowest cost solution in the current converter technology. Therefore, it is a very urgent task to design a wide input voltage range and input and output in-phase high-power circuit. SUMMARY

[0003] The application aims to provide an input and output in-phase step-up and step-down DC conversion circuit, which is simple, controllable and practical, can both step-up and step-down the DC voltage, and the input voltage and the output voltage are in the same phase.

[0004] The application is achieved by the following scheme:

[0005] The application discloses an input and output in-phase boost-buck DC conversion circuit, which comprises a PWM comparator U1, an error amplifier U2, a voltage comparator U3, a first electronic selection switch K1, a first diode D1, a third diode D3, a first inductor L1, a second inductor L2, a first MOS tube Q1, a second MOS tube Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a first capacitor C1. One end of the first resistor R1 is connected with one end of the second resistor R2, the other end of the first resistor R1 is connected with a voltage positive input end VI+, the other end of the second resistor R2 is connected with a voltage negative input end VI-, one end of the third resistor R3 is connected with one end of the fourth resistor R4 in series, the other end of the third resistor R3 is connected with a voltage positive output end VO+, the other end of the fourth resistor R4 is connected with a voltage negative output end VO-, the voltage negative input end VI- is connected with the voltage negative output end VO-, the drain of the first MOS tube Q1 is connected with the voltage positive input end VI+, the source of the first MOS tube Q1 is connected with the anode of the third diode D3 in series with the first inductor L1 and the second inductor L2, the cathode of the third diode D3 is connected with the voltage positive output end VO+, an arbitrary point between the first resistor R1 and the second resistor R2 is connected with the non-inverting input end of the voltage comparator U3, the output end S1 of the voltage comparator U3 is connected with the selection end (pin 4) of the first electronic selection switch K1 (when the selection end (pin 4) of the first electronic selection switch K1 inputs a high level 1, the input end (pin 1) of the first electronic selection switch K1 is communicated with the 1# output end (pin 2); when the selection end (pin 4) of the first electronic selection switch K1 inputs a low level 0, the input end (pin 1) of the first electronic selection switch K1 is communicated with the 0# output end (pin 3)), the 1# output end (pin 2) of the first electronic selection switch K1 is connected with the gate of the first MOS tube Q1, the 0# output end (pin 3) of the first electronic selection switch K1 is connected with the gate of the second MOS tube Q2, the input end of the first electronic selection switch K1 is connected with the output end of the PWM comparator U1, the non-inverting input end of the PWM comparator U1 is used for inputting a triangular wave function signal, the non-inverting input end of the PWM comparator U1 is connected with the output end of the error amplifier U2, the non-inverting input end of the error amplifier U2 is connected with an arbitrary point between the third resistor R3 and the fourth resistor R4, the non-inverting input end of the error amplifier U2 and the non-inverting input end of the voltage comparator U3 are respectively used for inputting a reference voltage, the drain of the second MOS tube Q2 is connected with an arbitrary point between the first inductor L1 and the second inductor L2, the source of the second MOS tube Q2 is connected with the voltage negative output end VO-, the cathode of the first diode D1 and one end of the first capacitor C1 are respectively connected with the gate of the first MOS tube Q1, the anode of the first diode D1 is connected with the gate of the second MOS tube Q2, the other end of the first capacitor C1 is grounded.

[0006] Further, a second diode D2 is also included, an anode of the second diode D2 is connected to the voltage negative output terminal VO-, and a cathode of the second diode D2 is connected to a source of the first MOS Q1.

[0007] Further, a second capacitor C2 is also included, one end of the second capacitor C2 is connected to the voltage positive output terminal VO+, and the other end of the second capacitor C2 is connected to the voltage negative output terminal VO-.

[0008] The application discloses an input and output in-phase boost-buck DC conversion circuit, which comprises a PWM comparator U1, an error amplifier U2, a voltage comparator U3, an inverter U4, a first electronic selection switch K1, a second electronic selection switch K2, a first diode D1, a fourth diode D4, a first inductor L1, a second inductor L2, a first MOS tube Q1, a second MOS tube Q2, a third MOS tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1 and a third capacitor C3, one end of the first resistor R1 is connected with one end of the second resistor R2, the other end of the first resistor R1 is connected with a voltage positive input end VI+, the other end of the second resistor R2 is connected with a voltage negative input end VI-, one end of the third resistor R3 is connected with one end of the fourth resistor R4 in series, the other end of the third resistor R3 is connected with a voltage positive output end VO+, the other end of the fourth resistor R4 is connected with a voltage negative output end VO-, the voltage negative input end VI- is connected with the voltage negative output end VO-, the drain of the first MOS tube Q1 is connected with the voltage positive input end VI+, the source of the first MOS tube Q1 is connected with the source of the third MOS tube Q3 in series after the first inductor L1 and the second inductor L2, the drain of the third MOS tube Q3 is connected with the voltage positive output end VO+, an arbitrary point between the first resistor R1 and the second resistor R2 is connected with the non-inverting input end of the voltage comparator U3, the output end S1 of the voltage comparator U3 is connected with the selection end (pin 4) of the first electronic selection switch K1 and the selection end (pin 4) of the second electronic selection switch K2 respectively, the 1# output end (pin 2) of the first electronic selection switch K1 is connected with the gate of the first MOS tube Q1, the 0# output end (pin 3) of the first electronic selection switch K1 is connected with the gate of the second MOS tube Q2, the input end (pin 1) of the first electronic selection switch K1 is connected with the output end of the PWM comparator U1, the inverting input end of the PWM comparator U1 is used for inputting a triangular wave function signal, the non-inverting input end of the PWM comparator U1 is connected with the output end of the error amplifier U2, the inverting input end of the error amplifier U2 is connected with an arbitrary point between the third resistor R3 and the fourth resistor R4, the non-inverting input end of the error amplifier U2 and the inverting input end of the voltage comparator U3 are used for inputting reference voltages respectively, the drain of the second MOS tube Q2 is connected with an arbitrary point between the first inductor L1 and the second inductor L2, the source of the second MOS tube Q2 is connected with the voltage negative output end VO-, the cathode of the first diode D1, one end of the first capacitor C1 and the anode of the fourth diode D4 are connected with the gate of the first MOS tube Q1 respectively, the cathode of the fourth diode D4 and one end of the third capacitor C3 are connected with the 1# output end (pin 2) of the second selection switch K2 respectively, the anode of the first diode D1 is connected with the gate of the second MOS tube Q2, the other end of the first capacitor C1 and the other end of the third capacitor C3 are grounded respectively.The input end (pin 1) of the second electronic selection switch K2 is connected to the gate of the third MOS tube Q3, the 0# output end (pin 3) of the second electronic selection switch K2 is connected to the output end of the inverter U4, and the input end of the inverter U4 is connected to the gate of the second MOS tube Q2.

[0009] Further, a second diode D2 is further included, the anode of the second diode D2 is connected to the voltage negative output end VO-, and the cathode of the second diode D2 is connected to the source of the first MOS tube Q1.

[0010] Further, a second capacitor C2 is further included, one end of the second capacitor C2 is connected to the voltage positive output end VO+, and the other end of the second capacitor C2 is connected to the voltage negative output end VO-.

[0011] The input and output phase-locked boost-buck DC conversion circuit of the present application is simple, controllable and practical, can boost and buck DC voltage, and has input voltage and output voltage in the same phase, is suitable for use in a wide voltage input bidirectional converter, uses double-inductor series design, thereby reducing the volume of a single inductor, improving voltage conversion efficiency and increasing conversion energy. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 The circuit schematic diagram of the input and output phase-locked boost-buck DC conversion circuit in Example 1 is shown in the figure.

[0013] Figure 2 The circuit schematic diagram of the input and output phase-locked boost-buck DC conversion circuit in Example 2 is shown in the figure. DETAILED DESCRIPTION

[0014] The present application is further described below in conjunction with examples and drawings, but is not limited to the description of the examples.

[0015] Example 1

[0016] An input and output phase-locked boost-buck DC conversion circuit, as shown in the figure. Figure 1As shown, including PWM comparator U1, error amplifier U2, voltage comparator U3, first electronic selection switch K1, first diode D1, second diode D2, third diode D3, first inductor L1, second inductor L2, first MOS tube Q1, second MOS tube Q2, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, first capacitor C1 and second capacitor C2, one end of the first resistor R1 is connected with one end of the second resistor R2, the other end of the first resistor R1 is connected with the voltage positive input end VI+, the other end of the second resistor R2 is connected with the voltage negative input end VI-, one end of the third resistor R3 is connected with one end of the fourth resistor R4 in series, the other end of the third resistor R3 is connected with the voltage positive output end VO+, the other end of the fourth resistor R4 is connected with the voltage negative output end VO-, the voltage negative input end VI- is connected with the voltage negative output end VO-, the drain of the first MOS tube Q1 is connected with the voltage positive input end VI+, the source of the first MOS tube Q1 is connected with the anode of the third diode D3 after being connected with the first inductor L1 and the second inductor L2 in series, the cathode of the third diode D3 is connected with the voltage positive output end VO+, an arbitrary point between the first resistor R1 and the second resistor R2 is connected with the non-inverting input end of the voltage comparator U3, the output end S1 of the voltage comparator U3 is connected with the selection end (pin 4) of the first electronic selection switch K1, the 1# output end (pin 2) of the first electronic selection switch K1 is connected with the gate of the first MOS tube Q1, the 0# output end (pin 3) of the first electronic selection switch K1 is connected with the gate of the second MOS tube Q2, the input end (pin 1) of the first electronic selection switch K1 is connected with the output end of the PWM comparator U1, the inverting input end of the PWM comparator U1 is used for inputting a triangular wave function signal 1, the non-inverting input end of the PWM comparator U1 is connected with the output end of the error amplifier U2, the inverting input end of the error amplifier U2 is connected with an arbitrary point between the third resistor R3 and the fourth resistor R4, the non-inverting input end of the error amplifier U2 and the inverting input end of the voltage comparator U3 are respectively used for inputting a reference voltage Uref, the drain of the second MOS tube Q2 is connected with an arbitrary point between the first inductor L1 and the second inductor L2, the source of the second MOS tube Q2 is connected with the voltage negative output end VO-, the cathode of the first diode D1 and one end of the first capacitor C1 are respectively connected with the gate of the first MOS tube Q1, the anode of the first diode D1 is connected with the gate of the second MOS tube Q2, the other end of the first capacitor C1 is grounded, the anode of the second diode D2 is connected with the voltage negative output end VO-, the cathode of the second diode D2 is connected with the source of the first MOS tube Q1, one end of the second capacitor C2 is connected with the voltage positive output end VO+, the other end of the second capacitor C2 is connected with the voltage negative output end VO-.

[0017] The output voltage Uo is compared with the reference voltage Uref through the voltage division of the third resistor R3 and the fourth resistor R4, and an error signal is obtained through the error amplifier U2. The error signal and the triangular wave function signal 1 inputted into the inverting input terminal of the PWM comparator are processed together through the PWM comparator, and then a PWM signal controlled by the output voltage Uo is outputted. The input voltage Uin is compared with the reference voltage Uref through the voltage division of the first resistor R1 and the second resistor R2. (1) When the voltage division value, i.e. the input voltage of the non-inverting input terminal of the voltage comparator U3, is greater than the reference voltage Uref, i.e. the input voltage of the inverting input terminal of the voltage comparator U3, the output terminal S1 of the voltage comparator U3 outputs a high level 1, and the logic judges that it is a step-down circuit. The selection terminal (pin 4) of the first electronic selection switch K1 inputs a high level 1. At this time, the input terminal (pin 1) of the first electronic selection switch K1 is connected with the 1# output terminal (pin 2). At this time, the PWM signal outputted by the PWM comparator is communicated with the PWM1 signal of the 1# output terminal (pin 2) of the first electronic selection switch K1. The gate of the first MOS tube Q1 is controlled by the PWM signal. At this time, the PWM2 signal of the 0# output terminal (pin 3) of the first electronic selection switch K1 is high resistance. The gate of the second MOS tube Q2 is low level and is turned off. At this time, the whole circuit works as a step-down Bulk circuit. When the PWM1 signal (i.e. the PWM signal) is a high level 1, the first MOS tube Q1 is turned on. The first inductor L1 and the second inductor L2 store energy. When the PWM1 signal (i.e. the PWM signal) is low level, the first MOS tube Q1 is cut off. The first inductor L1 and the second inductor L2 release energy. The induced potential is reversed. The second diode D2 continues to flow. (2) When the voltage division value, i.e. the input voltage of the non-inverting input terminal of the voltage comparator U3, is less than the reference voltage Uref, i.e. the input voltage of the inverting input terminal of the voltage comparator U3, the output terminal S1 of the voltage comparator U3 outputs a low level 0, and the logic judges that it is a step-up circuit. The selection terminal (pin 4) of the first electronic selection switch K1 inputs a low level 0. At this time, the input terminal (pin 1) of the first electronic selection switch K1 is connected with the 0# output terminal (pin 3). At this time, the PWM signal outputted by the PWM comparator is communicated with the PWM2 signal of the 0# output terminal (pin 3) of the first electronic selection switch K1. The gate of the second MOS tube Q2 is controlled by the PWM signal. At this time, the PWM1 signal of the 1# output terminal (pin 2) of the first electronic selection switch K1 is high resistance. The PWM2 signal (i.e. the PWM signal) is connected with the gate of the first MOS tube Q1 after being rectified by the first diode D1 and filtered by the first capacitor C1. The first MOS tube Q1 is always turned on. At this time, the whole circuit works as a step-up Boost circuit. When the PWM2 signal is a high level, the second MOS tube Q2 is turned on. The PWM2 signal is low level after being reversed. The first inductor L1 stores energy. When the PWM2 signal is low level, the second MOS tube Q2 is cut off. The first inductor L1 releases energy. The induced potential is reversed. The potential is superimposed on the input voltage Uin, and the step-up effect is achieved.

[0018] The output voltage Uo of the input and output in-phase step-up and step-down DC conversion circuit of Example 1 = Uref x (1 + R3 / R4), and the voltage value of the reference voltage Uref can be obtained according to this formula. If the duty ratio of the PWM driving waveform is D, when used as a step-down circuit, Uo = Uin x D; when used as a step-up circuit, Uo = Uin / (1-D).

[0019] Example 2

[0020] An input and output in-phase step-up and step-down DC conversion circuit, such as Figure 2As shown, including PWM comparator U1, error amplifier U2, voltage comparator U3, inverter U4, the first electronic selection switch K1, the second electronic selection switch K2, the first diode D1, the second diode D2, the fourth diode D4, the first inductor L1, the second inductor L2, the first MOS tube Q1, the second MOS tube Q2, the third MOS tube Q3, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first capacitor C1, the second capacitor C2 and the third capacitor C3, one end of the first resistor R1 is connected with one end of the second resistor R2, the other end of the first resistor R1 is connected with the voltage positive input terminal VI+, the other end of the second resistor R2 is connected with the voltage negative input terminal VI-, one end of the third resistor R3 is connected with one end of the fourth resistor R4 in series, the other end of the third resistor R3 is connected with the voltage positive output terminal VO+, the other end of the fourth resistor R4 is connected with the voltage negative output terminal VO-, the voltage negative input terminal VI- is connected with the voltage negative output terminal VO-, the drain of the first MOS tube Q1 is connected with the voltage positive input terminal VI+, the source of the first MOS tube Q1 is connected with the source of the third MOS tube Q3 in series after the first inductor L1 and the second inductor L2, the drain of the third MOS tube Q3 is connected with the voltage positive output terminal VO+, an arbitrary point between the first resistor R1 and the second resistor R2 is connected with the non-inverting input terminal of the voltage comparator U3, the output terminal S1 of the voltage comparator U3 is connected with the selection terminal (pin 4) of the first electronic selection switch K1 and the selection terminal (pin 4) of the second electronic selection switch K2 respectively, the 1# output terminal (pin 2) of the first electronic selection switch K1 is connected with the gate of the first MOS tube Q1, the 0# output terminal (pin 3) of the first electronic selection switch K1 is connected with the gate of the second MOS tube Q2, the input terminal (pin 1) of the first electronic selection switch K1 is connected with the output terminal of the PWM comparator U1, the inverting input terminal of the PWM comparator U1 is used for inputting the triangular wave function signal 1, the non-inverting input terminal of the PWM comparator U1 is connected with the output terminal of the error amplifier U2, the inverting input terminal of the error amplifier U2 is connected with an arbitrary point between the third resistor R3 and the fourth resistor R4, the non-inverting input terminal of the error amplifier U2 and the inverting input terminal of the voltage comparator U3 are used for inputting the reference voltage respectively, the drain of the second MOS tube Q2 is connected with an arbitrary point between the first inductor L1 and the second inductor L2, the source of the second MOS tube Q2 is connected with the voltage negative output terminal VO-, the cathode of the first diode D1, one end of the first capacitor C1 and the anode of the fourth diode D4 are connected with the gate of the first MOS tube Q1 respectively, the cathode of the fourth diode D4 and one end of the third capacitor C3 are connected with the 1# output terminal (pin 2) of the second selection switch K2 respectively, the anode of the first diode D1 is connected with the gate of the second MOS tube Q2, the other end of the first capacitor C1 and the other end of the third capacitor C3 are grounded respectively, the input terminal (pin 1) of the second electronic selection switch K2 is connected with the gate of the third MOS tube Q3, the 0# output terminal (pin 3) of the second electronic selection switch K2 is connected with the output terminal of the inverter U4.The input end of the inverter U4 is connected with the gate of the second MOS Q2, the anode of the second diode D2 is connected with the negative voltage output terminal VO-, the cathode of the second diode D2 is connected with the source of the first MOS Q1, one end of the second capacitor C2 is connected with the positive voltage output terminal VO+, and the other end of the second capacitor C2 is connected with the negative voltage output terminal VO-.

[0021] The working principle of the input and output same phase boost-buck DC conversion circuit of the embodiment 2 is basically same as that of the input and output same phase boost-buck DC conversion circuit of the embodiment 1, and the difference is that when the whole circuit operates as a boost circuit, the second electronic selection switch K2 selects the 0# output terminal (pin 3), that is, the input end (pin 1) of the second electronic selection switch K2 is in communication with the 0# output terminal (pin 3), when the PWM2 signal of the 0# output terminal (pin 3) of the first electronic selection switch K1 is high, the second MOS Q2 is turned on, and the PWM2 signal is inverted to low by the inverter U4, at this time, the third MOS Q3 is cut off, and the first inductor L1 stores energy; when the PWM2 signal of the 0# output terminal (pin 3) of the first electronic selection switch K1 is low, the second MOS Q2 is cut off, and the PWM2 signal is inverted to high by the inverter U4, at this time, the third MOS Q3 is turned on, the first inductor L1 releases energy, and the induced potential is reversed, which is superimposed on the input voltage Uin to play a role of boosting. When the whole circuit operates as a bulk circuit, the second electronic selection switch K2 selects the 1# output terminal (pin 2), that is, the input end (pin 1) of the second electronic selection switch K2 is in communication with the 1# output terminal (pin 2), at this time, the gate of the third MOS Q3 is in communication with the cathode of the fourth diode D4, the gate of the first MOS Q1 is driven by the PWM1 signal (that is, the PWM signal) of the 1# output terminal (pin 2) of the first electronic selection switch K1, the PWM1 signal is converted to high level by the fourth diode D4 and the third capacitor C3, and the third MOS Q3 is driven by the high level of the PWM1 signal, the third MOS Q3 is always turned on in the process of bucking, when the PWM1 signal (that is, the PWM signal) is high, the first MOS Q1 is turned on, the first inductor L1 and the second inductor L2 store energy, when the PWM1 signal (that is, the PWM signal) is low, the first MOS Q1 is cut off, the first inductor L1 and the second inductor L2 release energy, and the induced potential is reversed, and the second diode D2 continues to flow.

[0022] In the input and output same phase boost-buck DC conversion circuit of the embodiment 2, the third MOS Q3 replaces the third diode D3 to play a role of synchronous rectification, which can reduce the voltage of the diode, reduce the power loss, and improve the conversion efficiency.

Claims

1. A step-up / step-down DC-DC converter circuit with input and output in phase, characterized in that: The PWM comparator (U1), error amplifier (U2), voltage comparator (U3), first electronic selection switch (K1), first diode (D1), third diode (D3), first inductor (L1), second inductor (L2), first MOS tube (Q1), second MOS tube (Q2), first resistor (R1), second resistor (R2), third resistor (R3), fourth resistor (R4) and first capacitor (C1), one end of the first resistor (R1) is connected with one end of the second resistor (R2), the other end of the first resistor (R1) is connected with the voltage positive input end (VI+), the other end of the second resistor (R2) is connected with the voltage negative input end (VI-), one end of the third resistor (R3) is connected with one end of the fourth resistor (R4) in series, the other end of the third resistor (R3) is connected with the voltage positive output end (VO+), the other end of the fourth resistor (R4) is connected with the voltage negative output end (VO-), the voltage negative input end (VI-) is connected with the voltage negative output end (VO-), the drain of the first MOS tube (Q1) is connected with the voltage positive input end (VI+), the source of the first MOS tube (Q1) is connected with the anode of the third diode (D3) after being connected with the first inductor (L1) and the second inductor (L2) in series, the cathode of the third diode (D3) is connected with the voltage positive output end (VO+), an arbitrary point between the first resistor (R1) and the second resistor (R2) is connected with the non-inverting input end of the voltage comparator (U3), the output end of the voltage comparator (U3) is connected with the selection end of the first electronic selection switch (K1), the 1# output end of the first electronic selection switch (K1) is connected with the gate of the first MOS tube (Q1), the 0# output end of the first electronic selection switch (K1) is connected with the gate of the second MOS tube (Q2), the input end of the first electronic selection switch (K1) is connected with the output end of the PWM comparator (U1), the non-inverting input end of the PWM comparator (U1) is used for inputting a triangular wave function signal, the non-inverting input end of the PWM comparator (U1) is connected with the output end of the error amplifier (U2), the non-inverting input end of the error amplifier (U2) is connected with an arbitrary point between the third resistor (R3) and the fourth resistor (R4), the non-inverting input end of the error amplifier (U2) and the non-inverting input end of the voltage comparator (U3) are respectively used for inputting a reference voltage, the drain of the second MOS tube (Q2) is connected with an arbitrary point between the first inductor (L1) and the second inductor (L2), the source of the second MOS tube (Q2) is connected with the voltage negative output end (VO-), the cathode of the first diode (D1) and one end of the first capacitor (C1) are respectively connected with the gate of the first MOS tube (Q1), the anode of the first diode (D1) is connected with the gate of the second MOS tube (Q2), the other end of the first capacitor (C1) is grounded.

2. The input and output in-phase boost-buck DC conversion circuit according to claim 1, characterized by: A second diode (D2) is further included, an anode of the second diode (D2) is connected to the voltage negative output end (VO-), and a cathode of the second diode (D2) is connected to a source of the first MOS tube (Q1).

3. The input and output in-phase boost-buck DC conversion circuit according to claim 1 or 2, characterized by: A second capacitor (C2) is further included, one end of the second capacitor (C2) is connected to the voltage positive output end (VO+), and the other end of the second capacitor (C2) is connected to the voltage negative output end (VO-).

4. A buck-boost DC-DC converter circuit with input and output in phase, characterized in that: The PWM comparator (U1), error amplifier (U2), voltage comparator (U3), inverter (U4), first electronic selection switch (K1), second electronic selection switch (K2), first diode (D1), fourth diode (D4), first inductor (L1), second inductor (L2), first MOS tube (Q1), second MOS tube (Q2), third MOS tube (Q3), first resistor (R1), second resistor (R2), third resistor (R3), fourth resistor (R4), first capacitor (C1) and third capacitor (C3), one end of the first resistor (R1) is connected with one end of the second resistor (R2), the other end of the first resistor (R1) is connected with the voltage positive input end (VI+), the other end of the second resistor (R2) is connected with the voltage negative input end (VI-), one end of the third resistor (R3) is connected with one end of the fourth resistor (R4) in series, the other end of the third resistor (R3) is connected with the voltage positive output end (VO+), the other end of the fourth resistor (R4) is connected with the voltage negative output end (VO-), the voltage negative input end (VI-) is connected with the voltage negative output end (VO-), the drain of the first MOS tube (Q1) is connected with the voltage positive input end (VI+), the source of the first MOS tube (Q1) is connected with the source of the third MOS tube (Q3) after being connected with the first inductor (L1) and the second inductor (L2) in series, the drain of the third MOS tube (Q3) is connected with the voltage positive output end (VO+), an arbitrary point between the first resistor (R1) and the second resistor (R2) is connected with the non-inverting input end of the voltage comparator (U3), the output end of the voltage comparator (U3) is connected with the selection end of the first electronic selection switch (K1) and the selection end of the second electronic selection switch (K2) respectively, the 1# output end of the first electronic selection switch (K1) is connected with the gate of the first MOS tube (Q1), the 0# output end of the first electronic selection switch (K1) is connected with the gate of the second MOS tube (Q2), the input end of the first electronic selection switch (K1) is connected with the output end of the PWM comparator (U1), the non-inverting input end of the PWM comparator (U1) is used for inputting a triangular wave function signal, the non-inverting input end of the PWM comparator (U1) is connected with the output end of the error amplifier (U2), the non-inverting input end of the error amplifier (U2) is connected with an arbitrary point between the third resistor (R3) and the fourth resistor (R4), the non-inverting input end of the error amplifier (U2) and the non-inverting input end of the voltage comparator (U3) are used for inputting a reference voltage respectively, the drain of the second MOS tube (Q2) is connected with an arbitrary point between the first inductor (L1) and the second inductor (L2), the source of the second MOS tube (Q2) is connected with the voltage negative output end (VO-), the cathode of the first diode (D1), one end of the first capacitor (C1) and the anode of the fourth diode (D4) are connected with the gate of the first MOS tube (Q1) respectively,The cathode of the fourth diode (D4) and one end of the third capacitor (C3) are connected to the 1# output end of the second selection switch (K2) respectively, the anode of the first diode (D1) is connected to the gate of the second MOS tube (Q2), the other end of the first capacitor (C1) and the other end of the third capacitor (C3) are grounded respectively, the input end of the second electronic selection switch (K2) is connected to the gate of the third MOS tube (Q3), the 0# output end of the second electronic selection switch (K2) is connected to the output end of the inverter (U4), and the input end of the inverter (U4) is connected to the gate of the second MOS tube (Q2).

5. The input and output in-phase boost-buck DC conversion circuit according to claim 4, characterized by: A second diode (D2) is further included, an anode of the second diode (D2) is connected to the voltage negative output end (VO-), and a cathode of the second diode (D2) is connected to a source of the first MOS tube (Q1).

6. The input and output in-phase boost-buck DC conversion circuit according to claim 4 or 5, characterized by: A second capacitor (C2) is further included, one end of the second capacitor (C2) is connected to the voltage positive output end (VO+), and the other end of the second capacitor (C2) is connected to the voltage negative output end (VO-).

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