Digital clock data recovery circuit and method

Abstract

The invention provides a digital clock data recovery circuit and method. The digital clock data recovery circuit comprises an analog-to-digital converter used for sampling an analog input signal under the control of a sampling clock signal and converting the sampled signal into a digital signal; the error detector is used for carrying out phase error detection according to the digital signal to obtain a phase error estimation value; the frequency deviation detector is used for acquiring a frequency deviation estimation value according to the phase error estimation value; the loop filter is used for filtering according to the phase error estimation value and the frequency deviation estimation value and outputting a filtering signal; the phase code generator is used for generating a phase code according to the filtering signal; and the phase interpolator is used for generating the sampling clock signal according to the phase code so as to control the sampling phase of the analog-to-digital converter. The digital clock data recovery circuit can quickly capture clock frequency deviation.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of clock data recovery, and relates to a digital clock data recovery circuit, in particular to a digital clock data recovery circuit and method. BACKGROUND

[0002] CDR (Clock Data Recovery) is a key technology in digital communication, which is mainly used to recover an accurate clock signal from input data and to recover and synchronize data according to the clock signal. Within a limited frequency deviation (the deviation between the sampling clock frequency and the clock frequency of the input data), a CDR circuit based on phase error can well capture the frequency deviation. However, when the communication rate is improved, the loop delay rises due to the limitation of circuit parameters, the CDR convergence frequency range decreases, and the frequency deviation caused by the clock difference still rises, which leads to a longer capture time of the CDR circuit based on phase error, or the frequency deviation needs to be captured through multiple different frequency offset initializations, or even error-locked on a certain biased frequency. That is, the existing CDR circuit based on phase error is not suitable for application scenarios with large frequency deviation, especially scenarios with SSC (Spread Spectrum Clocking).

[0003] Therefore, in the application scenario of large frequency deviation, how to quickly and accurately capture the frequency deviation is still a problem to be solved. SUMMARY

[0004] The purpose of the present application is to provide a digital clock data recovery circuit and method for quickly capturing clock frequency deviation in the application scenario of large frequency deviation.

[0005] In a first aspect, an embodiment of the present application provides a digital clock data recovery circuit, comprising: an analog-to-digital converter configured to sample an analog input signal under the control of a sampling clock signal and convert the sampled signal into a digital signal; an error detector configured to perform phase error detection based on the digital signal to obtain a phase error estimate; a frequency deviation detector configured to obtain a frequency deviation estimate based on the phase error estimate; a loop filter configured to filter based on the phase error estimate and the frequency deviation estimate and output a filtered signal; a phase code generator configured to generate a phase code based on the filtered signal; and a phase interpolator configured to generate the sampling clock signal based on the phase code to control the sampling phase of the analog-to-digital converter.

[0006] In some embodiments, the phase interpolator adjusts the phase of a local reference clock based on the phase code to generate the sampling clock signal.

[0007] In some embodiments, the frequency deviation detector comprises: a pre-processing unit configured to pre-process the received phase error estimation values; a difference calculation unit configured to obtain a difference sequence from the pre-processed phase error estimation values; and a frequency deviation calculation unit configured to calculate the frequency deviation estimation value from the difference sequence.

[0008] In some embodiments, the difference sequence is an indication signal of phase error estimation value jump.

[0009] In some embodiments, the difference calculation unit calculates the indication signal of phase error estimation value jump according to the following formula:

[0010] f(i) = compare(s(i) - s(i - τ), th1);

[0011]

[0012] where s(i) is the pre-processed phase error estimation value, th1 is a first threshold value, τ is a time interval between adjacent two phase error estimation values, and sign is a sign function.

[0013] In some embodiments, the frequency deviation calculation unit is configured to calculate the frequency deviation estimation value from an integral value of the indication signal of phase error estimation value jump within a specific time interval.

[0014] In some embodiments, the frequency deviation calculation unit calculates the frequency deviation estimation value Δfrq(i) according to the following formula:

[0015]

[0016] frqdetintg(i) = frqdetintg(i - 1) + f(i);

[0017]

[0018] where frqdetintg(i) is a cumulative indication signal of phase error estimation value jump, f(i) is the indication signal of phase error estimation value jump, mod is a modulo function, T is the specific time interval, frqslp is a slope of the integral value of the indication signal of phase error estimation value jump, floor is a floor function, and frqth is a cumulative count threshold of phase error estimation value jump.

[0019] In some embodiments, the frequency deviation calculation unit is configured to calculate the frequency deviation estimation value from a time required for the indication signal of phase error estimation value jump to be integrated to an upper limit or a lower limit value.

[0020] In some embodiments, the loop filter is a second order filter.

[0021] In some embodiments, the frequency integral branch of the second order filter is described by:

[0022] intg(i) = intg(i-1) + β * ted(i) + Δfrq(i) ;

[0023] where intg(i) is the output of the loop filter at time i, intg(i-1) is the output of the loop filter at the previous time of time i, β is a coefficient, ted(i) is the phase error estimate, and Δfrq(i) is the frequency deviation estimate.

[0024] In some embodiments, when the number of detections of the frequency deviation detector reaches a detection threshold, and all the detected frequency deviation estimates are less than a second threshold, the frequency deviation detector is turned off, and the loop filter obtains the filtered signal according to the phase error estimate.

[0025] In some embodiments, the number of phase error estimates is multiple, and the frequency deviation detector obtains the frequency deviation estimate according to the average of multiple phase error estimates.

[0026] In a second aspect, an embodiment of the present application provides a digital clock data recovery method, which is applied to a digital clock data recovery circuit, the circuit comprising an analog-to-digital converter, an error detector, a frequency deviation detector, a loop filter, a phase code generator, and a phase interpolator; the method comprising: sampling an analog input signal under the control of a sampling clock signal by the analog-to-digital converter and converting the sampled signal into a digital signal; detecting a phase error according to the digital signal by the error detector to obtain a phase error estimate; obtaining a frequency deviation estimate according to the phase error estimate by the frequency deviation detector; filtering according to the phase error estimate and the frequency deviation estimate by the loop filter and outputting a filtered signal; generating a phase code according to the filtered signal by the phase code generator; and generating the sampling clock signal according to the phase code by the phase interpolator.

[0027] The digital clock data recovery circuit provided by the embodiment of the present application utilizes the corresponding relationship between the time sequence of the phase error estimation value and the frequency deviation estimation value, embeds the frequency deviation detector into the CDR circuit based on the phase error, and makes the frequency deviation detector calculate the change slope of the phase error estimation value according to the phase error estimation value, and then estimates the frequency deviation according to the change slope. The frequency deviation estimated based on the frequency deviation detector can quickly limit the residual clock frequency deviation within the working range of the CDR circuit, and then the CDR circuit can quickly track and capture the clock signal. In this way, the CDR circuit can obtain a larger frequency deviation capture range, and in the application scenario of large frequency deviation, the frequency deviation can be quickly and accurately captured.

[0028] In addition, the clock frequency deviation tracking is limited by the circuit delay, which means a higher processing clock or fewer processing beats for the digital receiving end of the high-speed interface. The embodiment of the present application introduces the frequency deviation detector in the digital clock data recovery circuit, reduces the timing requirements of the circuit, and brings greater flexibility to the circuit design.

[0029] Furthermore, the digital clock data recovery circuit provided by the embodiment of the present application only needs to add a frequency deviation detector in the CDR circuit to greatly expand the lock range of the frequency deviation, has low complexity, and is easier to implement. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 An example diagram showing the frequency deviation between the clock frequency of the error lock and the actual clock frequency in the large frequency deviation scenario.

[0031] Figure 2A A structural schematic diagram of the digital clock data recovery circuit provided by the embodiment of the present application is shown.

[0032] Figure 2B An example diagram showing that the sampling clock frequency is locked from the error lock on the bias frequency to the successful lock on the actual clock frequency in the embodiment of the present application.

[0033] Figure 3A A relationship diagram of the sampling phase and the phase error estimation value when the data frequency is correctly locked in the embodiment of the present application.

[0034] Figure 3B A relationship diagram of the sampling phase and the phase error estimation value in the large frequency deviation scenario in the embodiment of the present application.

[0035] Figure 4 A structural schematic diagram of the frequency deviation detector in the embodiment of the present application is shown.

[0036] Figure 5 A simulation diagram showing the relationship between frqdetintg and the actual frequency deviation in the embodiment of the present application.

[0037] Figure 6 A flow chart of a digital clock data recovery method provided by embodiments of the present application is shown. DETAILED DESCRIPTION

[0038] The above objectives and other advantages of the present application are achieved by the embodiments described below. Other advantages of the present application will be realized and appreciated by those skilled in the art, upon reading this specification and / or upon learning by practice of the application. In some embodiments, the following described aspects, embodiments and / or examples can be mixed and / or combined with each other.

[0039] It is to be understood that the above-mentioned arrangements are merely meant to illustrate the general principles of embodiments of the application, and the drawings are merely meant to illustrate the general structure of embodiments of the application and are not drawn to scale, and the actual implementation of the components shown in the drawings can vary greatly in terms of shape, size and number, and the layout of the components can also be more complex.

[0040] In the description of the present application, the terms "first", "second", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically defined.

[0041] In the present application, unless otherwise specifically defined and limited, the terms "connected", "connected" and the like should be understood in a broad sense, for example, it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0042] For the CDR circuit, loop locking refers to the process that the control loop in the CDR circuit successfully locks to the clock frequency (hereinafter also referred to as data frequency) and phase of the input data, and can maintain this locked state. When the frequency deviation between the sampling clock frequency and the data frequency is large, loop locking is more difficult, and may appear the situation of not locking or false locking.

[0043] In cases of fault locking, the presence of a large frequency deviation causes the sampling phase to rapidly traverse the entire cycle. The value of the phase error detection signal (e.g., the timing error detection signal) will repeatedly traverse from positive to negative or from negative to positive, resulting in a frequency integral of 0. Consequently, the sampling clock frequency and the data frequency will always deviate by a fixed value, such as... Figure 1 As shown, Figure 1 The actual clock frequency is used to indicate the data frequency, while the clock frequency for error locking is used to indicate the sampling clock frequency. In the event of error locking, the CDR circuit needs to be detected and reset, which affects the establishment of clock synchronization and prolongs the time to enter the normal receiving state. Some technical solutions solve the error locking problem by adding a frequency discriminator; however, this method involves a large amount of computation and has high latency requirements, resulting in a high circuit implementation cost.

[0044] In cases where locking is not possible, the CDR circuit cannot successfully lock onto the clock frequency and phase of the input data, which prevents the receiver from sampling the data correctly, resulting in reception failure.

[0045] To address at least the aforementioned problems, embodiments of this application provide a digital clock data recovery circuit. The technical solutions in these embodiments will now be described in detail with reference to the accompanying drawings.

[0046] Figure 2A The diagram shown is a structural schematic of a digital clock data recovery circuit provided in an embodiment of this application. Figure 2A As shown, the digital clock data recovery circuit 2 includes an analog-to-digital converter (ADC) 21, an error detector 22, a frequency deviation detector 23, a loop filter (LF) 24, a phase code generator 25, and a phase interpolator (PI) 26.

[0047] The analog-to-digital converter 21 is used to sample the analog input signal under the control of the sampling clock signal and convert the sampled signal into a digital signal for subsequent signal processing and clock recovery.

[0048] Error detector 22 is used to perform phase error detection based on the digital signal output by analog-to-digital converter 21 to obtain a phase error estimate. The phase error estimate is used to indicate the offset of the sampling phase corresponding to the analog input signal relative to the ideal sampling phase, which is the middle phase within a unit time interval (i.e., 1 UI (Unit Interval)).

[0049] In some embodiments, the error detector 22 can employ a BB-like algorithm based on a high multiple of the sampling rate or a MM-like algorithm based on the baud rate for phase error detection.

[0050] In some embodiments, the error detector 22 can be a phase error detector (PED) or a timing error detector (TED).

[0051] The phase error estimate detected by the error detector 22 is output to the frequency deviation detector 23 and the loop filter 24 respectively.

[0052] The frequency deviation detector 23 is configured to obtain a frequency deviation estimate from the phase error estimate. The working principle of the frequency deviation detector 23 will be described in detail below.

[0053] The loop filter 24 is configured to filter the phase error estimate output by the error detector 22 and the frequency deviation estimate output by the frequency deviation detector 23 and output a filtered signal. The filtered signal is used to represent the frequency deviation between the sampling clock frequency and the data frequency.

[0054] The phase code generator 25 is configured to generate a phase code from the filtered signal. In some embodiments, the phase code can be an interpolated phase code of a phase interpolator.

[0055] The phase interpolator 26 is configured to generate a sampling clock signal from the phase code to control the sampling phase of the analog-to-digital converter 21.

[0056] In some embodiments, a local reference clock can be provided, and the phase interpolator 26 can adjust the phase of the local reference clock according to the phase code to generate the sampling clock signal.

[0057] The digital clock data recovery circuit provided by the embodiments of the present application can quickly achieve loop locking. Figure 2B The figure shows an example of the sampling clock frequency being locked from an offset frequency to the actual clock frequency in the embodiments of the present application. As can be seen, the embodiments of the present application can quickly establish clock synchronization, which is beneficial to shorten the time for the receiving end to enter the normal receiving state.

[0058] Next, the principle of the frequency deviation detector 23 will be introduced. Specifically, when the phase error is detected by the error detector 22, the phase error estimate output by the error detector 22 is different for different sampling phases. When sampling at the ideal sampling phase, the phase error estimate is 0. When sampling in advance, the phase error estimate is positive. When sampling with lag, the phase error estimate is negative.

[0059] Figure 3A A graph showing the relationship between the sampling phase and the phase error estimate when the data frequency is locked correctly, where the horizontal axis represents the sampling phase corresponding to different UIs, and the vertical axis represents the phase error estimate output by the error detector 22. As shown in Figure 3A , when the data frequency is locked correctly, the sampling phase wanders within region A. At this time, the phase error estimate fluctuates within a small range, and the phase error estimates of adjacent UIs are similar.

[0060] Figure 3B A graph showing the relationship between the sampling phase and the phase error estimate when the frequency offset is large, where the horizontal axis represents the sampling phase corresponding to different UIs, and the vertical axis represents the phase error estimate output by the error detector 22. As shown in Figure 3B , when the sampling clock frequency is largely offset from the data frequency, the sampling phase will cross the entire UI, and even appear to flip across the UI. At this time, the error detector 22 will periodically output values from negative to positive or from positive to negative, the differential value of the phase error estimate is large, and there can be a large value polarity jump between adjacent phase error estimates (for example, from a negative maximum value to a positive maximum value, or from a positive maximum value to a negative maximum value), as indicated by arrows B and C in Figure 3B . If the sampling clock frequency is slower than the data frequency, the jump indicated by arrow B will occur, and if the sampling clock frequency is faster than the data frequency, the jump indicated by arrow C will occur, and the jump interval is proportional to the size of the frequency offset. Based on this, the frequency offset detector 23 can determine whether the data frequency is locked correctly by detecting whether there is a jump in the phase error estimate. Further, in the unlocked or incorrectly locked state, the frequency offset detector 23 can estimate the size of the frequency offset to obtain a frequency offset estimate by detecting the size of the jump interval. The jump interval refers to the time interval between two occurrences of a positive-to-negative or negative-to-positive phase error estimate.

[0061] Referring to Figure 4 , in some embodiments, the frequency offset detector 23 includes a preprocessing unit 231, a difference calculation unit 232, and a frequency offset calculation unit 233. The preprocessing unit 231 is configured to preprocess the received phase error estimate to reduce the noise of the phase error estimate. The difference calculation unit 232 is configured to obtain a difference sequence from the preprocessed phase error estimate, the difference sequence being used to indicate the change slope of the phase error estimate. The frequency offset calculation unit 233 is configured to calculate a frequency offset estimate from the difference sequence.

[0062] Exemplarily, the preprocessing unit 231 can be a low-pass filter (LPF). The low-pass filter is configured to low-pass filter the phase error estimate, as shown in the following formula (1):

[0063] s(i) = ted(i) * a + s(i-1) * (1-a), equation (1);

[0064] where s(i) is the output of the pre-processing unit 231 at time i, ted(i) is the phase error estimate output by the error detector 22, a is the coefficient of the low-pass filter, and s(i-1) represents the output of the pre-processing unit 231 at the previous time of time i.

[0065] Exemplarily, the pre-processing unit 231 can also be a median filter (MF).

[0066] It should be noted that the low-pass filter and the median filter described above are only two implementation manners of the pre-processing unit 231 in the embodiments of the present application, but the present application is not limited thereto.

[0067] In some embodiments, the differential sequence is an indication signal f(i) of a phase error estimate jump. The differential calculation unit 232 can calculate the indication signal f(i) of the phase error estimate jump based on the following equation (2) and equation (3):

[0068] f(i) = compare(s(i)-s(i-τ), th1), equation (2);

[0069]

[0070] where s(i) is the pre-processed phase error estimate, τ is the calculation interval, i.e., the time interval between the output of two adjacent phase error estimates, th1 is the first threshold value, which can be set according to actual requirements or experience, sign is the sign function, and abs is the absolute value function.

[0071] In some embodiments, the frequency offset calculation unit 233 can calculate the frequency deviation estimate Δfrq(i) according to the integral value of the indication signal f(i) of the phase error estimate jump within a specific time interval.

[0072] Exemplarily, the frequency offset calculation unit 233 can calculate the frequency deviation estimate Δfrq(i) according to the following equations (4) to (6):

[0073]

[0074] where frqdetintg(i) = frgdetintg(i-1) + f(i), equation (5);

[0075] est is a look-up table operation, and the mapping relationship is:

[0076] wherein frqdetintg(i) is a cumulative indication signal of phase error estimation value jump, mod is a modulo function, T is a specific time interval, floor is a floor function, plays a role of rounding off frqth is a cumulative count threshold of phase error estimation value jump, which is proportional to the specific time interval T, so that can represent the proportion of phase error estimation value jump in the specific time interval T. frqslp is the slope of the integral value of the indication signal of phase error estimation value jump, which is a constant for example, and the specific value can be set according to actual requirements or experience. In some embodiments, the value of frqslp can also be estimated by simulation. For example, Figure 5 shows a simulation diagram of the relationship between frqdetintg and the actual frequency deviation, and the slope in the diagram is frqslp.

[0077] Exemplarily, if the frequency deviation convergence boundary of the CDR circuit is cdrppmth, in ppm, the above specific time interval T needs to satisfy Only in this way can the coverage of the frequency deviation range and the accuracy of the calculation be ensured.

[0078] In some embodiments, the time interval T can not be specified, but the upper and / or lower limit values of frqdetintg can be specified, and the frequency deviation estimation value can be calculated according to the time required for frqdetintg to reach the upper or lower limit value. Specifically, the greater the frequency deviation, the faster the integral of the indication signal of phase error estimation value jump. Based on this, the frequency deviation calculation unit 233 in the embodiments of the present application can calculate the frequency deviation estimation value according to the integral value of the indication signal of phase error estimation value jump in the specific time interval T, or according to the time required for the integral of the indication signal of phase error estimation value jump to reach the upper or lower limit value.

[0079] It should be noted that there are many ways for the frequency deviation calculation unit 233 to calculate the frequency deviation estimation value, and the above only exemplarily lists two ways, but the present application is not limited thereto.

[0080] In some embodiments, the loop filter 24 can be a second-order filter. The frequency integral branch thereof can be described by the following formula (7):

[0081] intg(i) = intg(i-1) + β*ted(i) + Δfrq(i), formula (7);

[0082] Wherein, intg(i) is the output of the loop filter 24 at time i, intg(i-1) is the output of the loop filter 24 at the last time of time i, β is a coefficient, which can be set according to requirements or experience, ted(i) is the phase error estimation value output by the error detector 22, and Δfrq(i) is the frequency deviation estimation value output by the frequency deviation detector 23. It can be seen that the filtered signal output by the loop filter 24 includes the frequency deviation estimation value calculated according to the phase error estimation value and the frequency deviation estimation value output by the frequency deviation detector 23. This is because when the frequency deviation between the sampling clock frequency and the data frequency is too large, the phase error estimation value periodically changes from negative to positive or from positive to negative, and the frequency deviation estimation value calculated according to the phase error estimation value can be 0. Therefore, if the frequency deviation is calculated only according to the phase error estimation value, the actual frequency deviation estimation value cannot be correctly obtained, and at this time, the frequency deviation between the sampling clock frequency and the data frequency needs to be obtained according to the frequency deviation estimation value output by the frequency deviation detector 23.

[0083] In some embodiments, the loop filter 24 can be implemented in a multi-order PI (Proportional-Integral) structure, and the specific order can be set according to actual requirements or experience.

[0084] In some embodiments, a detection threshold can be set, and if the frequency deviation estimation values detected by the frequency deviation detector 23 for multiple times (the number of detection times reaches the detection threshold) are all less than the second threshold, it indicates that the frequency deviation is small, at this time, the frequency deviation detector 23 can be closed, and the loop filter 24 can obtain the filtered signal according to the phase error estimation value. The values of the detection threshold and the second threshold can be set according to actual requirements or experience.

[0085] In some embodiments, the number of phase error estimation values can be multiple. For example, the ADC-based RX includes multiple analog-to-digital converters, and the error detector can obtain multiple phase error estimation values according to the digital signals output by the multiple analog-to-digital converters. At this time, the phase error estimation values output by the error detector appear in the form of blocks, and the digital calculation clock corresponds to multiple data clocks. In these embodiments, the frequency deviation detector 23 can calculate the frequency deviation estimation value according to the average of the multiple phase error estimation values.

[0086] In summary, the embodiment of the present application provides a digital clock data recovery circuit, which utilizes the correspondence between the time series of the phase error estimation value and the frequency deviation estimation value, embeds a frequency deviation detector in the phase error-based CDR circuit, and causes the frequency deviation detector to calculate the change slope of the phase error estimation value according to the phase error estimation value, and further estimate the frequency deviation according to the change slope. The frequency deviation estimated based on the frequency deviation detector can quickly limit the residual clock frequency deviation within the working range of the CDR circuit, and further cause the CDR circuit to quickly track and capture the clock signal. In this way, the CDR circuit can obtain a larger frequency deviation capture range, and can quickly and accurately capture the frequency deviation in the application scenario of large frequency deviation.

[0087] In addition, the clock frequency deviation tracking is limited by the circuit delay, which means a higher processing clock or fewer processing beats for the digital receiving end of the high-speed interface. The embodiment of the present application introduces a frequency deviation detector in the digital clock data recovery circuit, reduces the timing requirements of the circuit, and brings greater flexibility to the circuit design.

[0088] Furthermore, the digital clock data recovery circuit provided by the embodiment of the present application only needs to add a frequency deviation detector in the CDR circuit to greatly expand the locking range of the frequency deviation, has low complexity, and is easier to implement.

[0089] The embodiment of the present application also provides a digital clock data recovery method, which can be applied to the above-mentioned digital clock data recovery circuit. Figure 6 A flowchart of the digital clock data recovery method is shown. As shown in Figure 6 The digital clock data recovery method includes:

[0090] S61, sampling the analog input signal under the control of the sampling clock signal by the analog-to-digital converter and converting the sampled signal into a digital signal.

[0091] S62, performing phase error detection by the error detector according to the digital signal to obtain a phase error estimation value.

[0092] S63, obtaining a frequency deviation estimation value by the frequency deviation detector according to the phase error estimation value.

[0093] S64, filtering by the loop filter according to the phase error estimation value and the frequency deviation estimation value and outputting a filtered signal.

[0094] S65, generating a phase code by the phase code generator according to the filtered signal.

[0095] S66, generating a sampling clock signal by the phase interpolator according to the phase code.

[0096] It should be noted that the steps S61 to S66 described above correspond one-to-one to the corresponding modules in the digital clock data recovery circuit shown in Figure 2A and will not be described here.

[0097] The protection scope of the digital clock data recovery method described in the embodiments of the present application is not limited to the above-mentioned step execution order, and any scheme realized by adding, reducing or replacing steps of the prior art according to the principles of the present application is included in the protection scope of the present application.

[0098] The digital clock data recovery circuit provided in the embodiments of the present application can implement the digital clock data recovery method provided in the embodiments of the present application, but the implementation device of the digital clock data recovery method provided in the embodiments of the present application includes but is not limited to the digital clock data recovery circuit listed in the embodiments of the present application, and any structural deformation and replacement of the prior art according to the principles of the embodiments of the present application is included in the protection scope of the present application.

[0099] In several embodiments provided in the present application, it should be understood that the disclosed system, device or method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the modules / units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, device or module or unit indirect coupling or communication connection, which can be electrical, mechanical or other forms.

[0100] The modules / units described as separate components can or can not be physically separated, and the components shown as modules / units can or can not be physical modules, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the modules / units can be selected to achieve the purpose of the embodiments of the present application. For example, the functional modules / units in each embodiment of the present application can be integrated in one processing module, or each module / unit can be physically separated, or two or more modules / units can be integrated in one module / unit.

[0101] Those skilled in the art should further understand that units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in the above description in a general manner. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0102] The descriptions of the corresponding processes or structures of each of the above figures have different focuses, and the parts not described in detail in a certain process or structure can be referred to the related descriptions of other processes or structures.

[0103] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea of the present application should be covered by the claims of the present application.

Claims

1. A digital clock data recovery circuit, characterized by, The application relates to an analog-to-digital converter, comprising: an analog-to-digital converter for sampling an analog input signal under the control of a sampling clock signal and converting the sampled signal into a digital signal; an error detector for phase error detection based on the digital signal to obtain a phase error estimate; a frequency deviation detector for obtaining a frequency deviation estimate based on the phase error estimate; a loop filter for filtering based on the phase error estimate and the frequency deviation estimate and outputting a filtered signal; a phase code generator for generating a phase code based on the filtered signal; a phase interpolator for generating the sampling clock signal based on the phase code to control the sampling phase of the analog-to-digital converter.

2. The digital clock data recovery circuit of claim 1, wherein, The phase interpolator adjusts the phase of a local reference clock based on the phase code to generate the sampling clock signal.

3. The digital clock data recovery circuit of claim 1, wherein, The frequency deviation detector comprises: a preprocessing unit for preprocessing the received phase error estimate; a difference calculation unit for obtaining a difference sequence based on the preprocessed phase error estimate; a frequency deviation calculation unit for calculating the frequency deviation estimate based on the difference sequence.

4. The digital clock data recovery circuit of claim 3, wherein, The difference sequence is an indication signal of phase error estimate jump.

5. The digital clock data recovery circuit of claim 4, wherein, The difference calculation unit calculates the indication signal of phase error estimate jump according to the following formula: f(i) = compare (s(i) - s(i-τ), th1); where s(i) is the preprocessed phase error estimate, th1 is a first threshold value, τ is the time interval between the output of two adjacent phase error estimates, and sign is a sign function.

6. The digital clock data recovery circuit of claim 4, wherein, The frequency deviation calculation unit is configured to calculate the frequency deviation estimate based on the integral value of the indication signal of phase error estimate jump within a specific time interval.

7. A digital clock data recovery circuit as claimed in claim 6, characterized in that, The frequency deviation calculation unit calculates the frequency deviation estimate Δfrq(i) according to the following formula: frqdetintg(i) = frqdetintg(i-1) + f(i); where frqdetintg(i) is a cumulative indication signal of phase error estimate jump, f(i) is an indication signal of phase error estimate jump, mod is a modulo function, T is the specific time interval, frqslp is the slope of the integral value of the indication signal of phase error estimate jump, floor is a floor function, and frqth is a cumulative count threshold of phase error estimate jump.

8. The digital clock data recovery circuit of claim 4, wherein, The frequency deviation calculation unit is configured to calculate the frequency deviation estimate based on the time required for the integral of the indication signal of phase error estimate jump to reach an upper limit or a lower limit.

9. The digital clock data recovery circuit of claim 1, wherein, The loop filter is a second-order filter.

10. The digital clock data recovery circuit of claim 9, wherein, The frequency integral branch of the second-order filter is described by the following formula: intg(i) = intg(i-1) + β*ted(i) + Δfrq(i); where intg(i) is the output of the loop filter at time i, intg(i-1) is the output of the loop filter at the previous time of time i, β is a coefficient, ted(i) is the phase error estimate, and Δfrq(i) is the frequency deviation estimate.

11. The digital clock data recovery circuit of claim 1, wherein, When the number of detections of the frequency deviation detector reaches a detection threshold, and the detected frequency deviation estimation values are all less than a second threshold, the frequency deviation detector is closed, and the loop filter acquires the filtered signal according to the phase error estimation value.

12. The digital clock data recovery circuit of claim 1, wherein, The number of phase error estimation values is multiple, and the frequency deviation detector acquires the frequency deviation estimation value according to an average of multiple phase error estimation values.

13. A method of digital clock data recovery, characterized by, The method is applied to a digital clock data recovery circuit, which comprises an analog-to-digital converter, an error detector, a frequency deviation detector, a loop filter, a phase code generator and a phase interpolator; the method comprises: sampling an analog input signal under the control of a sampling clock signal by the analog-to-digital converter and converting the sampled signal into a digital signal; detecting a phase error according to the digital signal by the error detector to acquire a phase error estimation value; acquiring a frequency deviation estimation value according to the phase error estimation value by the frequency deviation detector; filtering according to the phase error estimation value and the frequency deviation estimation value by the loop filter and outputting a filtered signal; generating a phase code according to the filtered signal by the phase code generator; generating the sampling clock signal according to the phase code by the phase interpolator.

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