Optical module

Abstract

The invention discloses an optical module, and relates to the technical field of optical communication, and the optical module comprises a power supply circuit, an electrical interface circuit, a digital signal processing unit, a main control circuit, an optical transmitting assembly, an optical receiving assembly, a laser driver and a bias current driving circuit, the light receiving assembly is connected with the digital signal processing unit, the digital signal processing unit is connected with the electrical interface circuit and the main control circuit, the input end of the laser driver is connected with the digital signal processing unit, the output end of the laser driver is connected with the light emitting assembly, and the input end of the bias current driving circuit is connected with the main control circuit. And the output end of the bias current driving circuit is connected with the laser driver. The invention provides the optical module adopting the PAM4 modulation technology, which is low in power consumption, small in packaging and high in transmission rate of 9.8-106.25 Gbps.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of optical communication technology, in particular to an optical module. BACKGROUND

[0002] For the future deployment of ultra-high channel Massive MIMO, 6-7GHz frequency band, millimeter wave base station and other scenarios, if the number of antennas and air interface bandwidth is further increased, operators need to expand more ports and consume more optical fibers to cope with it. The base station has always been one of the most important factors for port density, power consumption and optical fiber resources. By upgrading the single-channel rate from 50Gbps to 100Gbps, 100% of the ports can be saved, and 25% of the power consumption can be reduced, creating more flexibility for further improvement of front-end bandwidth. The application of single-channel 100Gbps PAM4 modulation SFP112 small package, low power consumption, high performance, high reliability and low cost temperature optical module in mobile front-end will become a challenge. SUMMARY

[0003] The present application aims to overcome at least one of the defects in the prior art, and provides an optical module.

[0004] The purpose of the present application is achieved by the following scheme: the present application discloses an optical module, comprising a power supply circuit, an electrical interface circuit, a digital signal processing unit, a main control circuit, an optical transmitting assembly, an optical receiving assembly, a laser driver and a bias current driving circuit, the power supply circuit is used to provide power supply for the whole optical module, the optical receiving assembly is connected with the digital signal processing unit, the digital signal processing unit is connected with the electrical interface circuit and the main control circuit, the input end of the laser driver is connected with the digital signal processing unit, the output end of the laser driver is connected with the optical transmitting assembly, the input end of the bias current driving circuit is connected with the main control circuit, and the output end of the bias current driving circuit is connected with the optical transmitting assembly.

[0005] In some embodiments, the power supply circuit comprises a first power management circuit, a second power management circuit and a third power management circuit, the input ends of the first power management circuit, the second power management circuit and the third power management circuit are connected with the output end of the slow start load switch circuit, the input end of the slow start load switch circuit is connected with the electrical interface circuit, the output end of the first power management circuit is connected with the first power input end of the digital signal processing unit, for providing the first voltage to the digital signal processing unit, the output end of the second power management circuit is connected with the second power input end of the digital signal processing unit, for providing the second voltage to the digital signal processing unit, the output end of the third power management circuit is connected with the power input end of the laser driver, for providing the third voltage to the laser driver, and the control ends of the first power management circuit, the second power management circuit and the third power management circuit are connected with the main control circuit respectively.

[0006] In some embodiments, the first power management circuit includes a first buck chip, an enable terminal of the first buck chip is connected with the main control circuit, the second power management circuit includes a second buck chip, an enable terminal of the second buck chip is connected with the main control circuit, and the third power management circuit includes a third buck chip, an enable terminal of the third buck chip is connected with the main control circuit.

[0007] In some embodiments, the bias current driving circuit includes an operational amplifier and a transistor, a non-inverting input terminal of the operational amplifier is connected with an output terminal of the DAC input circuit, an input terminal of the DAC input circuit is connected with a DAC output terminal of the main control circuit, the non-inverting input terminal of the operational amplifier is connected with the ground through a first resistor, the non-inverting input terminal of the operational amplifier is connected with an output terminal of the operational amplifier through a first capacitor, the output terminal of the operational amplifier is connected with a control electrode of the transistor, a first electrode of the transistor is connected with a power supply, a second electrode of the transistor is connected with the non-inverting input terminal of the operational amplifier through a third resistor, the second electrode of the transistor is connected with an output terminal of the bias current driving circuit, and the output terminal of the bias current driving circuit is connected with the laser driver for providing a D_Bias bias current for the laser driver.

[0008] In some embodiments, a second resistor is connected in series between the second electrode of the transistor and the output terminal of the bias current driving circuit, and the output terminal of the bias current driving circuit is connected with the non-inverting input terminal of the operational amplifier through a fourth resistor.

[0009] The signal conditioning circuit is further provided, two input terminals of the signal conditioning circuit are connected with two ends of the second resistor respectively, and an output terminal of the signal conditioning circuit is connected with the main control circuit.

[0010] And / or,

[0011] The DAC input circuit includes a voltage dividing network, the voltage dividing network includes a fifth resistor and a sixth resistor, one end of the fifth resistor and one end of the sixth resistor are connected with a DAC output terminal of the main control circuit, the other end of the fifth resistor is connected with the non-inverting input terminal of the operational amplifier, and the other end of the sixth resistor is connected with the ground.

[0012] And / or,

[0013] The DAC input circuit further includes a second capacitor, one end of the second capacitor is connected with the non-inverting input terminal of the operational amplifier, and the other end of the second capacitor is connected with the ground.

[0014] And / or,

[0015] The bias current driving circuit further includes a third capacitor, one end of the third capacitor is connected with the power supply, and the other end of the third capacitor is connected with the ground.

[0016] And / or,

[0017] The bias current driving circuit further comprises a fourth capacitor, one end of the fourth capacitor being connected to the output end of the bias current driving circuit, and the other end of the fourth capacitor being grounded.

[0018] In some embodiments, the optical module of the present application further comprises a crystal oscillator circuit for providing a reference clock for the digital signal processing unit, the crystal oscillator circuit comprising an active crystal oscillator module and a crystal oscillator voltage divider circuit, the crystal oscillator voltage divider circuit comprising a first voltage dividing resistor and a second voltage dividing resistor, one end of the first voltage dividing resistor being connected to a first output end of the active crystal oscillator module, the other end of the first voltage dividing resistor being grounded, one end of the second voltage dividing resistor being connected to a second output end of the active crystal oscillator module, the other end of the second voltage dividing resistor being grounded, a first attenuation resistor and a first AC coupling capacitor being connected in series between the first output end of the active crystal oscillator module and a first reference clock pin of the digital signal processing unit, and a second attenuation resistor and a second AC coupling capacitor being connected in series between the second output end of the active crystal oscillator module and a second reference clock pin of the digital signal processing unit.

[0019] In some embodiments, the digital signal processing unit comprises a receive automatic gain control module, a receive ADC module, a receive clock data recovery circuit, a receive FFE / DFE equalization module, a receive DAC module, and a receive limiting amplifier circuit, the receive automatic gain control module being configured to perform gain adjustment on an electrical signal output by the optical receiving assembly, the receive ADC module being configured to perform ADC conversion on the electrical signal output by the optical receiving assembly, the receive clock data recovery circuit being configured to perform clock data recovery on the electrical signal output by the optical receiving assembly, the receive FFE / DFE equalization module being configured to perform reflection cancellation and multipath interference compensation on the electrical signal output by the optical receiving assembly and provide a level-dependent equalizer, the receive DAC module being configured to perform DAC conversion on the electrical signal output by the optical receiving assembly, and the receive limiting amplifier circuit being configured to amplify the electrical signal output by the optical receiving assembly to a set value and output the amplified signal to the electrical interface circuit.

[0020] The digital signal processing unit comprises a transmit CTLE equalization module, a transmit ADC module, a transmit clock data recovery circuit, a transmit FFE / DFE equalization module, and a transmit DAC module, the transmit CTLE equalization module being configured to compensate for distortion of an electrical signal output by the electrical interface circuit, the transmit ADC module being configured to perform ADC conversion on the electrical signal output by the electrical interface circuit, the transmit clock data recovery circuit being configured to perform clock data recovery shaping on the electrical signal output by the electrical interface circuit, the transmit FFE / DFE equalization module being configured to perform reflection cancellation and multipath interference compensation on the electrical signal output by the electrical interface circuit and provide a level-dependent equalizer, and the transmit DAC module being configured to perform DAC conversion on the electrical signal output by the electrical interface circuit and output the converted signal to the laser driver.

[0021] In some embodiments, the digital signal processing unit further comprises a transmit automatic gain control module for gain adjustment of the electrical signal output by the electrical interface circuit.

[0022] In some embodiments, the digital signal processing unit further comprises a transmit FIR filter module on the transmit link. The transmit FIR filter module is located between the transmit FFE / DFE equalization module and the transmit DAC module.

[0023] In some embodiments, the digital signal processing unit further comprises a receive FIR filter module on the receive link. The receive FIR filter module is located between the receive FFE / DFE equalization module and the receive DAC module.

[0024] In some embodiments, the digital signal processing unit further comprises a transmit high-speed serializer for converting the parallel digital signal into a high-speed serial signal.

[0025] In some embodiments, the digital signal processing unit further comprises a receive high-speed serializer for converting the high-speed serial signal into a parallel digital signal.

[0026] In some embodiments, the laser driver and the optical transmitting component are electrically connected by a single-ended AC coupling driving mode.

[0027] and / or,

[0028] The optical receiving component and the digital signal processing unit are electrically connected by a high-speed differential AC coupling capacitor.

[0029] The laser driver and the optical transmitting component are electrically connected by a first flexible FPC board, and the optical receiving component and the digital signal processing unit are electrically connected by a second flexible FPC board.

[0030] In some embodiments, at least one of the electrical interface circuit, the digital signal processing unit, the main control circuit, the laser driver, and the bias current driving circuit is arranged on a main PCB board, the optical transmitting component, the optical receiving component, and the main PCB board are mounted between a module base and a module upper cover, the module base is detachably fixed with an optical port pressing block for fixing the optical transmitting component and the optical receiving component, the optical transmitting component and the main PCB board are electrically connected by a first flexible FPC board, and the optical receiving component and the main PCB board are electrically connected by a second flexible FPC board.

[0031] In some embodiments, the optical module of the present application further comprises a secondary PCB board, part of the electrical interface circuit, the digital signal processing unit, the main control circuit, and the laser driver and the bias current driving circuit are arranged on the secondary PCB board, and the other part is arranged on the main PCB board, and the secondary PCB board is connected with the main PCB board through a third flexible FPC board;

[0032] and / or,

[0033] The module base is fixed with a fixing support for fixing the main PCB board.

[0034] The present application has the following advantages:

[0035] The present application provides a low-power, small package, high-speed 9.8-106.25Gbps transmission rate optical module adopting PAM4 modulation technology, which can be used for 100G Ethernet and 6th Generation wireless network base station front transmission and medium transmission scheme construction; the present application manages the DSP clock recovery circuit and the 100G laser driver circuit voltage through the first, second and third power management circuits respectively, that is, ensures the stable working voltage of each chip, and does not appear voltage instability working transmission error problem caused by external 3.3V voltage fluctuation, at the same time, also realizes low-power driving, ensures the quality shaping recovery of clock data signal, and the output voltage of the third power management circuit after voltage reduction supplies power to the laser driver, thereby providing sufficient voltage for the laser driver, ensuring that the circuit works under good bias voltage, and maintaining lower power consumption.

[0036] Meanwhile, the present application adopts a low-cost driver bias current driving circuit, which is realized by using one double-channel small package operational amplifier and NPN transistor, and realizes the adjustable IDAC function through the operational amplifier and high-precision resistor, with wide output range, high precision, simple circuit, solving the problems of large IDAC chip package and high power consumption, and saving the whole PCB layout space.

[0037] And the external crystal oscillator voltage dividing circuit adopted by the present application solves the problem of mismatching of different DSPs to the crystal oscillator output level, so that the DSP works in the best input amplitude working state, improves the clock accuracy of the whole circuit, realizes 100G signal transmission, and makes the whole module circuit and optical device meet the SFP112 small package. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 The principle block diagram of the optical module provided by an embodiment of the present application is shown in the figure;

[0039] Figure 2 The principle block diagram of the digital signal processing unit provided by an embodiment of the present application is shown in the figure;

[0040] Figure 3 A circuit diagram of a first power management circuit provided for an embodiment of the present application;

[0041] Figure 4 A circuit diagram of a second power management circuit provided for an embodiment of the present application;

[0042] Figure 5 A circuit diagram of a third power management circuit provided for an embodiment of the present application;

[0043] Figure 6 A circuit diagram of a bias current driving circuit provided for an embodiment of the present application;

[0044] Figure 7 A circuit diagram of a crystal oscillator circuit provided for an embodiment of the present application;

[0045] Figure 8 A structural schematic diagram of an optical module provided for an embodiment of the present application;

[0046] Figure 9 An exploded schematic diagram of an optical module provided for an embodiment of the present application;

[0047] Figure 10 A structural schematic diagram of an optical transmitting assembly provided for an embodiment of the present application;

[0048] Figure 11 A structural schematic diagram of an optical receiving assembly provided for an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0050] In view of the research and development requirements of a low-cost, high-speed, low-power, small package 100G SFP112PAM4 LR optical module for a next-generation 6G front-haul wireless access optical network, it is urgent to solve the problem of insufficient transmission link budget. A low-cost, low-power, high-reliability, small package, long-distance transmission is developed for the first time based on DSP digital signal processing technology, integrated with high-speed, low-loss, enhanced signal integrity PCB design and excellent heat dissipation management technology. The performance meets the requirements of the next-generation 6G front-haul wireless access optical network and the relevant IEEE standards, has batch production capacity, and forms industrialization.

[0051] In order to effectively improve or even completely solve the above problems existing in the related art, the present disclosure provides a corresponding solution, and develops a 24.33-106.25 Gbps transmission rate, low cost, high reliability, and application to 6G front-end industrial temperature work optical module with PAM4 modulation mode, high bandwidth, low power consumption, small package, high speed.

[0052] The main research is to realize the transmission distance of 2-10km PAM signal transmission by adopting SFP112 package based on DSP technology and refrigeration EML (or non-refrigeration) laser for 100G product, supporting-40-85℃ industrial temperature application, and the overall power consumption is less than 3W.

[0053] The application discloses a kind of to be applied to next generation mobile communication 6G front-end 100G SFP112 LR 10km PAM4 (4Pulse Amplitude Modulation: 4 pulse amplitude modulation) modulation hot plug miniaturized package optical module. Figure 1 The principle block diagram of the optical module provided by the embodiment of the present disclosure is shown in Figure Figure 1 As shown in the figure, the optical module includes: power supply circuit, electrical interface circuit (gold finger circuit), digital signal processing unit, main control circuit, optical transmitting assembly, optical receiving assembly, laser driver and bias current driving circuit, the power supply circuit is used to provide power supply for the whole optical module, the optical receiving assembly is connected with the digital signal processing unit, the digital signal processing unit is connected with the electrical interface circuit and the main control circuit, the input end of the laser driver is connected with the digital signal processing unit, the output end of the laser driver is connected with the optical transmitting assembly, the input end of the bias current driving circuit is connected with the main control circuit, and the output end of the bias current driving circuit is connected with the optical transmitting assembly.

[0054] In some embodiments, the optical module further includes analog front-end circuit AFE, temperature control circuit, electric absorption modulation (EA) control circuit. Analog front-end circuit AFE processes analog signals, and temperature control circuit and electric absorption modulation (EA) control circuit are responsible for temperature control (TEC) and electric absorption modulation control (EA) of EML.

[0055] In some embodiments, the power supply circuit includes a first power management circuit, a second power management circuit and a third power management circuit, the input terminals of the first, second and third power management circuits are connected with the output terminal of the soft-start load switch circuit, the input terminal of the soft-start load switch circuit is connected with the electrical interface circuit, the output terminal of the first power management circuit is connected with the first power input terminal of the digital signal processing unit for providing the first voltage to the digital signal processing unit, the output terminal of the second power management circuit is connected with the second power input terminal of the digital signal processing unit for providing the second voltage to the digital signal processing unit, the output terminal of the third power management circuit is connected with the power input terminal of the laser driver for providing the third voltage to the laser driver, and the control terminals of the first, second and third power management circuits are respectively connected with the main control circuit.

[0056] In some embodiments, the first power management circuit includes a first buck chip, the enable terminal of the first buck chip is connected with the main control circuit, the second power management circuit includes a second buck chip, the enable terminal of the second buck chip is connected with the main control circuit, and the third power management circuit includes a third buck chip, the enable terminal of the third buck chip is connected with the main control circuit.

[0057] In some embodiments, the input supply voltage of the electrical interface circuit is 3.3V, the first power management circuit reduces the input voltage 3.3V to 0.8V to supply power to the phase-locked loop (PLL) circuit of the DSP clock data recovery circuit, thereby reducing the overall power consumption of the optical module. The second power management circuit reduces the input voltage 3.3V to 1.8V to supply power to the phase-locked loop (PLL) circuit of the DSP clock data recovery circuit, thereby further reducing the overall power consumption and heat of the module. The third power management circuit reduces the input voltage 3.3V to 3.0V to supply power to the laser driver, thereby reducing the overall power consumption of the module.

[0058] As Figure 3As shown, the first power management circuit includes DC-DC step-down chip U2 and inductor L1, the input end of DC-DC step-down chip U2 is connected with one end of capacitor C3 and first voltage input end (such as 3V3_Tree) respectively, the other end of capacitor C3 is grounded, one end of inductor L1 is connected with SW pin of DC-DC step-down chip U2, the other end is connected with voltage dividing feedback resistor R7 and filter capacitors C4 and C6 respectively and connected to output end VDD_0P8 of the first power management circuit, the other end of C6 is connected with GND, the other end of resistor R7 and the other end of filter capacitor C4 are connected with FB pin of DC-DC step-down chip U2 and connected with one end of resistor R8, the other end of resistor R8 is grounded, to form a first series feedback circuit for adjusting the output voltage of the first power management circuit to 0.8V, the enable EN pin of DC-DC step-down chip U2 is connected with VDD_0P8_EN output pin of the main controller circuit and connected with one end of resistor R6, the other end of resistor R6 is grounded. The output end VDD_0P8 of the first power management circuit is used to supply power to the phase-locked loop PLL circuit of the DSP clock data recovery circuit, and the power supply ripple is required to be <5mV under the condition of bandwidth 100kHz.

[0059] As shown in Figure 4 The second power management circuit includes DC-DC step-down chip U3 and inductor L29, the input end of DC-DC step-down chip U3 is connected with one end of capacitor C7 and first voltage input end (3V3_Tree) respectively, the other end of capacitor C7 is grounded, one end of inductor L29 is connected with SW pin of DC-DC step-down chip U3, the other end is connected with voltage dividing feedback resistor R9 and filter capacitors C95 and C8 respectively and connected to output end VDD_1P8 of the second power management circuit, the other end of capacitor C8 is connected with GND, the other end of resistor R9 and the other end of capacitor C95 are connected with FB pin of DC-DC step-down chip U3 and connected with one end of resistor R10, the other end of resistor R10 is grounded, to form a second series feedback circuit for adjusting the output voltage of the second power management circuit to 1.8V, the enable EN pin of DC-DC step-down chip U3 is connected with VDD_1P8_EN output pin of the main controller circuit and connected with one end of resistor R56, the other end of R56 is grounded. The output end VDD_1P8 of the second power management circuit is used to supply power to the phase-locked loop PLL of the DSP clock data recovery circuit, and the power supply ripple is required to be <15mV under the condition of bandwidth 100kHz.

[0060] As shown in Figure 5As shown, the third power management circuit includes an LDO voltage reduction chip U4, the input end of the LDO voltage reduction chip U4 is connected with one end of a capacitor C9 and a first voltage input end (3V3_Tree) respectively, the other end of the capacitor C9 is grounded, the output end OUT of the LDO voltage reduction chip is connected with a voltage dividing feedback resistor R11 and a filter capacitor C10 and both are connected to the output end VD_3P0 of the third power management circuit, the other end of the capacitor C10 is connected with GND, the other end of the resistor R11 is connected with the FB pin of the LDO voltage reduction chip U4 and is connected with one end of a resistor R12, the other end of the resistor R12 is grounded, a third series feedback circuit is formed, which is used for adjusting the output voltage of the third power management circuit to be 3.0V, and the enable EN pin of the third LDO voltage reduction chip U4 is connected with the VDD_3P0_EN output pin of the main controller circuit. The third power management circuit outputs 3.0V voltage to drive the laser driver, that is, LDDriver, to reduce the heat of the entire optical module and realize lower power consumption. In the case of a bandwidth of 100kHz, the power ripple is required to be <15mV.

[0061] In some embodiments, the main control circuit includes a microcontroller (MCU) which is used for ODSFP microcode control and digital and analog circuit high-frequency signal algorithm compensation writing and control of the operation of the laser integrated drive circuit to realize digital diagnosis and automatic optical power control (APC: Automatic power control) and automatic temperature regulation control of the TEC circuit. The microcontroller (MCU) is also used for controlling the real-time ADC sampling monitoring of the output amplitude and optical power of the 100Gbps high-bandwidth linear receiver probe assembly PINROSA. The microcontroller MCU controls the output amplitude of the probe TIA through the DAC, and the MCU also participates in the initialization register configuration of the entire optical module, controls the power-on timing of the first power management circuit, the second power management circuit and the third power management circuit, and is also responsible for loading the DSP microcode stored in the FLASHS flash memory into the DSP through SPI at a high speed to make it quickly enter normal work, thereby shortening the starting time of the entire module. At the same time, the MCU adjusts the TEC power chip and the bias current modulation current and the laser EA modulation negative voltage control circuit through the sampling of the module temperature and the TOSA internal temperature in real time, so that the entire APC, ATC (automatic temperature control) circuit is in the best working state, and the module optical power and eye diagram extinction ratio work optimally, which ensures the stability of the receiving transmission error rate. At the same time, the DSP chip, the laser drive chip and the TOSA, ROSA report current and optical power and various state LOS / LOL and SNR information are read in real time and reported to the corresponding CMIS protocol bit, and the host also issues commands for real-time processing feedback, so that the system is in a high-efficiency normal transmission state.

[0062] In some embodiments, referring to Figure 6The bias current driving circuit comprises an operational amplifier U16 and a transistor U17, the non-inverting input terminal of the operational amplifier U16 is connected with the output terminal of the DAC input circuit, the input terminal of the DAC input circuit is connected with the DAC output terminal of the main control circuit, the inverting input terminal of the operational amplifier U16 is grounded through a resistor R69, the inverting input terminal of the operational amplifier U16 is connected with the output terminal of the operational amplifier U16 through a capacitor C108, the output terminal of the operational amplifier U16 is connected with the control electrode (such as the base) of the transistor U17 through a resistor R72, the first electrode (such as the collector) of the transistor U17 is connected with the power supply, the second electrode (such as the emitter) of the transistor U17 is connected with the inverting input terminal of the operational amplifier U16 through a resistor R71, the second electrode (such as the emitter) of the transistor U17 is connected with the output terminal of the bias current driving circuit, and the output terminal of the bias current driving circuit is connected with the laser driver for providing the D_Bias bias current for the laser driver.

[0063] In some embodiments, a resistor R67 is connected in series between the second electrode of the transistor U17 and the output terminal of the bias current driving circuit, and the output terminal of the bias current driving circuit is connected with the non-inverting input terminal of the operational amplifier U16 through a resistor R70.

[0064] In some embodiments, the optical module of the present application further comprises a signal conditioning circuit, two input terminals of the signal conditioning circuit are connected with two ends of the resistor R67 respectively, and the output terminal of the signal conditioning circuit is connected with the main control circuit. The signal conditioning circuit and the resistor R67 constitute a current sampling circuit, the current sampling circuit is used for collecting the current flowing through the resistor R67, obtaining the bias current output from the bias current driving circuit to the laser driver, and transmitting the bias current to the main control circuit.

[0065] The D_Bias bias current is directly provided for the LDDriver through the resistor R67 in series with the transistor emitter, so that the Driver works at the optimal working point.

[0066] The entire bias current driving circuit is realized by using one double-channel operational amplifier and an NPN transistor, the adjustable IDAC function is realized by using the operational amplifier and high-precision resistors, the load capacity is 0-320mA, which is much larger than the bias pressure range of the LDDriver, and high-precision adjustment is realized, the output current calculation formula is I= (VLD_Bias+-VLD_Bias-) / R67=R71 / R68 / R67*VDAC_D_Bias. VDAC_D_Bias is programmable and adjustable output through the DAC port of the main control circuit, and the range is 0-2.5V. Compared with the IDAC multi-channel chip, the entire circuit is simple and has lower cost, small size, and the PCB layout space is reduced by 30%, the layout space is more precious for a single-channel 100GSFP112 module, so that the SFP112 small-size packaged transmission 100G signal can be realized.

[0067] In some embodiments, the supply voltage +VS pin of the operational amplifier U16 is connected to the LD supply voltage (e.g., VLD_3P3V) and to one end of a filter capacitor C60, and the other end of the filter capacitor C60 is connected to ground.

[0068] The collector of the transistor is connected to the LD supply voltage (e.g., VLD_3P3V) to provide the working voltage for the transistor to be turned on. The collector of the transistor is connected to one end of a filter capacitor C62, and the other end of the filter capacitor C62 is connected to ground.

[0069] In some embodiments, the DAC input circuit includes a voltage dividing network including resistors R68 and R66, one end of the resistor R68 and one end of the resistor R66 are connected to the DAC output terminal of the main control circuit, the other end of the resistor R68 is connected to the non-inverting input terminal of the operational amplifier, and the other end of the resistor R66 is connected to ground.

[0070] In some embodiments, the DAC input circuit further includes a capacitor C107, one end of the capacitor C107 is connected to the non-inverting input terminal of the operational amplifier, and the other end of the capacitor C107 is connected to ground. The capacitor C107 is a filter capacitor.

[0071] In some embodiments, the bias current driving circuit further includes a capacitor C109, one end of the capacitor C109 is connected to the output terminal of the bias current driving circuit, and the other end of the capacitor C109 is connected to ground.

[0072] In some embodiments, the optical module of the present application further includes a crystal oscillator circuit and a FLASH memory circuit, which respectively provide a high-precision reference clock for a digital signal processing unit (DSP) and a large FLASH memory (for fast storage of high-order software algorithms of the DSP to ensure stable and high-speed operation of the entire optical module). As a preferred solution, the packaging of the crystal oscillator and the FLASH chip is currently the smallest available packaging, which is 1.75*2.15mm and 1.28*1.52mm respectively, so as to be placed inside the SFP structure packaging, and the crystal oscillator rate is 156.25MHz, and the FLASH is 4Mbit to meet the high-order algorithm of the DSP.

[0073] In some embodiments, referring to Figure 7The crystal oscillator circuit comprises an active crystal oscillator module and a crystal oscillator voltage dividing circuit, the crystal oscillator voltage dividing circuit comprises a first voltage dividing resistor R73 and a second voltage dividing resistor R74, one end of the first voltage dividing resistor R73 is connected with a first output end of the active crystal oscillator module, the other end of the first voltage dividing resistor R73 is grounded, one end of the second voltage dividing resistor R74 is connected with a second output end of the active crystal oscillator module, the other end of the second voltage dividing resistor R74 is grounded, a first attenuation resistor R71 and a first AC coupling capacitor C32 are connected in series between the first output end of the active crystal oscillator module and a first reference clock pin of the digital signal processing unit, and a second attenuation resistor R72 and a second AC coupling capacitor C33 are connected in series between the second output end of the active crystal oscillator module and a second reference clock pin of the digital signal processing unit. The first voltage dividing resistor and the second voltage dividing resistor of the crystal oscillator voltage dividing circuit are connected in parallel to the ground, the crystal oscillator output level is adjusted through impedance voltage division, and the input amplitude of the DSP is matched. The active crystal oscillator output impedance is low (usually < 50Ω), and the PCB wiring and the DSP input capacitor can introduce parasitic inductance / capacitance, which is easy to cause signal reflection. The first attenuation resistor and the second attenuation resistor of the application simultaneously assume the dual roles of "impedance matching" and "filtering resistor", which not only suppresses reflection through impedance matching with the transmission line to reduce the overshoot and ringing of the clock edge, indirectly improves the clock precision, but also cooperates with the first AC coupling capacitor and the second AC coupling capacitor to form RC filtering, realizes filtering, and finally makes the input clock signal of the DSP more stable and the edge more smooth.

[0074] The application solves the problem of different DSPs not matching the crystal oscillator output level by adopting the external crystal oscillator voltage dividing circuit, so that the DSP works in the best input amplitude working state, improves the clock precision of the whole circuit, realizes 100G signal transmission, and makes the whole module, the circuit and the optical device meet the SFP112 extremely small package.

[0075] Specifically, the active crystal chip frequency of the crystal oscillator circuit is 156.25MHz, a small chip is selected, the 6-pin thereof is connected with a power supply VCC OSC 3.3V, an external power supply provides a working voltage for normal working of the active crystal, a bypass filter capacitor C31 is connected with the power supply VCC OSC, the other end of the C31 is connected with a power supply ground, the 1-pin of the active crystal is connected with an MCU for enabling normal working and is pulled down to the power supply ground through a R7510K resistor, the 3-pin of the active crystal is also connected with the power supply ground for working loop. The 4-pin and 5-pin of the active crystal output are connected with each other in series through R71 and R72 and are connected with each other at one end of the differential AC coupling capacitors C32 and C33. The C32 and C33 are connected with the reference clock pins REFCLKP and REFCLKN of the DSP chip to provide a differential reference clock for the DSP as a precise frequency reference and to provide the circuits of the DSP PLL for normal clock and data processing. In order to make the active crystal output level in the optimal range of the DSP working, the series resistors R71 and R72 are reserved to attenuate the LVPECL level of the active crystal output, and one end of the R71 and R72 is also connected with the matching network pull-down resistors R74 and R73 respectively. The active crystal output differential clock is used as a reference for the internal clock frequency synthesizer of the DSP. The differential 100Ω terminal load bias (single-ended 50Ω) is used in the DSP. By adjusting the resistance values of the attenuation resistors R71 and R72, the LVPECL level of the whole circuit output can be in the range of 0.8-1.6V required by the DSP. The circuit compatibility is better, and it is suitable for the optimal working amplitude required by different DSP reference clocks.

[0076] In some embodiments, referring to Figure 2 , the receiving link of the digital signal processing unit comprises a receiving automatic gain control (VGA) module, a receiving ADC module, a receiving clock data recovery circuit (CDR), a receiving FFE / DFE equalization module, a receiving FIR filtering module, a receiving DAC module, and a receiving limiting amplification circuit. The receiving automatic gain control module comprises a variable gain amplifier (VGA) for gain adjustment of the electrical signal output by the optical receiving component. The VGA fine adjustment input swing is adapted to the dynamic range of the ADC to achieve the optimal signal-to-noise ratio. The receiving ADC module is used for ADC conversion of the electrical signal output by the optical receiving component. The receiving clock recovery (CDR) circuit comprises a PLL phase-locked loop circuit for clock data recovery of the electrical signal output by the optical receiving component. The receiving FFE / DFE equalization module is used for reflection cancellation and compensation of multipath interference and provides a level-dependent equalizer for the electrical signal output by the optical receiving component. The receiving limiting amplification circuit is used for signal amplitude amplification of the electrical signal received by the optical receiving component to a set value output to the golden finger circuit.

[0077] The transmit link of the digital signal processing unit comprises a transmit CTLE equalization module, a transmit automatic gain control module, a transmit clock data recovery circuit, a transmit FFE / DFE equalization module, a transmit FIR filter module, and a transmit DAC module. The DAC module is configured to perform DAC conversion on the electrical signal output by the electrical interface circuit. The transmit CTLE equalization module compensates for the distortion of the signal by adjusting the frequency response of the signal, so that the signal reaches a more ideal signal quality before entering the analog-to-digital converter (ADC). The transmit automatic gain control module is configured to perform gain adjustment on the electrical signal. The transmit ADC module is configured to perform ADC conversion on the electrical signal output by the electrical interface circuit. The transmit clock recovery circuit is configured to perform clock data recovery shaping on the electrical signal. The transmit FFE / DFE equalization module is configured to perform reflection cancellation and compensate for multipath interference on the electrical signal output by the electrical interface circuit and provide a level-dependent equalizer. The transmit DAC module is configured to perform DAC conversion on the electrical signal output by the electrical interface circuit and output to the laser driver. The PLL phase-locked loop circuit is included in the transmit and receive clock recovery circuit (CDR). The FFE is a linear equalization technology based on the frequency domain or time domain, which compensates for the distortion of the channel by adjusting the frequency response (or time response) of the signal. The DFE is a nonlinear equalization technology that combines the current input signal and the previous output signal (through a feedback mechanism) to eliminate intersymbol interference.

[0078] In some embodiments, the digital signal processing unit further comprises a transmit automatic gain control module configured to perform gain adjustment on the electrical signal output by the electrical interface circuit.

[0079] In some embodiments, the digital signal processing unit further comprises a transmit FIR filter module located between the transmit FFE / DFE equalization module and the transmit DAC module. In some embodiments, the transmit FIR filter module can implement a static nonlinear transfer function to enhance the signal and calibrate nonlinear effects.

[0080] In some embodiments, the digital signal processing unit further comprises a receive FIR filter module located between the receive FFE / DFE equalization module and the receive DAC module. In some embodiments, the receive FIR filter module can implement a static nonlinear transfer function to enhance the signal and calibrate nonlinear effects.

[0081] In some embodiments, the digital signal processing unit further comprises a transmit high-speed serializer configured to convert the parallel digital signal into a high-speed serial signal.

[0082] In some embodiments, the digital signal processing unit further comprises a receiving high-speed serializer for converting the high-speed serial signal into a parallel digital signal.

[0083] The digital signal processing unit comprises a linear equalizer (CTLE) and a transmitting and receiving clock recovery (CDR) unit circuit, a high-speed ADC and DAC sampling circuit, a transmitting feed-forward equalization (FFE) and decision feedback equalization (DFE), a VGA gain control circuit, a power management automatic adjustment circuit, a micro processing unit interface circuit, an IIC and SPI control circuit, a temperature and LOS, LOL, SNR, CID, reflection compensation detection, eye scan state detection circuit, and a limiting amplification unit circuit and a forward error correction circuit (FEC), a self-generating code and decoding PRBS, a BER detection circuit, etc., and the CTLE adaptive equalization has a 15dB compensation capability for compensating the loss between Serdes and the gold finger and DSP. The transmitting FIR has a 7tapFIR function for compensating the high-speed signal loss between the DSP and the laser driver, and the laser driver also has a 10dB adjustable gain for compensating the link loss or attenuation between the laser driver and the laser. The digital signal processing unit output signal is amplified by the laser driver, drives the 100G micro BOX EML laser TOSA to emit light, and the laser driver and the 100G EML TOSA are connected through a flexible FPC, so that the 100G laser outputs a modulated optical signal, and the optical signal rate of the laser is 9.8-106.25Gbps.

[0084] In some embodiments, the digital signal processing unit adopts a DSP chip. The DSP chip is externally connected with an active crystal reference clock circuit and an external large memory FLASH flash circuit.

[0085] In some embodiments, referring to Figure 8 and Figure 9 The optical module of the present application comprises a module base 11 and a module cover 12, at least one of the electrical interface circuit, the digital signal processing unit, the main control circuit, the laser driver and the bias current driving circuit is arranged on the main PCB 16, the optical transmitting assembly 18 and the optical receiving assembly 17 are installed between the module base 11 and the module cover 12, the optical port pressing block 13 for fixing the optical transmitting assembly 18 and the optical receiving assembly 17 is detachably fixed on the module base 11, the optical transmitting assembly 18 is electrically connected with the main PCB 16 through the first flexible FPC 19, and the optical receiving assembly 17 is electrically connected with the main PCB 16 through the second flexible FPC 20. The optical port pressing block 13 is inverted inside the module base 11 and the module cover 12, and the optical port pressing block 13 is movable and detachable, so that the optical port is freely adapted to release the plugging stress. An EMI tape is attached in the optical module to improve the EMI performance.

[0086] In some embodiments, the optical module of the present application further comprises a secondary PCB board 15, part of the electrical interface circuit, digital signal processing unit, main control circuit, and laser driver and bias current driving circuit are arranged on the secondary PCB board, and the other part is arranged on the main PCB board, and the secondary PCB board 15 is connected with the main PCB board 16 through a third flexible FPC board. Since it is an SFP small package, part of the circuit of the present application is placed on the main PCB board, and the other part of the circuit is placed on the secondary PCB board 15. In some embodiments, the secondary PCB board is provided with a main control circuit (microprocessor controller MCU) and a TEC power supply control chip, and a three-stage DC-DC power supply control circuit.

[0087] In some embodiments, a fixing support 14 for fixing the main PCB board is fixed on the module base.

[0088] The fixing support 14 is pressed in the clamping hole of the main PCB board 16 and the module base 11, and the fixing PCB is started to prevent shaking and increase firmness.

[0089] In some embodiments, the optical transmitting assembly comprises an EML laser, an adapter and a tube base, the adapter is connected with the tube base through an adjusting ring, the EML laser is arranged in the tube base, and the tube base is further provided with a lens.

[0090] Specifically, the optical transmitting assembly is a micro high-bandwidth 100G laser transmitting assembly BOX EML TOSA, as shown in Figure 10 The internal structure comprises a micro LC pin assembly adapter 181, an embedded small aperture isolator 182, an adjusting ring 183, a micro lens 184, an EML laser COC 185, a TEC 186, a thermistor 187, a micro BOX tube base 188, and a backlight monitoring diode MPD 189. The 186 is adhered in the cavity of the BOX tube base 188 through conductive silver adhesive, the 185 and 187 are attached above the 186, and the 189 is attached on the right side of the 185 to monitor the backlight of the EML laser and sample the MCU for real-time optical power monitoring. The 186 is connected to the PCB power chip through the TXFPC 19 to control the laser temperature stability, so that the laser and the DSP transmitting link can normally work in the speed range of 9.8-106.25 Gbps.

[0091] Specifically, the optical receiving assembly is a micro high-bandwidth 100G detector receiving assembly ROSA, as shown in Figure 11As shown, its interior contains PDTO 171, welding tube 172, adjusting ring 173, micro pin assembly 174, wherein PDTO 171 also contains TO cap and high-speed transimpedance amplifier TIA and high-speed backlight PD diode, which are all mounted inside the TO base, and the PD and TIA are directly connected by gold wire, the length of the gold wire and the placement of the PD directly affect the ROSA response and high-frequency transmission characteristics. And the ROSA PDTO also contains several wire capacitors to filter the power supply noise interference, ensuring excellent transmission performance. The PD is 0±30um relative to the center of the base, and the cap is 0±50um relative to the center of the base; bonding uses 25um gold wire, ball bonding process; the ① signal input line and the ② signal output line do not exceed the size of the mark in the figure, and the shorter the better; all ground wires cannot exceed 0.16mm, the shorter the better, to ensure that the probe and the DSP receive link work normally within the 9.8-106.25Gbps rate range.

[0092] In some embodiments, the 100G optical probe receives an optical signal, which is amplified by TIA and then output as an electrical signal to the DSP through RX FPC. After ADC conversion and RX automatic CTLE equalization and AGC automatic gain adjustment, the electrical signal is output to the DSP receive clock recovery circuit CDR for clock recovery and data shaping. After signal amplification and 3TAP FFE equalization by the receive limiting amplifier circuit (with equalization capability reaching 7dB), the 9.8-106.25Gbps electrical signal is output to the Serdes.

[0093] The laser driver and the optical transmitting component are electrically connected in a single-ended AC coupling driving mode, and the laser driver is arranged outside the optical transmitting component, which enhances heat dissipation and reduces the power consumption of the laser, thereby ensuring the excellent thermal performance of the optical chip. The optical receiving component and the digital signal processing unit are electrically connected through a high-speed differential AC coupling capacitor. In order to obtain sufficient good optical signal output quality, the optical receiving component and the digital signal processing unit are electrically connected through a second flexible FPC board, so that the signal can obtain good signal integrity during transmission. In order to ensure the continuous characteristic impedance on the transmission line, the impedance of each point on the transmission line needs to be continuous, and the number of separate components on the transmission line needs to be reduced. In the embodiment, the laser driver and the optical transmitting component realize signal driving in a very simple end AC coupling mode. By using this mode, the number of separate components on the transmission line is reduced, the high-frequency signal loss and external interference are reduced, the continuous characteristic impedance on the transmission line is ensured, and the laser driver and the optical transmitting component are electrically connected through a first flexible FPC board. Under the condition that each component meets the signal integrity, high-speed 9.8-106.25Gbps signal transmission is realized.

[0094] The application provides a low-power-consumption, small-package, high-speed 9.8-106.25 Gbps transmission rate optical module adopting a PAM4 modulation technology, which can be used in the construction of 100G Ethernet and 6th Generation wireless network base station front transmission and middle transmission schemes; the application manages the voltages of a DSP clock recovery circuit and a 100G laser driver circuit by adopting first, second and third power management circuits, that is, ensures the stable working voltages of the chips, avoids the voltage instability and working transmission error caused by the external 3.3V voltage fluctuation, and also realizes low-power-consumption driving, guarantees the clock data signal quality shaping recovery, and the output voltage of the third power management circuit after voltage reduction supplies power to the laser driver, so as to provide sufficient voltage for the laser driver, ensure that the circuit works under a good bias voltage, and maintain lower power consumption.

[0095] Meanwhile, the bias current driving circuit of the application includes a low-cost Driver bias current driving circuit, which is realized by using one double-channel small package operational amplifier and NPN triode, realizes the adjustable IDAC function by the operational amplifier and high-precision resistance, has wide output range and high precision, and is simple, solves the problems of large IDAC chip package and high power consumption, and saves the whole PCB layout space.

[0096] And the external crystal oscillator voltage division circuit adopted by the application solves the problem of different DSPs not matching the crystal oscillator output level, makes the DSP work in the best input amplitude working state, improves the clock precision of the whole circuit, realizes 100G signal transmission, and makes the whole module circuit and optical device meet the SFP112 small package.

[0097] In summary, the circuit of the application adopts small package chips and 100G micro-BOX EMLTOSA and 100G ROSA, the whole PCB layout area is reduced by 30%, the module overall power consumption is reduced by 20%, the industrial temperature and high-speed link transmission quality are ensured, the 6G optical transmission high-speed optical module is realized, and the chip, device and module developed based on the project are used to build a comprehensive test analysis platform, complete the next-generation typical 6G front transmission optical module localization layout, and reach the international leading level.

[0098] The above-described embodiments only express several implementation manners of the present application, which are described in a more specific and detailed manner, but cannot be understood as a limitation on the patent scope of the present application. The application is applied to a 6G next-generation front-haul and Ethernet 100GSFP112LRPAM4 optical module. It should be noted that the optical module structure design, 100G laser and 100G detector packaging, and various control circuit diagrams described above all belong to the protection scope of the present application. The airtight packaging principle of the optical module laser and detector, the power management control algorithm and control circuit principle, electromagnetic compatibility simulation, signal integrity simulation technology, advanced thermal fluid analysis, magnetic heat coupling, and thermal stress management technology are protected by the present patent. For ordinary personnel in the field, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims

1. An optical module characterized by comprising: The power supply circuit, the electrical interface circuit, the digital signal processing unit, the main control circuit, the optical transmitting component, the optical receiving component, the laser driver and the bias current driving circuit, the power supply circuit is used for providing power supply for the whole optical module, the optical receiving component is connected with the digital signal processing unit, the digital signal processing unit is connected with the electrical interface circuit and the main control circuit, the input end of the laser driver is connected with the digital signal processing unit, the output end of the laser driver is connected with the optical transmitting component, the input end of the bias current driving circuit is connected with the main control circuit, and the output end of the bias current driving circuit is connected with the laser driver.

2. The optical module according to claim 1, characterized by: The power supply circuit includes a first power management circuit, a second power management circuit and a third power management circuit, the input ends of the first power management circuit, the second power management circuit and the third power management circuit are connected with the output end of the soft-start load switch circuit, the input end of the soft-start load switch circuit is connected with the electrical interface circuit, the output end of the first power management circuit is connected with the first power input end of the digital signal processing unit, used for providing the first voltage for the digital signal processing unit, the output end of the second power management circuit is connected with the second power input end of the digital signal processing unit, used for providing the second voltage for the digital signal processing unit, the output end of the third power management circuit is connected with the power input end of the laser driver, used for providing the third voltage for the laser driver, and the control ends of the first power management circuit, the second power management circuit and the third power management circuit are connected with the main control circuit respectively.

3. The optical module of claim 2, wherein: The first power management circuit includes a first buck chip, the enable end of the first buck chip is connected with the main control circuit, the second power management circuit includes a second buck chip, the enable end of the second buck chip is connected with the main control circuit, and the third power management circuit includes a third buck chip, the enable end of the third buck chip is connected with the main control circuit.

4. The optical module of claim 1, wherein: The bias current driving circuit includes an operational amplifier and a transistor, the non-inverting input end of the operational amplifier is connected with the output end of the DAC input circuit, the input end of the DAC input circuit is connected with the DAC output end of the main control circuit, the inverting input end of the operational amplifier is connected with the output end of the operational amplifier through a first resistor, the inverting input end of the operational amplifier is connected with the output end of the operational amplifier through a first capacitor, the output end of the operational amplifier is connected with the control electrode of the transistor, the first electrode of the transistor is connected with the power supply, the second electrode of the transistor is connected with the inverting input end of the operational amplifier through a third resistor, the second electrode of the transistor is connected with the output end of the bias current driving circuit, the output end of the bias current driving circuit is connected with the laser driver, used for providing the D_Bias bias current for the laser driver.

5. The optical module of claim 4, wherein: The second electrode of the transistor is connected with the output end of the bias current driving circuit through a second resistor, and the output end of the bias current driving circuit is connected with the non-inverting input end of the operational amplifier through a fourth resistor. The signal conditioning circuit is further included, two input ends of the signal conditioning circuit are connected with two ends of the second resistor respectively, and the output end of the signal conditioning circuit is connected with the main control circuit. And / or, The DAC input circuit comprises a voltage division network, the voltage division network comprises a fifth resistor and a sixth resistor, one end of the fifth resistor and one end of the sixth resistor are connected with a DAC output end of the main control circuit, the other end of the fifth resistor is connected with a non-inverting input end of the operational amplifier, and the other end of the sixth resistor is grounded; and / or, The DAC input circuit further comprises a second capacitor, one end of the second capacitor is connected with the non-inverting input end of the operational amplifier, and the other end of the second capacitor is grounded; and / or, The bias current driving circuit further comprises a third capacitor, one end of the third capacitor is connected with the power supply, and the other end of the third capacitor is grounded; and / or, The bias current driving circuit further comprises a fourth capacitor, one end of the fourth capacitor is connected with an output end of the bias current driving circuit, and the other end of the fourth capacitor is grounded.

6. The optical module of claim 1, wherein: Further comprising a crystal oscillator circuit for providing a reference clock for the digital signal processing unit, the crystal oscillator circuit comprises an active crystal oscillator module and a crystal oscillator voltage division circuit, the crystal oscillator voltage division circuit comprises a first voltage division resistor and a second voltage division resistor, one end of the first voltage division resistor is connected with a first output end of the active crystal oscillator module, the other end of the first voltage division resistor is grounded, one end of the second voltage division resistor is connected with a second output end of the active crystal oscillator module, the other end of the second voltage division resistor is grounded, a first attenuation resistor and a first AC coupling capacitor are connected in series between the first output end of the active crystal oscillator module and a first reference clock pin of the digital signal processing unit, and a second attenuation resistor and a second AC coupling capacitor are connected in series between the second output end of the active crystal oscillator module and a second reference clock pin of the digital signal processing unit.

7. The optical module of claim 1, wherein: The digital signal processing unit comprises a receive automatic gain control module, a receive ADC module, a receive clock data recovery circuit, a receive FFE / DFE equalization module, a receive DAC module, and a receive limiting amplification circuit, the receive automatic gain control module is used for gain adjustment of an electrical signal output by an optical receiving component, the receive ADC module is used for ADC conversion of the electrical signal output by the optical receiving component, the receive clock data recovery circuit is used for clock data recovery of the electrical signal output by the optical receiving component, the receive FFE / DFE equalization module is used for reflection cancellation and compensation of multipath interference of the electrical signal output by the optical receiving component and provides a level-dependent equalizer, the receive DAC module is used for DAC conversion of the electrical signal output by the optical receiving component, and the receive limiting amplification circuit is used for signal amplitude amplification of the electrical signal output by the optical receiving component to a set value and outputs to an electrical interface circuit. The digital signal processing unit comprises a transmitting CTLE equalization module, a transmitting ADC module, a transmitting clock data recovery circuit, a transmitting FFE / DFE equalization module and a transmitting DAC module.

8. The optical module of claim 1, wherein: The laser driver and the optical transmitting assembly are electrically connected in a single-ended AC coupling driving mode. And / or, The optical receiving assembly and the digital signal processing unit are electrically connected through a high-speed differential AC coupling capacitor.

9. The optical module of claim 1, wherein: At least one of the electrical interface circuit, the digital signal processing unit, the main control circuit, the laser driver and the bias current driving circuit is arranged on the main PCB board.

10. The optical module of claim 9, wherein: A sub-PCB board is further included, and part of the electrical interface circuit, the digital signal processing unit, the main control circuit, the laser driver and the bias current driving circuit is arranged on the sub-PCB board, and the other part is arranged on the main PCB board. The sub-PCB board and the main PCB board are connected through a third flexible FPC board. And / or, The module base is fixed with a fixing support for fixing the main PCB board.

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