Semiconductor device and preparation method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof, and a memory system. The semiconductor device comprises a connecting layer, a laminated structure and a first contact structure. The laminated structure is located on one side of the connecting layer in the first direction. The first contact structure comprises a first medium filling part and a first conducting layer surrounding the first medium filling part, and the first medium filling part and the first conducting layer extend in the laminated structure in the first direction and are in contact with the connecting layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a semiconductor device, a method for manufacturing a semiconductor device, and a memory system. BACKGROUND

[0002] With the rise and development of the fields of artificial intelligence, big data, Internet of Things, mobile communication, mobile devices, and cloud storage, the demand for semiconductor devices such as three-dimensional memory is also increasing. However, as the number of stacked layers in semiconductor devices such as three-dimensional memory increases and the storage density per unit area improves, the process steps in the manufacturing of semiconductor devices become complex and lengthy, and the manufacturing cost of semiconductor devices gradually increases.

[0003] Therefore, how to simplify the manufacturing process of semiconductor devices, reduce the manufacturing cost of semiconductor devices, and improve the reliability and overall performance of semiconductor devices is a problem to be solved at present. SUMMARY

[0004] Embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and a memory system, which can at least partially solve the above technical problems or other problems.

[0005] In one aspect, the present application provides a semiconductor device, comprising: a connection layer; a stack structure located on one side of the connection layer along a first direction; and a first contact structure comprising a first dielectric filling portion and a first conductive layer surrounding the first dielectric filling portion, wherein the first dielectric filling portion and the first conductive layer both extend in the stack structure along the first direction and are in contact with the connection layer.

[0006] In one embodiment of the present application, the first conductive layer comprises at least one of a metal material layer and a metal compound material layer; and the first dielectric filling portion comprises an insulating material layer.

[0007] In one embodiment of the present application, the metal compound material layer contains at least one of titanium, tantalum, chromium, tungsten, nitrogen, and silicon.

[0008] In one embodiment of the present application, the size of the first dielectric filling portion along the first direction is equal to the size of the first conductive layer along the first direction.

[0009] In one embodiment of the present application, the semiconductor device further comprises: a second conductive layer located between the first conductive layer and the first dielectric filling portion, wherein the first conductive layer comprises at least one of a metal material layer and a metal compound material layer; and the second conductive layer comprises at least one of a metal material layer and a semiconductor material layer.

[0010] In one embodiment of the present application, the first conductive layer has a dimension along the first direction that is greater than a dimension of the second conductive layer along the first direction; and the first conductive layer extends along the first direction and includes an end portion in contact with the connection layer, wherein the end portion extends along a direction that is transverse to the first direction.

[0011] In one embodiment of the present application, the first conductive layer has a dimension along the first direction that is equal to a dimension of the second conductive layer along the first direction; and the first conductive layer and the second conductive layer both extend along the first direction and are in contact with the connection layer.

[0012] In one embodiment of the present application, the semiconductor device further includes: a channel structure extending along the first direction in the stack structure and including a channel layer and a functional layer surrounding the channel layer, wherein the connection layer extends along a direction that is transverse to the first direction and is connected to the channel layer of the plurality of channel structures.

[0013] In one embodiment of the present application, a cross-sectional shape of the first conductive layer in a plane transverse to the first direction includes a ring shape.

[0014] In one embodiment of the present application, the semiconductor device further includes: a second contact structure including a second dielectric filling portion and a third conductive layer surrounding the second dielectric filling portion, wherein the third conductive layer extends along the first direction and is in contact with the gate layer of the stack structure.

[0015] In one embodiment of the present application, the third conductive layer includes a first portion and a second portion connected to each other, wherein the first portion extends along the first direction and surrounds the second dielectric filling portion; and the second portion extends along a direction that is transverse to the first direction and is in contact with the gate layer.

[0016] In one embodiment of the present application, the first portion and the second dielectric filling portion both extend from a first side of the stack structure to a second side of the stack structure, the first side and the second side being oppositely arranged along the first direction, wherein a dimension of the first portion along the first direction is less than a dimension of the second dielectric filling portion along the first direction.

[0017] In one embodiment of the present application, a cross-sectional shape of the second portion in a plane transverse to the first direction includes a ring shape.

[0018] In one embodiment of the present application, the second portion is co-layered with the gate layer along the first direction.

[0019] In one embodiment of the present application, a dimension of the second portion along the first direction is greater than or equal to a dimension of the gate layer along the first direction.

[0020] In one embodiment of the present application, the semiconductor device further includes a first dielectric layer disposed in the same layer as the gate layer along a first direction, wherein the second contact structure extends along the first direction, passes through the first dielectric layer, and is connected with the gate layer.

[0021] In one embodiment of the present application, the plurality of second contact structures have different sizes in a direction intersecting the first direction and are adjacent in the direction intersecting the first direction.

[0022] In one embodiment of the present application, the third conductive layer includes at least one of a metal material layer and a metal compound material layer; and the second dielectric filling portion includes an insulating material layer.

[0023] In one embodiment of the present application, the second contact structure further includes a fourth conductive layer between the third conductive layer and the second dielectric filling portion, wherein the fourth conductive layer includes a third portion and a fourth portion connected with each other; the third portion extends along the first direction and surrounds the second dielectric filling portion; and the fourth portion extends along a direction intersecting the first direction and contacts the gate layer.

[0024] In one embodiment of the present application, the second contact structure further includes a fourth conductive layer between the portion of the third conductive layer extending along the first direction and the second dielectric filling portion.

[0025] In one embodiment of the present application, the third conductive layer includes at least one of a metal material layer and a metal compound material layer; and the fourth conductive layer includes at least one of a metal material layer and a semiconductor material layer.

[0026] In yet another aspect of the present application, a method for manufacturing a semiconductor device is provided, the method including: forming a stack structure on one side of a substrate along a first direction; forming a first contact structure extending along the first direction in the stack structure; and removing the substrate and forming a connection layer, wherein the first contact structure includes a first dielectric filling portion and a first conductive layer surrounding the first dielectric filling portion; and the first dielectric filling portion and the first conductive layer both extend along the first direction and contact the connection layer.

[0027] In one embodiment of the present application, forming the first contact structure extending along the first direction in the stack structure includes: forming a first contact hole in the stack structure, wherein the first contact hole extends along the first direction and includes a first end portion extending into the substrate; forming an initial first conductive layer in the first contact hole; removing part of the initial first conductive layer to form the first conductive layer and expose part of the first end portion; and forming the first dielectric filling portion in the remaining space of the first contact hole.

[0028] In one embodiment of the present application, forming the first contact structure extending in the first direction in the stack structure further includes: forming an initial second conductive layer on a surface of the initial first conductive layer; and removing part of the initial second conductive layer in the process of removing part of the initial first conductive layer, to form the second conductive layer.

[0029] In one embodiment of the present application, the method further includes forming the second contact structure, wherein the second contact structure includes a second dielectric filling portion and a third conductive layer surrounding the second dielectric filling portion, the third conductive layer extending in the first direction and contacting the gate layer of the stack structure.

[0030] In one embodiment of the present application, forming the second contact structure includes: forming a second contact hole in the stack structure, wherein the second contact hole extends in the first direction and includes a second end portion connected to the gate layer; forming an initial third conductive layer in the second contact hole; removing part of the initial third conductive layer to form the third conductive layer and expose part of the second end portion; and forming the second dielectric filling portion in the remaining space of the second contact hole.

[0031] In one embodiment of the present application, the method further includes: forming the first contact structure and the second contact structure in the same process.

[0032] In still another aspect of the present application, a memory system is provided, including: a controller; and the semiconductor device provided in any one of the aspects of the present application, the controller being coupled to the semiconductor device and configured to control the semiconductor device to store data. BRIEF DESCRIPTION OF DRAWINGS

[0033] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a cross-sectional schematic view of a semiconductor device according to one embodiment of the present application;

[0035] Figure 2 is Figure 1 is an enlarged schematic view of a semiconductor device A shown;

[0036] Figure 3 is a cross-sectional schematic view of a semiconductor device according to another embodiment of the present application;

[0037] Figure 4 is Figure 3 is an enlarged schematic view of a semiconductor device B shown;

[0038] Figure 5 is a cross-sectional schematic view of a semiconductor device according to one embodiment of the present application;

[0039] Figure 6 is a cross-sectional view of a semiconductor device according to another embodiment of the present application;

[0040] Figure 7 is a cross-sectional view of a semiconductor device according to an embodiment;

[0041] Figure 8 is Figure 1 is an enlarged view of the semiconductor device C shown in FIG. 1 according to an embodiment of the present application;

[0042] Figure 9 is a cross-sectional view of a second contact structure according to an embodiment of the present application;

[0043] Figure 10 is a bottom view of a second contact structure according to an embodiment of the present application;

[0044] Figure 11 is Figure 1 is an enlarged view of the semiconductor device C shown in FIG. 1 according to another embodiment of the present application;

[0045] Figure 12 is a cross-sectional view of a second contact structure according to another embodiment of the present application;

[0046] Figure 13 is a bottom view of a second contact structure according to another embodiment of the present application;

[0047] Figure 14 is a top view of a semiconductor device according to an embodiment of the present application;

[0048] Figures 15-20 are process diagrams of a method of manufacturing a semiconductor device according to an embodiment, respectively;

[0049] Figure 21 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present application;

[0050] Figures 22-26 are process diagrams of a method of manufacturing a semiconductor device according to an embodiment of the present application, respectively; and

[0051] Figure 27 is a structure diagram of a memory system according to an embodiment of the present application.

[0052] DETAILED DESCRIPTION

[0053] The present application will be described in detail by explaining exemplary embodiments of the application with reference to the attached drawings. The exemplary embodiments of the present application described herein are merely exemplary and are not intended to limit the scope of the present application. Throughout the specification, like drawing reference numerals will be understood to refer to the same element.

[0054] In the drawings, the thicknesses of components, sizes, and shapes can be exaggerated slightly for ease of explanation. The drawings are merely schematic and are not intended to be drawn to scale. As used herein, the terms "substantially," "approximately," and similar terms, are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0055] It should also be understood that the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprise", "comprising", "containing", "containing", "have", "having", and / or "including" are to be construed open-ended, in that they mean "including, but not limited to", unless otherwise noted. Additionally, when combinations are recited, such as "at least one of A and B", it is intended that the scope of the application includes each of the following alternatives: A alone, B alone, and both A and B. Furthermore, the use of "about" in relation to a value means that the exact value is not required, but rather the stated value plus or minus a margin of error, which is inherent to the measurement of values. Furthermore, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". Also, the term "exemplary" is intended to mean an example or illustration.

[0056] In addition, in the present application, when the expressions "connected", "covered", and / or "formed on" and the like are used, it can mean a direct or indirect connection between the respective components, unless there is a clear other limitation or it can be inferred from the context. In addition, "connected" can also mean an electrical connection, such as an on state of a circuit in a semiconductor device in an operating state. In addition, in the present application, when the expression "contact" is used, it can mean direct contact or direct connection between the respective components, unless there is a clear other limitation or it can be inferred from the context.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In addition, unless explicitly stated otherwise, words defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0058] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other as long as there is no conflict. In addition, unless explicitly limited or contradictory to the context, the specific steps of the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0059] Figure 1is a cross-sectional schematic view of a semiconductor device 1000 according to an embodiment of the present application. Figure 2 is Figure 1 is an enlarged schematic view of a semiconductor device A. Figure 3 is a cross-sectional schematic view of a semiconductor device 1000 according to another embodiment of the present application. Figure 4 is Figure 3 is an enlarged schematic view of a semiconductor device B.

[0060] As shown in Figures 1-4 The semiconductor device 1000 can include a connection layer 100, a stack structure 200, and a first contact structure 501. The stack structure 200 can be located on one side of the connection layer 100 along a first direction (z direction). The first contact structure 501 can include a first dielectric filling portion 510 and a first conductive layer 520 surrounding the first dielectric filling portion 510, where both the first dielectric filling portion 510 and the first conductive layer 520 can extend in the stack structure 200 along the z direction and contact the connection layer 100.

[0061] According to the semiconductor device provided by at least one embodiment of the present application, the first contact structure includes the first dielectric filling portion and the first conductive layer surrounding the first dielectric filling portion, both of which can contact the connection layer, thus effectively reducing the contact area between the first conductive layer and the connection layer, which reduces the degree of plasma induced damage (PID) caused by plasma process in the process of preparing the semiconductor device.

[0062] Specifically, the plasma process can include plasma etching process, plasma enhanced chemical vapor deposition, ion implantation, etc. In the process of forming the above-mentioned first contact structure and the connection layer by using plasma process, plasma charge can be introduced, and when the accumulated plasma charge is more and more, plasma induced damage is easy to occur. The smaller the contact area between the first conductive layer and the connection layer, the less the probability of the plasma charge being introduced into other structures of the semiconductor device, thus improving the reliability and overall performance of the semiconductor device.

[0063] As shown in Figure 1 and Figure 3 The connection layer 100 can extend along a direction intersecting the z direction (for example, the x direction) and can include a conductive material, such as any one or combination of conductive metal material and semiconductor material, where the conductive metal material can include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the semiconductor material can include any one or combination of doped crystalline silicon or silicide.

[0064] The stack structure 200 can include a first dielectric layer 220 disposed in the same layer as the gate layer 210 along the z direction. In addition, the semiconductor device 1000 further includes a second dielectric layer 230 stacked alternately with the gate layer 210 along the z direction. In other words, the stack structure 200 can include the second dielectric layer 230 and the composite layer stacked alternately, where the composite layer can include the gate layer 210 and the first dielectric layer 220 disposed in the same layer. The gate layer 210 and the first dielectric layer 220 can be distributed in connection with each other in an x-y plane intersecting the z direction. For example, the gate layer 210 can extend along the x direction and be connected with the first dielectric layer 220 disposed in the same layer.

[0065] Optionally, the gate layer 210 can include any suitable conductive material, for example, the conductive material can include any one or combination of a metal material, a metal compound material, and a semiconductor material, where the metal material can be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), chromium (Cr), etc., the metal compound material can include at least one of titanium nitride (TiNx), tantalum nitride (TaNx), chromium nitride (CrNx), tungsten nitride (WNx), silicon titanium nitride (TiSixNy), silicon tantalum nitride (TaSixNy), silicon chromium nitride (CrSixNy), and silicon tungsten nitride (WSixNy), and the semiconductor material can be, for example, doped crystalline silicon or silicide, etc., which are not limited in the present application.

[0066] The first dielectric layer 220 and the second dielectric layer 230 can respectively include a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials for forming the first dielectric layer 220 and the second dielectric layer 230 can respectively include silicon nitride and silicon oxide.

[0067] In addition, as the demand for storage capacity of semiconductor devices such as three-dimensional memory increases, the number of the above-mentioned stacked layers gradually increases. The stack structure 200 can include a plurality of sub-stack structures formed by, for example, a double stack technology or a multi-stack technology. The plurality of sub-stack structures can be stacked in sequence in a stacking direction (for example, the z direction), thereby forming the stack structure 200, where the sub-stack structure includes the gate layer and the second dielectric layer stacked with each other, and the first dielectric layer and the second dielectric layer stacked with each other. The number of layers of the sub-stack structure can be the same or different. The content described below for a single stack structure can be fully or partially applicable to the stack structure formed by the plurality of sub-stack structures, and thus the related or similar content is not described again.

[0068] In addition, the semiconductor device 1000 can further include a channel structure 300, which can include a channel layer 330 and a functional layer 320 surrounding the channel layer 330, where the functional layer 320 and the channel layer 330 can both extend along the z direction.

[0069] In some embodiments of the present application, the functional layer 320 can include a blocking layer, a charge trapping layer, and a tunneling layer. For example, the functional layer 320 can include a blocking layer formed on the inner wall of the channel hole (not shown) to block the flow of charges, a charge trapping layer formed on the surface of the blocking layer to store charges during the operation of the semiconductor device, and a tunneling layer formed on the surface of the charge trapping layer. Alternatively, the functional layer 320 can include an Oxides Nitride Oxides (ONO) structure. However, in some other embodiments, the functional layer 320 can also have a structure different from the ONO configuration.

[0070] In addition, the channel layer 330 can be formed on the surface of the tunneling layer and can be used to transport the required charges (electrons or holes). Alternatively, the channel layer 330 can be made of a semiconductor material such as polysilicon or monocrystalline silicon and can have conductive impurities. For example, the channel layer 330 can include an N-type doped or P-type doped polysilicon layer. The channel layer 330 can have a cylindrical or columnar shape extending in the z direction.

[0071] In some embodiments of the present application, the connection layer 100 can extend in a direction intersecting the z direction (for example, the x direction) and be connected to the channel layers 330 of the plurality of channel structures 300.

[0072] Figure 5 is a cross-sectional view of a semiconductor device 1000 according to an embodiment of the present application. Figure 6 is a cross-sectional view of a semiconductor device 1000 according to another embodiment of the present application.

[0073] As shown in Figure 5 and Figure 6 In some embodiments of the present application, the semiconductor device 1000 can include a memory array, where the memory array can include the channel structure 300. In addition, the semiconductor device 1000 can also include a peripheral circuit structure 600, which can be understood as an operating circuit. Alternatively, the peripheral circuit structure 600 can include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory array in the semiconductor device 1000. For example, the peripheral circuit structure 600 can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sensing structure (e.g., a bit line sense amplification structure), a driving structure (e.g., a word line driving structure), an input / output circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion of the above functional circuitry (e.g., a sub-circuit), or any active or passive components of the circuitry (e.g., a transistor, a diode, a resistor, or a capacitor), without limitation.

[0074] In some embodiments of the present application, the peripheral circuit structure 600 can be connected to the stack structure 200 by bonding. In this embodiment, the semiconductor device 1000 can further include a wafer connection structure 700 extending through the bonding layer in the z direction. Optionally, the wafer connection structure 700 can include a vertical interconnect via. With the vertical interconnect via, the transmission speed of input and output between the two bonded wafers can be improved. Optionally, the wafer connection structure 700 between the two bonded wafers can connect the connection portion 701 of the first contact structure 501.

[0075] It should be noted that in the drawings herein, the structure, number and position of the peripheral circuit and the interconnect structure (e.g., interconnect layer, interconnect via and interconnect line) are shown only by way of example, but it can be understood that the peripheral circuit and the interconnect structure shown in the drawings herein and the related content are shown only for the purpose of illustration, and the present application is not limited thereto. Those skilled in the art can adjust the peripheral circuit and the interconnect structure to achieve the same technical effect according to the idea of the present application.

[0076] In combination Figure 3 and Figure 5 In some embodiments of the present application, the stack structure 200 can include two opposite sides in the z direction, such as a first side 200-1 and a second side 200-2. Optionally, the peripheral circuit structure 600 can be disposed on at least one of the first side 200-1 and the second side 200-2. In addition, the peripheral circuit structure 600 can also be disposed on other parts of the semiconductor device 1000, which is not limited by the present application.

[0077] Optionally, the first contact structure 501 can extend in the z direction, through the first dielectric layer 220 and the second dielectric layer 230, and connect the peripheral circuit structure 600 and the connection layer 100. In other words, the first dielectric layer 220 and the second dielectric layer 230 can form an insulating dielectric material stack layer. By disposing the first contact structure in the insulating dielectric material stack layer, the possibility of short circuit can be reduced while achieving electrical communication between the first contact structure and the connection layer.

[0078] As Figures 1-4 shown, in some embodiments of the present application, the first dielectric filling portion 510 of the first contact structure 501 can include an insulating material layer, and the first conductive layer 520 can include at least one of a metal material layer and a metal compound material layer. Optionally, the metal compound material layer can contain at least one of titanium, tantalum, chromium, tungsten, nitrogen and silicon elements.

[0079] Exemplarily, the metal material layer can include at least one of titanium, tantalum, chromium, etc. The metal compound material layer can include at least one of titanium nitride, tantalum nitride, chromium nitride, tungsten nitride, silicon titanium nitride, silicon tantalum nitride, silicon chromium nitride, and silicon tungsten nitride.

[0080] Optionally, the first dielectric filling part 510 can include insulating gaps. In the process of forming the first dielectric filling part 510, a plurality of insulating gaps can be formed in the insulating material layer of the first dielectric filling part 510 by controlling the filling process to relieve structural stress.

[0081] Reference Figure 2 and Figure 4 In some embodiments of the present application, the size d1 of the first dielectric filling part 510 along the z direction can be equal to the size of the first conductive layer 520 along the z direction. It should be noted that, due to the limitation of the process, the error range of the size mentioned in the present embodiment and the size mentioned in other embodiments below relative to the reference plane can be between -10% and 10%.

[0082] In addition, in some embodiments of the present application, the first contact structure 501 can further include a second conductive layer 530 between the first dielectric filling part 510 and the first conductive layer 520. For example, the first conductive layer 520 can include at least one of a metal material layer and a metal compound material layer, and the second conductive layer 530 can include at least one of a metal material layer and a semiconductor material layer. Exemplarily, the metal material layer included in the second conductive layer 530 can be, for example, tungsten, cobalt, copper, aluminum, etc., and the semiconductor material layer included in the second conductive layer 530 can be, for example, doped crystalline silicon or silicide, etc., which are not limited in the present application.

[0083] As shown in Figure 1 and Figure 2 , as an option, the size d2 of the first conductive layer 520 along the z direction can be greater than the size d3 of the second conductive layer 530 along the z direction. The first conductive layer 520 extends along the z direction and includes an end portion 5201 in contact with the connection layer 100, wherein the end portion 5201 of the first conductive layer 520 can extend along a direction intersecting the z direction (for example, the x direction), which can improve the connection effect between the first conductive layer and the connection layer.

[0084] As shown in Figure 3 and Figure 4 , as another option, the size d2 of the first conductive layer 520 along the z direction can be equal to the size d3 of the second conductive layer 530 along the z direction, which can make the first conductive layer 520 and the second conductive layer 530 both extend along the z direction and be in contact with the connection layer 100.

[0085] Figure 7This is a cross-sectional schematic diagram of a semiconductor device 1 according to one embodiment.

[0086] like Figure 7 As shown, in one embodiment, the first contact structure 5011 of the semiconductor device 1 may extend along the z-direction and be connected to the connection layer 11. The first contact structure 5011 may include a first insulating dielectric filling portion 51 and a first conductive material layer 52 surrounding the first insulating dielectric filling portion 51, wherein the first conductive material layer 52 may include a "bottom" that contacts the connection layer 11 and a "sidewall" connected to the "bottom", and both the "bottom" and the "sidewall" of the first conductive material layer 52 are in contact with the first insulating dielectric filling portion 51.

[0087] In other words, the first conductive material layer 52 can be "barrel-shaped" surrounding the "bottom" and "sidewall" of the first insulating dielectric filling portion 51, wherein the "bottom" of the first insulating dielectric filling portion 51 is the end near the connecting layer 11, and the "sidewall" of the first insulating dielectric filling portion 51 is the surface connected to its "bottom". In this embodiment, the cross-sectional shape of the "bottom" of the first conductive material layer 52 in a plane intersecting the z-direction (e.g., the xy-plane) can be circular. That is, the area of ​​the "bottom" of the first conductive material layer 52 is relatively large, and therefore the contact area between the first conductive material layer 52 and the connecting layer 11 is relatively large. It should be noted that the "bottom" and "sidewall" mentioned above are intended to indicate different parts of the first conductive material layer 52 or different parts of the first insulating dielectric filling portion 51, which can also be referred to as the "first end", "side surface", etc., and this application does not limit them.

[0088] In the process of forming semiconductor device 1, a stacked structure 12 needs to be formed on one side of a substrate (not shown), and the aforementioned first contact structure 5011 is formed in the stacked structure 12. Then, the intermediate body with the first contact structure 5011 is flipped 180°, the substrate is removed, and the "bottom" of the first contact structure 5011 is exposed, thereby forming a connection layer 11 that contacts the first contact structure 5011. During the above fabrication process, the contact area between the first conductive material layer 52 and the connection layer 11 is too large, thus increasing the probability of plasma charge being introduced into other structures of the semiconductor device and increasing the degree of plasma-induced damage caused by the plasma process.

[0089] Refer again Figure 1 and Figure 3In some embodiments of this application, the cross-sectional shape of the first conductive layer 520 in a plane intersecting the z-direction (e.g., the xy-plane) may include an annular shape. Furthermore, the cross-sectional shape of the second conductive layer 530 in a plane intersecting the z-direction (e.g., the xy-plane) may also include an annular shape. The fact that at least one of the first and second conductive layers can have an annular cross-sectional shape in a plane intersecting the z-direction effectively reduces the contact area between the first conductive layer and the interconnecting layer, or between the second conductive layer and the interconnecting layer, thereby reducing the degree of plasma-induced damage and improving the reliability and overall performance of the semiconductor device.

[0090] It should be noted that the structure, quantity, and location of the first contact structure 501 are only shown as an example in the accompanying drawings. It is understood that the depiction of the first contact structure 501 in the drawings and related content is for illustrative purposes only and is not intended to limit the scope of this application. Although an exemplary structure of the first contact structure 501 is described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the first contact structure 501. For example, the first contact structure 501 may also include an isolation protective layer located between the stacked structure 200 and the first conductive layer 520. Furthermore, the materials of the exemplified layers are merely exemplary. Similarly, the structure of the second contact structure described below may also be omitted, substituted, or added, which will not be elaborated upon here.

[0091] Figure 8 yes Figure 1 The diagram shown is an enlarged view of the semiconductor device C in one embodiment of this application. Figure 9 This is a cross-sectional schematic diagram of the second contact structure 502 according to one embodiment of this application. Figure 10 This is a bottom view of the second contact structure 502 according to one embodiment of this application. Figure 11 yes Figure 1 The diagram shown is an enlarged view of the semiconductor device C in another embodiment of this application. Figure 12 This is a cross-sectional schematic diagram of the second contact structure 502 according to another embodiment of this application. Figure 13 This is a bottom view of the second contact structure 502 according to another embodiment of this application.

[0092] Taking a three-dimensional memory as an example, some semiconductor devices may include a stacked structure formed by alternating stacked gate layers and dielectric layers, wherein word line contacts located in the step region of the stacked structure can enable the gate layer to connect with the external circuit structure.

[0093] However, as the number of stacked layers increases, forming a word line contact in the step region requires a plurality of processes such as photolithography and etching to form a ladder-shaped morphology of the steps, which greatly increases the manufacturing cost of the semiconductor device; in addition, the more steps there are, the larger the area of the step region that needs to be formed, which is not conducive to improving the integration of the semiconductor device. In addition, as the number of stacked layers increases, the degree of warping of the wafer increases, and it is more difficult to align the step faces in the step region when forming the word line contact.

[0094] In some embodiments of the present application, the semiconductor device does not need to form the above-mentioned steps and the word line contacts corresponding to the steps, and the communication between the gate layers at different stacking heights and the external circuit structure can be achieved by a plurality of second contact structures with different extension lengths, which simplifies the semiconductor device preparation process and reduces the generation cost, while reducing the volume of the semiconductor device, improving the unit area storage density, reliability and overall performance of the semiconductor device.

[0095] Specifically, as shown in Figure 1 、 Figure 8 and Figure 11 In some embodiments of the present application, the gate layer 210 can include a first gate layer 211 and a second gate layer 212 surrounding the first gate layer 211. For example, the first gate layer 211 can include any one or a combination of conductive metal materials, such as tungsten, cobalt, copper, aluminum, etc., and doped semiconductor materials, such as doped crystalline silicon or silicide, etc., which are not limited in the present application. The second gate layer 212 can include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. The second gate layer 212 is used to block the diffusion of ions in the first gate layer 211 and can improve the adhesion between the first gate layer 211 and the second dielectric layer 230. It should be noted that Figure 8 and Figure 11 show the internal structure of the gate layer 210 and the second contact structure 502, in order to facilitate observation, Figure 8 and Figure 11 The gate layer 210 and the second contact structure 502 shown in the above figures adopt different patterns.

[0096] As shown in Figure 1 、 Figure 3 and Figures 8-13 The semiconductor device 1000 can also include a second contact structure 502, which can include a second dielectric filling portion 540 and a third conductive layer 550 surrounding the second dielectric filling portion 540, wherein the third conductive layer 550 can extend in the z direction and be in contact with the gate layer 210.

[0097] In some embodiments of the present application, the second dielectric filling portion 540 can include a layer of insulating material, and the third conductive layer 550 can include at least one of a layer of metal material and a layer of metal compound material. Optionally, the layer of metal compound material can include at least one of titanium element, tantalum element, chromium element, tungsten element, nitrogen element, and silicon element.

[0098] By way of example, the layer of metal material can include at least one of a layer of titanium, tantalum, chromium, and the like. The layer of metal compound material can include at least one of titanium nitride, tantalum nitride, chromium nitride, tungsten nitride, silicon titanium nitride, silicon tantalum nitride, silicon chromium nitride, and silicon tungsten nitride.

[0099] Optionally, the third conductive layer 550 can include a first portion 550-1 and a second portion 550-2 connected to each other, wherein the first portion 550-1 can extend along the z direction and surround the second dielectric filling portion 540, and the second portion 550-2 can extend along a direction intersecting the z direction (e.g., the x direction, the y direction) and contact the gate layer 210. It should be noted that the third conductive layer is divided into multiple portions and each portion is named for the convenience of description throughout the present application. However, it should be understood by those skilled in the art that the third conductive layer is actually an integral structure, and the above-mentioned multiple portions do not have obvious boundaries in the actual integral structure. In addition, the fourth conductive layer described later is also similar, and will not be described here.

[0100] Optionally, in combination with Figure 1 , Figure 3 , Figure 9 and Figure 12 , the first portion 550-1 and the second dielectric filling portion 540 can both extend from the first side 200-1 of the laminated structure 200 to the second side 200-2 of the laminated structure, wherein the size d4 of the first portion 550-1 along the z direction can be smaller than the size d5 of the second dielectric filling portion 540 along the z direction.

[0101] Again referring to Figure 7In one embodiment, the second contact structure 5021 of the semiconductor device 1 can extend along the z direction and be connected with the gate layer 121 of the stack structure 12. The second contact structure 5021 can include a second insulating medium filling portion 53 and a second conductive material layer 54 surrounding the second insulating medium filling portion 53, where the second conductive material layer 54 can include a "bottom" in contact with the gate layer 121 and a "sidewall" connected with the "bottom", and the "bottom" and the "sidewall" of the second conductive material layer 54 are both in contact with the second insulating medium filling portion 53. In other words, the second conductive material layer 54 can be in a "barrel shape" surrounding the second insulating medium filling portion 53. In this embodiment, the cross-sectional shape of the "bottom" of the second conductive material layer 54 in a plane intersecting the z direction (for example, the x-y plane) can include a circular shape. That is, the "bottom" of the second conductive material layer 54 has a relatively large area.

[0102] As shown in Figure 10 and Figure 13 , the cross-sectional shape of the second portion 550-2 in a plane intersecting the z direction (for example, the x-y plane) can include a ring shape. In other words, the cross-sectional shape of the second portion in a plane intersecting the z direction includes a ring shape, which effectively reduces the use of conductive material and increases the use of insulating medium material, while reducing structural stress and saving the preparation cost of the semiconductor device.

[0103] Optionally, the second medium filling portion 540 can include insulating gaps. In the process of forming the second medium filling portion 540, a plurality of insulating gaps can be formed in the insulating material layer of the second medium filling portion 540 by controlling the filling process to reduce the structural stress.

[0104] In addition, as shown in Figure 1 and Figure 3 , the second portion 550-2 is disposed in the same layer as the gate layer 210 in the z direction. As shown in Figure 3 , the size d6 of the second portion 550-2 along the z direction can be greater than or equal to the size of the gate layer 210 along the z direction. In other words, in some embodiments, the thickness of the third conductive layer in which the second portion is located is increased and is greater than the thickness of the gate layer, which can reduce the resistance of the third conductive layer and improve the electrical performance of the semiconductor device.

[0105] Optionally, the second contact structure 502 can extend along the z direction, pass through the first medium layer 220 and the second medium layer 230, and be connected with the gate layer 210. This allows the second contact structure to be disposed in the insulating medium material stack layer, which reduces the short circuit between different gate layers while achieving electrical communication between the second contact structure and the corresponding gate layer.

[0106] In addition, referring again to Figure 1 , Figures 8-13In some embodiments of the present application, the second contact structure 502 further includes a fourth conductive layer 560. Optionally, the fourth conductive layer 560 can include at least one of a metal material layer and a semiconductor material layer. For example, the fourth conductive layer 560 can include a metal material layer such as tungsten, cobalt, copper, aluminum, etc., and a semiconductor material layer such as doped crystalline silicon or silicide, etc., without limitation.

[0107] Alternatively, as shown in FIGS. 5B and 5C, the fourth conductive layer 560 can be located between the third conductive layer 550 and the second dielectric filling portion 540, wherein the fourth conductive layer 560 can include a third portion 560-1 and a fourth portion 560-2 connected to each other. The third portion 560-1 can extend along the z direction and surround the second dielectric filling portion 540, and the fourth portion 560-2 can extend along a direction intersecting the z direction (e.g., the x direction or the y direction) and contact the gate layer 210. For example, the fourth portion 560-2 can contact the first gate layer 211, and the second portion 550-2 can contact the second gate layer 212. Figure 1 、 Figures 8-10

[0108] Alternatively, as shown in FIGS. 5B and 5C, the fourth conductive layer 560 can be located between the third conductive layer 550 and the second dielectric filling portion 540, wherein the fourth conductive layer 560 can include a third portion 560-1 and a fourth portion 560-2 connected to each other. The third portion 560-1 can extend along the z direction and surround the second dielectric filling portion 540, and the fourth portion 560-2 can extend along a direction intersecting the z direction (e.g., the x direction or the y direction) and contact the gate layer 210. For example, the fourth portion 560-2 can contact the first gate layer 211, and the second portion 550-2 can contact the second gate layer 212. Figure 1 、 Figures 11-13

[0109] Figure 14 is a top view of a semiconductor device 1000 according to an embodiment of the present application.

[0110] As shown in FIG. 5D, in some embodiments of the present application, the semiconductor device 1000 can include a plurality of second contact structures 502, such as a first sub-contact structure 502-1, a second sub-contact structure 502-2, and a third sub-contact structure 502-3, etc., wherein the plurality of second contact structures 502 can respectively contact different gate layers 210. Figure 14 、

[0111] ​​Optionally, the plurality of second contact structures 502 can have different sizes in the direction intersecting the z direction (e.g., the x direction, the y direction), and can be arranged adjacently in the direction intersecting the z direction. For example, the first sub-contact structure 502-1, the second sub-contact structure 502-2, and the third sub-contact structure 502-3 can have a first size m1, a second size m2, and a third size m3 in the y direction intersecting the z direction and the x direction, respectively, where the first size m1, the second size m2, and the third size m3 can be different from each other, and the first sub-contact structure 502-1, the second sub-contact structure 502-2, and the third sub-contact structure 502-3 can be arranged adjacently along the y direction. It should be noted that the size of the second contact structure in the direction intersecting the z direction can be understood as the maximum size of the second contact structure in the plane intersecting the z direction (e.g., the x-y plane).

[0112] In this embodiment, the sizes of some of the second contact structures in the plane intersecting the z direction can be reduced while meeting the design requirements, and these second contact structures with different sizes can be arranged adjacently, thereby reducing the area of the region where the second contact structures are located, and improving the storage density of the semiconductor device. In addition, the sizes of these second contact structures in the plane intersecting the z direction are reduced, and accordingly, the cross-sectional sizes of the second portions of the third conductive layers of these second contact structures in the plane intersecting the z direction (e.g., the x-y plane) are also reduced, which reduces the structural stress while saving the manufacturing cost of the semiconductor device.

[0113] In addition, as shown in FIG. 1, Figure 1 the first contact structure 501 and the second contact structure 502 have similar structures, and thus can be formed in the same process, which can improve the reliability and overall performance of the semiconductor device while simplifying the manufacturing process of the semiconductor device and reducing the manufacturing cost of the semiconductor device.

[0114] Again referring to Figure 1 , Figure 3 and Figure 14 , in some embodiments of the present application, the semiconductor device 1000 can further include a gate line isolation structure 400, which can pass through the stack structure 200 along the z direction. In addition, the gate line isolation structure 400 can also extend in the stack structure 200 along the y direction.

[0115] Optionally, the gate line isolation structure 400 can include a gate line isolation layer and a gate line filling layer surrounded by the gate line isolation layer. Optionally, the material of the gate line isolation layer can include at least one of a high dielectric constant dielectric layer and an insulating dielectric material layer such as a silicon oxide layer. In addition, the material of the gate line filling layer can include at least one of a semiconductor material such as polysilicon and an insulating dielectric material layer such as a silicon oxide, silicon nitride, silicon oxynitride layer. Optionally, the material of the gate line filling layer can further include a conductive material layer. The present application does not limit the inner filling material of the gate line isolation structure 400.

[0116] Thus, according to at least one embodiment of the present application, the first contact structure includes a first dielectric filling portion and a first conductive layer arranged around the first dielectric filling portion, both of which can be in contact with the connection layer, thus effectively reducing the contact area between the first conductive layer and the connection layer, which can reduce the probability of plasma charges generated by plasma process in the process of preparing the semiconductor device being introduced into other structures of the semiconductor device, thus improving the reliability and overall performance of the semiconductor device.

[0117] Figures 15-20 Process schematic diagrams of a method for preparing a semiconductor device according to an embodiment.

[0118] As shown in Figure 15 , a laminated structure 12 can be formed on one side of a substrate 11' in the z direction, where the substrate 11' can include an etching stop layer 124, and the laminated structure 12 can include a gate layer 121. In addition, the laminated structure 12 further includes a second dielectric layer 122 alternately stacked with the gate layer 121 in the z direction and a first dielectric layer 123 arranged in the same layer as the gate layer 121 in the z direction.

[0119] After the formation of the laminated structure 12, a first contact hole 50 and a second contact hole 50' can be formed by an etching process, where the first contact hole 50 can extend to the etching stop layer 124 in the z direction, and the second contact hole 50' can extend to the corresponding gate layer 121 in the z direction.

[0120] As shown in Figure 15 and Figure 16 , after the formation of the first contact hole 50 and the second contact hole 50', a first initial conductive layer 52' and a second initial conductive layer 55' can be sequentially formed by a deposition process. The first initial conductive layer 52' can be formed on the surface of the laminated structure 12 away from the substrate 11', the inner surface of the first contact hole 50, and the inner surface of the second contact hole 50', where the first initial conductive layer 52' can be in contact with the etching stop layer 124 and the gate layer 121. The second initial conductive layer 55' can be formed on the surface of the first initial conductive layer 52'.

[0121] As shown in Figure 16 and Figure 17As shown, a first initial insulating dielectric filling portion 51' can be formed on the surface of the second initial conductive layer 55' through a deposition process. The first initial insulating dielectric filling portion 51' can fill the first contact hole 50 (e.g., Figure 15 The remaining space (as shown) and the second contact hole 50' (as shown) Figure 15 In the remaining space (as shown).

[0122] like Figures 17-19 As shown, after the first initial insulating dielectric filling portion 51' is formed, a portion of the first initial insulating dielectric filling portion 51', a portion of the second initial conductive layer 55', and a portion of the first initial conductive layer 52' ​​can be removed sequentially by etching process, polishing process, etc., thereby forming a first contact structure 5011 that contacts the etching stop layer 124 and a second contact structure 5021 that contacts the gate layer 121.

[0123] The first contact structure 5011 may include a first insulating dielectric filling portion 51 and a first conductive material layer 52 surrounding the first insulating dielectric filling portion 51, wherein the first conductive material layer 52 may include a "bottom" in contact with the etch stop layer 124. The second contact structure 5021 may extend along the z-direction and is connected to the gate layer 121 of the stacked structure 12. The second contact structure 5021 may include a second insulating dielectric filling portion 53 and a second conductive material layer 54 surrounding the second insulating dielectric filling portion 53, wherein the second conductive material layer 54 may include a "bottom" in contact with the gate layer 121.

[0124] like Figures 19-20 As shown, after forming the first contact structure 5011 and the second contact structure 5021, the... Figure 19 After the intermediate shown is flipped 180°, the substrate 11' can be removed using an etching process including plasma etching, exposing the "bottom" of the first contact structure 5011, thereby forming a connection layer 11 that contacts the contact structure 5011. During the above fabrication process, the "bottom" area of ​​the first conductive material layer 52 is too large, thus increasing the probability of plasma charges generated by the plasma process being introduced into other structures of the semiconductor device, and increasing the degree of plasma-induced damage.

[0125] Figure 21 This is a flowchart of a method for fabricating a semiconductor device according to one embodiment of this application, 2000. Figures 22-26 These are schematic diagrams of a semiconductor device fabrication method 2000 according to one embodiment of this application.

[0126] like Figure 15 As shown, the semiconductor device fabrication method 2000 may include:

[0127] S1, a laminated structure is formed on one side of the substrate along the first direction.

[0128] S2, forming a first contact structure extending in the stacked structure along a first direction, wherein the first contact structure includes a first dielectric filling portion and a first conductive layer surrounding the first dielectric filling portion.

[0129] S3, remove the substrate and form a connecting layer, wherein the first dielectric filling portion and the first conductive layer both extend along the first direction and are in contact with the connecting layer.

[0130] The following will combine Figures 22-26 The specific processes of each step of the above preparation method 2000 in the embodiments of this application are described in detail.

[0131] Step S1

[0132] Figure 22 This is a cross-sectional schematic diagram of the structure formed after forming the first contact hole 5111 according to a preparation method of one embodiment of this application.

[0133] like Figure 22 As shown, step S1, which forms a stacked structure on one side of the substrate along the first direction, may include, for example, alternatingly stacking a second dielectric layer 230 and a gate sacrificial layer (not shown) along the z-direction to form a stacked structure (not shown); and replacing a portion of the gate sacrificial layer with a gate layer 210 to form a stacked structure 200.

[0134] Specifically, in the following embodiments, the process of forming a single stacked structure will be described as an example. However, this application does not limit the number of stacked structures or the specific structure of the stacked structures. In other words, the content, preparation method, structure, and beneficial effects of the semiconductor device fabrication method including a single stacked structure described in this application can be fully or partially applied to the fabrication method of a semiconductor device including multiple sub-stacked structures. Therefore, related or similar content will not be repeated. The number of multiple sub-stacked structures is greater than or equal to 2.

[0135] In some embodiments of this application, the semiconductor device fabrication method 2000 may further include providing a substrate 100' before forming the stacked structure.

[0136] Alternatively, the substrate 100' can be made of any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds. Furthermore, single-crystal silicon can be selected as the substrate 100'.

[0137] In one embodiment of the present application, the substrate 100' can be, for example, a composite substrate for supporting a device structure thereon. The substrate 100' can be formed by sequentially disposing a plurality of layers made of different materials through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

[0138] The substrate 100' can include an etch stop layer 110. The etch stop layer 110 can include a single layer, multiple layers, or a suitable composite layer. For example, the etch stop layer 110 can include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In addition, the etch stop layer 110 can also include a layer of a semiconductor material, such as a polysilicon layer. Alternatively, the etch stop layer 110 can also include a high dielectric constant dielectric layer.

[0139] A portion of the substrate 100' can also form a well region doped with an N-type or P-type dopant via an ion implantation or diffusion process. The dopant can include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well regions can be prepared with the same dopant, or can be prepared with different dopants. In addition, the well regions can have the same doping concentration, or can have different doping concentrations, without limitation.

[0140] In some embodiments of the present application, the stack structure can be formed by alternately stacking the second dielectric layers 230 and the gate sacrificial layers along one side of the substrate 100' in the z-direction.

[0141] Specifically, after the substrate 100' is formed, the stack structure can be formed on one side of the substrate 100' through one or more thin film deposition processes, which can include, but are not limited to, a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, without limitation.

[0142] The stack structure can include a plurality of pairs of the second dielectric layers 230 and the gate sacrificial layers alternately stacked with each other, where the second dielectric layers 230 and the gate sacrificial layers form pairs of dielectric layers. For example, the sub-stack structure can include a plurality of pairs of the pairs of dielectric layers, such as 64 pairs, 128 pairs, or more than 128 pairs of the second dielectric layers 230 and the gate sacrificial layers.

[0143] In some embodiments, the second dielectric layer 230 and the gate sacrificial layer can include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the second dielectric layer 230 and the gate sacrificial layer can include silicon oxide and silicon nitride, respectively. The silicon oxide layer can be used as an isolation stack, while the silicon nitride layer can be used as a sacrificial stack. Subsequently, portions of the sacrificial stack can be etched away, and the etched-away portions of the sacrificial stack can be replaced with a conductor layer including a conductive material to form the gate layer 210 of the semiconductor device.

[0144] In some embodiments of the present disclosure, the method 2000 of fabricating a semiconductor device further includes forming a channel structure 300, which can include, for example, forming channel holes (not shown) that can extend in the z-direction through the stack structure; forming a functional layer 320 in the channel holes 310; and forming a channel layer 330 on a surface of the functional layer 320.

[0145] The channel structure 300 can include a semiconductor layer and a composite dielectric layer filled in the channel holes, for example, the channel structure 300 can include the functional layer 320 and the channel layer 330 surrounded by the functional layer 320.

[0146] Specifically, the plurality of channel holes can be formed by, for example, a dry etching process or a combination of a dry etching process and a wet etching process; other fabrication processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., can also be performed.

[0147] Optionally, the plurality of channel holes can have the same depth in the z-direction to reduce the difficulty of fabricating the semiconductor device and to reduce the cost of fabricating the semiconductor device.

[0148] After the plurality of channel holes are formed, the functional layer can be formed on the inner walls of the channel holes 310 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0149] The functional layer 320 can include a barrier layer formed on the inner walls of the channel holes to block the flow of charges; a charge trapping layer formed on a surface of the barrier layer to store charges during operation of the semiconductor device; and a tunneling layer formed on a surface of the charge trapping layer.

[0150] In some embodiments of the present disclosure, the functional layer 320 can include an ONO structure. However, in some other embodiments, the functional layer 320 can have a structure different from the ONO configuration.

[0151] Furthermore, those skilled in the art will appreciate that the functional layer can be formed on the sidewalls and the bottom of the channel hole or on the sidewalls of the channel hole without departing from the teachings of the present application, and the present application is not limited in this regard.

[0152] After the functional layer 320 is formed, a channel layer 330 can be formed on the surface of the tunneling layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0153] Optionally, the channel layer 330 can be used to transport the desired charge (electrons or holes). The channel layer 330 can be made of a semiconductor material such as polysilicon or monocrystalline silicon and can have conductive impurities. For example, the channel layer 330 can include an N-type doped or P-type doped polysilicon layer. Similar to the channel hole, the channel layer 330 can also have a cylindrical or columnar shape extending along the z direction. Alternatively, the channel layer 330 can also extend into the substrate 100'.

[0154] Furthermore, the channel structure 300 can also include a channel plug formed at the end of the channel hole away from the substrate 100', which can be understood as the top end of the channel structure 300. Specifically, after the channel layer 330 is formed, a channel fill dielectric layer can be used to fill the remaining space of the channel hole. The channel fill dielectric layer can include an oxide dielectric layer such as silicon oxide. Furthermore, during the filling process, a plurality of insulating gaps can be formed in the channel fill dielectric layer by controlling the channel filling process to relieve the structural stress. The channel plug can then be formed in the portion of the channel fill dielectric layer on top of the channel hole. The channel plug can be made of the same material as the channel layer 330, such as an N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer 330.

[0155] Furthermore, in some embodiments of the present application, the method 2000 of fabricating a semiconductor device further includes forming a gate line isolation structure 400.

[0156] The gate line gaps (not shown) generated during the formation of the gate line isolation structure 400 can serve as a path to provide an etchant, so that a portion of the gate sacrificial layer can be removed using a process such as wet etching. Thereafter, the gate layer 210 can be formed in the voids (not shown) formed after the removal of the portion of the gate sacrificial layer.

[0157] Specifically, the gate line gaps can be formed by a process such as a dry etching process or a combination of dry and wet etching processes, and other fabrication processes such as patterning processes including photolithography, cleaning, and chemical mechanical polishing can also be performed. At least one of the plurality of gate line gaps can extend along the y direction. Furthermore, the gate line gaps can also extend through the stack structure along the z direction and into the substrate 100'.

[0158] After the formation of the gate line gap, a portion of the gate sacrificial layer can be removed by a process such as wet etching. By the gate line gap, the etchant and chemical precursor are contacted to the portion of the gate sacrificial layer, and in turn, the portion of the gate sacrificial layer is removed to form a sacrificial void.

[0159] In addition, in at least one embodiment of the present application, the layout of the gate line gap in the x-y plane can be selected according to different settings of the architecture of the semiconductor device to be finally formed, so as to reduce the size of the gate line isolation structure formed based on the gate line gap, increase the storage density of the semiconductor device to be finally formed, and optimize the process window of the above-mentioned step of removing the gate sacrificial layer.

[0160] After the formation of the sacrificial void, the gate layer 210 can be formed in the sacrificial void by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The gate layer 210 can include a conductive material, which can include any one or a combination of a conductive metal material such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and a doped semiconductor material such as doped crystalline silicon or silicide, etc., without limitation.

[0161] In addition, in some embodiments of the present application, after the gate layer 210, the gate line isolation structure 400 can also be formed by filling the gate line gap. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form a gate line isolation layer and a gate line filling layer on the surface of the gate line isolation layer in the gate line gap.

[0162] Optionally, the material of the gate line isolation layer can include at least one of a high dielectric constant dielectric layer and an insulating dielectric material layer such as a silicon oxide layer. In addition, the material of the gate line filling layer can include at least one of a semiconductor material such as polysilicon and an insulating dielectric material layer such as a silicon oxide, silicon nitride, silicon oxynitride, etc. Optionally, the material of the gate line filling layer can also include a conductive material layer. The present application does not limit the internal filling material of the gate line isolation structure 400.

[0163] In addition, after the formation of the gate layer 210 in the stack structure, the stack structure is formed into a laminated structure 200, in which the remaining gate sacrificial layer is formed into a first dielectric layer 220.

[0164] Step S2

[0165] Figure 23 is a sectional view of a structure formed after the formation of an initial first conductive layer 520' according to the preparation method of one embodiment of the present application. Figure 24is a cross-sectional schematic view of a structure formed after forming the first contact structure 501 according to the manufacturing method of one embodiment of the present application. Figure 25 is a cross-sectional schematic view of a structure formed after forming the initial first dielectric filling portion 510' according to the manufacturing method of one embodiment of the present application. Figure 26 is a cross-sectional schematic view of a structure formed after forming the first contact structure 501 according to the manufacturing method of one embodiment of the present application.

[0166] As shown in Figures 22-26 , step S2 forms the first contact structure extending in the first direction in the stack structure, where the first contact structure includes the first dielectric filling portion and the first conductive layer surrounding the first dielectric filling portion. The forming of the first contact structure can include, for example: forming the first contact hole 5111 in the stack structure 200, where the first contact hole 5111 extends in the z direction and includes the first end portion 5111-1 extending into the substrate 100'; forming the initial first conductive layer 520' in the first contact hole 5111; removing part of the initial first conductive layer 520' to form the first conductive layer 520 and expose part of the first end portion 5111-1; and forming the first dielectric filling portion 510 in the remaining space of the first contact hole 5111.

[0167] Specifically, as shown in Figure 22 , in some embodiments of the present application, the first contact hole 5111 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc. The first contact hole 5111 can extend in the z direction and include the first end portion 5111-1 and the third end portion 5111-2 opposite to each other in the z direction, where the first end portion 5111-1 can extend to the etching stop layer 110 of the substrate 100'.

[0168] Optionally, referring again to Figures 22-26 , to simplify the manufacturing process of the semiconductor device and reduce the manufacturing cost, the first contact structure 501 and the second contact structure 502 in contact with the gate layer 210 can be formed in the same process. Hereinafter, the forming process of the first contact structure 501 and the second contact structure 502 will be described by taking the first contact structure 501 and the second contact structure 502 formed in the same process as an example. It should be noted that the first contact structure 501 and the second contact structure 502 can be formed in the same process or in different processes, which is not limited in the present application.

[0169] Optionally, the second contact structure 502 may include a second dielectric filling portion 540 and a third conductive layer 550 surrounding the second dielectric filling portion 540, the third conductive layer 550 extending along the z-direction and contacting the gate layer 210.

[0170] like Figure 22 As shown, during the formation of the first contact hole 5111, a second contact hole 5112 for accommodating the second contact structure 502 can be formed. The second contact hole 5112 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. The second contact hole 5112 may extend along the z-direction and includes a second end 5112-1 and a fourth end 5112-2 opposite to each other in the z-direction, wherein the second end 5112-1 may contact the gate layer 210.

[0171] like Figure 22 and Figure 23 As shown, after forming the first contact hole 5111, an initial first conductive layer 520' can be formed through one or more thin film deposition processes. These thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; this application does not limit the specific processes. The initial first conductive layer 520' is formed on the surface of the stacked structure 200 away from the substrate 100', the inner wall of the first contact hole 5111, and the inner wall of the second contact hole 5112. The portion of the initial first conductive layer 520' located in the first contact hole 5111 can contact the etch stop layer 110, and the portion of the initial first conductive layer 520' located in the second contact hole 5112 can contact the gate layer 210. It should be noted that the portion of the initial first conductive layer 520' located in the second contact hole 5112 can also be understood as being used to form the second contact structure 502 (e.g., ...). Figure 26 The third conductive layer 550 (as shown) Figure 26 The initial third conductive layer 550' (as shown).

[0172] The initial first conductive layer 520' may include at least one of a metal material layer and a metal compound material layer. Optionally, the metal compound material layer may include at least one of titanium, tantalum, chromium, tungsten, nitrogen, and silicon. Exemplarily, the aforementioned metal material layer may include at least one of titanium, tantalum, chromium, and other metallic materials. The aforementioned metal compound material layer may include at least one of titanium nitride, tantalum nitride, chromium nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, chromium silicon nitride, and tungsten silicon nitride.

[0173] Optionally, after the initial first conductive layer 520' is formed, an initial second conductive layer 530' can also be formed on the surface of the initial first conductive layer 520' by one or more thin film deposition processes, which can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, or any combination thereof, without limitation. It should be noted that the portion of the initial second conductive layer 530' located in the second contact hole 5112 can also be understood as an initial fourth conductive layer 560' for forming the fourth conductive layer 560 (as shown in Figure 26 ) in the second contact structure 502 (as shown in Figure 26 ).

[0174] The initial second conductive layer 530' can include at least one of a metal material layer and a semiconductor material layer. For example, the metal material layer included in the initial second conductive layer 530' can be tungsten, cobalt, copper, aluminum, etc., and the semiconductor material layer included in the initial second conductive layer 530' can be doped crystalline silicon or silicide, etc., without limitation.

[0175] As shown in Figures 23-24 , by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., can also be performed to remove part of the initial first conductive layer 520' to form the first conductive layer 520 and expose part of the first end portion 5111-1. In addition, during the removal of part of the initial first conductive layer 520', the same process can also be used to remove part of the initial second conductive layer 530' to form the second conductive layer 530.

[0176] In addition, during the formation of the first conductive layer 520 and the exposure of part of the first end portion 5111-1, the same process can also be used to remove part of the initial first conductive layer 520' to form the third conductive layer 550 and expose part of the second end portion 5112-1 of the second contact hole 5112 (as shown in Figure 22 ). In addition, during the formation of the third conductive layer 550, the same process can also be used to remove part of the initial second conductive layer 530' to form the fourth conductive layer 560.

[0177] As shown in Figure 24 and Figure 25As shown, after the first conductive layer 520 is formed, an initial first dielectric fill 510' can be formed by one or more thin film deposition processes, which can include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, or any combination thereof, without limitation.

[0178] The initial first dielectric fill 510' can be formed on surfaces of the stack structure 200 distal from the surface of the substrate 100', the surface of the second conductive layer 530, and the surface of the fourth conductive layer 560. In other words, the initial first dielectric fill 510' can fill in the remaining space of the first contact hole 5111 (as shown in Figure 22 ) formed with the first conductive layer 520 and the second conductive layer 530. In addition, the initial first dielectric fill 510' can also fill in the remaining space of the second contact hole 5112 (as shown in Figure 22 ) formed with the third conductive layer 550 and the fourth conductive layer 560. It is noted that the portion of the initial first dielectric fill 510' located in the second contact hole 5112 can also be understood as an initial second dielectric fill 540' for forming the second dielectric fill 540 (as shown in Figure 26 ) in the second contact structure 502 (as shown in Figure 26 ).

[0179] The initial first dielectric fill 510' can include any suitable insulating material layer. Exemplarily, the initial first dielectric fill 510' can include a silicon oxide layer. In addition, during the formation of the initial first dielectric fill 510', a plurality of insulating gaps can be formed in the first contact hole 5111 (as shown in Figure 22 ) and the second contact hole 5112 (as shown in Figure 22 ) by controlling the fill process to mitigate structural stress.

[0180] As shown in Figure 25 and Figure 26 , by way of example, a portion of the initial first dielectric fill 510' can be removed by a dry etching process or a combination of dry and wet etching processes, and other fabrication processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., can also be performed to form the first contact structure 501 and the second contact structure 502.

[0181] The first contact structure 501 can include a first dielectric filling portion 510 and a first conductive layer 520 surrounding the first dielectric filling portion 510, wherein the first dielectric filling portion 510 and the first conductive layer 520 can both extend in the z direction in the stack structure 200 and contact the etching stop layer 110. The second contact structure 502 can include a second dielectric filling portion 540 and a third conductive layer 550 surrounding the second dielectric filling portion 540, wherein the third conductive layer 550 can extend in the z direction and contact the gate layer 210.

[0182] Step S3

[0183] Referring again to Figure 1 and Figure 26 , the step S3 of removing the substrate and forming the connection layer, wherein the first dielectric filling portion and the first conductive layer both extend in the first direction and contact the connection layer, can for example include: removing the substrate 100’ and exposing an end of the first contact structure 501 that contacts the etching stop layer 110; and forming the connection layer 100, wherein the first dielectric filling portion 510 and the first conductive layer 520 both contact the connection layer 100.

[0184] After forming the first contact structure 501 and the second contact structure 502, the substrate 100’ can be removed and an end of the first contact structure 501 that contacts the etching stop layer 110 can be exposed by, for example, a dry etching process or a combination of a dry etching process and a wet etching process, wherein the dry etching process includes a plasma etching process. Other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., can also be performed.

[0185] Since the contact area between the first conductive layer 520 and the etching stop layer 110 in the first contact structure 501 is small, the contact area between the first conductive layer 520 and the subsequently formed connection layer 100 is also small, which can reduce the probability of plasma charges introduced by the plasma process being introduced into other structures of the semiconductor device, thereby improving the reliability and overall performance of the finally formed semiconductor device.

[0186] After exposing the end of the first contact structure 501 that contacts the etching stop layer 110, the connection layer 100 can be formed by one or more thin film deposition processes, wherein the thin film deposition process can include, but is not limited to, a chemical vapor deposition (CVD), a physical vapor deposition (PVD), an atomic layer deposition (ALD), or any combination thereof, without limitation in the present application.

[0187] The connection layer 100 can extend in a direction intersecting the z-direction (e.g., the x-direction) and can include a conductive material, such as any one or a combination of a conductive metallic material, which can include tungsten, cobalt, copper, aluminum, etc., and a semiconductive material, which can include any one or a combination of doped crystalline silicon or silicide.

[0188] Further, referring to Figure 5 and Figure 26 In some embodiments of the present application, the method 2000 of fabricating a semiconductor device further includes providing a peripheral circuit structure 600; and connecting the peripheral circuit structure 600 and the stack structure 200.

[0189] As an option, the semiconductor device 1000 can include a memory array, which can include the channel structure 300. The peripheral circuit structure 600 can include any suitable digital, analog, and / or mixed-signal circuitry for facilitating operation of the memory array in the semiconductor device 1000. For example, the peripheral circuit structure 600 can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sensing structure (e.g., a bit line sense amplification structure), a driving structure (e.g., a word line driving structure), an input / output circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion of the above functional circuitry (e.g., a sub-circuit), or any active or passive components of the circuitry (e.g., a transistor, a diode, a resistor, or a capacitor).

[0190] According to some embodiments, the peripheral circuit structure 600 can be implemented using, for example, complementary metal-oxide-semiconductor (CMOS) technology and designed according to actual needs, which are not described herein in detail.

[0191] Further, in some embodiments of the present application, the memory array and the peripheral circuit structure 600 connected thereto can be formed on two different wafers (e.g., a memory array wafer and a peripheral circuit wafer) respectively, and then the peripheral circuit wafer is bonded to the memory array wafer through a process such as wafer bonding, and the peripheral circuit structure 600 and the memory array circuit are connected together through, for example, an interconnection layer, an interconnection via, an interconnection line, and a connection line.

[0192] Optionally, in some other embodiments of the present application, the memory array and the peripheral circuit structure 600 can also be formed directly on the same wafer without forming a connection through the above-mentioned wafer bonding process, which is not limited in the present application.

[0193] Optionally, in the case of using a bonding process, the wafer connection structure 700 can be formed along the z direction through the bonding layer. Optionally, the wafer connection structure 700 can include a vertical interconnection channel. By using the vertical interconnection channel, the transmission speed of input and output between the two bonded wafers can be improved, and the connection of the wafer connection structure 700 to the connection part 701 of the first contact structure 501 between the two bonded wafers is facilitated.

[0194] Therefore, according to the method for manufacturing a semiconductor device provided by at least one embodiment of the present application, the first contact structure includes a first dielectric filling part and a first conductive layer arranged around the first dielectric filling part, both of which can be in contact with the connection layer, thereby effectively reducing the contact area between the first conductive layer and the connection layer, which reduces the degree of plasma-induced damage in the process of manufacturing the semiconductor device by plasma process. In the process of using plasma process to form the above-mentioned first contact structure and the connection layer, plasma charges are introduced. When the accumulated plasma charges are more and more, plasma-induced damage is easily generated. The contact area between the first conductive layer and the connection layer is smaller, which can reduce the probability of plasma charges being introduced into other structures of the semiconductor device, thereby improving the reliability and overall performance of the semiconductor device.

[0195] In addition, Figure 27 is a structural schematic diagram of a memory system 30000 according to an embodiment of the present application.

[0196] As Figure 27 indicated, at least one embodiment of another aspect of the present application further provides a memory system 30000. The memory system 30000 can include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 can be the same as the semiconductor device described in any of the above embodiments, and the present application will not be repeated here. The semiconductor device 20000 can be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device, which will be described below taking a three-dimensional semiconductor device as an example.

[0197] As an option, the three-dimensional semiconductor device can include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0198] The memory system 30000 can include the semiconductor device 20000 and a controller 32000. The semiconductor device 20000 can be the same as the semiconductor device described in any of the embodiments above, and the description thereof will not be repeated herein. The controller 32000 can control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 can perform an operation based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 can receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 can perform an internal operation corresponding to the command on the region selected by the address.

[0199] In some embodiments, the three-dimensional memory system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of RS-MMC and micro-SD, a secure digital card in the form of SD, mini-SD and micro-SD, a storage device of a personal computer memory card international association (PCMCIA) card type, a storage device of a peripheral component interconnect (PCI) type, a storage device of a high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card, or a memory stick, etc. The memory system provided by the present application has the same advantageous effects as the semiconductor device due to the provision of the semiconductor device provided by the present application, and the description thereof will not be repeated herein.

[0200] Although exemplary methods of fabrication and structures of the semiconductor device are described herein, it is understood that one or more features can be omitted, substituted, or added from the structure of the semiconductor device. In addition, the materials of the example layers are merely exemplary.

[0201] The above description is merely exemplary of the application and the application of the principles thereof. It is understood that variations in the described embodiments can be made by those skilled in the art without departing from the scope of the application as described and claimed herein. For example, equivalent and / or alternative implementations of the features described herein are possible.

Claims

1. A semiconductor device, comprising: a connection layer; a stack structure located at one side of the connection layer along a first direction; a first contact structure including a first dielectric filling portion and a first conductive layer surrounding the first dielectric filling portion, wherein the first dielectric filling portion and the first conductive layer both extend in the stack structure along the first direction and contact the connection layer.

2. The semiconductor device of claim 1, wherein, the first conductive layer includes at least one of a metal material layer and a metal compound material layer; and the first dielectric filling portion includes an insulating material layer.

3. The semiconductor device of claim 2, wherein, the metal compound material layer contains at least one of titanium element, tantalum element, chromium element, tungsten element, nitrogen element and silicon element. 4.The semiconductor device of claim 1, wherein a size of the first dielectric filling portion along the first direction is equal to a size of the first conductive layer along the first direction.

5. The semiconductor device of claim 1, wherein, the first contact structure further includes: a second conductive layer located between the first conductive layer and the first dielectric filling portion, wherein the first conductive layer includes at least one of a metal material layer and a metal compound material layer; and the second conductive layer includes at least one of a metal material layer and a semiconductor material layer.

6. The semiconductor device of claim 5, wherein, a size of the first conductive layer along the first direction is greater than a size of the second conductive layer along the first direction; and the first conductive layer extends along the first direction and includes an end portion contacting the connection layer, wherein the end portion extends along a direction intersecting the first direction.

7. The semiconductor device of claim 5, wherein, a size of the first conductive layer along the first direction is equal to a size of the second conductive layer along the first direction; and the first conductive layer and the second conductive layer both extend along the first direction and contact the connection layer.

8. The semiconductor device of claim 1, wherein, the semiconductor device further includes: a channel structure extending in the stack structure along the first direction and including a channel layer and a functional layer surrounding the channel layer, wherein the connection layer extends along a direction intersecting the first direction and connects the channel layers of a plurality of the channel structures.

9. The semiconductor device of claim 1, wherein, a cross-sectional shape of the first conductive layer in a plane intersecting the first direction includes a ring shape.

10. The semiconductor device according to any one of Claims 1-9, wherein, the semiconductor device further includes: a second contact structure including a second dielectric filling portion and a third conductive layer surrounding the second dielectric filling portion, wherein the third conductive layer extends along the first direction and contacts a gate layer of the stack structure.

11. The semiconductor device of claim 10, wherein, the third conductive layer includes a first portion and a second portion connected to each other, wherein the first portion extends along the first direction and surrounds the second dielectric filling portion; and the second portion extends along a direction intersecting the first direction and contacts the gate layer.

12. The semiconductor device of claim 11, wherein, the first portion and the second dielectric filling portion both extend from a first side of the stack structure to a second side of the stack structure, the first side and the second side being oppositely arranged along the first direction, wherein a size of the first portion along the first direction is smaller than a size of the second dielectric filling portion along the first direction.

13. The semiconductor device of claim 11, wherein, a cross-sectional shape of the second portion in a plane intersecting the first direction includes a ring shape.

14. The semiconductor device of claim 11, wherein, The second portion is arranged in the same layer as the gate layer along the first direction.

15. The semiconductor device of claim 11, wherein, A dimension of the second portion along the first direction is greater than or equal to a dimension of the gate layer along the first direction.

16. The semiconductor device of claim 10, wherein, The semiconductor device further comprises: a first dielectric layer arranged in the same layer as the gate layer along the first direction, wherein the second contact structure extends along the first direction, passes through the first dielectric layer, and is connected with the gate layer.

17. The semiconductor device of claim 10, wherein, A plurality of the second contact structures have different dimensions in a direction intersecting the first direction and are adjacent in the direction intersecting the first direction.

18. The semiconductor device of claim 10, wherein, The third conductive layer comprises at least one of a metal material layer and a metal compound material layer; and The second dielectric filling portion comprises an insulating material layer.

19. The semiconductor device of claim 10, wherein, The second contact structure further comprises: a fourth conductive layer between the third conductive layer and the second dielectric filling portion, wherein the fourth conductive layer comprises a third portion and a fourth portion connected with each other; the third portion extends along the first direction and surrounds the second dielectric filling portion; and the fourth portion extends along a direction intersecting the first direction and is in contact with the gate layer.

20. The semiconductor device of claim 10, wherein, The second contact structure further comprises: a fourth conductive layer between the third conductive layer and the second dielectric filling portion.

21. The semiconductor device of claim 19 or 20, wherein, The third conductive layer comprises at least one of a metal material layer and a metal compound material layer; and The fourth conductive layer comprises at least one of a metal material layer and a semiconductor material layer.

22. A method for manufacturing a semiconductor device, comprising: forming a stack structure on one side of a substrate along a first direction; forming a first contact structure extending in the stack structure along the first direction; and removing the substrate and forming a connection layer, wherein the first contact structure comprises a first dielectric filling portion and a first conductive layer surrounding the first dielectric filling portion; and the first dielectric filling portion and the first conductive layer both extend along the first direction and are in contact with the connection layer.

23. The method of claim 22, wherein, forming a first contact structure extending in the stack structure along the first direction comprises: forming a first contact hole in the stack structure, wherein the first contact hole extends along the first direction and comprises a first end portion extending into the substrate; forming an initial first conductive layer in the first contact hole; removing part of the initial first conductive layer to form the first conductive layer and expose part of the first end portion; and forming the first dielectric filling portion in the remaining space of the first contact hole.

24. The method of claim 23, wherein, forming a first contact structure extending in the stack structure along the first direction further comprises: forming an initial second conductive layer on a surface of the initial first conductive layer; and in the process of removing part of the initial first conductive layer, part of the initial second conductive layer is removed to form a second conductive layer.

25. The method of claim 22, wherein, The method further comprises forming a second contact structure, wherein the second contact structure comprises a second dielectric filling portion and a third conductive layer surrounding the second dielectric filling portion, the third conductive layer extending along the first direction and being in contact with a gate layer of the stack structure.

26. The method of claim 25, wherein, forming a second contact structure comprises: forming a second contact hole in the stack structure, wherein the second contact hole extends along the first direction and includes a second end portion in contact with the gate layer; forming an initial third conductive layer in the second contact hole; removing a portion of the initial third conductive layer to form a third conductive layer and expose a portion of the second end portion; and forming a second dielectric fill in a remaining space of the second contact hole.

27. The method of claim 25, wherein, The method further includes: forming the first contact structure and the second contact structure in a same process.

28. A memory system, comprising: at least one semiconductor device as claimed in any one of claims 1-21; and a controller coupled to the semiconductor device and configured to control the semiconductor device to store data.

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