3D integrated short-channel IGZO thin film transistor based on multi-grid regulation and preparation method thereof

Abstract

The invention discloses a 3D integrated short-channel IGZO thin film transistor based on multi-grid regulation and control and a preparation method thereof, the transistor comprises a substrate, the substrate is at least provided with an IGZO active layer, a dielectric layer, a source electrode and a drain electrode, the IGZO active layer is provided with a grid stacking structure, the grid stacking structure comprises at least two grids, each grid is independently or cooperatively controlled, and the grid stacking structure is provided with at least one grid electrode. And a multi-state output mode is realized. According to the invention, a working mode that a plurality of grids independently or cooperatively regulate and control transistors is adopted, accurate multi-stage control of a channel electric field can be realized through independent or cooperative control of the grids, a short-channel effect is inhibited, the problems of performance deterioration of a short-channel device and the like are solved, monolithic integration of the device is realized, and the reliability of the device is improved. Compared with the prior art, the chip has the advantages that the overall integration level of the chip is improved, meanwhile, the performance of a traditional planar device is kept or even exceeded, great significance is achieved for storage and calculation application, a larger degree of freedom is provided for achieving a more complex neuromorphic calculation function, and the chip is suitable for a low-energy-consumption, high-density and more complex circuit system.

Description

TECHNICAL FIELD

[0001] The application relates to a monolithic 3D integrated short channel device for multi-level control of channel electric field, in particular to a 3D integrated short channel IGZO thin film transistor structure based on multi-gate regulation, and belongs to the technical field of semiconductor transistors. BACKGROUND

[0002] With the rapid development of information technology, integrated circuits continue to break through in size, performance and function, especially the demand for high integration, high performance and low power consumption devices is increasing. In the post-Moore era, the traditional two-dimensional device architecture faces challenges in physical limits and process complexity, which prompts people to actively explore new device structures and material systems. Three-dimensional integration technology, as a key way to improve chip integration and performance, not only effectively reduces chip area but also shortens interconnection length, thereby reducing power consumption and improving running speed, and has become a research hotspot in the semiconductor field.

[0003] Among many semiconductor materials, indium gallium zinc oxide (IGZO) thin film transistor (TFT) has become a key core component in the field of new generation display technology (such as OLED display screen) and flexible electronic devices due to its high electron mobility, low leakage current, high on-off ratio, and excellent uniformity and stability. The emergence of IGZO TFT has greatly promoted the development of high-performance, low-power display driving circuits. However, with the continuous reduction of device size, especially when the channel length enters the short channel region, IGZO TFT also faces a series of challenges.

[0004] The traditional planar IGZO TFT structure will exhibit obvious short channel effects when the channel length is shortened to microns or even sub-microns. These effects include threshold voltage drift, subthreshold swing (SS) deterioration, drain-induced barrier lowering (DIBL), and reduction of source-drain breakdown voltage. These short channel effects not only reduce the reliability and stability of the device, but also significantly increase the static power consumption, thereby limiting the further application of IGZO TFT in high-performance integrated circuits. To cope with short channel effects, the existing technology mainly adopts the following strategies:

[0005] 1. Channel engineering

[0006] By optimizing the composition, thickness or doping of the channel material, the carrier transport characteristics are improved and the short channel effect is suppressed. However, this method is often limited by the physical properties of the material itself, and the process window is narrow.

[0007] 2. Insulation layer thickness optimization

[0008] Reducing the thickness of the gate insulation layer can enhance the control ability of the gate on the channel, thereby suppressing the short channel effect. However, an excessively thin insulation layer will increase the gate leakage current, reduce the reliability of the device, and require higher process precision.

[0009] 3. Device structure innovation

[0010] For example, by using a dual-gate (DG) or gate-all-around (GAA) structure, the short channel effect can be effectively suppressed by increasing the electrostatic control ability of the gate on the channel. Although these structures improve the performance of the device to some extent, the manufacturing process is complex, the cost is high, and additional challenges are faced in three-dimensional integration, such as how to efficiently and accurately control multiple gates independently or cooperatively to further optimize device performance and reduce power consumption, which is still a problem to be solved.

[0011] In addition, although three-dimensional integration technology provides broad prospects for improving integration, how to effectively combine high-performance IGZO TFT with three-dimensional integration technology while overcoming the challenges brought by the short channel effect is still a key and difficult point of current research. In particular, in a three-dimensional stacked structure, the performance optimization and energy management of a single TFT device become particularly critical, as local thermal effects and interlayer crosstalk can further exacerbate device performance degradation.

[0012] In the prior art, the three-dimensional integration multi-gate regulation technology for IGZO TFT is still in its early stages of development. How to achieve accurate control of short channel devices, effectively suppress leakage current and reduce power consumption while ensuring high integration is a key technical problem to be solved. There is a lack of a solution that has high integration, a relatively simple preparation process, and can effectively utilize the advantages of multi-gate regulation to optimize the performance of short channel IGZO TFT. SUMMARY

[0013] To overcome the short channel effect, single gate control mode, and low device integration of the prior art, the present application provides a 3D integrated short channel IGZO thin film transistor based on multi-gate regulation, which realizes accurate multi-level control of the channel electric field by independently or cooperatively biasing the four gates, providing greater freedom for more complex neuromorphic computing functions.

[0014] The 3D integrated short channel IGZO thin film transistor based on multi-gate regulation of the present application adopts the following technical solutions.

[0015] The transistor comprises a substrate, at least an IGZO active layer, a dielectric layer, a source electrode and a drain electrode are arranged on the substrate, the distance between the source electrode and the drain electrode is a channel length, a gate stack structure is arranged on the IGZO active layer, the gate stack structure comprises at least two gates, each gate is independently or cooperatively controlled, and different potential voltages are written to the gates to realize a multi-state output mode.

[0016] Further limitations are described below.

[0017] The substrate is SiO2, the dielectric layer is Al2O3, and the materials of the source electrode, the drain electrode and the gate electrode include but are not limited to TiN, ITO, W and Mo.

[0018] The thickness of the substrate is 100 nm, the thickness of the dielectric layer is 20 nm, the thickness of the source electrode and the drain electrode is 30 nm, the thickness of the gate electrode is 10 nm, the channel length is 90 nm, and the channel width is 20 nm.

[0019] The elements in the IGZO active layer are in any ratio, and the preferred ratio is In:Ga:Zn=1:1:1.

[0020] The gate stack structure is a vertical gate stack structure, at least two gates are stacked in the vertical direction (Z axis), and a barrier layer is arranged below each gate; specifically, the source electrode is arranged on the substrate, at least two gates are arranged on the source electrode, a dielectric layer is arranged in the barrier layer and the gate, an IGZO active layer is arranged in the dielectric layer, a vertical barrier layer is arranged in the IGZO active layer, and the drain electrode is arranged above the dielectric layer, the IGZO active layer and the vertical barrier layer. The barrier layer and the vertical barrier layer are SiO2.

[0021] The preparation method of the above-mentioned vertical gate stack structure comprises the following steps:

[0022] (1) patterning the source electrode on the substrate and peeling off;

[0023] (2) making the barrier layer and the gate on the source electrode, repeating at least twice to make at least two alternating barrier layers and gates;

[0024] (3) etching a through hole in each barrier layer and gate, and the depth of the through hole is the total thickness of each barrier layer and gate;

[0025] (4) growing a dielectric layer in the through hole etched in the barrier layer and the gate;

[0026] (5) etching a through hole in the dielectric layer;

[0027] (6) growing an IGZO active layer in the through hole etched in the dielectric layer;

[0028] (7) etching a through hole in the IGZO active layer;

[0029] (8) Growth of vertical blocking layer in etched via of IGZO active layer;

[0030] (9) Fabrication of drain on dielectric layer, IGZO active layer and vertical blocking layer.

[0031] The above blocking layer, dielectric layer and IGZO active layer are fabricated by using existing atomic layer deposition technology, with nanometer-level precision of thin film thickness control and excellent step coverage. Etched via uses existing dry etching technology. Source, drain and gate are fabricated by using existing magnetron sputtering technology.

[0032] The gate stack structure can also be a planar gate integrated structure, which is spaced apart at least two gates in the plane (XY plane), specifically, an IGZO active layer is arranged on the substrate, a dielectric layer is arranged on the IGZO active layer, a source and a drain are arranged in the dielectric layer, and horizontally spaced apart gates are arranged on the dielectric layer.

[0033] The preparation method of the above planar gate integrated structure includes the following steps:

[0034] (1) Fabrication of IGZO active layer on SiO2 substrate;

[0035] (2) Fabrication of dielectric layer on IGZO active layer;

[0036] (3) Fabrication of at least two gates on dielectric layer;

[0037] (4) Etching of source via and drain via on dielectric layer;

[0038] (5) Fabrication of source and drain in source via and drain via, respectively.

[0039] The above IGZO active layer and dielectric layer are fabricated by using existing atomic layer deposition technology. Etched via uses existing dry etching technology. Source, drain and gate are fabricated by using existing magnetron sputtering technology.

[0040] The gate is written, defining V G V TH as write 1, V G < V TH as write 0; the source is grounded, and the drain voltage is 3.3 V. Among them, V G is the voltage applied to the gate, and V TH is the minimum voltage required for the device to turn on, i.e. threshold voltage.

[0041] The multi-state output mode determines the number of output modes according to the 0 / 1 working state of the gate write, if the number of gates is n, n 2, the number of output modes is n+1, including full writing 0 in each gate, writing one bit 1, writing two bits 1, writing three bits 1, and writing n bits 1;

[0042] The 0 / 1 working state of the gate writing is V G When Vg is 1, the voltage applied is 3.3 V, V G When Vg is 0, the voltage applied is -1 V; V TH When Vg is 0.1 V.

[0043] In one aspect of the application, the device size is nanoscale, and the transistor structure includes a substrate, a gate, a dielectric layer, an IGZO active layer, a barrier layer, a source and a drain.

[0044] The self-limiting reaction mechanism of the atomic layer deposition technology can realize precise nanoscale thickness control and excellent step coverage. The atomic layer deposition technology is used to grow the dielectric layer, the IGZO active layer and the barrier layer, which can not only realize uniform film quality but also control the device size to be nanoscale. The channel width of the device is the thickness of the IGZO active layer (20 nm), and the channel length of the device is the growth depth of the IGZO active layer in the etched via (90 nm). The preparation of the short channel device with simple process is realized.

[0045] In the second aspect of the application, the working mode is to change the electron concentration of the IGZO active layer by independently or cooperatively controlling the electric field between the gate and the source through the four gates.

[0046] In the third aspect of the application, the vertical gate stack structure and the planar gate integrated structure are both composed of a common source, a common drain and four gates. Each gate and source-drain can be regarded as an independent device. The structure is equivalent to vertically or horizontally integrating four devices, realizing the monolithic integrated mode of the device.

[0047] The application provides a new monolithic 3D integrated short channel device structure. The four gates can be independently or cooperatively biased to realize precise multi-level control of the channel electric field, provide greater freedom for realizing more complex neuromorphic computing functions, and be suitable for low-energy-consumption high-density more complex circuit systems. Compared with the prior art, the application has the following beneficial effects:

[0048] (1) The application adopts four gate electrodes to independently or cooperatively regulate the working mode of the transistor, and through writing different potential voltages to the gate electrodes, the output mode of multiple states can be realized, the writing state can be up to 16, and the output current state is 5; through applying differential control voltages to multiple independent gate electrodes, the multiple modulation of the channel carrier transport behavior is realized, the multi-level current state beyond the traditional dual-state (linear / saturated) output is generated, and the circuit logic expression ability and analog signal processing potential are significantly enhanced;

[0049] (2) The application greatly enhances the modulation ability of the gate electrode to the channel carrier by increasing the number of gate electrodes; this multi-dimensional electric field control can more effectively limit the modulation of the channel potential barrier by the drain electric field, reduce the DIBL effect, and improve the control efficiency of the gate to the channel, reduce the SS value, so that the device can still maintain excellent switching characteristics and stability under short channel conditions; in addition, the enhanced gate control is also helpful to improve the long-term reliability of the device, such as the stability under bias stress, which is crucial for the stable operation of high-integration circuits;

[0050] (3) The multi-gate regulation structure of the application can realize more precise control of the channel electric field by independently or cooperatively biasing multiple gate electrodes, so as to accurately set and adjust the threshold voltage in a wider range, and this flexibility enables the application to adapt to the specific requirements of V TH for different circuit applications, simplifies the circuit design, and has the potential to realize dynamic V TH adjustment of the device under different working modes, thereby optimizing power consumption and performance;

[0051] (4) The 3D integrated short channel IGZO thin film transistor structure based on multi-gate regulation proposed by the application can perfectly meet the needs of 3D integrated architecture. The application not only realizes high-density vertical integration, but also enhances the gate control ability through the synergistic effect of multiple gates, avoiding the performance degradation problem of traditional planar devices in the scaling process. This structure enables IGZO TFTs to be integrated into multi-layer circuits in a more compact form, significantly improving the overall integration of chips, while maintaining or even surpassing the performance of traditional planar devices, which is of great significance for storage and computing applications. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 The structure diagram of the IGZO transistor provided by the application is a vertical gate stack structure;

[0053] Figure 2 The structure diagram of the IGZO transistor provided by the application is a planar gate integrated structure;

[0054] Figure 3The equivalent circuit diagram of an IGZO transistor with a vertical gate stack structure;

[0055] Figure 4 The equivalent circuit diagram of an IGZO transistor with a planar gate integrated structure;

[0056] Figure 5 The simulation results of the output curve of the IGZO transistor with a vertical gate stack structure are shown in the figure.

[0057] Figure 6 The simulation results of the transfer curve of the IGZO transistor with a vertical gate stack structure are shown in the figure.

[0058] In the diagram: 1. Source, 2. Barrier layer, 3. Gate, 4. Dielectric layer, 5. Drain, 6. IGZO active layer, 7. Vertical barrier layer. Detailed Implementation

[0059] Example 1

[0060] This embodiment discloses an IGZO transistor with a vertical gate stacked structure having four gates, such as... Figure 1 As shown, the transistor includes a substrate 8, a source 1, a barrier layer 2, a gate 3, a dielectric layer 4, a drain 5, an IGZO active layer 6, and a vertical barrier layer 7. The source 1 is disposed on the substrate 8. Barrier layers 2 and gate 3 are alternately disposed on the source 1, with four barriers 2 and four gates 3 arranged alternately vertically. The dielectric layer 4 is disposed within the barrier layers 2 and 3, penetrating each barrier layer 2 and gate 3. The IGZO active layer 6 is disposed within the dielectric layer 4, and the vertical barrier layer 7 is disposed within the IGZO active layer 6. The drain 5 is disposed above the dielectric layer 4, the IGZO active layer 6, and the vertical barrier layer 7. The substrate 8 is a SiO2 substrate, the source 1 is TiN, the barrier layer 2 is a SiO2 barrier layer, the gate 3 is TiN, the dielectric layer 4 is Al2O3, the vertical barrier layer 7 is SiO2, and the drain 5 is TiN. The distance between the source 1 and the drain 5 (90 nm) is the channel length of the transistor. The thickness (20nm) of the IGZO active layer 6 is equal to the channel width.

[0061] The fabrication method of the above-mentioned vertical gate stacked IGZO transistor includes the following steps.

[0062] (1) A patterned source electrode is fabricated on substrate 8 and then stripped off; the specific process is as follows:

[0063] Spin the positive glue on the SiO2 substrate 8 with a thickness of 100 nm, first rotate at a speed of 500 rpm for 5 s, then rotate at a speed of 3000 rpm for 60 s, dry at 110°C for 60 s, expose for 4.8 s, soak in the developing solution for 40 s, take out and rinse with deionized water, and then dry with a nitrogen gun; magnetron sputtering 30 nm TiN source electrode 1, power 90 W, gas Ar, flow rate 4 sccm; acetone peeling of excess TiN, ethanol cleaning, and drying.

[0064] (2) Make the upper and lower alternating arrangement of the barrier layer 2 and the gate 3 on the source 1; the specific process is:

[0065] Depositing a thickness of 10 nm SiO2 barrier layer 2 on the source 1 by atomic layer deposition technology, using H2O and SiH4 as precursors, and the reaction temperature is 200°C; then growing a thickness of 10 nm TiN gate 3 on the barrier layer 2 by magnetron sputtering, the specific growth conditions are the same as those in step (1) (power 90 W, gas Ar, flow rate 4 sccm; acetone peeling of excess TiN, ethanol cleaning, and drying);

[0066] Repeat the above four preparation processes of SiO2 barrier layer 2 and TiN gate 3 to obtain the upper and lower alternating arrangement structure of SiO2 barrier layer 2 and TiN gate 3, from bottom to top, it is 10 nm SiO2, 10 nm TiN, 10 nm SiO2, 10 nm TiN, 10 nm SiO2, 10 nm TiN, 10 nm SiO2 and 10 nm TiN.

[0067] (3) Etch a through hole in the four barrier layers 2 and gates 3, the cross section of the through hole is 100x100 nm, and the depth of the through hole is the total thickness of the four barrier layers 2 and the four gates 3, which is 80 nm; the specific process is:

[0068] First, define the size of the through hole to be etched (cross section 100x100 nm) by photolithography, then use CHF3 / O2 mixed gas to etch the SiO2 barrier layer 2 by dry etching, CHF3 flow rate 35 sccm, O2 flow rate 15 sccm, ICP power 100 W; use BCl3 / Ar mixed gas to etch the TiN gate 3 by dry etching, BCl3 flow rate 20 sccm, Ar flow rate 5 sccm, ICP power 300 W.

[0069] (4) Grow a thickness of 90 nm Al2O3 dielectric layer 4 in the etched through hole (10 nm higher than the depth of the through hole); the specific process is:

[0070] Al2O3 with thickness of 90 nm is grown in the via etched in step (3) as the dielectric layer 4 using atomic layer deposition technology, and H2O and TMA (trimethylaluminum) are used as precursors, and the reaction temperature is 200 °C.

[0071] (5) A via is etched in the Al2O3 dielectric layer 4, the cross-sectional size of the via is 60x60 nm, and the depth is 90 nm; the specific process is as follows:

[0072] First, the size of the via to be etched (the cross-section is 60x60 nm) is defined by photolithography, and then BCl3 is used for dry etching of Al2O3, the flow rate of BCl3 is 20 sccm, and the ICP power is 100 W.

[0073] (6) IGZO active layer 6 with thickness of 90 nm is grown in the via etched in the Al2O3 dielectric layer 4, and the element ratio in the IGZO active layer 6 is In:Ga:Zn = 1:1:1; the specific process is as follows:

[0074] IGZO active layer with thickness of 90 nm is grown in the via etched in step (5) using atomic layer deposition technology, and H2O and INTI (alkyl indium), TMGa (trimethyl gallium) and DEZ (diethyl zinc) are used as precursors, and the reaction temperature is 200 °C.

[0075] (7) A via is etched in the IGZO active layer 6, the cross-sectional size of the via is 20x20 nm, and the depth of the via is 90 nm; the specific process is as follows:

[0076] First, the size of the via to be etched (20x20 nm) is defined by photolithography, and then CH4 and H2 are used for dry etching of IGZO, the flow rate of CH4 is 30 sccm, the flow rate of H2 is 15 sccm, and the ICP power is 200 W.

[0077] (8) SiO2 vertical barrier layer 7 with thickness of 90 nm is grown in the via etched in the IGZO active layer 6, and the specific process is as follows:

[0078] SiO2 vertical barrier layer 7 with thickness of 90 nm is grown in the via etched in step (7) using atomic layer deposition technology, and the specific growth conditions of SiO2 are the same as those in step (1).

[0079] (9) A drain 5 is prepared on the Al2O3 dielectric layer 4, the IGZO active layer 6 and the SiO2 vertical barrier layer 7, the size of the drain 5 is equal to the cross-sectional size of the Al2O3 dielectric layer 4, which is 100x100 nm, and the drain 5 is peeled off; the specific process is as follows:

[0080] First, the size of the drain 5 (the cross-section is 100x100 nm) is defined by photolithography; 30 nm of TiN is magnetron sputtered as the drain 5, and the specific growth conditions are the same as those in step (1).

[0081] Figure 3 The equivalent circuit of the IGZO transistor of the vertical gate stack structure prepared in Embodiment 1 is given, wherein the Source end is always grounded, the Drain end is applied with a constant voltage of 3.3 V, and Gate1, Gate2, Gate3 and Gate4 are written with different voltages to control the output end current.

[0082] It should be noted that the minimum voltage required for the transistor to turn on when the device has only one gate in the present application is defined as the threshold voltage V TH , and the simulation result is V TH =0.1 V; therefore, when V G >V TH , it is written as 1, and when V G <V TH , it is written as 0; specifically, when V G is written as 1, the voltage applied to the Gate end is 3.3 V, and when V G is written as 0, the voltage applied to the Gate end is -1 V.

[0083] Further, according to the different write voltages, the working modes can be divided into five kinds, and the specific operations are as follows:

[0084] (1) Working mode 1: all four gates are written as 0 (0000), and the voltages applied to Gate1, Gate2, Gate3 and Gate4 are all -1 V; at this time, the gate electric field depletes the electrons in the IGZO active layer, and the device is in the off state, and the current is the weakest, and the output current is recorded as I D1 .

[0085] (2) Working mode 2: four gates are written as one bit 1 (1000 / 0100 / 0010 / 0001), Gate1 is applied with a voltage of 3.3 V, and Gate2, Gate3 and Gate4 are applied with a voltage of -1 V; at this time, one gate has a positive electric field acting on the IGZO active layer, and the electron concentration of the IGZO active layer begins to increase, and the conductivity is enhanced, and the output current is recorded as I D2 .

[0086] It should be noted that working mode 2 only introduces the specific operation of one voltage, and the other three voltage operations are not described again, and it is assumed that the output currents of the four voltage operations of working mode 2 are the same;

[0087] (3) Working mode 3: 4 gates write two bits 1 (1100 / 1010 / 1001 / 0110 / 0101 / 0011), Gate1, Gate2 apply 3.3V voltage, Gate3, Gate4 apply -1V voltage; at this time, two gate positive electric fields act on the IGZO active layer, the electron concentration of the IGZO active layer increases, the conductivity is enhanced, and the output current is recorded as I D3 .

[0088] It should be noted that working mode 3 only introduces a specific operation of one voltage, and the other five voltage operations are not described again, and it is assumed that the output currents of the six voltage operations of working mode 3 are the same.

[0089] (4) Working mode 4: 4 gates write three bits 1 (1110 / 1011 / 1101 / 0111), Gate1, Gate2, Gate3 apply 3.3V voltage, Gate4 applies -1V voltage; at this time, three gate electric fields act on the IGZO active layer, the electron concentration of the IGZO active layer continues to increase, and the conductivity continues to increase, and the output current is recorded as I D4 .

[0090] It should be noted that working mode 4 only introduces a specific operation of one voltage, and the other three voltage operations are not described again, and it is assumed that the output currents of the four voltage operations of working mode 4 are the same.

[0091] (5) Working mode 5: 4 gates write 1 (1111), Gate1, Gate2, Gate3, Gate4 apply 3.3V voltage; at this time, the control ability of the gate to the IGZO active layer reaches the strongest, the electron concentration of the IGZO active layer is the largest, and the conductivity is the strongest, and the output current is recorded as I D5 .

[0092] The output mode results of the above five working modes are shown in Figure 5 and Figure 6 . Figure 5 and Figure 6 are the simulation results of the vertical gate stack structure, and the specific parameters of the simulation program to build the structure are the same as the above structure. It should be noted that since the device works in working mode 1 in the off state, its output current I D1 is always in the off state of 10 -12 A, and therefore is not shown in Figure 5 and Figure 6 . Specifically, the output characteristic curves of the vertical gate stack structure in working mode 2, working mode 3, working mode 4 and working mode 5 are shown in Figure 5 , and the transfer characteristic curves are shown in Figure 6 ; as the number of gate voltages applied 3.3V increases, the output current ID always increases.

[0093] The following Table 1 shows the IGZO transistor electrical performance calculation results of the vertical gate stack structure.

[0094] Table 1 IGZO transistor electrical performance calculation results of the vertical gate stack structure

[0095] As shown in Table 1, from working mode 2 to working mode 5, the I D increases by about 13 times, and the mobility increases by about 8 times, further confirming that as the control ability of the gate increases, the electron concentration of the IGZO active layer increases, and the channel conductivity becomes stronger;

[0096] As shown in Table 1, from working mode 2 to working mode 5, the subthreshold swing SS of the device always decreases, and the current on-off ratio always increases, further confirming that as the number of gates increases, the suppression ability of the short channel effect will be further improved, and the DIBL effect will be significantly reduced, and the SS value will be closer to the theoretical limit (about 60 mV / decade at room temperature), thereby realizing a more steep subthreshold slope and a larger on-off ratio.

[0097] Embodiment 2

[0098] This embodiment discloses an IGZO transistor of a planar gate integrated structure, which has a structure as shown in Figure 2 The IGZO transistor of the planar gate integrated structure includes a substrate 8, an IGZO active layer 6, a dielectric layer 4, a source 1, a drain (source-drain electrode) 5, and a gate 3. The IGZO active layer 6 is arranged on the substrate 8, the dielectric layer 4 is arranged on the IGZO active layer 6, the source 1 and the drain 5 are arranged in the dielectric layer 4 and reach the IGZO active layer 6, four gates 3 are arranged on the dielectric layer 4 with a horizontal interval of 10 nm, and the four gates 3 are between the source 1 and the drain 5. The substrate 8 is a SiO2 substrate, the dielectric layer 4 is an Al2O3 dielectric layer, and the drain 5 is TiN. The distance (90 nm) between the source 1 and the drain 5 is the channel length of the transistor. The thickness (20 nm) of the IGZO active layer 6 is the channel width.

[0099] The preparation method of the above-mentioned planar gate integrated structure IGZO transistor includes the following steps.

[0100] (1) Fabricating the IGZO active layer 6 on the substrate 8

[0101] An IGZO active layer 6 with a thickness of 20 nm is grown on a SiO2 substrate 8 with a thickness of 100 nm using atomic layer deposition technology. The precursors use H2O and INTI (alkyl indium), TMGa (trimethyl gallium), and DEZ (diethyl zinc), and the reaction temperature is 200°C.

[0102] (2) Fabricating the dielectric layer 4 on the IGZO active layer 6

[0103] An Al2O3 dielectric layer 4 with a thickness of 20 nm is grown using an atomic layer deposition technique, the precursors being H2O and TMA (trimethylaluminum), and the reaction temperature being 200 °C; the positions of the IGZO / Al2O3 are defined by photolithography, and the IGZO / Al2O3 is etched to obtain discrete devices, the etching conditions being the same as those in steps (5) and (7) in Example 1.

[0104] (3) Preparing 4 gates 3 on the dielectric layer 4

[0105] The positions of the 4 gates 3 are defined by photolithography, and TiN with a thickness of 20 nm is magnetron sputtered, the specific growth conditions being the same as those in step (1) in Example 1, and the adjacent gates are spaced apart by 10 nm.

[0106] (4) Etching source and drain through-holes on the dielectric layer 4

[0107] The source and drain positions are defined by photolithography, and the Al2O3 dielectric layer 4 is etched, the etching conditions being the same as those in step (5) in Example 1. The distance between the source and drain through-holes is 90 nm.

[0108] (5) Preparing a source 1 and a drain 5 in the source and drain through-holes etched on the dielectric layer 4

[0109] TiN source 1 with a thickness of 30 nm and TiN drain 5 with a thickness of 30 nm are magnetron sputtered in the source and drain through-holes etched on the dielectric layer 4 in step (4), the distance between the source 1 and the drain 2 being 90 nm, and the specific growth conditions being the same as those in step (1) in Example 1, and the source 1 and the drain 2 are peeled off.

[0110] Figure 4 An equivalent circuit diagram of the planar gate integrated structure IGZO transistor prepared in this example is given,

[0111] Since the planar gate integrated structure IGZO transistor in this example has the same working principle and specific working mode as the vertical gate stacked structure IGZO transistor in Example 1, the simulation results of Example 2 are not shown.

Claims

1. A 3D integrated short channel IGZO thin film transistor based on multi-gate regulation, characterized in that, The application relates to a multi-gate IGZO active layer, which comprises a substrate, at least an IGZO active layer, a dielectric layer, a source electrode and a drain electrode on the substrate, and a gate stack structure on the IGZO active layer.

2. The 3D integrated short channel IGZO thin film transistor based on multi-gate regulation of claim 1, wherein, The substrate is SiO2, the dielectric layer is Al2O3, and the materials of the source electrode, the drain electrode and the gate electrode include but are not limited to TiN, ITO, W and Mo.

3. The multi-gate regulated 3D integrated short channel IGZO thin film transistor according to claim 1, wherein, The thickness of the substrate is 100 nm, the thickness of the dielectric layer is 20 nm, the thickness of the source electrode and the drain electrode is 30 nm, the thickness of the gate electrode is 10 nm, the channel length is 90 nm, and the channel width is 20 nm.

4. The multi-gate regulated 3D integrated short channel IGZO thin film transistor according to claim 1, wherein, The elements in the IGZO active layer are in any ratio.

5. The multi-gate regulated 3D integrated short channel IGZO thin film transistor according to claim 1, characterized in that, The gate stack structure is a vertical gate stack structure, at least two gates are stacked in the vertical direction, and a barrier layer is arranged below each gate. Specifically, the source electrode is arranged on the substrate, at least two alternating barrier layers and gate electrodes are arranged on the source electrode, a dielectric layer is arranged in the barrier layers and the gate electrodes, an IGZO active layer is arranged in the dielectric layer, a vertical barrier layer is arranged in the IGZO active layer, and a drain electrode is arranged above the dielectric layer, the IGZO active layer and the vertical barrier layer.

6. The method for preparing the 3D integrated short channel IGZO thin film transistor based on multi-gate regulation according to claim 5, characterized in that, The method comprises the following steps: (1) patterning the source electrode on the substrate and stripping; (2) etching a through hole in each of the barrier layers and the gate electrodes, and the depth of the through hole is the total thickness of the barrier layers and the gate electrodes; (3) growing the dielectric layer in the through hole etched in the barrier layers and the gate electrodes; (4) etching a through hole in the dielectric layer; (5) growing the IGZO active layer in the through hole etched in the dielectric layer; (6) etching a through hole in the IGZO active layer; (7) growing the vertical barrier layer in the through hole etched in the IGZO active layer; (8) preparing the drain electrode on the dielectric layer, the IGZO active layer and the vertical barrier layer. The gate stack structure can also be a planar gate integrated structure, at least two gates are distributed in the plane, specifically, the IGZO active layer is arranged on the substrate, the dielectric layer is arranged on the IGZO active layer, the source electrode and the drain electrode are arranged in the dielectric layer, and the gate electrodes are arranged in the dielectric layer in a horizontal interval.

7. The multi-gate regulated 3D integrated short channel IGZO thin film transistor according to claim 1, wherein, The method comprises the following steps:

8. A method for fabricating a 3D integrated short-channel IGZO thin-film transistor based on multi-gate control as described in claim 7, characterized in that, (1) preparing the IGZO active layer on the SiO2 substrate; (2) preparing the dielectric layer on the IGZO active layer; (3) preparing at least two gate electrodes on the dielectric layer; (4) etching a source electrode through hole and a drain electrode through hole on the dielectric layer; (5) preparing the source electrode and the drain electrode in the source electrode through hole and the drain electrode through hole respectively. ​ 9. The multi-gate regulated 3D integrated short channel IGZO thin film transistor according to claim 1, wherein, The gate write, defining V G V TH For write 1, V G V TH For write 0; source grounded, drain voltage 3.3 V; where V G is the voltage applied to the gate, V TH is the minimum voltage required for the device to turn on, i.e. the threshold voltage.

10. The multi-gate regulated 3D integrated short channel IGZO thin film transistor according to claim 1, wherein, The multi-state output mode determines the number of output modes according to the 0 / 1 working state of the gate writing, if the number of gates is n, n 2, the number of output modes is n+1, including all writing 0 in each gate, writing one bit 1, writing two bits 1, writing three bits 1, …, writing n bits 1; The 0 / 1 working state of the gate write is V G 1, the voltage applied is 3.3 V, V G 0, the voltage applied is -1 V; V TH 0.1 V; where V G is the voltage applied to the gate, V TH is the minimum voltage required for the device to turn on, i.e., the threshold voltage.

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