Semiconductor device

Abstract

A semiconductor device includes: an active pattern extending on a substrate in a first direction; a channel pattern vertically stacked on the active pattern; a separation structure extending in the second direction and separating each of the active pattern and the channel pattern into a first portion and a second portion; a gate structure extending in a second direction and onto a first portion of the channel pattern; a separation pattern extending in a first direction, separating a first portion of the channel pattern into a first channel pattern and a second channel pattern, and separating the gate structure into a first gate structure and a second gate structure; and a third gate structure extending in the second direction and onto the second portion of the channel pattern. The second portion of the channel pattern has a width greater than a sum of the first width and the second width of the first channel pattern and the second channel pattern, respectively.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0095586, filed July 19, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present inventive concepts relate to semiconductor devices. BACKGROUND

[0003] As the demand for high performance, high speed, and / or multi-functionality of semiconductor devices increases, the degree of integration of semiconductor devices has been increasing. According to the high degree of integration of semiconductor devices, the semiconductor devices can have reduced or degraded operating characteristics. Accordingly, various methods of forming semiconductor devices having excellent performance while overcoming limitations caused by the high degree of integration of semiconductor devices have been studied. For example, to overcome limitations on operating characteristics caused by scaling, semiconductor devices having a three-dimensional channel structure have been developed. SUMMARY

[0004] One aspect of the present inventive concepts provides a semiconductor device having a high degree of integration and improved electrical characteristics.

[0005] According to one aspect of the inventive concept, a semiconductor device includes: first and second units in first and second rows, respectively, wherein the first and second rows extend in a first direction and the first and second rows are adjacent to each other in a second direction that intersects the first direction; a merge unit extending in the second direction across the first and second rows, wherein the merge unit is adjacent to the first and second units in the first direction; a separation pattern extending in the first direction at a boundary between the first and second units, the separation pattern having first and second side surfaces facing the first and second units, respectively; and at least one separation structure extending in the second direction between the first and second units and the merge unit. The first unit includes first active patterns extending in the first direction along the first side surface of the separation pattern, first channel patterns adjacent to the first side surface of the separation pattern, the first channel patterns stacked on the first active patterns and spaced apart from each other in a third direction that is perpendicular to the first and second directions, first gate structures extending in the second direction and on the first channel patterns, and first source / drain patterns connected to opposite sides of the first channel patterns in the first direction, respectively. The second unit includes second active patterns extending in the first direction along the second side surface of the separation pattern, second channel patterns adjacent to the second side surface of the separation pattern, the second channel patterns stacked on the second active patterns and spaced apart from each other in the third direction, second gate structures separated from the first gate structures by the separation pattern, the second gate structures extending in the second direction and on the second channel patterns, and second source / drain patterns connected to opposite sides of the second channel patterns in the first direction, respectively. The merge unit includes third active patterns separated from the first and second active patterns by the separation structure, the third active patterns extending in the first direction, third channel patterns stacked on the third active patterns and spaced apart from each other in the third direction, third gate structures extending in the second direction and on the third channel patterns, and third source / drain patterns connected to opposite sides of the third channel patterns in the first direction, respectively.

[0006] According to another aspect of the inventive concepts, a semiconductor device includes: first and second units in first and second rows, respectively, wherein the first and second rows extend in a first direction and the first and second rows are adjacent to each other in a second direction that intersects the first direction; a merge unit extending in the second direction across the first and second rows, wherein the merge unit is adjacent to the first and second units in the first direction; and a separation pattern extending in the first direction at a boundary between the first and second units, the separation pattern having first and second side surfaces facing the first and second units, respectively. The first unit includes first active and channel patterns, the first active pattern extending in the first direction along the first side surface of the separation pattern, the first channel pattern being adjacent to the first side surface of the separation pattern, the first channel pattern being stacked on the first active pattern and spaced apart from each other in a third direction that is perpendicular to the first and second directions. The second unit includes second active and channel patterns, the second active pattern extending in the first direction along the second side surface of the separation pattern, the second channel pattern being adjacent to the second side surface of the separation pattern, the second channel pattern being stacked on the second active pattern and spaced apart from each other in the third direction. The merge unit includes third active and channel patterns, the third active pattern overlying at least a portion of each of the first and second active patterns in the first direction, the third active pattern extending in the first direction, the third channel pattern being stacked on the third active pattern and spaced apart from each other in the third direction. A width of the third active pattern in the second direction is greater than a sum of respective widths of the first and second active patterns in the second direction.

[0007] According to another aspect of the inventive concepts, a semiconductor device includes: an active pattern extending on a substrate in a first direction; a separation structure extending in a second direction that intersects the first direction; channel patterns stacked on the active pattern and spaced apart from each other in a third direction that is perpendicular to the first and second directions, wherein the separation structure separates each of the active and channel patterns into first and second portions; a gate structure extending in the second direction and onto the first portion of the channel pattern; a separation pattern extending in the first direction, wherein the separation pattern separates the first portion of the channel pattern into first and second channel patterns and separates the gate structure into first and second gate structures; and a third gate structure extending in the second direction and onto the second portion of the channel pattern. The second portion of the channel pattern has a width in the second direction that is greater than a sum of first and second widths of the first and second channel patterns, respectively, in the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other aspects, features, and advantages of the inventive concepts will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] FIG. 1 is a plan view of a semiconductor device according to an example embodiment of the inventive concept.

[0010] FIG. 2A and FIG. 2B are cross-sectional views of the semiconductor device shown in FIG. 1 is a cross-sectional view of the semiconductor device shown in

[0011] FIG. 3A and FIG. 3B are cross-sectional views of the semiconductor device shown in FIG. 1 is a cross-sectional view of the semiconductor device shown in

[0012] FIG. 4A and FIG. 4B are cross-sectional views of the semiconductor device shown in FIG. 1 is a cross-sectional view of the semiconductor device shown in

[0013] FIG. 5 is a plan view of a semiconductor device according to an example embodiment of the inventive concept.

[0014] FIG. 6A and FIG. 6B are cross-sectional views of the semiconductor device shown in FIG. 5 is a cross-sectional view of the semiconductor device shown in

[0015] FIG. 7 is a plan view of a semiconductor device according to an example embodiment of the inventive concept.

[0016] FIG. 8A and FIG. 8B are cross-sectional views of the semiconductor device shown in FIG. 7 is a cross-sectional view of the semiconductor device shown in

[0017] FIG. 9 and FIG. 10 are plan views of semiconductor devices according to various example embodiments of the inventive concept. DETAILED DESCRIPTION

[0018] Hereinafter, various example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The terms "first", "second", and the like can be used herein to simply distinguish one component, layer, direction, etc. from another component, layer, direction, etc. When the terms "include" and / or "comprise" are used herein, it specifies the presence of stated elements but does not preclude the presence or addition of additional elements. The term "and / or" includes any and all combinations of one or more of the associated listed items. The term "connected" can be used herein to refer to physical and / or electrical connections. When a component or layer is referred to as "directly" on, or "directly contacting" or "directly connected" another component or layer, there are no intermediate components or layers present. Likewise, when components are "immediately" to one another, there can not be intermediate components present.

[0019] FIG. 1 is a plan view of a semiconductor device according to an example embodiment of the inventive concept. FIG. 2A and FIG. 2B are cross-sectional views of the semiconductor device shown in FIG. 1 FIG. 3A and FIG. 3B are cross-sectional views of the semiconductor device shown in FIG. 1 FIG. 4A and FIG. 4B are cross-sectional views of the semiconductor device shown in FIG. 1

[0020] Referring to FIG. 1 , a semiconductor device 100 according to the present example embodiment can include a first unit LC1, a second unit LC2, and a third unit LC3 disposed on a substrate 101. The first unit LC1 and the second unit LC2 can be disposed in first and second rows, respectively, extending along a first direction D1, the first and second rows being adjacent to each other and can be arranged parallel to each other in a second direction D2 intersecting the first direction D1. The third unit LC3 can be a merged unit adjacent to the first and second units LC1 and LC2 across the first and second rows. Here, the third unit LC3 can also be referred to as a merged unit.

[0021] ​​​Logic transistors included in the logic circuit can be provided in each of the first cell LC1 and the second cell LC2 and the merged cell LC3. The first cell LC1 and the second cell LC2 can include the same or different logic circuits, and the first cell LC1 and the second cell LC2 can also be referred to as a first logic cell and a second logic cell, respectively. In the present example embodiment, the first cell LC1 and the second cell LC2 can have a first cell height CH1 and a second cell height CH2, respectively, and the first cell height CH1 and the second cell height CH2 can be the same as or different from each other. The merged cell LC3 can have a cell height CH3 corresponding to a sum (CH1+CH2) of the first cell height and the second cell height. Here, the "cell height" can also be referred to as a width in the second direction.

[0022] The substrate 101 can include, for example, a semiconductor such as Si or Ge or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In another example, the substrate 101 can have a silicon-on-insulator (SOI) structure. The substrate 101 can include an active region 105, and can include, for example, a well doped with impurities of a certain conductivity type. A plurality of active patterns AP extending in a first direction (e.g., a direction of D1) can be provided on the active region 105, respectively, and each of the active patterns AP can have a protruding fin-type structure.

[0023] The isolation layer 110 can be provided on the substrate 101 to define the active region 105 including the active patterns AP. For example, the isolation layer 110 can include silicon oxide or a silicon oxide-based insulating material. In the present example embodiment, (see FIG. 3A and FIG. 3B ) the isolation layer 110 can be a first isolation layer 110a (also referred to as a deep trench isolation (DTI)) defining the active region 105 and a second isolation layer 110b (also referred to as a shallow trench isolation (STI)) defining the active patterns AP.

[0024] Referring to FIG. 1 , the active region 105 of the substrate 101 can be divided into a PMOSFET region PR and an NMOSFET region NR. Each of the first cell LC1 and the second cell LC2 can include the PMOSFET region PR and the NMOSFET region NR arranged in the second direction D2. The PMOSFET region PR and the NMOSFET region NR can be separated from each other by the first isolation layer 110a.

[0025] In the present example embodiment, the PMOSFET regions PR of the first and second cells LC1, LC2 can be disposed opposite each other and can be disposed as a single active region across the cell boundary. Optionally, in some example embodiments, the NMOSFET regions NR of the first and second cells LC1, LC2 can be disposed opposite each other.

[0026] The substrate 101 can include an isolation region IR between the first and second cells LC1, LC2 and the merged cell LC3. In the present example embodiment, the isolation region IR can be defined as the region between a first isolation structure DB1 and a second isolation structure DB2. The first isolation structure DB1 can be disposed adjacent to the first and second cells LC1, LC2 and the second isolation structure DB2 can be disposed adjacent to the merged cell LC3. The first and second isolation structures DB1, DB2 can extend in the second direction D2 in a similar manner to the gate structure GS and can be arranged in the first direction D1 with a pitch that is the same as the pitch of the gate structure GS.

[0027] The first and second isolation structures DB1, DB2 can be lower in the third direction D3 (also referred to as the vertical direction) relative to the lower ends of the source / drain patterns 120 (e.g., the first source / drain pattern 120A and the third source / drain pattern 120C) of the substrate 101. Unless otherwise indicated, spatially relative terms such as "above," "upper," "below," "lower," "sideward," "vertical," "horizontal," and the like can be used herein for ease of description to FIG. 2A refer to the orientation of the device as shown in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or operation, depending on the particular viewpoint. In the present example embodiment, the first and second isolation structures DB1, DB2 can extend in the third direction D3 to a depth that is lower than the depth of the lower ends of the active patterns AP. The active patterns that extend across other cells in the first direction D1 can be separated by the first and second isolation structures DB1, DB2 into the active patterns API, AP2, AP4, and AP5 of the first and second cells LC1, LC2 and the active patterns AP3, AP6, and AP7 of the merged cell LC3. The first and second isolation structures DB1, DB2 can extend in the second direction D2 to cross the first and second active patterns API, AP2 and the third active pattern AP3, to cross the fourth and sixth active patterns AP4, AP6, and to cross the fifth and seventh active patterns AP5, AP7.

[0028] In the present example embodiment, the epitaxial pattern 120' can be disposed on the active pattern between the first separation structure DB1 and the second separation structure DB2. The gate spacers 141 can be disposed on the upper sidewalls of each of the first separation structure DB1 and the second separation structure DB2. The lower surfaces of the first separation structure DB1 and the second separation structure DB2 can be located at a higher level than the lower surface of the isolation layer 110 with respect to the substrate 101. The term "level" can be used herein to mean a distance (e.g., in the vertical direction D3) from a reference surface or element (e.g., the substrate 101). In some example embodiments, the lower surfaces of the first separation structure DB1 and the second separation structure DB2 can be located at a lower level than the lower surface of the second isolation layer 101b with respect to the substrate 101. The upper surfaces of the first separation structure DB1 and the second separation structure DB2 can be coplanar with the upper surface of the gate cap layer 147 and the upper surfaces of the gate spacers 141. The first separation structure DB1 and the second separation structure DB2 can comprise a material different from that of the isolation layer 110. For example, the first separation structure DB1 and the second separation structure DB2 can comprise silicon nitride.

[0029] As described above, the plurality of active patterns AP can extend in the first direction D1 on the substrate 101, and can be portions of the substrate 101 that protrude in the third direction D3.

[0030] The first cell LC1 can have the first active pattern AP1 and the fourth active pattern AP4, and the second cell LC2 can have the second active pattern AP2 and the fifth active pattern AP5. The first active pattern AP1 and the second active pattern AP2 can be arranged, for example, to oppose each other in the second direction D2. The merged cell LC3 can include the third active pattern AP3 that is superimposed in the first direction D1 with the combination of the first active pattern AP1 and the second active pattern AP2, and the sixth active pattern AP6 and the seventh active pattern AP7 that are superimposed in the first direction D1 with the fourth active pattern AP4 and the fifth active pattern AP5, respectively. Here, the active patterns that are superimposed in the first direction D1 with each other can be understood as patterns derived from a single active pattern by the first separation structure DB1 and the second separation structure DB2 that extend in the second direction D2. More generally, components or layers described in terms of "superimposition" in a particular direction can be at least partially blocked from each other when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction.

[0031] Referring to FIG. 1 , FIG. 3A and FIG. 4AThe first active pattern AP1 and the second active pattern AP2 can be separated from each other by a first separation pattern SP1 extending in the first direction D1 along a boundary between the first cell LC1 and the second cell LC2. The first separation pattern SP1 can have a first side surface and a second side surface facing or facing toward the first cell LC1 and the second cell LC2, respectively, and (see FIG. 2B ) can be formed to have a depth that is the same as or similar to depths of the first separation structure DB1 and the second separation structure DB2. The first active pattern AP1 can extend in the first direction D1 along the first side surface of the first separation pattern SP1, and the second active pattern AP2 can extend in the first direction D1 along the second side surface of the first separation pattern SP1.

[0032] Referring to FIG. 3A , the first channel pattern 130A can be vertically stacked on the first active pattern AP1 and spaced apart from each other in the third direction D3, and the second channel pattern 130B can be vertically stacked on the second active pattern AP2 and spaced apart from each other in the third direction D3. The first channel pattern 130A and the second channel pattern 130B can also be separated from each other by the first separation pattern SP1 in a similar manner to the first active pattern AP1 and the second active pattern AP2. The first channel pattern 130A can be stacked on the first active pattern AP1 and adjacent to the first side surface of the first separation pattern SP1, and the second channel pattern 130B can be stacked on the second active pattern AP2 and adjacent to the second side surface of the first separation pattern SP1. For example, a width of the first channel pattern 130A can be substantially equal to a width of the second channel pattern 130B.

[0033] The third active pattern AP3 of the merge cell LC3 can be overlaid with the first active pattern AP1 and the second active pattern AP2 in the first direction D1. The third active pattern AP3 can have a width greater than a width of each of the first active pattern AP1 and the second active pattern AP2. In the present example embodiment, the width of the third active pattern AP3 can be greater than a sum of the respective widths of the first active pattern AP1 and the second active pattern AP2, and can be substantially equal to a sum of the respective widths of the first active pattern AP1 and the second active pattern AP2 and a width of the separation pattern SP1 between the first active pattern AP1 and the second active pattern AP2.

[0034] Referring to FIG. 1 and FIG. 2BThe first separation pattern SP1 can extend to a space between the first active pattern AP1 and the second active pattern AP2 in the first cell LC1 and the second cell LC2, but can not extend to the merged cell LC3. That is, the merged cell LC3 can not be affected by the first separation pattern SP1. In the present example embodiment, the first separation pattern SP1 can extend across or through the first separation structure DB1 to the epitaxial pattern 120'. For example, a cross section SPE of the first separation pattern SP1 can be in contact with the epitaxial pattern 120'. The first active pattern AP1 and the second active pattern AP2 can be understood as patterns derived from a single active pattern and separated by the first separation pattern SP1 extending in the first direction D1. In the present example embodiment, the single active pattern can have a width substantially equal to a width of the third active pattern AP3.

[0035] Referring to FIG. 3B The third channel pattern 130C can be vertically stacked on the third active pattern AP3 and spaced apart from each other in the third direction D3. In a similar manner to the third active pattern AP3, the third channel pattern 130C can have a width W3 greater than a width W1a of the first channel pattern 130A or a width W1b of the second channel pattern 130B. In the present example embodiment, the width W3 of the third channel pattern 130C can be greater than a sum of the widths W1a and W1b of the first channel pattern 130A and the second channel pattern 130B, and can have a width substantially equal to a sum of the widths W1a and W1b of the first channel pattern 130A and the second channel pattern 130B and the width W2 of the first separation pattern SP1. The first channel pattern 130A and the second channel pattern 130B can be patterns derived from a channel pattern having a wide width and separated by the first separation pattern SP1 extending in the first direction D1. In the present example embodiment, each of the channel patterns having a wide width can have a width substantially equal to the width of the third channel pattern 130C.

[0036] As described, the transistor located on the middle portion of the merged cell LC3 can ensure the third channel pattern 130C having an extended effective width.

[0037] Each of the first channel pattern 130A to the third channel pattern 130C according to the present example embodiment can include a plurality of semiconductor patterns sequentially stacked. For example, the semiconductor pattern can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The number of the semiconductor patterns is shown as three, but the number and shape of the semiconductor patterns can be changed in various ways.

[0038] Referring to FIG. 1 , FIG. 2A , FIG. 2B , FIG. 4A and FIG. 4BThe first source / drain pattern 120A, the second source / drain pattern 120B, and the third source / drain pattern 120C can be disposed on the first active pattern AP1 to the third active pattern AP3, respectively.

[0039] Referring to FIG. 1 and FIG. 2A In the first cell LC1, a pair of the first source / drain patterns 120A can be disposed on the first active pattern AP1 and can be connected to both sides (e.g., opposite sides) of the first channel pattern 130A in the first direction D1, respectively. In the merged cell LC3, a pair of the third source / drain patterns 120C can be disposed on the third active pattern AP3 and can be connected to both sides (e.g., opposite sides) of the third channel pattern 130C in the first direction D1, respectively. Although not shown, in the second cell LC2, a pair of the second source / drain patterns 120B can be disposed on the second active pattern AP2 and can be connected to both sides (e.g., opposite sides) of the second channel pattern 130B in the first direction D1, respectively, in a similar manner to the pair of the first source / drain patterns 120A.

[0040] Referring to FIG. 4B The third source / drain pattern 120C can include an epitaxial pattern grown from one region of the third active pattern AP3 and a side surface of the third channel pattern 130C. Referring to FIG. 4A Each of the first source / drain pattern 120A and the second source / drain pattern 120B can have a structure obtained by separating a single epitaxial pattern by the first separation pattern SP1.

[0041] In the present example embodiment, the single epitaxial pattern can be grown similar to the growth of the third source / drain pattern 120C before the first separation pattern SP1 is formed. In a subsequent process, the single epitaxial pattern can be separated into the first source / drain pattern 120A and the second source / drain pattern 120B by the first separation pattern SP1 together with the first channel pattern 130A and the second channel pattern 130B. The first source / drain pattern 120A to the third source / drain pattern 120C can be formed using a selective epitaxial growth (SEG) process. Referring to FIG. 4A The first source / drain pattern 120A and the second source / drain pattern 120B can include an upper separation pattern SPU extending on the first separation pattern SP1 to be separated. The upper separation pattern SPU according to the present example embodiment can be configured to separate contact structures connected to the first source / drain pattern 120A and the second source / drain pattern 120B into the first contact structure 180A and the second contact structure 180B.

[0042] The first and second source / drain patterns 120A and 120B can be impurity regions having a first conductivity type (e.g., P-type). The third source / drain pattern 120C can be an impurity region having a first conductivity type (e.g., P-type) that is the same as the first conductivity type (e.g., P-type) of the first and second source / drain patterns 120A and 120B. As the P-type impurity, boron (B), indium (In), gallium (Ga), boron trifluoride (BF3), or the like can be used. The first to third source / drain patterns 120A to 120C can include a semiconductor element having a lattice constant larger than a lattice constant of a semiconductor element of the substrate 101 (particularly, the first to third channel patterns 130A to 130C). As a result, the first to third source / drain patterns 120A to 120C can provide a compressive stress to the channel patterns between the first to third source / drain patterns 120A to 120C.

[0043] Referring to FIG. 1 The first and second cells LC1 and LC2 can include fourth and fifth active patterns AP4 and AP5, respectively, extending in the first direction D1. Similarly, the merged cell LC3 can include sixth and seventh active patterns AP6 and AP7 extending in the first direction D1. The sixth active pattern AP6 can be superposed with the fourth active pattern AP4 in the first direction D1, and the seventh active pattern AP7 can be superposed with the fifth active pattern AP5 in the first direction D1. Unlike the first to third active patterns AP1 to AP3, the fourth to seventh active patterns AP4 to AP7 can be located in the NMOS region NR. As described above, the first and second separation structures DB1 and DB2 can extend in the second direction to separate the fourth and sixth active patterns AP4 and AP6 from each other, and the fifth and seventh active patterns AP5 and AP7 from each other.

[0044] The fourth active pattern AP4 and the sixth active pattern AP6 can be disposed adjacent to a second separation pattern SP2 extending in the first direction D1 along the upper boundary. In a similar manner to the first active pattern API and the second active pattern AP2, the fourth active pattern AP4 and the sixth active pattern AP6 can be understood as patterns obtained by separating other adjacent unit's active patterns (not shown) by the second separation pattern SP2. Similarly, the fifth active pattern AP5 and the seventh active pattern AP7 can be disposed adjacent to a third separation pattern SP3 extending in the first direction D1 along the lower boundary. In a similar manner to the fourth active pattern AP4 and the sixth active pattern AP6, the fifth active pattern AP5 and the seventh active pattern AP7 can be understood as patterns obtained by separating other active patterns (not shown) of other adjacent units by the third separation pattern SP3. In an example embodiment, the separation patterns SP can include the first separation pattern SP1, the second separation pattern SP2, and the third separation pattern SP3.

[0045] As described, the second separation pattern SP2 and the third separation pattern SP3 can extend to or into the merged cell LC3 after passing through the first cell LC1 and the second cell LC2 along the upper boundary and the lower boundary, respectively. In contrast, the first separation pattern SP1 described above can separate the first active pattern API and the second active pattern AP2 from each other at the boundary between the first cell LC1 and the second cell LC2, but can not extend to or into the merged cell LC3. As a result, the semiconductor device 100 according to the present example embodiment can have the third active pattern AP3 having a relatively wide width and the third channel pattern 130C having a relatively wide width in the merged cell LC3 that is not affected by the first separation pattern SP1.

[0046] The first cell LC1 can include fourth channel patterns (not shown) vertically stacked on the fourth active pattern AP4 and spaced apart from each other in the third direction D3, and fourth source / drain patterns 120D connected to both sides (e.g., opposite sides) of the fourth channel patterns (not shown) in the first direction D1, respectively. Similarly, the second cell LC2 can include fifth channel patterns (not shown) vertically stacked on the fifth active pattern AP5 and spaced apart from each other in the third direction D3, and fifth source / drain patterns 120E connected to both sides (e.g., opposite sides) of the fifth channel patterns (not shown) in the first direction D1, respectively.

[0047] The merge unit LC3 can include sixth and seventh channel patterns (not shown) respectively provided on the sixth and seventh active patterns AP6 and AP7, the sixth and seventh channel patterns being vertically stacked and spaced apart from each other in the third direction D3, the sixth source / drain pattern 120F being respectively connected to both sides (e.g., opposite sides) of the sixth channel pattern (not shown) in the first direction D1 on the sixth active pattern AP6, and the seventh source / drain pattern 120G being respectively connected to both sides (e.g., opposite sides) of the seventh channel pattern (not shown) in the first direction D1 on the seventh active pattern AP7. In an example embodiment, the source / drain patterns 120 can include the first to seventh source / drain patterns 120A to 120G.

[0048] In the present example embodiment, the fourth and fifth source / drain patterns 120D and 120E can have a different conductive type from that of the first and second source / drain patterns 120A and 120B, and the sixth and seventh source / drain patterns 120F and 120G can have a different conductive type from that of the third source / drain pattern 120C.

[0049] The fourth to seventh source / drain patterns 120D to 120G can be impurity regions having a second conductive type (e.g., N-type). For example, the fourth to seventh source / drain patterns 120D to 120G can include Si, and the N-type impurity can include phosphorus (P), nitrogen (N), arsenic (As), and / or antimony (Sb).

[0050] Referring to FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3B , the semiconductor device 100 according to the present example embodiment can include a first gate structure GS1 extending in the second direction D2 in the first unit LC1, a second gate structure GS2 extending in the second direction D2 in the second unit LC2, and a third gate structure GS3 extending in the second direction D2 in the merge unit LC3, the first gate structure GS1 surrounding the first channel pattern 130A, the second gate structure GS2 surrounding the second channel pattern 130B, and the third gate structure GS3 surrounding the third channel pattern 130C. The term "surrounding" or "covering" or "filling" as can be used herein can not require completely surrounding or covering or filling the described element or layer, but can for example indicate partially surrounding or covering or filling the described element or layer (e.g., with voids or other spaces therethrough). (In particular, see FIG. 3AThe first gate structure GS1 and the second gate structure GS2 can be stacked on each other in the second direction D2 and can be separated from each other by the first separation pattern SP1.

[0051] Similarly, referring to FIG. 1 , the first gate structure GS1 can extend in the second direction D2 toward the second separation pattern SP2 to surround the fourth channel pattern, and the second gate structure GS2 can extend in the second direction D2 toward the third separation pattern SP3 to surround the fifth channel pattern (not shown). In addition, the third gate structure GS3 can extend in the second direction D2 toward the second separation pattern SP2 and the third separation pattern SP3 to surround the sixth channel pattern and the seventh channel pattern (not shown).

[0052] As shown in FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3B , the first gate structure GS1 to the third gate structure GS3 can include gate electrodes 145 extending in the second direction D2 and surrounding the first channel pattern to the third channel pattern 130A, 130B and 130C, gate insulating films 142 provided between the gate electrodes 145 and the relevant channel patterns 130A, 130B and 130C, gate spacers 141 provided on both (e.g., opposite) surfaces of a portion of the gate electrodes 145 on the uppermost semiconductor pattern, and gate cap layers 147 provided on the gate electrodes 145 between the gate spacers 141.

[0053] The gate electrodes 145 can include a conductive material. For example, the gate electrodes 145 can include at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN and TaAlC. In some example embodiments, the gate electrodes 145 can include a semiconductor material such as doped polysilicon. At least one of the gate electrodes 145 can include a multi-layer structure formed by different materials.

[0054] The gate insulating films 142 can include a dielectric material. For example, the gate insulating films 142 can include an oxide, a nitride or a high-k material. The high-k material can denote a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2), and the high-k material can be, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y), lanthanum aluminum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and praseodymium oxide (Pr2O3). In some example embodiments, the gate insulating film 142 can include two or more other dielectric layers.

[0055] The gate spacers 141 can include an insulating material. For example, the gate spacers 141 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some example embodiments, the gate spacers 141 can include a multi-layer structure formed of different materials. The gate cap layer 147 can include, for example, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxynitride.

[0056] The first to third gate structures GS1 to GS3 according to the present example embodiment can include inner spacers IS. The inner spacers IS can be respectively disposed on both sides (e.g., opposite sides) of the gate electrode portions 145S located between the channel patterns 130A, 130B, and 130C. For example, the inner spacers can include a low-k dielectric such as an oxide, a nitride, and an oxynitride. In some example embodiments, the gate electrode portions 145S can be surrounded by the gate insulating portions 142S in the first direction D1. The gate electrode portions 145S and the gate insulating portions 142S can be spaced apart from the first to third source / drain patterns 120A, 120B, and 120C by the inner spacers IS. The inner spacers IS can have convex side surfaces toward the gate electrode portions 145S, but the inventive concept is not limited thereto.

[0057] As a result, three P-type transistors can be formed in the PMOSFET region PR, and four N-type transistors can be formed in the NMOSFET region NR.

[0058] The semiconductor device 100 according to the present example embodiment can further include a first interlayer insulating layer 151 disposed on the isolation layer 110 to cover the source / drain pattern 120 and a second interlayer insulating layer 152 covering the gate structure GS on the first interlayer insulating layer 151. For example, the first interlayer insulating layer 151 and the second interlayer insulating layer 152 can include a spin-on hard mask (SOH), a flowable oxide (FOX), a tonen silazane (TOSZ), an undoped silicon dioxide glass (USG), a borosilicate glass (BSG), a phosphosilicate glass (PSG), a borophosphosilicate glass (BPSG), a plasma-enhanced tetraethyl orthosilicate (PETEOS), a flowable silicate glass (FSG), a high-density plasma (HDP) oxide, a plasma-enhanced oxide (PEOX), a flowable CVD (FCVD) oxide, or a combination thereof. Each of the first interlayer insulating layer 151 and the second interlayer insulating layer 152 can be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin-on process.

[0059] The semiconductor device 100 according to the present example embodiment can include contact structures 180 (e.g., a first contact structure 180A, a second contact structure 180B, and a third contact structure 180C) respectively connected to the source / drain pattern 120 and passing through the interlayer insulating layer 150 between the gate structures GS. Each of the contact structures 180 can include a contact plug 185 and a barrier layer 182 surrounding the contact plug 185. For example, the contact plug 185 can include Cu, Co, Mo, Ru, W, or an alloy thereof. For example, the barrier layer 182 can include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof.

[0060] Metal semiconductor compound layers SC can be respectively disposed between the contact structures 180 and the source / drain pattern 120. The contact structures 180 can have a low resistance contact with the source / drain pattern 120 through the metal semiconductor compound layers SC. The metal semiconductor compound layers SC can include a metal silicide, and can include at least one of, for example, titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0061] Referring to FIG. 4A The first contact structure 180A and the second contact structure 180B can be respectively connected to the first source / drain pattern 120A and the second source / drain pattern 120B separated from each other by the first separation pattern SP1. The first contact structure 180A and the second contact structure 180B can be separated from each other by the upper separation pattern SPU connected to the first separation pattern SP1, and can be respectively electrically connected to the first source / drain pattern 120A and the second source / drain pattern 120B. Referring to FIG. 4BThe third contact structure 180C can be connected to the third source / drain pattern 120C. The gate contact GC can pass through the second interlayer insulating layer 152 and the gate cap layer 147, and can be connected to the gate electrode 145.

[0062] The semiconductor device 100 according to the present example embodiment can include an interconnect structure 190. The interconnect structure 190 can be disposed on the front side of the semiconductor device 100. The interconnect structure 190 can include a first interconnect insulating layer 191 and a second interconnect insulating layer 192, an interconnect line ML disposed in the second interconnect insulating layer 192, and an interconnect via V passing through the first interconnect insulating layer 191, the interconnect via V being connected to the interconnect line ML. The interconnect line ML and the interconnect via V can be formed using a dual damascene process. The interconnect line ML can be connected to each of the contact structures 180 and the gate contact GC through the interconnect via V. For example, the first interconnect insulating layer 191 and the second interconnect insulating layer 192 can include a low-k material such as silicon oxide, silicon oxynitride, SiOC, or SiCOH. For example, the interconnect line ML and the interconnect via V can include copper or a copper-containing alloy.

[0063] In example embodiments of the inventive concept, although not shown, an interconnect line stacked on an additional interconnect insulating layer can additionally be provided. The stacked interconnect line can include a routing line and a power line. For example, the power line can be provided on the boundary between the first cell and the second cell.

[0064] According to the example embodiments described above, the first separation pattern SP1 separating the first gate structure GS1 and the second gate structure GS2 from each other and separating the first channel pattern 130A and the second channel pattern 130B from each other along the boundary between the first cell LC1 and the second cell LC2 can not extend into the merged cell LC3, thereby enabling the merged cell LC3 without a separation pattern. In other words, the merged cell LC3 can be free from the separation pattern SP1, and the third gate structure GS3 can continuously extend (without separation) in the second direction D2 between the boundaries (e.g., as defined by the second separation pattern SP2 and the third separation pattern SP3) of the merged cell LC3. As a result, the third channel pattern 130C (and the third active pattern AP3) of the merged cell LC3 overlaid with the first channel pattern 130A and the second channel pattern 130B (and the first active pattern AP1 and the second active pattern AP2) in the first direction D1 can have a sufficient effective width.

[0065] In addition, unlike the present example embodiment, when the first split pattern SP1 extends to the merge unit LC3, the third gate structure GS3 can be split into two gate structures, and thus an electrical connection between the split gate structures (for example, by providing an additional gate connection pattern) can be required. Accordingly, in the present example embodiment, an increase in electrical resistance caused by the additional gate connection pattern or other electrical connection between the split gate structures can be prevented.

[0066] FIG. 5 is a plan view of a semiconductor device according to an example embodiment of the present inventive concept. FIG. 6A and FIG. 6B are cross-sectional views of the semiconductor device shown in FIG. 5 .

[0067] Referring to FIG. 5 , FIG. 6A and FIG. 6B , the semiconductor device 100A according to the present example embodiment can be understood to have a structure similar to that of the semiconductor device 100 shown in FIG. 1 to FIG. 4B , except that the arrangement of the NMOSFET region NR and the PMOSFET region PR in each of the units LC1, LC2 and LC3 (for example, the first unit LC1, the second unit LC2 and the third unit LC3) is reversed, and the width W3' of the third active pattern AP3 of the merge unit LC3 is slightly smaller than the sum (W1a+W1b+W2) of the widths of the first active pattern AP1 and the second active pattern AP2 and the first split pattern SP1. In addition, unless otherwise described, components of the present example embodiment can be understood with reference to the description of the same or similar components of the semiconductor device 100 shown in FIG. 1 to FIG. 4B .

[0068] In the present example embodiment, the active region 105 of the substrate 101 can be divided into the PMOSFET region PR and the NMOSFET region NR, and each of the first unit LC1 and the second unit LC2 can include the PMOSFET region PR and the NMOSFET region NR arranged in the second direction D2. As shown in FIG. 5As shown in FIG. 1, the NMOSFET regions NR of the first and second cells LC1 and LC2 can be disposed opposite each other, and can be disposed as a single active region with the first and second active patterns disposed across the cell boundary. The third active pattern AP3 of the merged cell LC3 can be superimposed with the first and second active patterns AP1 and AP2 in the first direction, and can be disposed as the NMOSFET region NR. The first and second source / drain patterns 120A and 120B, and the third source / drain pattern 120C can be impurity regions having a second conductivity type (e.g., N-type), respectively, and the source / drain patterns 120 disposed on the active patterns (i.e., the fourth through seventh active patterns AP4 through AP7) of the first and second cells LC1 and LC2, and the merged cell LC3, respectively, can be impurity regions having a first conductivity type (e.g., P-type).

[0069] In the present example embodiment, the width W3' of the third channel pattern 130C in the second direction D2 can be slightly smaller than the sum of the widths W1a and W1b of the first and second channel patterns 130A and 130B in the second direction D2, and the width W2 of the first separation pattern SP1 in the second direction D2. However, the width W3' of the third channel pattern 130C can be larger than the sum of the widths W1 and W2 of the first and second channel patterns 130A and 130B. The first separation pattern SP1 can be formed between the first and second active patterns AP1 and AP2 in such a manner that the first and second channel patterns 130A and 130B can have substantially equal widths (W1a = W1b).

[0070] FIG. 7 is a plan view of a semiconductor device according to an example embodiment of the inventive concepts. FIG. 8A and FIG. 8B are cross-sectional views taken along lines I1-I1' and I2-I2', respectively, FIG. 7 is a cross-sectional view of the semiconductor device shown in

[0071] Referring to FIG. 7 , FIG. 8A and FIG. 8B , the semiconductor device 100B according to the present example embodiment can be understood to have a structure similar to that of the semiconductor device 100 shown in FIG. 1 to FIG. 4B , except that a single separation structure DB is disposed between the first and second cells LC1 and LC2 and the merged cell LC3, and the first separation pattern SP1 extends to the separation structure DB. In addition, components of the present example embodiment can be understood with reference to the description of the same or similar components of the semiconductor device 100 shown in FIG. 1 to FIG. 4B , unless otherwise described.

[0072] In the present example embodiment, the semiconductor device 100B can include a single separation structure DB extending in the second direction D2 between the first and second cells LC1 and LC2 and the merged cell LC3. The separation structure DB can be arranged to have the same pitch as the pitch of the gate structure GS in the first direction D1. The separation structure DB can be provided between the first and second active patterns AP1 and AP2 and the third active pattern AP3 to separate the first and second active patterns AP1 and AP2 from the third active pattern AP3 from each other. The separation structure DB can extend to the upper and lower boundaries, respectively, to cross the fourth and sixth active patterns AP4 and AP6, and to cross the fifth and seventh active patterns AP5 and AP7.

[0073] In the present example embodiment, the first separation pattern SP1 can extend to the separation structure DB, but can not extend beyond the separation structure DB or into the merged cell LC3. For example, the cross section SPE of the first separation pattern SP1 can be configured to contact a side surface of the separation structure DB.

[0074] FIG. 9 is a plan view of a semiconductor device according to an example embodiment of the inventive concepts.

[0075] Referring to FIG. 9 , the semiconductor device 100C according to the present example embodiment can be understood to have a structure similar to that of the semiconductor device 100 shown in FIG. 1 to FIG. 4B , except that a gate cut structure CT is formed in the third gate structure GS3, and a dummy cell DC having a dummy pattern exists in a region adjacent to the upper boundary of the merged cell LC3. In addition, unless otherwise described, components of the present example embodiment can be understood with reference to the description of the same or similar components of the semiconductor device 100 shown in FIG. 1 to FIG. 4B . In addition, unless otherwise described, components of the present example embodiment can be understood with reference to the description of the same or similar components of the semiconductor device 100 shown in

[0076] In the present example embodiment, the merged cell LC3 can include a dummy cell DC in a region adjacent to the upper boundary of the merged cell LC3. The dummy cell DC can not include a transistor. The cell height CH3' of the merged cell LC3 can be smaller than the sum of the cell heights (CH1+CH2) of the first and second cells LC1 and LC2 by the height of the dummy cell DC. In the third gate structure GS3, a gate cut structure CT can be formed in a region adjacent to the upper boundary of the merged cell LC3 such that the gate structure (or, the third gate structure GS) is separated into two gate structures. The dummy cell DC can include a dummy pattern DP that overlaps the fourth active pattern AP4 of the first cell LC1 in the first direction D1.

[0077] FIG. 10 is a plan view of a semiconductor device according to an example embodiment of the inventive concepts.

[0078] Referring to FIG. 10 , the semiconductor device 100D according to the present example embodiment can be understood to have a structure similar to that of the semiconductor device 100 shown in FIG. 1 to FIG. 4B except that the width of the third active pattern AP3 is increased as the width of the dummy pattern DP is decreased, and in a similar manner to the example embodiment of FIG. 9 , a gate cut structure CT is formed in the third gate structure GS3, and a dummy cell DC exists in a region adjacent to the upper boundary of the merged cell LC3. In addition, components of the present example embodiment can be understood with reference to the description of the same or similar components of the semiconductor device 100 shown in FIG. 1 to FIG. 4B , unless otherwise described.

[0079] In the present example embodiment, the dummy pattern DP of the dummy cell DC can overlap the fourth active pattern AP4 of the first cell LC1 in the first direction D1. The dummy pattern DP can not contribute to the configuration of a transistor. The width of the dummy pattern DP in the second direction D2 can decrease by a predetermined width dl in the second direction D2 (e.g., relative to the width of the fourth active pattern AP4 in the second direction D2). As shown in FIG. 10 , the side surface of the dummy pattern DP facing the third active pattern AP3 can be recessed, such that the dummy pattern DP can have a width that is smaller than the width of the fourth active pattern AP4 of the first cell LC1. The third active pattern AP3 can have a portion having a surface that protrudes toward the dummy pattern DP. The third active pattern AP3 can have a width that increases the width d2 of the protruding portion in the second direction D2.

[0080] As noted, even if the width of the third active pattern AP3 of the merged cell LC3 is increased, the width of the adjacent dummy pattern DP can be decreased, thereby maintaining the separation distance between the third active pattern AP3 and the dummy pattern DP (e.g., in the second direction D2) at substantially the same height or distance as the distance between the first active pattern AP1 and the fourth active pattern AP4 (in the second direction D2). As a result, in the present example embodiment, the width of the third channel pattern (130C) stacked on the third active pattern AP3 can be additionally increased to ensure a further extended effective channel width. FIG. 3B

[0081] ​According to example embodiments of the inventive concept, a separation pattern formed along a boundary between cells can not extend into a merged cell, the separation pattern separating the gate structure and the channel pattern from each other, thereby enabling a merged cell that is not affected by or does not have the separation pattern. As a result, sufficient channel width can be ensured, and an increase in gate resistance caused by an additional gate connection pattern that would otherwise be required to provide electrical connection of the gate structure due to the extension of the separation pattern into the merged cell can be prevented.

[0082] While example embodiments have been shown and described above, it will be clear to those of ordinary skill in the art that modifications and changes can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: first and second units in first and second rows, respectively, wherein the first and second rows extend in a first direction and the first and second rows are adjacent to each other in a second direction that intersects the first direction; a merged unit extending in the second direction across the first and second rows, wherein the merged unit is adjacent to the first and second units in the first direction; a separation pattern extending in the first direction at a boundary between the first and second units, the separation pattern having first and second side surfaces facing the first and second units, respectively; and at least one separation structure extending in the second direction between the first and second units and the merged unit, wherein the first unit includes first active patterns extending in the first direction along the first side surface of the separation pattern, first channel patterns adjacent to the first side surface of the separation pattern, the first channel patterns stacked on the first active patterns and spaced apart from each other in a third direction that is perpendicular to the first and second directions, first gate structures extending in the second direction and on the first channel patterns, and first source / drain patterns connected to opposite sides of the first channel patterns in the first direction, respectively, wherein the second unit includes second active patterns extending in the first direction along the second side surface of the separation pattern, second channel patterns adjacent to the second side surface of the separation pattern, the second channel patterns stacked on the second active patterns and spaced apart from each other in the third direction, second gate structures separated from the first gate structures by the separation pattern, the second gate structures extending in the second direction and on the second channel patterns, and second source / drain patterns connected to opposite sides of the second channel patterns in the first direction, respectively, and wherein the merged unit includes third active patterns separated from the first and second active patterns by the at least one separation structure, the third active patterns extending in the first direction, third channel patterns stacked on the third active patterns and spaced apart from each other in the third direction, third gate structures extending in the second direction and on the third channel patterns, and third source / drain patterns connected to opposite sides of the third channel patterns in the first direction, respectively.

2. The semiconductor device according to claim 1, wherein a third width of the third channel patterns in the second direction is greater than a sum of first and second widths of the first and second channel patterns, respectively, in the second direction.

3. The semiconductor device according to claim 1, wherein the third width of the third channel patterns in the second direction is equal to a sum of the first and second widths of the first and second channel patterns, respectively, in the second direction and a width of the separation pattern in the second direction.

4. The semiconductor device according to claim 1, wherein the first and second widths of the first and second channel patterns, respectively, in the second direction are equal to each other. the first and second widths of the first and second channel patterns, respectively, in the second direction are equal to each other.

5. The semiconductor device according to claim 1, wherein The at least one separation structure includes a first separation structure adjacent to the first cell and the second cell, and a second separation structure adjacent to the merged cell.

6. The semiconductor device of claim 5, further comprising: an epitaxial pattern on the third active pattern between the first separation structure and the second separation structure, wherein the separation pattern extends to the epitaxial pattern across the first separation structure, and wherein the merged cell is free of the separation pattern.

7. The semiconductor device of claim 1, wherein the at least one separation structure includes a single separation structure separating the third active pattern from the first active pattern and the second active pattern, and the separation pattern extends to the single separation structure such that the merged cell is free of the separation pattern.

8. The semiconductor device of any one of claims 1 to 7, wherein the first cell further includes a fourth active pattern extending in the first direction at a boundary opposite the boundary between the first cell and the second cell, fourth channel patterns stacked on the fourth active pattern and spaced apart from each other in the third direction, and fourth source / drain patterns on the fourth active pattern respectively connected to opposite sides of the fourth channel patterns in the first direction, the second cell further includes a fifth active pattern extending in the first direction at a boundary opposite the boundary between the first cell and the second cell, fifth channel patterns stacked on the fifth active pattern and spaced apart from each other in the third direction, and fifth source / drain patterns on the fifth active pattern respectively connected to opposite sides of the fifth channel patterns in the first direction, and the first gate structure extends in the second direction and on the fourth channel patterns, and the second gate structure extends in the second direction and on the fifth channel patterns.

9. The semiconductor device of claim 8, wherein the first source / drain pattern and the second source / drain pattern have a first conductivity type, and the fourth source / drain pattern and the fifth source / drain pattern have a second conductivity type different from the first conductivity type of the first source / drain pattern and the second source / drain pattern.

10. The semiconductor device according to claim 8, wherein the merged cell includes: a sixth active pattern extending in the first direction, the sixth active pattern being superposed with the fourth active pattern in the first direction, the sixth active pattern being separated from the fourth active pattern by the at least one separation structure; a seventh active pattern extending in the first direction, the seventh active pattern being superposed with the fifth active pattern in the first direction, the seventh active pattern being separated from the fifth active pattern by the at least one separation structure; sixth channel patterns stacked on the sixth active pattern and spaced apart from each other in the third direction; seventh channel patterns stacked on the seventh active pattern and spaced apart from each other in the third direction; sixth source / drain patterns on the sixth active pattern respectively connected to opposite sides of the sixth channel patterns in the first direction; and seventh source / drain patterns on the seventh active pattern respectively connected to opposite sides of the seventh channel patterns in the first direction, The third gate structure extends in the second direction and is on the sixth and seventh channel patterns.

11. The semiconductor device according to claim 10, wherein The sixth and seventh source / drain patterns have a second conductivity type different from a first conductivity type of the third source / drain pattern.

12. The semiconductor device according to claim 8, wherein The merging unit includes a dummy pattern extending in the first direction, the dummy pattern being superposed with the fourth active pattern in the first direction, the dummy pattern being separated from the fourth active pattern by the at least one separation structure.

13. The semiconductor device according to claim 12, wherein a side surface of the dummy pattern facing the third active pattern is recessed, such that the dummy pattern has a width in the second direction smaller than a width of the fourth active pattern, and a portion of the third active pattern protrudes toward the dummy pattern in the second direction, such that a width of the third active pattern in the second direction is increased by the portion protruding toward the dummy pattern.

14. A semiconductor device comprising: first and second units in first and second rows, respectively, wherein the first and second rows extend in a first direction, and the first and second rows are adjacent to each other in a second direction intersecting the first direction; a merging unit extending in the second direction across the first and second rows, wherein the merging unit is adjacent to the first and second units in the first direction; and a separation pattern extending in the first direction at a boundary between the first and second units, the separation pattern having first and second side surfaces facing the first and second units, respectively, wherein the first unit includes first active patterns extending in the first direction along the first side surface of the separation pattern, and first channel patterns adjacent to the first side surface of the separation pattern, the first channel patterns being stacked on the first active patterns and spaced apart from each other in a third direction perpendicular to the first and second directions, wherein the second unit includes second active patterns extending in the first direction along the second side surface of the separation pattern, and second channel patterns adjacent to the second side surface of the separation pattern, the second channel patterns being stacked on the second active patterns and spaced apart from each other in the third direction, wherein the merging unit includes a third active pattern superposed with at least a portion of each of the first and second active patterns in the first direction, the third active pattern extending in the first direction, and third channel patterns stacked on the third active pattern and spaced apart from each other in the third direction, and wherein a width of the third active pattern in the second direction is larger than a sum of respective widths of the first and second active patterns in the second direction.

15. The semiconductor device according to claim 14, wherein the third active pattern has a width equal to a sum of the respective widths of the first and second active patterns and a width of the separation pattern in the second direction.

16. The semiconductor device according to claim 14, further comprising: first and second separation structures extending in the second direction between the first and second units and the merging unit, wherein the first and second separation structures are spaced apart from each other in the first direction, and the first and second separation structures are superposed with the first and second active patterns in the first direction, respectively. wherein, in the first direction, the first separation structure is adjacent to the first cell and the second cell, and the second separation structure is adjacent to the merged cell.

17. The semiconductor device of claim 16, further comprising: an epitaxial pattern on the third active pattern between the first separation structure and the second separation structure, wherein the separation pattern extends to the epitaxial pattern across the first separation structure, and wherein the merged cell is free of the separation pattern.

18. The semiconductor device of claim 14, further comprising: a single separation structure separating the third active pattern from the first active pattern and the second active pattern, wherein the separation pattern extends to the single separation structure, and wherein the merged cell is free of the separation pattern.

19. A semiconductor device, comprising: active patterns extending on a substrate in a first direction; a separation structure extending in a second direction intersecting the first direction; channel patterns stacked on the active patterns and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, wherein the separation structure separates each of the active patterns and the channel patterns into a first portion and a second portion; gate structures extending in the second direction and extending onto the first portions of the channel patterns; a separation pattern extending in the first direction, wherein the separation pattern separates the first portions of the channel patterns into first channel patterns and second channel patterns, and separates the gate structures into first gate structures and second gate structures; and third gate structures extending in the second direction and extending onto the second portions of the channel patterns, wherein the second portions of the channel patterns have a width in the second direction greater than a sum of first and second widths of the first channel patterns and the second channel patterns in the second direction, respectively.

20. The semiconductor device according to claim 19, wherein the width of the second portions of the channel patterns is equal to a sum of the first and second widths of the first and second channel patterns and a width of the separation pattern in the second direction. the width of the second portions of the channel patterns is equal to a sum of the first and second widths of the first and second channel patterns and a width of the separation pattern in the second direction.

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