Micro light-emitting element and preparation method thereof

Abstract

The invention discloses a micro light-emitting element and a preparation method thereof. The micro light-emitting element comprises a driving substrate; the first bonding layer is arranged on the driving substrate, and the first bonding layer comprises metal layers arranged at certain intervals and insulating layers arranged between the metal layers; a second bonding layer; the first bonding layer is arranged on the first bonding layer and comprises a dielectric layer and a plurality of through holes, the through holes penetrate through the dielectric layer, conductive materials are filled in the through holes, and the dielectric layer is made of insulating materials; the plurality of epitaxial layers are arranged on the second bonding layer according to a certain interval; the passivation layer is arranged on the outer wall of the epitaxial layer and the second bonding layer, and open holes are formed in the upper surface of the epitaxial layer and the upper surface of the second bonding layer; and the N electrode layer is arranged above the passivation layer. According to the design of the invention, the two adjacent epitaxial layers are electrically isolated, etching of the bonding layer is not needed, the problems of excessive etching, incomplete etching, side wall metal residue and the like of the micro light-emitting element are effectively avoided, and the product yield of the Micro LED is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor display, in particular, to a micro light emitting element and a preparation method thereof. BACKGROUND

[0002] In recent years, light emitting diodes (LEDs) have been widely used in the field of lighting and other fields due to their unique advantages, and have replaced the original traditional lighting sources. With the development of the display industry, there is a higher demand for small-sized LEDs.

[0003] Micro LED (micro light emitting element) display technology refers to a display technology in which self-luminous micro-sized LEDs are used as light emitting pixel units, and the units are assembled on a CMOS driving panel to form a high-density LED array. Due to the small size, high integration and self-luminous characteristics of Micro-LED, the Micro-LED has great advantages in brightness, resolution, contrast, energy consumption, service life, response speed and thermal stability compared with LCD and OLED in the field of display, and can be applied in the fields of AR / VR, wearable devices, automotive head-up HUD, micro projection, 3D printing and other display fields.

[0004] To realize display, a plurality of Micro LED chips and a driving substrate are assembled together. The wafer to wafer bonding method is widely used because it does not need to be aligned. The conventional method is to respectively plate metals on the driving substrate side and the Micro LED chip epitaxial side, then bond them together by using the thermal expansion characteristics of the metals, and then completely disconnect each LED unit from the epitaxial layer to the bonding layer by etching process, so as to realize independent control of the Micro LED, as shown in FIG. 1. Figure 1 In this process, due to the extremely small size of the Micro LED and the small spacing between adjacent epitaxial layers 104, the etching difficulty is extremely high, the aspect ratio of the etching opening 150 is large, the process window is small, and problems such as over-etching, incomplete etching, and metal residue on the sidewall may occur, which affects the product yield of the Micro LED. At the same time, with the emergence of new display technologies such as AR and VR, the demand for light emitting brightness of Micro LED is also increasing. SUMMARY

[0005] To solve the above problems, the present application provides a micro light emitting element, comprising: a driving substrate; a first bonding layer arranged on the driving substrate, the first bonding layer comprising metal layers arranged at a certain interval and insulating layers arranged between the metal layers; a second bonding layer arranged on the first bonding layer, comprising a dielectric layer and a plurality of through holes, the plurality of through holes penetrating through the dielectric layer, the through holes being filled with conductive material, and the dielectric layer being an insulating material; A plurality of epitaxial layers are arranged on the second bonding layer at a certain interval, each epitaxial layer comprising: a second semiconductor layer arranged on the second bonding layer; an active layer arranged on the second semiconductor layer; and a first semiconductor layer arranged on the active layer; A passivation layer is arranged on the outer wall of the epitaxial layer and the second bonding layer, and has an opening on the upper surface of the epitaxial layer and the upper surface of the second bonding layer; An N electrode layer is arranged above the passivation layer.

[0006] The application further provides a manufacturing method of the micro light emitting element. S1, providing a driving substrate, depositing an insulating material on the driving substrate to form an insulating layer, and exposing the driving substrate by using a photolithography process to obtain a patterned insulating layer; S2, depositing a metal material on the driving substrate, and then removing the excess metal material on the surface of the insulating layer until the surface of the insulating layer is exposed, so that the metal material forms a metal layer, and the metal layer and the insulating layer constitute a first bonding layer; S3, providing an LED growth substrate, growing epitaxial layers on the LED substrate in sequence, i.e., a first semiconductor layer, an active layer and a second semiconductor layer; depositing a transparent conductive layer on the second semiconductor layer, and forming a dielectric layer by evaporating a dielectric material on the surface of the transparent conductive layer; S4, obtaining a plurality of through holes penetrating the dielectric layer by using a photolithography and etching process, and filling the through holes with a conductive material, so that the through holes and the dielectric layer jointly form a second bonding layer; S5, bonding the first bonding layer and the second bonding layer by using a bonding process to combine the LED wafer and the driving substrate; S6, peeling off the LED substrate; S7, etching the LED epitaxial layer until the transparent conductive layer is exposed to obtain a plurality of completely disconnected epitaxial layers; S8, etching the transparent conductive layer until the second bonding layer is exposed; S9, depositing an insulating material to form a passivation layer, and opening the passivation layer on the upper surface of the epitaxial layer and the second bonding layer; S10, depositing a metal conductive material to form an N electrode layer, the N electrode layer is electrically connected to the first semiconductor layer of each epitaxial layer, the plurality of epitaxial layers are connected by the N electrode layer, and the N electrode layer surrounds the periphery of the driving substrate.

[0007] The application has the following beneficial effects: A micro light emitting element is provided, a first bonding layer on a driving substrate side is provided as a patterned metal layer, the metal layer is interrupted by an insulating layer; a second bonding layer is a dielectric layer with conductive vias, the dielectric layer is insulating and conductive at the vias. Such a design makes the two adjacent epitaxial layers electrically isolated, thus without etching the bonding layer, the problems of over-etching, incomplete etching, and sidewall metal residue are effectively avoided, and the product yield of the Micro LED is improved.

[0008] A method for manufacturing a micro light emitting element is also provided, before wafer bonding: the first bonding layer on the driving substrate is patterned, and the metal layer is interrupted by an insulating material; the second bonding layer on the epitaxial layer side is only conductive at the vias, achieving electrical isolation between the epitaxial layers. The step of etching the metal bonding layer is reduced, the process window is expanded, and the damage to the epitaxial layer and the micro light emitting element structure during etching is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a cross-sectional schematic diagram of a micro light emitting element in the prior art; Figure 2 is a cross-sectional schematic diagram of a micro light emitting element of embodiment 1 in the present application; Figure 3 is a partial enlarged schematic diagram of a micro light emitting element of embodiment 1 in the present application; Figure 4 is another partial enlarged schematic diagram of a micro light emitting element of embodiment 1 in the present application; Figure 5 is a top view schematic diagram of a metal layer and a via of a micro light emitting element of embodiment 1 in the present application; Figure 6 is a top view of a micro light emitting element of embodiment 1 in the present application; Figures 7 to 16 is a preparation process of a micro light emitting element of embodiment 1 in the present application; BRIEF DESCRIPTION OF DRAWINGS 100: micro light emitting element 101: driving substrate 102: first bonding layer 1021: metal layer 1022: insulating layer 103: second bonding layer 1031: via 1032: dielectric layer 104: epitaxial layer 105: second semiconductor layer 106: active layer 107: first semiconductor layer 108: passivation layer 109: N electrode layer 110: transparent conductive layer 111: P-type electrical connection point 112: N-type electrical connection point 130: driving substrate periphery 140: epitaxial sidewall 150: etching opening 200: LED growth substrate DETAILED DESCRIPTION

[0010] This application will be further described in detail with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0011] To enable those skilled in the art to better understand the technical solution of this application, this application provides a detailed explanation of the problems existing in the prior art.

[0012] The concept of "micro-light-emitting element" mentioned in this embodiment usually refers to a structure with a size of less than 100μm.

[0013] In this embodiment, "extension", "pixel" and "light-emitting unit" are the same concept. Example 1

[0014] Figure 2 This is a cross-sectional schematic diagram of a micro-light-emitting element according to an embodiment of the present invention. For ease of understanding, Figure 2 Taking two extensions of 104 as an example, the actual number of extensions of 104 can be adjusted according to needs and is not limited to this. Please refer to Figure 2 In order to achieve at least one or more of the advantages of the present invention, an embodiment of the present invention provides a micro-light-emitting element 100, which includes a driving substrate 101, a first bonding layer 102 disposed on the driving substrate 101, a second bonding layer 103 disposed on the first bonding layer 102, a plurality of epitaxial layers 104 disposed on the second bonding layer 103, a passivation layer 108 and an N-electrode layer 109.

[0015] In this invention, the driving substrate 101 can be a CMOS substrate, a TFT glass substrate, or other substrates with driving circuits to provide current to the epitaxial layer 104 to make it emit light. In this embodiment, CMOS is used as the driving substrate. The driving substrate 101 is provided with a plurality of P-type electrical contacts 111 and N-type electrical contacts 112 to serve as circuit connections.

[0016] In this invention, a first bonding layer 102 is disposed on a driving substrate 101, and it is composed of a plurality of spaced metal layers 1021 and an insulating layer 1022 between the metal layers 1021. The first bonding layer 102 is electrically isolated in segments. Individual metal layers 1021 can conduct electricity, while adjacent metal layers 1021 are separated and insulated by the insulating layer 1022, and the insulating layer 1022 completely fills the portion between the metal layers 1021.

[0017] In some embodiments, the thickness of the metal layer 1021 in the first bonding layer 102 is 97%-103% of the thickness of the insulating layer 1022, and the optimal value is that the thickness of the metal layer 1021 is equal to the thickness of the insulating layer 1022, i.e., the first bonding layer 102 has a flat horizontal surface, but due to the process difficulty of the micro-LED and the difficulty of measurement, there may be some errors, so the thickness of the metal layer 1021 is set to be 97%-103% of the thickness of the insulating layer 1022, and in this embodiment, the thicknesses of the two are equal. To ensure smooth understanding, the thickness of the metal layer 1021 is defined as the thickness of the first bonding layer 102, and the two are the same concept.

[0018] In some embodiments, the thickness of the first bonding layer 102 is 0.3-3 um, if it is less than 0.3 um, the first bonding layer 102 is too thin, and the bonding effect is weak, if it is more than 3 um, the first bonding layer 102 is too thick, which is not conducive to heat dissipation and controlling the size of the micro light emitting element 100, and the cost is too high. In this embodiment, the thickness of the first bonding layer 102 is 0.5 um.

[0019] The material of the metal layer 1021 is a metal conductive material, including but not limited to one or a combination of several of Cr, Al, Ti, Pt, Au, Sn, Cu, Ag, and the material of the insulating layer 1022 is an insulating material, including but not limited to one or a combination of several of SiOx, SiNx, Al2O3, MgF2, SiF4, and NbOx.

[0020] The second bonding layer 103 is arranged above the first bonding layer 102, and the second bonding layer 103 includes a dielectric layer 1032 and a via 1031 filled with a conductive material such as one or a combination of several of Cr, Al, Ti, Pt, Au, Sn, Cu, Ag, and Ni. The material of the dielectric layer 1031 is an insulating dielectric material, which can be one or a combination of several of SiO2, Si3N4, Al2O3, MgF2, and SiF4. Through such a design, the metal layer 1021 of the first bonding layer 102 is electrically connected to the second bonding layer 103 through the via 1031, while the first bonding layer 102 and the second bonding layer 103 cannot be electrically connected in other parts. Without etching the first and second bonding layers, the epitaxial layer 104 is isolated, reducing product problems caused by process difficulty.

[0021] In some embodiments, the medium layer 1032 is an insulating transparent material, and the metal layer 1021 is a metal or alloy with a reflectivity of >60%. Further, the medium layer 1032 is one or a combination of SiOx, TiOx, Al2O3, NbOx, SiNx, and the metal layer 1021 is one or a combination of Al, Ag, Au, Cu, Mo. According to this design, the upper medium layer 1032 and the lower metal layer 1021 form an omnidirectional reflector (ODR) structure, which reflects small-angle light through the transparent insulating material and fills in the ability to reflect large-angle light through the highly reflective metal material, thereby reflecting in all directions. Thus, the light brightness of the micro light emitting element is improved. In this embodiment, the medium layer 1032 is SiOx, and the metal layer 1021 is Ag.

[0022] In some embodiments, the thickness of the second bonding layer 103 is in the range of 0.3-3 um. If it is less than 0.3 um, the second bonding layer 103 is too thin, and the bonding effect is weak. If it is more than 3 um, the second bonding layer 103 is too thick, which is not conducive to heat dissipation and controlling the size of the micro light emitting element 100, and the cost is too high. In this embodiment, the thickness of the second bonding layer 103 is in the range of 0.5 um.

[0023] The epitaxial layer 104 is arranged on the second bonding layer 103, and the epitaxial layer 104 is sequentially arranged from the direction away from the driving substrate as the second semiconductor layer 107, the active layer 106, and the first semiconductor layer 105.

[0024] The second semiconductor layer 107 is arranged above the second bonding layer 103, which can be a P-type semiconductor layer, such as the P-type GaN used in this embodiment, and can also be AlGaN, InGaN, GaAs, AlGaAS, AlGaInP, InGaAs, etc. according to different requirements.

[0025] The active layer 106 is arranged above the second semiconductor layer 107, which can be a multiple quantum well (MQW) structure.

[0026] The first semiconductor layer 105 is arranged above the active layer 106, which can be an N-type semiconductor layer, such as the N-type GaN used in this embodiment, and can also be AlGaN, InGaN, GaAs, AlGaAS, AlGaInP, InGaAs, etc. according to different requirements.

[0027] In some embodiments, the orthographic projection of the metal layer 1021 in the first bonding layer 102 is at least 90% within the orthographic projection range of the second semiconductor layer 107, which can ensure that most of the metal layer 1021 is directly below the epitaxial layer 104, improve the conductivity, and thus improve the light emitting intensity. In this embodiment, the orthographic projection of the metal layer 1021 is completely within the orthographic projection range of the second semiconductor layer 107. As shown in FIG. 1B, the orthographic projection of the metal layer 1021 is completely within the orthographic projection range of the second semiconductor layer 107.Figure 6 The four concentric circles are shown, the dashed line of the inner circle is the edge of the metal layer 1021, the solid line of the outer circle is the edge of the second semiconductor layer 107, and the dashed line is completely within the solid line, that is, the orthographic projection of the metal layer 1021 is completely within the orthographic projection range of the second semiconductor layer 107.

[0028] Reference Figure 3 , Figure 3 As Figure 2 is a partial enlarged schematic view, and numerical annotations are used. Select any metal layer 1021, point a is the leftmost point of the bottom surface of the metal layer, point b is the rightmost point of the bottom surface of the metal layer, the length L1 of the ab line is the width of the metal layer 1021, and similarly, the length L2 of the bc line at the end of the insulating layer 1022 is the width of the insulating layer 1022. In the present application, the width L2 of the insulating layer 1022 is also the spacing width between adjacent metal layers 1021, that is, the insulating layer 1022 completely fills the spacing between adjacent metal layers 1021.

[0029] In some embodiments, the width L1 of each metal layer 1021 is in the range of 0.5-50 μm, and the width (i.e. the spacing width between adjacent metal layers 1021) L2 of the insulating layer 1022 is in the range of 0.5-50 μm, which can further optimize the electrical isolation between the epitaxial layers 104. In the present embodiment, L1 is 2 μm and L2 is 3 μm.

[0030] In some embodiments, the orthographic projection area of the plurality of through holes 1031 of the second bonding layer 103 on the metal layer 1021 accounts for 1 / 5-2 / 3 of the area of the metal layer itself. Within this range, the electrical connection of the second bonding layer 103 and the first bonding layer 102 and the electrical isolation of adjacent epitaxial layers can be balanced. If the proportion is less than 1 / 5, only a small part of the first and second bonding layers is electrically connected, which is not conducive to light emission. On the other hand, if the proportion is greater than 2 / 3, the plurality of through holes 1031 are arranged closely, which is not conducive to the electrical isolation of adjacent through holes 1031, thereby affecting the electrical isolation of adjacent epitaxial layers 104. Moreover, when the proportion is greater than 2 / 3, the proportion of the dielectric layer 1032 above the metal layer 1021 will be less than 1 / 3, the area of the ODR total reflection mirror is small, and the light generating capacity of the reflective epitaxial layer 104 is weakened, which is not conducive to the improvement of light emission brightness.

[0031] As Figure 5 shown, Figure 5 is a top view schematic diagram of the metal layer 1021 and the through hole 1031 in the present embodiment. The large circle 1021 is the metal layer, and the small circle 1031 is the through hole. The proportion of the part of the through hole 1031 falling within the metal layer 1021 to the area of the metal layer 1021 itself is 1 / 5-2 / 3.

[0032] Reference Figure 3 , Figure 4In some embodiments, the cross-sectional width D1 of each via 1031 is greater than 0.25 μm and less than the spacing L3 between adjacent epitaxial layers 104. If it is less than 0.25 μm, the area that the first and second bonding layers can conduct electricity is too small, affecting the luminous efficiency; if it is greater than L3, the via 1031 will cross the spacing L3 between adjacent epitaxial layers 104 and conduct electricity to the adjacent epitaxial layers 104, making it impossible to achieve independent control of a single luminescent epitaxial layer.

[0033] refer to Figure 3 , Figure 4 In some embodiments, the spacing D2 between any two adjacent vias 1031 (i.e., the width of the dielectric layer 1032) is greater than 0.5 μm and less than the width L1 of the metal layer 1021. If it is less than 0.5 μm, the adjacent vias 1031 are too close together and are easily connected, thus failing to achieve isolation; if it is greater than L1, the dielectric layer 1032 may span a complete metal layer 1021, causing the epitaxial layer 104 to fail to be electrically connected to the underlying driving substrate 101, thus preventing it from emitting light.

[0034] Several epitaxial layers 104 are arranged at a certain distance L3, and in some embodiments, L3 ranges from 0.5 μm to 20 μm.

[0035] like Figure 3 As shown, in some embodiments, the epitaxial sidewall 140 has a horizontal angle α with the driving substrate 101, which ranges from 45° to 85°. An appropriate angle is beneficial for LED light emission and subsequent coverage by the passivation layer 108 and the N-electrode layer 109, reducing the risk of delamination. It should be noted here that the epitaxial sidewall 140 is defined as any sidewall of the first semiconductor layer 105, the active layer 106, or the second semiconductor layer 107.

[0036] In some embodiments, the width of the epitaxial layer 104 gradually increases from top to bottom, with the uppermost first semiconductor layer 105 having the smallest width on its upper surface and the lowermost second semiconductor layer 107 having the largest width on its lower surface.

[0037] refer to Figure 2 In some embodiments, a transparent conductive layer 110 is further disposed between the second semiconductor layer 107 and the second bonding layer 103. This layer can be made of materials such as ITO, TCO, and IZO. In this embodiment, ITO is used as the transparent conductive layer 110 to optimize the conductivity between the epitaxial layer 104 and the second bonding layer 103.

[0038] A passivation layer 108 is disposed on the surface of the second bonding layer 103 and outside the epitaxial layer 104 to protect the epitaxial layer 104. The passivation layer 108 is made of an insulating material, including but not limited to one or a combination of SiO2, Si3N4, Al2O3, MgF2, and SiF4. In this embodiment, the passivation layer 108 is made of Al2O3 and SiO2. The passivation layer 108 is partially opened on the surface of the epitaxial layer 104 and the surface of the second bonding layer 103 at the periphery 130 of the driving substrate 101 to connect with the electrodes. The size of the opening is adjusted according to the electrodes and is not limited here.

[0039] The micro light emitting element 100 further includes an N electrode layer 109 made of a metal conductive material, which can be one or a combination of Cr, Al, Ti, Pt, Au, Sn, Cu, and Ag, and is disposed on the passivation layer 108.

[0040] Referring to Figure 2 and Figure 6 , the N electrode layer 109 surrounds the outside of the driving substrate 101 and connects the surface of the first semiconductor layer 105 to connect the epitaxial layers 104 as a common N electrode. The connection principle is that the N-type electrical contact point 112 is disposed at the periphery 130 of the driving substrate 101, the N electrode layer 109 is electrically connected to the second bonding layer 103 through the partial opening of the passivation layer 108, is in ohmic contact with the N-type electrical contact point 112 of the driving substrate 101 through electrical connection with the conductive via 1031 and the metal layer 1021, and realizes common N electrode conduction with the first semiconductor layer 105 of each epitaxial layer 104. On the other hand, the epitaxial layers 104 are disconnected, the conductive vias 1031 of the second bonding layer 103 are arranged at intervals, and the first bonding layer 102 is electrically isolated by the insulating layer 1021. Therefore, the second semiconductor layers 107 of the epitaxial layers 104 are electrically isolated from each other, are connected to the P-type electrical contact point 111 on the driving substrate 101, and complete the P electrode conduction of each epitaxial layer 104 to realize the function of independent control of light emission. The P-type electrical contact point 111 is disposed below the epitaxial layers 104, and the N-type electrical contact point 112 surrounds the outside of the driving substrate 101.

[0041] Referring to Figure 6 , the N electrode layer 109 surrounds the outside of the driving substrate 101 as a common N electrode of the four epitaxial layers 104.

[0042] In some embodiments, a step is disposed on the surface of the first semiconductor layer 105, which is slightly lower than the flat surface of the first semiconductor layer 105 without the step, and part of the N electrode layer 109 is disposed on the step. This design is adopted in this embodiment to make the N electrode layer more easily adhere to the first semiconductor layer 105.

[0043] In some embodiments, the cross-sectional width of the transparent conductive layer 110 is longer than the cross-sectional width of the second semiconductor layer 107.

[0044] Beneficial effects: The present application proposes a micro light emitting element 100, the first bonding layer 102 is arranged as a metal layer 1021 arranged at intervals, the metal layer 1021 is disconnected by an insulating layer 1022; the second bonding layer 103 is a dielectric layer 1032 with a conductive via 1031, which is conductive at the via 1031, and the dielectric layer 1032 is insulating. Such design makes the two adjacent epitaxies 104 electrically isolated, so compared with the prior art, there is no need to etch the bonding layer, effectively avoiding problems such as over-etching, incomplete etching, and sidewall metal residue, improving the product yield of Micro LED. In addition, in some embodiments, the dielectric layer 1032 in the second bonding layer 103 and the metal layer in the first bonding layer form an ODR (Omni-directional reflector) total reflector, which improves the light reflection ability, is conducive to the light emitting from the front of the epitaxial layer 104, greatly improves the light emission efficiency, and improves the luminous brightness. Embodiment 2

[0045] In order to prepare the micro light emitting element of embodiment 1 described above, the present application also proposes an embodiment of a preparation method of a micro light emitting element, which is specifically described with reference to Figures 7 to 16 .

[0046] Referring to Figure 7 , a driving substrate 101 is provided, and in the present embodiment, the driving substrate 101 adopts a CMOS substrate, and TFT glass substrate and other substrates with driving circuit can be selected according to requirements. The CMOS substrate 101 has a plurality of electrical contacts, including a plurality of P-type electrical contacts 111 and a plurality of N-type electrical contacts 112. An insulating material is deposited on the CMOS substrate 101, which is SiO2 in the present embodiment, to form an insulating layer 1022. A photolithography process is used to obtain a patterned insulating layer 1022, which exposes the driving substrate 101. Referring to Figure 8 , a metal material is deposited on the CMOS substrate 101 obtained in the above step to form a metal layer 1021. The metal material can be a single layer or a stack of Cr, Al, Ti, Pt, Au, Sn, and Cu. Subsequently, the excess metal material on the surface is removed until the insulating layer 1022 is exposed. The insulating layer 1022 and the metal layer 1021 are almost level, with a difference controlled within ±3%, and in the present embodiment, they are level.

[0047] Referring to Figure 9, provide an LED growth substrate 200, which can be sapphire, silicon, gallium nitride, silicon carbide, aluminum nitride, etc. substrate, and the embodiment adopts sapphire substrate. Grow a first semiconductor layer 105, an active layer 106, a second semiconductor layer 107 on the growth substrate 200, then deposit a layer of transparent conductive layer 110, and the embodiment adopts ITO material, and evaporate a layer of dielectric layer 1032 as a second bonding layer 103 on the transparent conductive layer 110. The dielectric material can be one or a combination of SiO2, Si3N4, Al2O3, MgF2, SiF4, and the embodiment adopts SiO2.

[0048] Referring to Figure 10 — Figure 11 , a plurality of through holes are obtained through the dielectric layer 1032 by using a photolithography process, and a metal conductive material is filled in the through holes 1031, and the through holes 1031 and the dielectric layer 1032 together form a second bonding layer; Referring to Figure 12 — Figure 13 , the first bonding layer 102 and the second bonding layer 103 are bonded by using a wafer bonding process, such as hot pressing, and the LED growth substrate 200 is peeled off, and the peeling method can be laser peeling, chemical peeling, and mechanical grinding.

[0049] Referring to Figure 14 , the epitaxial layer 104 is etched until the transparent conductive layer 110 is exposed, and a plurality of completely disconnected epitaxial layers 104 are obtained. The specific etching method can be dry etching or ion beam etching, plasma etching, etc., and the embodiment adopts ion beam etching.

[0050] In some embodiments, after the above steps, a step is etched on the surface of the first semiconductor layer 105, and the height of the step is lower than the height of the unetched surface of the first semiconductor layer 105.

[0051] In some embodiments, the etching rate and angle of the LED epitaxial layer 104 are controlled, and the horizontal angle of the sidewall of the epitaxial layer 104 after etching is in the range of 45°-85° with the transparent conductive layer 110.

[0052] Referring to Figure 15 , continue to etch the transparent conductive layer 110 downward until the second bonding layer 103 is exposed. In some embodiments, the cross-sectional width of the transparent conductive layer 110 after etching is greater than the cross-sectional width of the second semiconductor layer 107.

[0053] Referring to Figure 16After the above steps, insulating material is deposited to form a passivation layer 108, and openings are made on the surface of the epitaxial layers and part of the surface of the second bonding layer. The material can be SiO2, Si3N4, Al2O3. In this embodiment, SiO2 and Al2O3 are used. Finally, conductive metal material, such as one or more of Cr, Al, Ti, Pt, Au, Sn, etc., is deposited to form an N electrode layer 109. In this embodiment, the metal material is a Cr, Pt, Au metal stack. The N electrode layer is electrically connected to the first semiconductor layer 105 of each epitaxial layer 104, and each adjacent epitaxial layer 104 is connected through the N electrode layer 109. The N electrode layer 109 surrounds the driving substrate 101 to form a common N electrode.

[0054] In some embodiments, the material of the metal layer 1021 is selected from a metal or alloy with reflectivity > 60%, and the material of the dielectric layer 1032 is an insulating transparent material. Further, the material of the metal layer 1021 is one or a combination of Al, Ag, Au, Cu, Mo, and the material of the dielectric layer 1032 is one or a combination of SiOx, TiOx, Al2O3, NbOx, SiNx. Such a design can make the dielectric layer and the underlying metal layer form an ODR mirror structure, improving the light brightness of the micro light emitting element.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the same. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements to some or all of the technical features. Such modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A micro light emitting diode, comprising: a driving substrate; a first bonding layer disposed on the driving substrate, the first bonding layer comprising metal layers arranged at intervals and insulating layers disposed between the metal layers; a second bonding layer disposed on the first bonding layer, the second bonding layer comprising a dielectric layer and a plurality of through holes, the plurality of through holes penetrating the dielectric layer, the through holes being filled with conductive material, and the dielectric layer being an insulating material; a plurality of epitaxial layers disposed on the second bonding layer at intervals, each epitaxial layer comprising: a second semiconductor layer disposed on the second bonding layer; an active layer disposed on the second semiconductor layer; and a first semiconductor layer disposed on the active layer; a passivation layer disposed on the outer walls of the epitaxial layers and the second bonding layer, and having openings on the upper surfaces of the epitaxial layers and the second bonding layer; and an N electrode layer disposed above the passivation layer. The orthographic projection of the metal layer is at least 90% within the orthographic projection range of the second semiconductor layer. The width of the metal layer ranges from 0.5 to 50 μm, and the width of the insulating layer ranges from 0.5 to 50 μm. The dielectric layer is an insulating transparent material, and the metal layer is a metal or alloy with a reflectivity of > 60%. The dielectric layer is one or a combination of SiOx, TiOx, Al2O3, NbOx, and SiNx, and the metal layer is one or a combination of Al, Ag, Au, Cu, and Mo. The area of the orthographic projection of the plurality of through holes on the metal layer accounts for 1 / 5 to 2 / 3 of the area of the metal layer. The cross-sectional width of any through hole is greater than 0.25 μm and less than the interval between adjacent epitaxial layers. The interval between any two adjacent through holes is greater than 0.5 μm and less than the width of the metal layer.

2. The micro light emitting element according to claim 1, characterized by, The interval between the plurality of epitaxial layers ranges from 0.5 to 20 μm.

3. The micro light emitting element according to claim 1, characterized by, The thickness of the first bonding layer ranges from 0.3 to 3 μm.

4. The micro light emitting element according to claim 1, wherein The thickness of the second bonding layer ranges from 0.3 to 3 μm.

5. The micro light emitting element according to claim 4, wherein The epitaxial side walls have an inclination angle with respect to the horizontal plane of the driving substrate, and the inclination angle ranges from 45° to 85°.

6. The micro light emitting element according to claim 1, wherein The epitaxial layers gradually widen from top to bottom, with the upper surface of the first semiconductor layer being the narrowest and the lower surface of the second semiconductor layer being the widest.

7. The micro light emitting element according to claim 1, wherein A transparent conductive layer is disposed between the second semiconductor layer and the second bonding layer.

8. The micro light emitting element according to claim 1, wherein The N electrode layer surrounds the entire periphery of the LED driving substrate and encloses the plurality of LED units on the driving substrate, forming a common N electrode for the plurality of LED units.

9. The micro light emitting element according to claim 1, wherein 16.A method for manufacturing a micro light emitting diode, comprising: S1 providing a driving substrate, depositing an insulating material on the driving substrate to form an insulating layer, and using a photolithography process to obtain a patterned insulating layer and expose the driving substrate; and S2 depositing a metal material on the driving substrate, and subsequently removing excess metal material on the surface of the insulating layer until the surface of the insulating layer is exposed, the metal material forming a metal layer, and the metal layer and the insulating layer constituting a first bonding layer.

10. The micro light emitting element according to claim 1, wherein ​ 11. The micro light emitting element according to claim 1, wherein ​ 12. The micro light emitting element according to claim 1, wherein ​ 13. The micro light emitting element according to claim 1, wherein ​ 14. The micro light emitting element according to claim 1, wherein ​ 15. The micro-LED element according to claim 1, wherein, ​ ​ ​ ​ ​ S3 provides an LED growth substrate, grows an epitaxial layer on the LED substrate, and sequentially forms a first semiconductor layer, an active layer, and a second semiconductor layer; a layer of transparent conductive layer is deposited on the second semiconductor layer, and a dielectric layer is formed by evaporating dielectric material on the surface of the transparent conductive layer; S4 uses a photoetching and etching process to obtain a plurality of through holes penetrating the dielectric layer, fills the through holes with conductive material, and the through holes and the dielectric layer together form a second bonding layer; S5 uses a bonding process to bond the first bonding layer and the second bonding layer in one plane, and combines the LED wafer and the driving substrate; S6 peels off the LED substrate; S7 etches the LED epitaxial layer until the transparent conductive layer is exposed, and a plurality of completely disconnected epitaxial layers are obtained; S8 etches the transparent conductive layer until the second bonding layer is exposed; S9 deposits an insulating material to form a passivation layer, and forms a part of the opening on the surface of the epitaxial layer and the second bonding layer; S10 deposits a metal conductive material to form an N electrode layer, the N electrode layer is electrically connected with the first semiconductor layer of each epitaxial layer, and the plurality of epitaxial layers are connected through the N electrode layer, and the N electrode layer surrounds the periphery of the driving substrate.

17. The method of claim 16, wherein the micro-LED is formed by a process comprising: The material of the metal layer in S2 is a metal or alloy with a reflectivity of >60%, and the dielectric layer in S3 is an insulating transparent material. ​ 18. The method for fabricating a micro-light-emitting element according to claim 17, characterized in that, The material of the metal layer in S2 is one or a combination of several of Al, Ag, Au, Cu, and Mo, and the material of the dielectric layer in S3 is one or a combination of several of SiOx, TiOx, Al2O3, NbOx, and SiNx.

19. The method of claim 16, wherein, In S6, the etching rate and angle of the LED epitaxial layer are controlled, and the horizontal angle between the sidewall of the epitaxial layer and the transparent conductive layer is between 45° and 85° after etching.

20. The method of claim 16, wherein, In S6-S7, the amount of etching dielectric is controlled, and the etched part from the top surface of the first semiconductor layer to the bottom surface of the second bonding layer is less and less.

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