Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a substrate, forming a dummy gate and a first interlayer dielectric layer surrounding the sidewall of the dummy gate on the substrate, removing the dummy gate, and forming a first trench in the first interlayer dielectric layer; forming a sacrificial layer on the sidewall of the first trench; forming a first metal layer in the first trench; removing part of the thickness of the first metal layer to form a second trench; removing the sacrificial layer to form a gap between the sidewall of the first metal layer and the sidewall of the first trench; and forming a second metal layer, which fills the gap and the second trench, and the second metal layer and the first metal layer jointly form a metal gate. The application removes the residues caused by planarization by removing part of the thickness of the first metal layer, and forms the second metal layer covering the top and sidewall of the first metal layer, so that even if there are residues in the first metal layer, the metal gate will not fail due to the presence of the second metal layer.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of integrated circuit technology, device size continues to shrink. In the manufacturing process of advanced logic circuit chips, the gate material will be replaced by metals such as aluminum and tungsten to avoid the depletion effect of polysilicon gates, which would cause transistor switching delay and thus limit the operating frequency of the device.

[0003] In the fabrication of metal gates, existing processes mostly involve forming a dummy gate and an interlayer dielectric layer on a substrate, removing the dummy gate to form a trench within the interlayer dielectric layer, filling the trench with metal material, and then performing chemical mechanical polishing (CMP) on the metal material to ultimately form the metal gate within the trench. However, CMP leaves polishing slurry residue, which can corrode aluminum when the metal material is aluminum, leading to metal gate failure. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which can prevent metal gate failure.

[0005] To address the aforementioned technical problems, according to a first aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising the following steps:

[0006] A substrate is provided, a dummy gate and a first interlayer dielectric layer surrounding the sidewalls of the dummy gate are formed on the substrate, the dummy gate is removed, and a first trench is formed in the first interlayer dielectric layer;

[0007] A sacrificial layer is formed on the sidewall of the first trench;

[0008] A first metal material layer is formed, which fills the first trench and covers the first interlayer dielectric layer. The first metal material layer is planarized to expose the first interlayer dielectric layer and the sacrificial layer, thereby forming the first metal layer.

[0009] A portion of the thickness of the first metal layer is removed to form a second trench;

[0010] Remove the sacrificial layer to form a gap between the sidewall of the first metal layer and the sidewall of the first trench; and,

[0011] A second metal layer is formed, which fills the gap and the second trench. The second metal layer and the first metal layer together constitute a metal gate. The corrosion rate of the planarized residue on the second metal layer is less than the corrosion rate on the first metal layer.

[0012] Optionally, a method for forming a sacrificial layer on the sidewall of the first trench includes:

[0013] A sacrificial material layer is conformally deposited on the surfaces of the first trench and the first interlayer dielectric layer; and...

[0014] The sacrificial material layer is etched back to retain the sacrificial material layer on the sidewall of the first trench as the sacrificial layer.

[0015] Optionally, a method for forming a second metal layer that fills the gap and the second trench includes:

[0016] A second metallic material layer is formed, which fills the gaps and the second trench and covers the first interlayer dielectric layer; and...

[0017] The second metal material layer is planarized to expose the first interlayer dielectric layer, and a second metal layer is formed in the gap and the second trench.

[0018] Optionally, the method of forming a dummy gate and a first interlayer dielectric layer surrounding the sidewalls of the dummy gate on the substrate includes:

[0019] A gate dielectric material layer and a virtual gate material layer are formed on the substrate;

[0020] The virtual gate material layer and the gate dielectric material layer are etched to form the virtual gate and the gate dielectric layer; and,

[0021] A first interlayer dielectric layer is formed on the substrate on both sides of the virtual gate and the gate dielectric layer.

[0022] Optionally, after forming the dummy gate and before forming the first interlayer dielectric layer, the method further includes: forming a sidewall between the dummy gate and the sidewall of the gate dielectric layer.

[0023] Optionally, after forming the first trench and before forming the sacrificial layer, the method further includes: forming a functional metal layer on the sidewalls and bottom of the first trench.

[0024] Optionally, after forming the metal gate, the process further includes:

[0025] A second interlayer dielectric layer is formed, which covers the first interlayer dielectric layer and the metal gate.

[0026] Etching the second interlayer dielectric layer forms contact holes that expose the metal gate; and,

[0027] A barrier layer is formed on the sidewall of the contact hole, and metal is filled into the contact hole to form a metal plug.

[0028] Optionally, the material of the first metal layer includes aluminum, and the material of the second metal layer includes tungsten.

[0029] To solve the above-mentioned technical problems, according to a second aspect of the present invention, a semiconductor device is provided, which is manufactured using the semiconductor device fabrication method described above, the semiconductor device comprising:

[0030] Substrate;

[0031] A first interlayer dielectric layer is located on the substrate, and a first trench exposing the substrate is formed within the first interlayer dielectric layer; and,

[0032] A metal gate is located within the first trench. The metal gate includes a first metal layer and a second metal layer, wherein the second metal layer covers the sidewalls and top of the first metal layer.

[0033] Optionally, the material of the first metal layer includes aluminum, and the material of the second metal layer includes tungsten.

[0034] In summary, the semiconductor device and its fabrication method provided by the present invention firstly provide a substrate, on which a dummy gate and a first interlayer dielectric layer surrounding the sidewalls of the dummy gate are formed. The dummy gate is removed, and a first trench is formed in the first interlayer dielectric layer. Next, a sacrificial layer is formed on the sidewalls of the first trench, and then a first metal material layer is formed. The first metal material layer fills the first trench and covers the first interlayer dielectric layer. The first metal material layer is planarized to expose the first interlayer dielectric layer and the sacrificial layer to form a first metal layer. Then, a portion of the thickness of the first metal layer is removed to form a second trench. Next, the sacrificial layer is removed, and a gap is formed between the sidewalls of the first metal layer and the sidewalls of the first trench. Then, a second metal layer is formed, which fills the gap and the second trench. The second metal layer and the first metal layer together constitute a metal gate. The unexpected effect of this invention is that by removing a portion of the thickness of the first metal layer to form a second trench, residues on the first metal layer after planarization can be removed. After forming the first trench, a sacrificial layer is formed on the sidewall of the first trench. After filling the first trench with the first metal layer, removing the sacrificial layer can create a gap between the sidewall of the first metal layer and the sidewall of the first trench. Forming a second metal layer in the second trench and the gap allows the second metal layer to cover the top and sidewall of the first metal layer. The corrosion rate of the planarized residue on the second metal layer is less than that on the first metal layer, meaning that the residue does not easily corrode the second metal layer or causes very little corrosion. This can prevent the failure of the metal gate. Furthermore, since the second metal layer covers the top and sidewall of the first metal layer, even if there are still residues in the first metal layer, the presence of the second metal layer will prevent the metal gate from failing. Attached Figure Description

[0035] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of the structure after forming a virtual gate and a first interlayer dielectric layer according to an embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of the structure after the formation of the first trench according to an embodiment of the present invention.

[0038] Figure 4 This is a schematic diagram of the structure after the formation of the sacrificial material layer according to an embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram of the structure after the formation of the sacrificial layer according to an embodiment of the present invention.

[0040] Figure 6 This is a schematic diagram of the structure after the formation of the first metal material layer according to an embodiment of the present invention.

[0041] Figure 7 This is a schematic diagram of the structure after the formation of the first metal layer according to an embodiment of the present invention.

[0042] Figure 8 This is a schematic diagram of the structure after the formation of the second trench according to an embodiment of the present invention.

[0043] Figure 9 This is a schematic diagram of the structure after the gap is formed, according to an embodiment of the present invention.

[0044] Figure 10 This is a schematic diagram of the structure after the formation of the second metal material layer according to an embodiment of the present invention.

[0045] Figure 11 This is a schematic diagram of the structure after the formation of the second metal layer according to an embodiment of the present invention.

[0046] Explanation of reference numerals in the attached figures:

[0047] 10-Substrate; 11-Gate dielectric layer; 12-Dummy gate; 13-Sidewall; 14-First interlayer dielectric layer; 15-First trench; 16-Work function metal layer; 17-Sacrificial material layer; 18-Sacrificial layer; 19-First metal material layer; 20-First metal layer; 21-Second trench; 22-Gap; 23-Second metal material layer; 24-Second metal layer. Detailed Implementation

[0048] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0049] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0050] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Please refer to... Figure 1 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention includes the following steps:

[0051] S1: Provide a substrate, form a dummy gate and a first interlayer dielectric layer surrounding the sidewalls of the dummy gate on the substrate, remove the dummy gate, and form a first trench in the first interlayer dielectric layer;

[0052] S2: A sacrificial layer is formed on the sidewall of the first trench;

[0053] S3: Form a first metal material layer, the first metal material layer fills the first trench and covers the first interlayer dielectric layer, planarize the first metal material layer to expose the first interlayer dielectric layer and the sacrificial layer, and form a first metal layer;

[0054] S4: Remove a portion of the thickness of the first metal layer to form a second trench;

[0055] S5: Remove the sacrificial layer to form a gap between the sidewall of the first metal layer and the sidewall of the first trench; and

[0056] S6: A second metal layer is formed, which fills the gap and the second trench. The second metal layer and the first metal layer together constitute a metal gate. The corrosion rate of the planarized residue on the second metal layer is less than the corrosion rate on the first metal layer.

[0057] Figures 2 to 11 This is a schematic diagram illustrating the structural steps of a semiconductor device fabrication method according to an embodiment of the present invention. Next, we will combine... Figure 1 and Figures 2 to 11 The method for fabricating the semiconductor device provided in the embodiments of the present invention will be described in detail.

[0058] In step S1, please refer to Figure 2 and Figure 3 As shown, a substrate 10 is provided, on which a dummy gate 12 and a first interlayer dielectric layer 14 surrounding the sidewalls of the dummy gate 12 are formed. The dummy gate 12 is removed, and a first trench 15 is formed in the first interlayer dielectric layer 14.

[0059] The substrate 10 can be made of silicon, germanium, germanium-silicon, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is preferably made of silicon. An isolation structure can be formed within the substrate 10 to isolate different semiconductor devices; the isolation structure can be a shallow trench isolation structure or a localized silicon oxide isolation structure. Various traps can also be formed within the substrate 10.

[0060] Please refer to Figure 2 As shown, firstly, a gate dielectric material layer and a dummy gate material layer are formed on the substrate 10. A patterned mask layer is then formed on the dummy gate material layer. Using the patterned mask layer as a mask, the dummy gate material layer and the gate dielectric material layer are etched to form a dummy gate 12 and a gate dielectric layer 11. Afterward, the patterned mask layer is removed. The patterned mask layer can be a photoresist layer or a hard mask layer such as silicon oxide or silicon nitride.

[0061] In one embodiment, the gate dielectric layer 11 is made of silicon oxide or a high-k dielectric material. The high-k dielectric material includes, but is not limited to, hafnium oxide, hafnium silicon oxide, hafnium oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, and aluminum oxide. In this embodiment, the high-k dielectric material is preferably hafnium oxide, zirconium oxide, or aluminum oxide. The gate dielectric material layer can be formed using any suitable process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The virtual gate 12 is made of at least one of the following: polycrystalline silicon (including doped polycrystalline silicon and / or undoped polycrystalline silicon), amorphous silicon (including doped amorphous silicon and / or undoped amorphous silicon), amorphous carbon, photoresist, or metal silicide. The virtual gate material layer can be formed using any suitable process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0062] In one embodiment, after forming the virtual gate 12, a sidewall material layer can be formed on the surfaces of the virtual gate 12 and the substrate 10. The sidewall material layer covers the top of the virtual gate 12, the sidewalls of the virtual gate 12 and the gate dielectric layer 11, and the surface of the substrate 10. The sidewall material layer is then etched to form a sidewall 13 located on the sidewalls of the virtual gate 12 and the gate dielectric layer 11. The sidewall material layer can be formed using any suitable process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The sidewall 13 can be a single-layer structure or a multi-layer stacked structure. The material of the sidewall 13 includes, but is not limited to, oxides and / or nitrides. Before or after forming the sidewall 13, source / drain regions can be formed in the substrate 10 on both sides of the virtual gate 12 using an ion implantation process.

[0063] Next, a first interlayer dielectric material layer is deposited on the surfaces of the substrate 10, the sidewalls 13, and the dummy gate 12. This first interlayer dielectric material layer includes, but is not limited to, silicon dioxide, silicon oxynitride, tetraethyl orthosilicate (TEOS), low-k dielectric materials with a dielectric constant less than that of silicon dioxide, and metal nitride. The first interlayer dielectric material layer can be formed using any suitable process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or coating. The thickness of the first interlayer dielectric material layer on the substrate 10 is greater than the stacked thickness of the gate dielectric layer 11 and the dummy gate 12. The first interlayer dielectric material layer is planarized to form a first interlayer dielectric layer 14 that exposes the top of the dummy gate 12 and the top of the sidewalls 13. The first interlayer dielectric layer 14 surrounds the sidewalls of the dummy gate 12.

[0064] Then, please refer to Figure 2 and Figure 3 As shown, the dummy gate 12 is removed, forming a first trench 15 within the first interlayer dielectric layer 14 to expose the substrate 10. The dummy gate 12 can be removed using dry etching or wet etching. In this embodiment, removing the dummy gate 12 exposes the gate dielectric layer 11; that is, the bottom of the first trench 15 is the gate dielectric layer 11, and the sidewalls of the first trench 15 are sidewalls 13. In another embodiment, the gate dielectric layer 11 can also be removed simultaneously with the dummy gate 12; that is, the bottom of the first trench 15 is the substrate 10, and the sidewalls of the first trench 15 are sidewalls 13. Subsequently, after forming the first trench, the gate dielectric layer is formed at the bottom of the first trench.

[0065] In one embodiment of the present invention, after forming the gate dielectric material layer and before forming the dummy gate material layer, a protective material layer may be formed on the gate dielectric material layer. Using a patterned mask layer as a mask, the dummy gate material layer, the protective material layer, and the gate dielectric material layer are sequentially etched to form a dummy gate 12, a protective layer, and a gate dielectric layer 11. The protective layer protects the gate dielectric layer 11. The material of the protective layer includes, but is not limited to, titanium nitride, tantalum nitride, or other suitable materials, and the protective material layer can be formed using any suitable process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0066] In another embodiment of the present invention, before forming the gate dielectric material layer, an interface material layer may be formed on the substrate 10. When etching is performed subsequently using the patterned mask layer as a mask, the interface material layer is etched to form an interface layer. The material of the interface layer may include silicon oxide. The interface layer is used to improve the interface characteristics between the gate dielectric layer 11 and the substrate 10.

[0067] In step S2, please refer to Figure 5 As shown, a sacrificial layer 18 is formed on the sidewall of the first trench 15.

[0068] In one embodiment of the present invention, please refer to Figure 4 As shown, a work function metal layer 16 is formed before the sacrificial layer 18. The work function metal layer 16 covers the sidewalls and bottom of the first trench 15 and the surface of the first interlayer dielectric layer 14. The work function metal layer 16 on the surface of the first interlayer dielectric layer 14 will be removed during subsequent planarization of the first metal material layer. The material of the work function metal layer 16 includes one or more layers of metal or metal compounds, including any one or more of titanium, tantalum, aluminum, zirconium, hafnium, and their alloys, and may also include carbides, nitrides, etc., of the above-mentioned metal elements. The work function metal layer 16 can be formed using any suitable method, such as radio frequency physical vapor deposition (RFPVD).

[0069] In another embodiment of the present invention, an adhesion layer may be formed before forming the work function metal layer 16. This adhesion layer covers the sidewalls and bottom of the first trench 15 and the surface of the first interlayer dielectric layer 14. The adhesion layer on the surface of the first interlayer dielectric layer 14 is removed during subsequent planarization of the first metal material layer. The material of the adhesion layer includes, but is not limited to, titanium or titanium nitride, to improve the adhesion between the work function metal layer 16 and the subsequently formed sacrificial material layer, the first metal material layer and the protective layer, and the sidewall 13. The adhesion layer can be formed using any suitable process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0070] In one embodiment of the present invention, the method for forming the sacrificial layer 18 includes: first, please refer to... Figure 4 As shown, a sacrificial material layer 17 is conformally deposited on the surfaces of the first trench 15 and the first interlayer dielectric layer 14. The sacrificial material layer 17 covers the sidewalls and bottom of the first trench 15 and the surface of the first interlayer dielectric layer 14 (or the surface of the work function metal layer 16); then, please refer to... Figure 5 As shown, the sacrificial material layer 17 is etched back, retaining the sacrificial material layer 17 on the sidewall of the first trench 15 as the sacrificial layer 18. The material of the sacrificial material layer 17 includes dielectric layers such as silicon nitride and silicon oxide, and of course, it can also be other materials known to those skilled in the art, such as a bottom anti-reflective layer. The sacrificial material layer 17 can be etched using a dry etching process to remove the sacrificial material layer 17 at the bottom of the first trench 15 and on the surface of the first interlayer dielectric layer 14, retaining the sacrificial material layer 17 on the sidewall of the first trench 15 as the sacrificial layer 18.

[0071] In step S3, please refer to Figure 6 and Figure 7 As shown, a first metal material layer 19 is formed, which fills the first trench 15 and covers the first interlayer dielectric layer 14. The first metal material layer 19 is planarized to expose the first interlayer dielectric layer 14 and the sacrificial layer 18, forming a first metal layer 20.

[0072] First refer to Figure 6 As shown, a first metallic material layer 19 is formed, which fills the first trench 15 and covers the first interlayer dielectric layer 14. The first metallic material layer 19 can be formed using any suitable process known to those skilled in the art, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

[0073] Next, please refer to Figure 7 As shown, the first metal material layer 19 is planarized to expose the first interlayer dielectric layer 14 and the sacrificial layer 18, forming a first metal layer 20 within the first trench 15. The planarization includes processes such as chemical mechanical polishing and wet etching. In one embodiment, the adhesion layer and the work function metal layer 16 on the surface of the first interlayer dielectric layer 14 are removed during the planarization process.

[0074] In this embodiment, after planarizing the first metal material layer 19 to form the first metal layer 20, residues, such as polishing slurry or etching solution, may remain on the first metal layer 20. These residues can corrode the first metal layer 20, leading to gate failure if the first metal layer 20 formed at this time is used as a metal gate. For example, when the material of the first metal material layer 19 is aluminum, the polishing slurry will corrode the aluminum. In this embodiment, the material of the first metal material layer 19 includes aluminum or any other metal material suitable for a metal gate but susceptible to corrosion by polishing slurry.

[0075] In step S4, please refer to Figure 8 As shown, a portion of the thickness of the first metal layer 20 is removed to form a second trench 21.

[0076] In this embodiment, a portion of the thickness of the first metal layer 20 is removed by etching back, and a second trench 21 is formed on top of the remaining first metal layer 20. The second trench 21 is formed within the original first trench 15, and the depth and width of the second trench 21 are both smaller than the depth and width of the first trench 15. The bottom of the second trench 21 is the first metal layer 20, and the sidewall is the sacrificial layer 18.

[0077] In step S5, please refer to Figure 8 and Figure 9 As shown, the sacrificial layer 18 is removed, forming a gap 22 between the sidewall of the first metal layer 20 and the sidewall of the first trench 15.

[0078] In this embodiment, a dry etching process can be used to completely remove the sacrificial layer 18, exposing the sidewalls and part of the bottom of the first trench 15, that is, exposing part of the gate dielectric layer 11 at the bottom of the first trench 15 and the sidewalls 13 of the sidewalls of the first trench 15. When the work function metal layer 16 is formed, the gap 22 actually exposes the work function metal layer 16.

[0079] In one embodiment of the present invention, the sacrificial layer 18 may be removed first to form the gap 22, and then a portion of the thickness of the first metal layer 20 may be removed to form the second trench 21. However, considering that removing the sacrificial layer 18 first to form the gap 22 exposes the sidewalls of the first metal layer 20, and that etching back the first metal layer 20 would also affect these sidewalls, it is preferable to form the second trench 21 first and then the gap 22 if etching of the sidewalls of the first metal layer 20 is not desired.

[0080] It should be noted that when the material of the sacrificial layer 18 is the same as that of some material layers on the sidewall of the first trench 15 (e.g., sidewall 13), removing the sacrificial layer 18 will also etch the same material layer. Therefore, to avoid this situation, different formation methods are needed to form layers of the same material with different densities. For example, when the material of the sacrificial layer 18 is silicon oxide, and the material of the sidewall 13 also contains silicon oxide, the sidewall 13 is formed using a furnace tube process, and the sacrificial layer 18 is formed using a chemical vapor deposition process. The sidewall 13 formed in this way is denser than the sacrificial layer 18, and the damage to the sidewall 13 during the removal of the sacrificial layer 18 will be smaller. Furthermore, after the second metal material layer is formed, chemical mechanical polishing can remove some of the damaged sidewall 13.

[0081] Similarly, when the material of the sacrificial layer 18 is the same as that of the first interlayer dielectric layer 14, such as silicon oxide, since the first interlayer dielectric layer 14 is a large area, the etching rate of the first interlayer dielectric layer 14 will be less than the etching rate of the sacrificial layer 18. When the sacrificial layer 18 is removed, the damage to the first interlayer dielectric layer 14 will be relatively small. After the second metal material layer is formed, the damaged first interlayer dielectric layer 14 can be removed by chemical mechanical polishing.

[0082] In step S6, please refer to Figure 10 and Figure 11 As shown, a second metal layer 24 is formed, which fills the gap 22 and the second trench 21. The second metal layer 24 and the first metal layer 20 together constitute a metal gate. The corrosion rate of the planarized residue on the second metal layer 24 is less than the corrosion rate on the first metal layer 20.

[0083] For example, first, please refer to Figure 10 As shown, a second metal material layer 23 is formed, which fills the gap 22 and the second trench 21 and covers the first interlayer dielectric layer 14. Then, please refer to... Figure 11 As shown, the second metal material layer 23 is planarized to expose the first interlayer dielectric layer 14, and a second metal layer 24 is formed within the gap 22 and the second trench 21. The planarization includes processes such as chemical mechanical polishing and wet etching.

[0084] It should be noted that the removal of the sacrificial layer 18 will damage other layers. Therefore, when planarizing the second metal material layer 23, part of the first interlayer dielectric layer 14 can be removed (e.g., it has been polished) to remove the damaged layers.

[0085] The corrosion rate of the planarized residue on the second metal layer 24 is less than that on the first metal layer 20. In other words, the planarized residue on the second metal layer 24 does not easily cause corrosion or causes very little corrosion to the second metal layer 24, thereby avoiding the failure of the metal gate.

[0086] When planarization is performed by chemical mechanical polishing, polishing slurry residue will remain after the chemical mechanical polishing. The corrosion rate of the residual polishing slurry on the second metal layer 24 is less than that on the first metal layer 20, or the residual polishing slurry does not easily cause corrosion to the second metal layer 24 or the corrosion is very small. Therefore, the residual polishing slurry after the second metal material layer 23 is chemically mechanically polished to form the second metal layer 24 will not affect the second metal layer 24, and thus will not affect the final metal gate.

[0087] In this embodiment, the material of the second metal material layer 23 includes tungsten, or any other metal material suitable for metal gates but not easily corroded by residual liquid after planarization.

[0088] The formation and removal of the sacrificial layer 18 creates a gap 22 on the sidewall of the first metal layer 20. A second trench 21 is formed on the top of the first metal layer 20 by etching back the first metal layer 20. A second metal layer 24 is formed within the second trench 21 and the gap 22, surrounding the top and sidewalls of the first metal layer 20. The second metal layer 24 exists throughout the entire vertical direction of the first trench 15, extending from the bottom to the top. Thus, even if residues remain within the first metal layer 20, the presence of the second metal layer 24 prevents metal gate failure.

[0089] Furthermore, the first metal layer 20 and the second metal layer 24 are made of different metal materials, and a portion of the second metal layer 24 is located on top of the first metal layer 20. The thickness of the first metal layer 20 and the second metal layer 24 located on top of the first metal layer 20 can be adjusted to change the content of the first metal layer 20 and the second metal layer 24 in the metal gate. In this embodiment, the thickness of the first metal layer 20 and the second metal layer 24 can be adjusted according to the actual needs of the device.

[0090] After forming the metal gate, the process further includes: forming a second interlayer dielectric layer covering the first interlayer dielectric layer 14 and the metal gate; then etching the second interlayer dielectric layer to form a contact hole exposing the metal gate; then forming a barrier layer on the sidewalls, bottom, and surface of the second interlayer dielectric layer of the via, the barrier layer being made of a titanium layer and a titanium nitride layer on the titanium layer, or a tantalum layer or a tantalum nitride layer on the tantalum layer; then removing the barrier layer on the bottom of the via and the surface of the second interlayer dielectric layer, retaining the barrier layer on the sidewalls of the via, the barrier layer being used to prevent the diffusion of subsequently filled metal into the sidewalls of the via; and then filling the contact hole with metal to form a metal plug.

[0091] In the method for fabricating a semiconductor device provided by the present invention, a substrate 10 is provided, a dummy gate 12 and a first interlayer dielectric layer 14 surrounding the sidewalls of the dummy gate 12 are formed on the substrate 10, the dummy gate 12 is removed, a first trench 15 is formed in the first interlayer dielectric layer 14, a sacrificial layer 18 is formed on the sidewalls of the first trench 15, and a first metal material layer 19 is formed, the first metal material layer 19 fills the first trench 15 and covers the first interlayer dielectric layer 14, the first metal material layer 19 is planarized to expose the first interlayer dielectric layer 14, a first metal layer 20 is formed, a portion of the thickness of the first metal layer 20 and the sacrificial layer 18 is removed, a second trench 21 is formed, the sacrificial layer 18 is then removed, a gap 22 is formed between the sidewalls of the first metal layer 20 and the sidewalls of the first trench 15, and a second metal layer 24 is formed, the second metal layer 24 fills the gap 22 and the second trench 21, the second metal layer 24 and the first metal layer 20 together constitute a metal gate. An unexpected effect of this invention is that by removing a portion of the thickness of the first metal layer 20 to form the second trench 21, residues on the first metal layer 20 after planarization of the first metal material layer 19 can be removed. After forming the first trench 15, a sacrificial layer 18 is formed on the sidewall of the first trench 15. After filling the first metal layer 20 into the first trench 15, removing the sacrificial layer 18 can form a gap 22 between the sidewall of the first metal layer 20 and the sidewall of the first trench 15. The formation of the second metal layer 24 in the second trench 21 and the gap 22 allows the second metal layer 24 to cover the top and sidewall of the first metal layer 20. The corrosion rate of the planarized residue on the second metal layer 24 is less than that on the first metal layer 20, meaning that the residue is not likely to cause corrosion of the second metal layer 24 or the corrosion is very small. This can prevent the failure of the metal gate. Furthermore, since the second metal layer 24 covers the top and sidewall of the first metal layer 20, even if there are still residues in the first metal layer 20, the presence of the second metal layer 24 will prevent the metal gate from failing.

[0092] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0093] Please refer to Figure 11 As shown, the semiconductor device includes:

[0094] Substrate 10;

[0095] A first interlayer dielectric layer 14 is located on the substrate 10, and a first trench 15 is formed within the first interlayer dielectric layer 14 to expose the substrate 10; and,

[0096] A metal gate is located within the first trench 15. The metal gate includes a first metal layer 20 and a second metal layer 24, with the second metal layer 24 covering the sidewalls and top of the first metal layer 20.

[0097] In one embodiment of the present invention, the material of the first metal layer 20 includes aluminum, and the material of the second metal layer 24 includes tungsten.

[0098] In one embodiment of the present invention, a sidewall 13 is formed on the sidewall of the first trench 15, and a gate dielectric layer 11 is formed at the bottom of the first trench 15.

[0099] In one embodiment of the present invention, an active function metal layer 16 is further formed on the sidewall and bottom of the first trench 15.

[0100] In this embodiment, the second metal layer 24 covers the top and sidewalls of the first metal layer 20. Thus, even if there are still residues caused by planarization in the first metal layer 20, the metal gate will not fail due to the presence of the second metal layer 24.

[0101] In summary, the semiconductor device and its fabrication method provided by the present invention firstly provide a substrate, on which a dummy gate and a first interlayer dielectric layer surrounding the sidewalls of the dummy gate are formed. The dummy gate is removed, and a first trench is formed in the first interlayer dielectric layer. Next, a sacrificial layer is formed on the sidewalls of the first trench, and then a first metal material layer is formed. The first metal material layer fills the first trench and covers the first interlayer dielectric layer. The first metal material layer is planarized to expose the first interlayer dielectric layer and the sacrificial layer to form a first metal layer. Then, a portion of the thickness of the first metal layer is removed to form a second trench. Next, the sacrificial layer is removed, and a gap is formed between the sidewalls of the first metal layer and the sidewalls of the first trench. Then, a second metal layer is formed, which fills the gap and the second trench. The second metal layer and the first metal layer together constitute a metal gate. The unexpected effect of this invention is that by removing a portion of the thickness of the first metal layer to form a second trench, residues on the first metal layer after planarization can be removed. After forming the first trench, a sacrificial layer is formed on the sidewall of the first trench. After filling the first trench with the first metal layer, removing the sacrificial layer can create a gap between the sidewall of the first metal layer and the sidewall of the first trench. Forming a second metal layer in the second trench and the gap allows the second metal layer to cover the top and sidewall of the first metal layer. The corrosion rate of the planarized residue on the second metal layer is less than that on the first metal layer, meaning that the residue does not easily corrode the second metal layer or causes very little corrosion. This can prevent the failure of the metal gate. Furthermore, since the second metal layer covers the top and sidewall of the first metal layer, even if there are still residues in the first metal layer, the presence of the second metal layer will prevent the metal gate from failing.

[0102] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate, forming a dummy gate and a first interlayer dielectric layer surrounding the sidewall of the dummy gate on the substrate, removing the dummy gate, forming a first trench in the first interlayer dielectric layer; forming a sacrificial layer on the sidewall of the first trench; forming a first metal material layer, the first metal material layer fills the first trench and covers the first interlayer dielectric layer, planarizing the first metal material layer to expose the first interlayer dielectric layer and the sacrificial layer, and forming a first metal layer; removing part of the thickness of the first metal layer to form a second trench; removing the sacrificial layer to form a gap between the sidewall of the first metal layer and the sidewall of the first trench; and forming a second metal layer, the second metal layer fills the gap and the second trench, and the second metal layer and the first metal layer together form a metal gate; wherein the etching rate of the planarization residue to the second metal layer is less than the etching rate to the first metal layer. The method for forming a sacrificial layer on the sidewall of the first trench comprises:

2. The method of manufacturing a semiconductor device according to claim 1, wherein conformally depositing a sacrificial material layer on the surface of the first trench and the first interlayer dielectric layer; and back-etching the sacrificial material layer to retain the sacrificial material layer on the sidewall of the first trench as a sacrificial layer. The method for forming a second metal layer filling the gap and the second trench comprises:

3. The method of manufacturing a semiconductor device according to Claim 1, wherein forming a second metal material layer, the second metal material layer fills the gap and the second trench and covers the first interlayer dielectric layer; and planarizing the second metal material layer to expose the first interlayer dielectric layer, and forming a second metal layer in the gap and the second trench. The method for forming a dummy gate and a first interlayer dielectric layer surrounding the sidewall of the dummy gate on the substrate comprises:

4. The method of manufacturing a semiconductor device according to Claim 1, wherein forming a gate dielectric material layer and a dummy gate material layer on the substrate; etching the dummy gate material layer and the gate dielectric material layer to form a dummy gate and a gate dielectric layer; and forming a first interlayer dielectric layer on the substrate on both sides of the dummy gate and the gate dielectric layer. After forming the dummy gate, before forming the first interlayer dielectric layer, the method further comprises forming a sidewall on the sidewall of the dummy gate and the gate dielectric layer.

5. The method of manufacturing a semiconductor device according to claim 4, wherein After forming the first trench, before forming the sacrificial layer, the method further comprises forming a function metal layer on the sidewall and the bottom of the first trench.

6. The method of fabricating a semiconductor device according to Claim 1, wherein After forming the metal gate, the method further comprises:

7. The method of fabricating a semiconductor device according to Claim 1, wherein forming a second interlayer dielectric layer covering the first interlayer dielectric layer and the metal gate; etching the second interlayer dielectric layer to form a contact hole exposing the metal gate; and forming a barrier layer on the sidewall of the contact hole and filling metal in the contact hole to form a metal plug. The material of the first metal layer comprises aluminum, and the material of the second metal layer comprises tungsten.

8. The method of manufacturing a semiconductor device according to any one of claims 1 to 7, wherein The semiconductor device is manufactured by using the method for manufacturing a semiconductor device according to any one of claims 1-8, and the semiconductor device comprises:

9. A semiconductor device, characterized by comprising: a substrate; ​ a first interlayer dielectric layer on the substrate, and a first trench is formed in the first interlayer dielectric layer to expose the substrate; and a metal gate in the first trench, the metal gate comprising a first metal layer and a second metal layer, the second metal layer covering a sidewall and a top of the first metal layer.

10. The semiconductor device of claim 9, wherein, The material of the first metal layer comprises aluminum, and the material of the second metal layer comprises tungsten.

Images