Formation method of semiconductor structure
By forming grooves of different depths during the fabrication of microelectromechanical sensors and using a cyclic process to remove the substrate material, the problems of poor heat dissipation and structural damage in suspended structures were solved, thereby improving product yield and structural quality.
Patent Information
- Application Number
- CN202511554600.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-28
- Publication Date
- 2026-01-23
AI Technical Summary
In the fabrication process of microelectromechanical sensors, heat accumulation in suspended structures leads to etching damage to the structural layers, resulting in low thermal conductivity and affecting device design and production. Existing improvement schemes cannot effectively solve the problem of thermal damage caused by high aspect ratio etching and structural release, resulting in low product yield.
By forming a first groove and an initial second groove of different depths, a cyclic process is used to remove the first substrate at the bottom of the initial second groove, including thermal oxidation and wet etching processes, to gradually remove excess material, forming a suspended structure, improving heat dissipation and maintaining structural quality.
It effectively solved the problem of poor heat dissipation in suspended structures, improved the morphology and structural quality of semiconductor structures, increased product yield, and reduced defects.
Smart Images
Figure CN121376904A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] In micro-electro-mechanical systems (MEMS) technology, SOI (solid-in-place) technology, which combines surface silicon (SSI) and bulk silicon (BIS) processes, has gradually become the mainstream manufacturing technology for high-end MEMS. In MEMS devices such as inertial sensors, micromirrors, and RF switches, suspended structures (such as mass blocks, movable beams, and movable combs) are crucial for achieving functionality.
[0003] However, as device sizes become smaller, the fabrication process for microelectromechanical sensors still needs continuous improvement. Summary of the Invention
[0004] This invention provides a method for forming a semiconductor structure to improve the fabrication process of microelectromechanical sensors.
[0005] According to a first aspect of the present invention, a method for forming a semiconductor structure is provided, comprising: providing a first substrate, the first substrate including a first base, a second base, and a buried oxide layer located between the first base and the second base; forming a first groove and an initial second groove in the first base, the bottom of the first groove exposing the surface of the buried oxide layer, the depth of the first groove being greater than the depth of the initial second groove, and the width of the first groove being greater than the width of the initial second groove; removing the first base at the bottom of the initial second groove using a cyclic process to form a second groove in the first base, the second groove exposing the surface of the buried oxide layer, the cyclic process including: a first step and a second step, the first step including: oxidizing the first base at the bottom of the initial second groove to form an oxide layer; the second step including: removing the oxide layer; providing a second substrate having a cavity therein; bonding the second substrate to the first substrate, the second substrate being in contact with the first base, the cavity communicating with the first groove, and the cavity communicating with the second groove.
[0006] Optionally, the process of oxidizing the first substrate at the bottom of the initial second groove includes a thermal oxidation process.
[0007] Optionally, the process for removing the oxide layer includes a wet etching process.
[0008] Optionally, the cycle process further includes a third step, which includes: cleaning the first groove and the initial second groove after removing the oxide layer; the cleaning process for the first groove and the initial second groove includes a wet cleaning process.
[0009] Optionally, the thickness of the buried oxide layer is less than the thickness of the first substrate at the bottom of the initial second groove; the thickness of the oxide layer is less than the thickness of the buried oxide layer.
[0010] Optionally, it also includes: removing the second substrate; and after removing the second substrate, removing the buried oxide layer.
[0011] Optionally, the process for removing the buried oxide layer includes a dry etching process.
[0012] Optionally, the cyclic process is repeated at least twice.
[0013] Optionally, the process of removing the first substrate at the bottom of the initial second groove using a cyclic process further includes: removing the buried oxide layer at the bottom of the first groove.
[0014] Optionally, the material of the buried oxide layer is the same as the material of the oxide layer.
[0015] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: The method of the present invention first forms a first groove and an initial second groove with different depths, and then uses a cyclic process to remove the first substrate at the bottom of the initial second groove. This effectively solves the problem of poor heat dissipation of the first substrate when forming grooves of different widths, while improving the morphology and structural quality of the formed first and second grooves, reducing defects, and improving the yield of semiconductor structures. Attached Figure Description
[0016] Figures 1 to 9 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation
[0017] As described in the background section, the fabrication process of microelectromechanical sensors still requires continuous improvement.
[0018] Specifically, in mainstream process solutions, the suspended structure layer is electrically connected to the substrate wafer with movable cavities via wafer bonding, and the bulk silicon process uses deep reactive ion etching (DRIE) technology to release the device layer structure. During the etching process of the suspended structure, the simultaneous occurrence of ion bombardment and chemical reaction during deep silicon etching generates a large amount of heat on the silicon structure surface. When the heat generated by etching on the structure cannot be dissipated in time through the silicon structure and anchor points, heat will accumulate on the sensitive structure.
[0019] Due to the inherent etching hysteresis effect (Lag effect) of deep reactive ion etching (DRIE), the ion transport efficiency in deep and narrow trenches decreases exponentially with the increase of the aspect ratio. When wide and narrow trenches are etched simultaneously, the wide trenches are quickly etched through and cannot transfer the large amount of heat generated by the etching. When the smallest trench is gradually etched completely, the effective heat conduction cross section of the suspended structure gradually decreases. Heat accumulates in the etched area, causing etching damage to the structural layer. Plasma accumulation at the bottom of the structural layer reverses the etching of the back side of the structure, resulting in severe morphological deformation.
[0020] The thermal conductivity of suspended structures is closely related to their structural design and wafer structure, such as the dimensions of beam structures and the area of MEMS suspended structures. Excessive temperature makes it difficult to guarantee the integrity of suspended structures, a common technological challenge in deep silicon etching of MEMS structures. This significantly restricts the design and fabrication of sensitive structures and has a major impact on the development and production of MEMS devices.
[0021] To achieve high aspect ratio etching and structure release in micro inertial devices, one approach is to fill deep silicon etch trenches with a sacrificial layer and polysilicon, and then remove the sacrificial layer between the polysilicon and silicon by patterning the polysilicon to obtain a suspended structure. This method is extremely difficult to fill with polysilicon and requires high-performance equipment. Another approach is to introduce silicon-glass bonding to fabricate the suspended structure, which requires the preparation of a metal such as alkanes (AL) on a glass substrate to increase heat dissipation during deep silicon etching. However, in this method, the silicon-glass bonding stress is too high, causing the structure layer to detach after the suspended structure is released. The wet etching method for removing Alkanes makes the suspended structure prone to adhesion phenomena, leading to structural performance failure and low product yield.
[0022] In addition, the improvement solutions to the above problems are as follows: (1) When designing MEMS structures, add heat dissipation structures such as metal layers, heat dissipation silicon pillars, and heat dissipation beam structures between suspended structures and bonding anchors or substrates. Such methods cannot avoid the thermal damage problem released by structures with large aspect ratios, cannot achieve product quantification, and are not suitable for all MEMS structures; (2) Adjust the etching menu from the perspective of deep silicon etching. High aspect ratio etching processes usually adopt Bosch processes. Bosch processes are etching-passivation cycle processes. A wait step is added between cycles to wait for the etching cavity to cool down. This method is not very effective and is prone to generating carbonized polymers in the etching area, while increasing the processing time and reducing efficiency.
[0023] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure. First, a first groove and an initial second groove of different depths are formed. Then, a cyclic process is used to remove the first substrate at the bottom of the initial second groove. This effectively solves the problem of poor heat dissipation of the first substrate when forming grooves of different widths. At the same time, it improves the morphology and structural quality of the formed first and second grooves, reduces defects, and improves the yield of the semiconductor structure.
[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.
[0025] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings.
[0026] Figures 1 to 9 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.
[0027] Please refer to Figure 1 A first substrate is provided, which may include a first substrate 202, a second substrate 200 and a buried oxide layer 201 located between the first substrate 202 and the second substrate 200.
[0028] In this embodiment, the first substrate may include a first device region A and a second device region B, which are used to form structures with different functions.
[0029] In this embodiment, the first device area A is used to form a mass block and a movable beam; the second device area B is used to form comb teeth.
[0030] In this embodiment, the first substrate 202 is made of silicon; the second substrate 200 is made of silicon; and the buried oxide layer 201 is made of silicon oxide.
[0031] Please refer to Figure 2A first groove 203 and an initial second groove 204 are formed in the first substrate 202. The bottom of the first groove 203 exposes the surface of the buried oxide layer 201. The depth of the first groove 203 is greater than the depth of the initial second groove 204, and the width of the first groove 203 is greater than the width of the initial second groove 204.
[0032] In this embodiment, the first groove 203 is located in the first device region A, and the initial second groove 204 is located in the second device region B.
[0033] In this embodiment, the second device region B is located between the first device regions A. The first device region A includes a first groove 203, and the second device region B includes a plurality of initial second grooves 204.
[0034] In other embodiments, the first device region A includes a plurality of first grooves.
[0035] In this embodiment, the width and depth of the plurality of initial second grooves 204 are the same.
[0036] In other embodiments, the width and depth of the plurality of initial second grooves may be different.
[0037] In this embodiment, the spacing between adjacent initial second grooves 204 is different.
[0038] In other embodiments, the spacing between adjacent initial second grooves may be the same.
[0039] In this embodiment, the method of forming a first groove 203 and an initial second groove 204 in the first substrate 202 may include: forming a patterned mask layer on the first substrate 202; etching the first substrate 202 with the patterned mask layer as a mask until the surface of the buried oxide layer 201 is exposed, forming a first groove 203 in the first device region A, and forming an initial second groove 204 in the second device region B.
[0040] The etching process for the first substrate 202 may include a dry etching process.
[0041] In this embodiment, the dry etching process may include deep reactive ion etching (DRIE). Since the width of the first groove 203 is greater than the width of the initial second groove 204, and the aspect ratio of the first groove 203 is less than that of the initial second groove 204, when etching the first substrate 202 using DRIE, based on the inherent etching lag effect of DRIE, the rate at which the first groove 203 is formed by DRIE is greater than the rate at which the initial second groove 204 is formed. Therefore, when etching stops after the first groove 203 exposes the buried oxide layer 201, there is still a certain thickness of first substrate 202 between the bottom of the formed initial second groove 204 and the buried oxide layer 201, and the depth of the formed first groove 203 is greater than the depth of the initial second groove 204.
[0042] In this embodiment, the thickness of the first substrate 202 between the bottom of the initial second groove 204 and the buried oxide layer 201 is T1.
[0043] In this embodiment, the thickness T2 of the buried oxide layer 201 is less than the thickness T1 of the first substrate 202 at the bottom of the initial second groove 204.
[0044] In this embodiment, the thickness of the buried oxide layer 201 ranges from 1 micrometer to 2 micrometers.
[0045] Next, a cyclic process is used to remove the first substrate 202 at the bottom of the initial second groove 204, forming a second groove within the first substrate 202. The second groove exposes the surface of the buried oxide layer 201. The cyclic process may include: a first step and a second step. The first step includes: oxidizing the first substrate 202 at the bottom of the initial second groove 204 to form an oxide layer. The second step includes: removing the oxide layer.
[0046] In this embodiment, the recycling process may further include a third step, which includes cleaning the first groove 203 and the initial second groove 204 after removing the oxide layer.
[0047] The cyclic process consists of multiple cycles of the first, second, and third steps until the first substrate 202 at the bottom of the initial second groove 204 is completely removed. In this embodiment, the first, second, and third steps are repeated at least twice.
[0048] For the process of removing the first substrate 202 at the bottom of the initial second groove 204 using a cyclic process, please refer to [reference needed]. Figures 3 to 6 .
[0049] Please refer to Figure 3The first step is to oxidize the first substrate 202 at the bottom of the initial second groove 204 to form an oxide layer 205.
[0050] In this embodiment, the process of oxidizing the first substrate 202 at the bottom of the initial second groove 204 includes a thermal oxidation process. The thermal oxidation process can react with the first substrate 202 to form a thin and uniform oxide layer. By controlling the process parameters, an oxide layer of a preset thickness can be obtained, thereby enabling better control of the oxide layer removal process.
[0051] The reaction temperature range of the thermal oxidation process is 800 degrees Celsius to 1000 degrees Celsius.
[0052] In this embodiment, the oxide layer 205 is also formed on the sidewall and top surface of the first groove 203, and also on the sidewall and top surface of the initial second groove 204.
[0053] In this embodiment, the thickness of the oxide layer 205 is h, which is less than the thickness T1 of the first substrate 202 at the bottom of the initial second groove 204, and less than the thickness T2 of the buried oxide layer 201.
[0054] In this embodiment, the thickness of the oxide layer 205 is less than or equal to 1 micrometer.
[0055] In this embodiment, the material of the oxide layer 205 is the same as that of the buried oxide layer 201, and the material of the oxide layer 205 is silicon oxide.
[0056] Please refer to Figure 4 Then proceed to the second step to remove the oxide layer 205.
[0057] In this embodiment, the process for removing the oxide layer 205 may include a wet etching process, and the etching solution for the wet etching process may include hydrofluoric acid.
[0058] In this embodiment, during the process of removing the oxide layer 205, a portion of the buried oxide layer 201 at the bottom of the first groove 203 is also removed.
[0059] Because the oxide layer 205 formed in a single step is relatively thin, the concentration of the etching solution in the wet etching process for removing the oxide layer 205 in a single step is also relatively low. This allows for less lateral etching when removing the buried oxide layer 201 at the bottom of the first groove 203 during the removal of the oxide layer 205 on the sidewalls of the first groove 203. Furthermore, since the buried oxide layer 201 is exposed at the bottom of the first groove 203, the sidewalls and bottom of the first groove 203 are made of the same material, silicon oxide. This makes it easier to remove the oxide layer 205 from the sidewalls of the first groove 203, ensuring a clean removal of the area where the sidewalls and bottom meet, and preventing the "footing" defect caused by incomplete etching. In summary, this method effectively preserves the morphology of the first groove 203.
[0060] In one embodiment, after forming the oxide layer 205, a third step may be performed to clean the first groove 203 and the initial second groove 204.
[0061] In this embodiment, the process of cleaning the first groove 203 and the initial second groove 204 may include a wet cleaning process. The wet cleaning process can remove reaction residues and etching solution from the wet etching process, and causes less damage to the first substrate 202.
[0062] In this embodiment, the cleaning solution used in the wet cleaning process is deionized water.
[0063] Please refer to Figure 5 Continue with the first, second and third steps, remove part of the first substrate 202 at the bottom of the initial second groove 204, and in this process, remove the buried oxide layer 201 at the bottom of the first groove 203, exposing the second substrate 200, and forming a third groove 206 in the buried oxide layer 201 at the bottom of the first groove 203.
[0064] In the above embodiments, since the oxide layer 205 formed in a single step is thin, the concentration of the etching solution in the wet etching process for removing the oxide layer 205 in a single step is also small. Therefore, when the buried oxide layer 201 at the bottom of the first groove 203 is etched multiple times until it is completely removed, lateral etching is less likely to occur, making it less likely that the bottom of the first substrate 202 will be damaged, and the morphology of the first groove 203 will remain good.
[0065] Please refer to Figure 6 Continue with the first, second and third steps until the first base 202 at the bottom of the initial second groove 204 is completely removed, and a second groove 207 is formed in the first base 202, exposing the buried oxygen layer 201.
[0066] In this embodiment, after the second substrate 200 is exposed in the third groove 206, the second substrate 200 at the bottom of the third groove 206 is also oxidized when the oxide layer is formed, and a portion of the second substrate 200 at the bottom of the third groove 206 is also removed when the oxide layer is removed.
[0067] In this embodiment, since the oxide layer 205 formed in a single step is thinner, the thickness of the first substrate 202 at the bottom of the initial second groove 204 is also thinner, and the oxide layer formation process is also more subtle. When reacting with the first substrate 202, it is not easy to extend into the first substrate 202. Thus, after multiple oxidation-etching processes, the sidewalls of the formed second groove 207 are also relatively straight, and the second groove 207 maintains a good morphology, resulting in a better yield of the formed device structure.
[0068] Please refer to Figure 7 A second substrate is provided, wherein the second substrate has a cavity 303.
[0069] In this embodiment, the second substrate may include a third substrate 300, a fourth substrate 302 and a buried oxide layer 301 located between the third substrate 300 and the fourth substrate 302, and the cavity 303 is located within the fourth substrate 302.
[0070] In one embodiment, cavity 303 exposes the surface of the buried oxide layer 301. Cavity 303 includes a first cavity and a second cavity that are connected to each other. The fourth substrate 302 exposes the top of the first cavity, and the second cavity exposes the surface of the buried oxide layer 301. The projection range of the second cavity on the third substrate 300 is within the projection range of the first cavity on the third substrate 300. Cavity 303 has a damascus steel structure. In other embodiments, the cavity is a single cavity, and the fourth substrate exposes the top of the cavity.
[0071] In this embodiment, the material of the third substrate 300 is silicon; the material of the fourth substrate 302 is silicon; and the material of the buried oxide layer 301 is silicon oxide.
[0072] In other embodiments, the second substrate may be a monolithic silicon substrate.
[0073] Please refer to Figure 8 The second substrate is bonded to the first substrate, the second substrate is connected to the first substrate 202, a portion of the cavity 303 is connected to the first groove 203, and a portion of the cavity 303 is connected to the second groove 207.
[0074] In the above embodiments, the cavity 303 is connected to the first groove 203, and the cavity 303 is connected to the second groove 207, so that the first base 201 and the fourth base 302 form a suspended structure. The cavity 303 and the first groove 203, the cavity 303 and the second groove 207, and the first base 201 and the fourth base 302 constitute a closed suspended structure activity space. The suspended structure formed by the method has good quality and good reliability.
[0075] In this embodiment, the first substrate 202 is bonded to the fourth substrate 302. The first substrate 202 and the fourth substrate 302 are made of the same material, silicon, which facilitates the formation of silicon-silicon bonds, resulting in a tighter chip bonding.
[0076] In this embodiment, the size of the second substrate matches the size of the first substrate, that is, the size of the second substrate is the same as the size of the first substrate.
[0077] In other embodiments, while ensuring that a portion of the cavity is connected to the first groove and a portion of the cavity is connected to the second groove, the size of the second substrate may be different from the size of the first substrate.
[0078] Please refer to Figure 9 Remove the second substrate 200; after removing the second substrate 200, remove the buried oxygen layer 201.
[0079] In one embodiment, the process for removing the second substrate 200 may include a chemical mechanical polishing (CMP) process, which is capable of rapidly removing the thickened second substrate 200 and can stop at the surface of the buried oxide layer 201.
[0080] In one embodiment, the process for removing the buried oxide layer 201 may include a dry etching process, wherein the etching gas in the dry etching process includes hydrogen fluoride. After the second substrate 200 is removed, the buried oxide layer 201 is fully exposed, and the dry etching process can fully contact the exposed buried oxide layer 201 to remove the buried oxide layer 201.
[0081] The above-described method first forms a first groove and an initial second groove with different depths, and then uses a cyclic process to remove the first substrate at the bottom of the initial second groove. This effectively solves the problem of poor heat dissipation of the first substrate when forming grooves of different widths, while improving the morphology and structural quality of the formed first and second grooves, reducing defects, and improving the yield of semiconductor structures.
[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a first substrate, the first substrate comprising a first base, a second base and a buried oxygen layer between the first base and the second base; forming a first recess and an initial second recess in the first base, the bottom of the first recess exposing the surface of the buried oxygen layer, the depth of the first recess being greater than the depth of the initial second recess, and the width of the first recess being greater than the width of the initial second recess; removing the first base at the bottom of the initial second recess by a cyclic process to form a second recess in the first base, the second recess exposing the surface of the buried oxygen layer, the cyclic process comprising a first step and a second step, the first step comprising oxidizing the first base at the bottom of the initial second recess to form an oxidation layer, and the second step comprising removing the oxidation layer; providing a second substrate, the second substrate having a cavity therein; bonding the second substrate to the first substrate, the second substrate being in contact with the first base, the cavity being in communication with the first recess, and the cavity being in communication with the second recess.
2. The method of forming a semiconductor structure of claim 1, wherein, The process of oxidizing the first base at the bottom of the initial second recess comprises a thermal oxidation process.
3. The method of forming a semiconductor structure of claim 1, wherein, The process of removing the oxidation layer comprises a wet etching process.
4. The method of forming a semiconductor structure of claim 3, wherein, The cyclic process further comprises a third step, the third step comprising cleaning the first recess and the initial second recess after the removal of the oxidation layer, and the process of cleaning the first recess and the initial second recess comprises a wet cleaning process.
5. The method of forming a semiconductor structure of claim 1, wherein, The thickness of the buried oxygen layer is less than the thickness of the first base at the bottom of the initial second recess, and the thickness of the oxidation layer is less than the thickness of the buried oxygen layer.
6. The method of forming a semiconductor structure of claim 1, wherein, The method further comprises the following steps: removing the second base; after the removal of the second base, removing the buried oxygen layer.
7. The method of forming a semiconductor structure of claim 6, wherein, The process of removing the buried oxygen layer comprises a dry etching process.
8. The method of forming a semiconductor structure of claim 1, wherein, The cyclic process is repeated at least twice.
9. The method of forming a semiconductor structure of claim 1, wherein, In the process of removing the first base at the bottom of the initial second recess by the cyclic process, the process further comprises removing the buried oxygen layer at the bottom of the first recess.
10. The method of forming a semiconductor structure of claim 9, wherein, The material of the buried oxygen layer is the same as the material of the oxidation layer.