Zero-crossing current detection circuit robust to PVT change and application of zero-crossing current detection circuit

Abstract

The invention belongs to the field of electric energy conversion, and discloses a zero-crossing current detection circuit robust to PVT change and application of the zero-crossing current detection circuit, and a ZCD circuit comprises a current signal detection unit, a current signal equal-ratio amplification unit, a current signal reconstruction unit and a reference voltage generation unit. Compared with the traditional zero-crossing current detection technology, the detection technology realizes the accurate detection of the zero-crossing current through the equal-ratio amplification of the current signal. The detection technology can be widely applied to any switch inductance converter circuit, and has extremely high robustness to PVT (process, voltage and temperature) changes. And meanwhile, when the technology is used, no extra current sampling resistor is introduced into the circuit, so that the influence on the overall efficiency is small.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of electric energy conversion, and particularly relates to a cross-zero current detection circuit with high robustness to PVT variation, which can be applied to any switched-inductor converter circuit. Compared with the traditional cross-zero current detection technology, the cross-zero current detection circuit can be applied to various switched-inductor converters without the need to change the topology structure. At the same time, due to the internal structure design, the cross-zero current detection circuit has high robustness to PVT variation. BACKGROUND

[0002] Discontinuos Conduction Mode (DCM) mode is mainly applied to scenes such as light load, high efficiency, low power consumption, small power or high power factor, and is the core control mode in portable, IoT and energy-saving power supply design. In DCM, the inductor current decreases to zero at the end of each period. The Zero Current Detection (ZCD) technology realizes accurate switching control and mode switching by monitoring the zero-crossing moment of the inductor current, and is a key support means for DCM control. Its application can effectively reduce switching loss, improve light load efficiency, suppress EMI, and is widely used in Internet of Things terminals, LED drives, energy harvesting and high power factor PFC circuits.

[0003] In order to improve the overall efficiency of the power converter, the parasitic resistance R LP of the power inductor is usually selected to be as small as possible. In this case, the extracted current signal I L R LP will be very weak, and the detection of the zero-crossing point will be very difficult when the system is in the DCM state.

[0004] The ZCD detects the moment when the inductor current decreases to zero, that is, when the energy storage element (usually an inductor or transformer) is completely discharged. The detection methods include but are not limited to: 1) external detection type, 2) internal detection type, and 3) current detection resistance type.

[0005] The basic principle of the external detection type is as follows: an auxiliary winding is added to the transformer (or inductor), and when the main inductor current decreases to zero, the auxiliary winding induced voltage will appear zero-crossing or reversal, and the ZCD moment can be judged by detecting the signal through the comparator. It has the advantages of high precision and good noise immunity. However, it needs to add an extra magnetic element, the structure is more complex, and it is not suitable for integrated or on-chip inductor systems, and the response delay is affected by the leakage inductance and distributed parameters of the magnetic element, which is easy to drift at high frequency.

[0006] The internal detection type is taken as an example to detect the voltage waveform on both sides of the source and drain of the power switch tube, and the basic principle is as follows: the detection of the zero-crossing current is realized by detecting the voltage drop caused by the inductance current and the parasitic resistance on the power tube. The method has the advantages of no additional sensor and low cost. However, the detection method is affected by the structure itself, the received signal noise is large, the zero point recognition is easy to misjudge, and the PVT influence is extremely serious.

[0007] The basic principle of the current detection resistance type is as follows: a detection resistance is added in the inductance path, and a ZCD signal is output when the detection current drops to zero. The advantages include high detection accuracy, rapid response and the like. However, the additional resistance will bring additional conduction loss, affecting the overall efficiency, and it is easy to be affected by noise and has poor PVT robustness. SUMMARY

[0008] The purpose of the present application is to overcome at least one of the deficiencies of the prior art and provide a zero-crossing current detection circuit robust to PVT changes and applications thereof.

[0009] The technical solution adopted by the present application is: In a first aspect, the present application provides: A zero-crossing current detection circuit robust to PVT changes, comprising: A resistance-capacitance matching network unit for collecting an inductance current signal of a power inductor I L ; A signal extraction unit extracts a direct current component voltage V2 reflecting the inductance current and an alternating current component voltage V1 from the inductance current signal collected by the resistance-capacitance matching network unit; A current signal reconstruction unit reconstructs a signal based on the direct current component voltage and the alternating current component voltage extracted by the signal extraction unit, to obtain an amplified voltage related to the inductance current V S ; A zero-current reference voltage generation unit for generating a reference voltage V REF , the reference voltage V REF contains a disordered voltage V OS in different functional unit implementations; A comparator for comparing V S and the reference voltage V REF to realize zero-crossing current detection.

[0010] In some examples, the resistance-capacitance matching network unit has a first input end (V X ) and a second input end (V Y), a first input terminal (V X ) and a second input terminal (V Y ), the first input terminal (V X ) and the second input terminal (V Y ) being connected in series with a first resistor R1 and a first capacitor C1 in that order, the first capacitor C1 being connected in parallel with a second resistor R2 and a second capacitor C2 in series, the first resistor R1, the second capacitor C2 and the second resistor R2 being connected in series in that order.

[0011] In some examples, the resistance-capacitance matching network unit has a first input terminal (V X ) and a second input terminal (V Y ), the first input terminal (V X ) and the second input terminal (V Y ) being connected in series with a first resistor R1 and a first capacitor C1 in that order, the first capacitor C1 being connected in parallel with a second resistor R2 and a second capacitor C2 in series, the first resistor R1, the second capacitor C2 and the second resistor R2 being connected in series in that order.

[0012] In some examples, the signal extraction unit has an alternating current signal extraction composed of a resistance-capacitance network of R1, C1 and a voltage subtractor circuit composed of R7, R8, R9, R 10 10 and an amplifier AMP2, the voltage difference between the two sides of the capacitor C1 being extracted as V1; R7 and R8 are connected in series, one end of R7 being connected to the wire between R1 and C1, one end of R9 being connected to the other end of C1 and connected in series with R 10 10, the non-inverting input terminal of the amplifier AMP2 being connected to the wire between R9 and R 10 10, the inverting input terminal being connected to the wire between R7 and R8, the other end of R8 being connected to the output terminal of the amplifier AMP2; The direct current signal extraction is composed of a low-pass filter network of R2, C2 in parallel with C1 and a voltage subtractor circuit composed of R3, R4, R5, R6 and an amplifier AMP1, the voltage difference between the two sides of the capacitor C2 being extracted as V2; R5 and R6 are connected in series, one end of R5 being connected to the wire between R2 and C2, one end of R3 being connected to the other end of C3 and connected in series with R4, the non-inverting input terminal of the amplifier AMP1 being connected to the wire between R5 and R6, the inverting input terminal being connected to the wire between R3 and R4, the other end of R4 being connected to the output terminal of the amplifier AMP1.

[0013] In some examples, the signal extraction unit further comprises a fixed lifting voltage V LU The generating unit is composed of a resistance R 20 and a MOS transistor M 15 .

[0014] In some examples, the fixed lifting voltage V LU The generating unit further comprises a resistance R 20High frequency filter capacitor C3 in series.

[0015] In some examples, the signal extraction unit further comprises a fixed lifting voltage V LU The generating unit is composed of resistance R 20 and MOS tube M 15 , resistance R 20 is in series with high frequency filter capacitor C3, and the other end of C3 is grounded.

[0016] In some examples, the current signal reconstruction unit applies a fixed lifting voltage V LU to MOS tube M1, MOS tube M3, resistance R 15 and amplifier AMP4 to convert into a current signal, which is amplified by MOS tube M1 and MOS tube M2, and converted into a bias voltage by MOS tube M4 to MOS tube M8 to form a current signal; V1 is converted into a current signal by MOS tube M5, MOS tube M7, resistance R 16 and amplifier AMP5, which is amplified by MOS tube M5 and MOS tube M6; V2 is converted into a current signal by MOS tube M9, MOS tube M 11 , resistance R 17 and amplifier AMP6, which is amplified by MOS tube M9 and MOS tube M 10 to copy, with a ratio of 1:1; The converted current signal, the current signal amplified by V1 conversion, and the copied current signal amplified by V2 conversion are combined V LU to obtain an amplified reconstructed current I S , which is converted into a voltage signal V 19 by resistance R S and output to the comparator. S

[0017] In some examples, the zero current reference voltage generating unit comprises a high frequency offset voltage and lifting voltage extraction circuit composed of resistance R 11 , R 12 , R 13 , R 14 and amplifier AMP3, wherein R 11 and R 12 are in series, R 13 and R 14 are in series, R 11 and R 13 receive the first input voltage V X , R 13 ​Receiving the boost voltage V LU The in-phase input of the amplifier AMP3 is connected to the wire between R 13 and R 14 The anti-phase input of the amplifier AMP3 is connected to the wire between R 11 and R 12 The output of the amplifier AMP3 is connected to the other end of R 12 and the in-phase input of the amplifier AMP7. The extracting circuit extracts the high-frequency offset voltage in the first input voltage V X and the boost voltage V LU and converts the extracted voltage into a current through the current conversion circuit composed of the amplifier AMP7, the MOS transistor M 12 , the MOS transistor M 14 and R 18 The current conversion circuit composed of the MOS transistor M 12 and the MOS transistor M 13 simultaneously simulates the offset current signal in the current amplification and gives it to the resistor R 21 , thereby comprehensively generating the zero-current reference voltage V REF and outputting to the comparator.

[0018] In some examples, the amplification factor is K times, KR2C2=R1C1.

[0019] In some examples, the amplification factor is K times, R1, C1 satisfy , and , the extracted voltage V1 satisfies , wherein, L is the power inductance, R PL is the inductance parasitic resistance, is the alternating current, is the direct current.

[0020] The above technical points can be combined arbitrarily without conflict.

[0021] In a second aspect of the present application, there is provided: A buck converter comprising the zero-current crossing detection circuit of the first aspect of the present application.

[0022] The present application has the following advantages: The cross-zero current detection circuit of some examples of the application can be applied to any switched inductor converter circuit and has high robustness to PVT variation. Through current signal extraction and reconstruction, the cross-zero current detection can be realized without affecting the efficiency of the converter and adding a secondary winding. Meanwhile, the zero-current voltage generation circuit removes the interference information caused by PVT variation and circuit offset voltage, thereby improving the anti-interference ability to PVT. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The structure diagram of a cross-zero current detection technology with high robustness to PVT variation that can be applied to any switched inductor converter circuit.

[0024] Figure 2 The structure diagram of a current signal amplification circuit.

[0025] Figure 3 The structure diagram of a signal reconstruction circuit.

[0026] Figure 4 The structure diagram of a zero-current reference voltage generation circuit.

[0027] Figure 5 The complete circuit structure diagram of a cross-zero current detection technology with high robustness to PVT variation that can be applied to any switched inductor converter circuit.

[0028] Figure 6 The structure diagram of the application of the cross-zero current detection technology in a current-mode buck converter.

[0029] Figure 7 The working process of the application of the cross-zero current detection technology in a buck converter under current-mode AOT control in DCM state.

[0030] Figure 8 The working process of the application of the cross-zero current detection technology in a buck converter under current-mode AOT control in different process corners in DCM state. DETAILED DESCRIPTION

[0031] The technical solutions of the application are further described below in combination with examples.

[0032] Figure 1 The structure diagram of a signal reconstruction circuit of a cross-zero current detection technology with high robustness to PVT variation that can be applied to any switched inductor converter circuit. PL L is a power inductor, I Lis the inductor current. A resistance-capacitance matching network is connected to both ends of the power inductor to realize the sensing of the inductor current signal I L . The current signal extraction circuit extracts a relevant voltage signal in the resistance-capacitance matching network. The extracted relevant voltage signal passes through a signal reconstruction circuit to obtain an amplified reconstructed voltage in a relevant multiple of the inductor current V S , V S = KR PL I L + V LU where K is an amplification multiple, V LU is a fixed raised voltage. The raised voltage contains PVT-related information to realize anti-interference improvement of the PVT. By comparing the voltage and a zero-current reference voltage, when the inductor current is greater than zero, V S the voltage is greater than the zero-current reference voltage, V ZCD the output voltage is high. When the inductor current is less than zero, V S the voltage is less than the zero-current reference voltage, V ZCD the output voltage is low. With the help of signal amplification reconstruction of the inductor current and the zero-current reference voltage, the application realizes accurate detection of the inductor current and zero-crossing judgment without increasing additional sampling resistance and auxiliary winding inductance.

[0033] Figure 2 The resistance-capacitance matching network and the current signal extraction circuit are shown. In order to improve the overall efficiency of the power converter, the parasitic resistance R LP of the power inductor needs to be as small as possible. In this case, the extracted current signal I L R LP will be very weak, and its zero-crossing detection will be very difficult when the system is in the DCM state. In order to enhance the extracted current signal, it needs to be amplified by K times through an amplification circuit. The signal amplification of the inductor current is divided into two parts, which are the alternating current signal (I ) and the direct current signal (I ). The alternating current signal extraction consists of a resistance-capacitance network composed of R1, C1 and a voltage subtractor circuit composed of R7, R8, R9, R 10 and an amplifier AMP2. The voltage difference between the two sides of the capacitor C1 is V1. Under the condition of the proposed amplification multiple K, the extracted voltage V1 needs to satisfy:

[0034] R1, C1 must satisfy:

[0035] and

[0036] wherein V LU is a fixed lifting voltage. In the actual design of the circuit, in order to maintain the normal operation of the amplifier itself, the output voltage of the amplifier needs to be greater than zero voltage 200 to 300 millivolts, otherwise the amplifier will not work normally. However, when the inductor current is zero, the signal obtained by the current signal acquisition will also be zero, and the overall circuit operation will be abnormal. In order to make up for this design defect, a fixed lifting voltage V LU When the inductor current is zero, the ideal output voltage of the voltage extraction circuit of the amplifier is V LU In order to meet the normal operation of the amplifier under all PVT conditions, V LU PVT related information needs to be included in the design. The V LU When designing, the resistance R 20 and the MOS tube M9 are composed, wherein C3 is a high-frequency filtering capacitor, which is used to remove the high-frequency signal crosstalk caused by the signal extraction circuit. In order to normally compare the inductor current across zero point later, it is necessary to rely on the zero current reference voltage generation circuit to eliminate the influence of this information in the comparison.

[0037] In order to make up for the insufficient amplification multiple of the direct current part in the V2 signal, it is necessary to extract the inductor direct current part voltage. In order to avoid introducing additional high-frequency alternating current signals, R2 and C2 low-pass filter network are connected in parallel on the sampling capacitor C1, and satisfy:

[0038] The voltage subtracter circuit composed of R3, R4, R5, R6 and amplifier AMP1 extracts the voltage difference V2 between the two sides of capacitor C2 as:

[0039] As Figure 3 shown is a current signal reconstruction circuit, wherein M1, M3, R 15 and amplifier AMP4 convert V LU the signal into a current signal. The current signal is amplified by M1 and M2 to K-1 times of the original current. And converted into a bias voltage by M4 to M8. Similarly, M5, M7, R 16Amplifier AMP5 converts V1 into a current signal. This current signal is amplified by M5 and M6 to K-1 times the original current. M9, M 11 R 17 Amplifier AMP5 converts V2 into a current signal. This current signal is then transmitted through M9 and M... 10 Perform a copy. Then through... Figure 3 The current relationship shown is through R 19 current

[0040] in This is the equivalent offset current of the current mirror when copying the current. This offset current is caused by the distortion of the amplifier circuit and signal extraction circuit when processing high-frequency signals under non-ideal conditions, which will seriously interfere with signal judgment and processing. In the design, let R... 15 =R 16 =R 17 =R 19 The voltage collected is V S Offset voltage ; .

[0041] like Figure 4 The diagram shows a zero-current reference voltage generation circuit. Where R... 11 R 12 R 13 R 14 And amplifier AMP3 will connect the first input terminal V X A co-current signal is extracted to simulate the distortion of high-frequency signals under non-ideal conditions, and this distortion is then extracted. This high-frequency offset voltage is combined with a fixed voltage ( V LU ), and then through amplifier AMP7, M 12 M 14 and R 18 The current conversion circuit formed converts the extracted voltage into current. 12 and M 13 The constructed current transducer circuit simultaneously simulates the offset current signal during current amplification and feeds it to resistor R. 21 This results in a zero-current reference voltage. V REF .

[0042] .

[0043] like Figure 5The figure shows the overall circuit architecture of a cross-zero current detection technique with extremely high robustness to PVT variations, which can be applied to any switched-inductor converter circuit. Through the current signal amplification and signal reconstruction circuit, the inductor current I L , and the voltage formed by the parasitic resistance R PL between them PL I L is amplified K times and lifted by a fixed lifting voltage V LU , which contains PVT-related information to achieve PVT interference resistance improvement. The reconstructed voltage V S is obtained through the current reconstruction circuit. To achieve accurate detection of the zero-crossing point of the inductor current, the zero-current reference voltage generation circuit V REF . The V REF voltage contains PVT-related information and circuit offset voltage-related information. By comparing V S and V REF , the zero-crossing current signal independent of PVT can be determined. When the inductor current is greater than zero V S > V REF , and when the inductor current is less than zero V S < V REF .

[0044] Figure 6 The figure shows the buck converter circuit diagram applied with the cross-zero current detection circuit. Figure 7 The figure shows the inductor current V S voltage and V REF voltage generated by the buck converter when it works in DCM state. As Figure 7 shown, through the resistance-capacitance matching network, current signal extraction circuit, and signal processing of the signal reconstruction circuit, the inductor current signal I L is amplified and reconstructed as a voltage signal V S . The V S signal is compared with the zero-current reference voltage V REF to obtain the current zero-crossing signal, achieving fast and distortionless detection of the inductor current across zero. In Figure 8 the figure, the inductor current,V S The voltage and V REF The working conditions of the voltage under different process conditions (tt, ss, ff, fs, sf). Under different process angle conditions, V S The voltage can be equal to the inductance current detection, and compared with the zero current reference voltage containing process information to obtain the cross zero point information of the inductance current. The experimental results verify the good robustness of the present example to process changes.

[0045] The above is a further detailed description of the present application, which cannot be considered as a specific implementation of the present application. For ordinary skilled persons in the technical field to which the present application belongs, simple deduction or replacement without departing from the concept of the present application is within the protection scope of the present application.

Claims

1. A cross zero current detection circuit robust to PVT variations, characterized in that, It comprises: a resistive-capacitive matching network unit for picking up an inductive current signal I of the power inductor L ; A signal extraction unit extracts a reactive inductance current DC component voltage V2 and an inductance current AC component voltage V1 from the inductance current signal collected from the resistance-capacitance matching network unit; a current signal reconstruction unit, which reconstructs a signal based on the DC component voltage and the AC component voltage extracted by the signal extraction unit to obtain an amplified voltage V related to the inductor current S ; A zero-current reference voltage generating unit for generating a reference voltage V REF , the reference voltage V REF contains a different function unit implementation in the offset voltage V OS ; a comparator for comparing V S and a reference voltage V REF , achieving zero-crossing current detection.

2. The zero-crossing detection circuit of claim 1, wherein, The resistance-capacitance matching network unit has a first input end (V X ) and a second input end (V Y ), a first resistance R1 and a first capacitance C1 are connected in series between the first input end (V X ) and the second input end (V Y ), the first capacitance C1 is connected in parallel with a second resistance R2 and a second capacitance C2 connected in series, and the first resistance R1, the second capacitance C2 and the second resistance R2 are connected in series.

3. The zero-crossing detection circuit of claim 2, wherein, The AC signal extraction unit extracts the signal from the resistor-capacitor network composed of R1 and C1, and from the network composed of R7, R8, R9, and R... 10 The circuit consists of a voltage subtractor composed of amplifier AMP2, extracting the voltage difference V1 across capacitor C1; R7 and R8 are connected in series, one end of R7 is connected to the wire between R1 and C1, and one end of R9 is connected to the other end of C1 and connected in series with R... 10 The non-inverting input of amplifier AMP2 is connected to R9 and R 10 The wire between R7 and R8 is connected to the non-inverting input terminal, and the other end of R8 is connected to the output terminal of amplifier AMP2. The DC signal extraction is composed of a voltage subtractor circuit composed of a parallel R2 and C1 on C1, a low-pass filter network of C2, R3, R4, R5, R6 and an amplifier AMP1, and extracts the voltage difference V2 between the two sides of the capacitor C2; R5 and R6 are connected in series, one end of R5 is connected to the wire between R2 and C2, one end of R3 is connected to the other end of C3 and connected in series with R4, the non-inverting input end of the amplifier AMP1 is connected to the wire between R5 and R6, the inverting input end is connected to the wire between R3 and R4, and the other end of R4 is connected to the output end of the amplifier AMP1.

4. The zero-crossing detection circuit of claim 3, wherein, The signal extraction unit further comprises a fixed lifting voltage V LU The generating unit is composed of a resistor R 20 and a MOS transistor M 15 ​ 5. The zero-crossing detection circuit of claim 4, wherein, The fixed elevated voltage V LU The generating unit further comprises a resistor R 20 A high-frequency filtering capacitor C3 in series.

6. The zero-crossing detection circuit of claim 3, wherein, The current signal reconstruction unit converts the fixed lifting voltage V LU Through MOS tube M1, MOS tube M3, resistance R 15 And amplifier AMP4 into a current signal, which is amplified by MOS tube M1 and MOS tube M2, and converted into a bias voltage by MOS tube M4 to MOS tube M8 to form a current signal; V1 is converted into a current signal by MOS transistor M5, MOS transistor M7, resistor R 16 and amplifier AMP5, which is amplified by MOS transistor M5 and MOS transistor M6. V2 is converted into a current signal by MOS transistor M9, MOS transistor M 11 , resistor R 17 and amplifier AMP6, which is copied by MOS transistor M9 and MOS transistor M 10 in a ratio of 1:

1. Comprehensive V LU The converted current signal, the current signal converted and amplified by V1, and the copy current signal converted and amplified by V2 are used to obtain the amplified reconstructed current I. S Through resistor R 19 Will I S Converted into voltage signal V S And output it to the comparator.

7. The zero-crossing detection circuit of claim 1, wherein, The zero-current reference voltage generation unit includes a resistor R. 11 R 12 R 13 R 14 The high-frequency offset voltage and boost voltage extraction circuit composed of amplifier AMP3, wherein R 11 and R 12 Series, R 13 and R 14 Series, R 11 and R 13 Receive the voltage V at the first input terminal X Input, R 13 Received boost voltage V LU The input, the non-inverting input of amplifier AMP3, is connected to R. 13 and R 14 The wires between them connect the out-of-phase input of amplifier AMP3 to R. 11 and R 12 The wires between the output terminals of amplifier AMP3 and R 12 The other end is connected to the non-inverting input of amplifier AMP7; The extraction circuit extracts the high frequency misadjustment voltage in the first input terminal voltage V X , and raises the voltage V LU , and converts the extracted voltage into current through the current conversion circuit composed of the amplifier AMP7, MOS transistor M 12 , MOS transistor M 14 , and R 18 , simultaneously simulates the misadjustment current signal when the current is amplified through the current conversion circuit composed of MOS transistor M 12 and MOS transistor M 13 , and provides it to the resistor R 21 , thereby comprehensively generating the zero current reference voltage V REF , and outputting it to the comparator.

8. The zero-crossing detection circuit of claim 3, wherein, In the case of preparing an amplification factor of K times, KR2C2=R1C1.

9. The zero-crossing detection circuit of claim 3, wherein, In the case of preparing a magnification of K times, R1, C1 satisfy , and , the extracted voltage V1 satisfies , wherein L is a power inductance, R PL is an inductance parasitic resistance, is an alternating current, is a direct current.

10. A buck converter characterized by, The cross-zero current detection circuit according to any one of claims 1 to 9.

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