Return address backup method and device, computer device and storage medium
By configuring a backup return address stack for each pipelined processing unit of the processor and updating it synchronously during pipeline flushing, the problem of prediction errors in RAS during pipeline flushing operations is solved, achieving higher return address prediction accuracy and processor execution efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 芯来智融半导体科技(上海)股份有限公司
- Filing Date
- 2025-12-22
- Publication Date
- 2026-04-24
AI Technical Summary
In processor microarchitecture, the RAS (Return Address Stack) is prone to return address prediction errors when encountering pipeline flushing operations caused by conditional jump instructions, which affects the execution accuracy of the processor.
Each pipeline processing unit is configured with an independent backup return address stack, and during pipeline flushing operations, the backup RAS content is copied to the primary RAS to ensure the accuracy of the primary RAS.
By using a multi-level return address stack synchronization and recovery mechanism, the accuracy of return address prediction is improved, the impact of pipeline flushing on RAS is eliminated, and the processor's execution efficiency is enhanced.
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Figure CN121387367B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of processor microarchitecture technology, and more specifically, to a return address backup method, apparatus, computer device, and storage medium. Background Technology
[0002] In the field of processor microarchitecture, the Return Address Stack (RAS) can effectively solve the problem of predicting the return address of the RETURN instruction. However, when encountering instructions such as conditional jump instructions that can initiate pipeline flushing, the RAS may fail to predict the return address of the RETURN instruction. A method is needed to avoid the impact of pipeline flushing and improve the accuracy of the RAS in predicting the return address. Summary of the Invention
[0003] This application provides a return address backup method, apparatus, computer device, and storage medium.
[0004] A first aspect of this application provides a return address backup method applied to a processor. The processor includes multiple pipelined processing units, including a first pipelined processing unit at a first pipeline stage, and at least one second pipelined processing unit supporting initiation of a pipeline flushing operation.
[0005] Obtain the return address stack (RAS) corresponding to the first pipeline processing unit, and configure the RAS corresponding to at least one second pipeline processing unit.
[0006] Obtain the sequence of instructions to be processed and perform pipelined processing on the sequence of instructions to be processed;
[0007] During the pipelined processing of the instruction sequence to be processed, in response to the pipeline flushing operation initiated by the target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit, wherein the target pipeline processing unit is one of at least one second pipeline processing unit.
[0008] In an optional embodiment of this application, during the pipelined processing of the instruction sequence to be processed, after copying the RAS corresponding to the target pipelined processing unit to the RAS corresponding to the first pipelined processing unit in response to the pipeline flushing operation initiated by the target pipelined processing unit, the method further includes:
[0009] The return address is predicted based on the RAS corresponding to the first pipeline processing unit.
[0010] In an optional embodiment of this application, the instruction sequence to be processed includes a CALL instruction, a RETURN instruction, and a return address prediction interference instruction, wherein the return address prediction interference instruction includes a conditional jump instruction.
[0011] In an optional embodiment of this application, pipelined processing of the instruction sequence to be processed includes:
[0012] The instruction input order is determined based on the sequence of instructions to be processed. The CALL instruction, RETURN instruction, and conditional jump instruction in the sequence of instructions to be processed are then input into the processor for instruction processing in sequence. The CALL instruction is used to perform a push operation on the RAS, the RETURN instruction is used to perform a pop operation on the RAS, and the conditional jump instruction is used by the processor to perform a branch processing operation.
[0013] In an optional embodiment of this application, configuring a RAS corresponding to at least one second pipeline processing unit includes:
[0014] During processor initialization, an independent address stack heap storage space is allocated for at least one second pipeline processing unit to configure the RAS corresponding to each of the at least one second pipeline processing unit.
[0015] In an optional embodiment of this application, return address prediction is performed based on the RAS corresponding to the first pipeline processing unit, including:
[0016] In response to the received RETURN instruction, the target return address is obtained from the RAS corresponding to the first pipeline processing unit;
[0017] Predict the return address based on the target return address.
[0018] In an optional embodiment of this application, it further includes:
[0019] While the processor is executing instructions normally, the RAS corresponding to the first pipeline processing unit is kept synchronized with at least one second pipeline processing unit.
[0020] A second aspect of this application provides a return address backup device applied to a processor. The processor includes multiple pipelined processing units, including a first pipelined processing unit at a first pipeline stage, and at least one second pipelined processing unit supporting the initiation of a pipeline flushing operation.
[0021] The configuration module is used to obtain the return address stack (RAS) corresponding to the first pipeline processing unit and configure the RAS corresponding to at least one second pipeline processing unit.
[0022] The processing module acquires the instruction sequence to be processed and performs pipelined processing on the instruction sequence to be processed. During the pipelined processing of the instruction sequence to be processed, in response to the pipeline flushing operation initiated by the target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit. The target pipeline processing unit is one of at least one second pipeline processing unit.
[0023] A third aspect of this application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.
[0024] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the method as described in any of the above. Attached Figure Description
[0025] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0026] Figure 1 A schematic diagram illustrating an application scenario of instruction calls in a processor microarchitecture provided in one embodiment of this application;
[0027] Figure 2 This is a schematic diagram illustrating the RAS push and pop process according to one embodiment of this application;
[0028] Figure 3 A schematic diagram illustrating the principle of return address prediction error provided in one embodiment of this application;
[0029] Figure 4 A schematic diagram illustrating the process of backing up the return address according to one embodiment of this application;
[0030] Figure 5 A schematic diagram illustrating the principle of the RAS backup mechanism in a five-stage pipelined processor provided in one embodiment of this application;
[0031] Figure 6 A schematic diagram of the return address prediction process provided in one embodiment of this application;
[0032] Figure 7 A detailed schematic diagram illustrating the steps of execution return address prediction provided in one embodiment of this application;
[0033] Figure 8 This is a schematic diagram of the return address backup device structure provided in one embodiment of this application;
[0034] Figure 9 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation
[0035] The technical solutions in this application will be clearly and thoroughly described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.
[0036] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
[0037] Please see Figure 1 In processor microarchitecture, Return Address Prediction (RAS) is a commonly used technique for predicting function return addresses. Function calls and returns utilize the CALL and RETURN instructions, respectively. The CALL instruction calls a subroutine at a fixed address (such as the starting address of a function), but the subroutine may be called in many places within the main program, thus changing the return address. The RETURN instruction, on the other hand, always targets the instruction following the most recent CALL instruction. Figure 1 As shown, the main program calls subroutine 1 through the Call Mul instruction, and subroutine 1 calls subroutine 2 through CallSub.
[0038] Reference Figure 2 The processor uses a Last-In-First-Out (LIFO) memory to store the return address of the next CALL instruction after the current CALL instruction. When the RETURN instruction is executed, the return address stored in memory is popped to predict the jump to the RETURN instruction. This memory works in the same way as the stack, hence it is called the Return Address Stack (RAS). When a CALL instruction is executed, a push operation is performed to store the return address; when a RETURN instruction is executed, the return address is popped from the stack. For example... Figure 2 As shown, the address of Mul is pushed onto the stack first, followed by the address of Add, and finally the address of Sub. When the RETURN instruction is executed, the addresses are retrieved in the reverse order.
[0039] However, refer to Figure 3Taking a classic five-stage pipelined processor as an example, when the first CALL instruction arrives at the IFU (Instruction Fetch Unit), its RAS (Return Address Storage) unit fills the stack with the return address of the CALL instruction. Next, the processor fetches a conditional jump instruction and performs branch prediction, which predicts no jump. Then, the processor sequentially fetches the second CALL instruction, and the RAS fills the stack with the return address of the second CALL instruction. When the processor's EXU (Execution Unit) discovers that the IFU's prediction of the jump direction for the conditional jump instruction was incorrect and that a jump should actually occur, the ALU (Arithmetic Logic Unit) flushes the CALL instruction from the DEC (Decoder Unit) pipeline and executes the destination address of the conditional jump instruction. The second CALL instruction is not actually executed; however, the RAS in the IFU has been updated by the second CALL instruction, containing two return addresses. When the first CALL instruction executes the RETURN instruction to return, the return address provided by the RAS is actually the return address of the flushed second CALL instruction, not the return address of the first CALL instruction, ultimately leading to an error in return address prediction.
[0040] To address the aforementioned issues, this application provides the following main solutions: Due to the need for accurate return address prediction, the stored return addresses need to be synchronously updated when the RAS encounters pipeline flushing. This application, through research, designs a backup return address stack for each pipeline processing unit that can initiate a flushing pipeline. These backup return stacks also perform push and pop operations respectively when encountering CALL and RETURN instructions, maintaining the return address stack of the corresponding pipeline processing unit. Once the pipeline initiates a flushing operation, the backup RAS of the corresponding pipeline processing unit will completely restore the RAS content to the IFU's RAS, ensuring that the IFU's RAS stack always stores the content of the RAS at the time of the flushing pipeline, without including the effects of push and pop operations caused by CALL and RETURN instructions flushed in the preceding pipeline. This application's method is applied to a processor, which includes multiple pipelined processing units. These pipelined processing units include a first pipelined processing unit at a first pipeline stage and at least one second pipelined processing unit supporting pipeline flushing operations. The specific implementation steps include: first, obtaining the Return Address Stack (RAS) corresponding to the first pipelined processing unit and configuring the RAS corresponding to each of the at least one second pipelined processing unit; obtaining the instruction sequence to be processed and performing pipelined processing on the instruction sequence; then, during the pipelined processing of the instruction sequence, in response to a pipeline flushing operation initiated by the target pipelined processing unit, copying the RAS corresponding to the target pipelined processing unit to the RAS corresponding to the first pipelined processing unit. The target pipelined processing unit is one of the at least one second pipelined processing unit. Using the method provided in this application, RAS backup can be achieved, thereby eliminating the impact of pipeline flushing on the RAS and improving the accuracy of the RAS in predicting the return address.
[0041] based on Figure 1 The scene shown below is an illustration; the following will combine... Figure 4 - Figure 7 The return address backup method provided in the embodiments of this application will be described in detail.
[0042] Please see Figure 4 , Figure 4 This is a flowchart illustrating a return address backup method provided in an embodiment of this application. Figure 4 As shown, the method is applied to a processor, which includes multiple pipeline processing units, including a first pipeline processing unit in a first pipeline stage, and at least one second pipeline processing unit that supports initiating a pipeline flushing operation. The method of this application embodiment may include the following steps S101-S103.
[0043] S101, obtain the return address stack (RAS) corresponding to the first pipeline processing unit, and configure the RAS corresponding to each of the at least one second pipeline processing unit.
[0044] Specifically, the processor involved in this embodiment refers to a central processing unit (CPU) with a pipelined architecture, which includes multiple sequentially connected pipelined processing units. A pipelined processing unit refers to a hardware module in the processor pipeline that performs a specific processing function, including an instruction fetch unit, a decoding unit, and an execution unit. The first pipeline stage refers to the pipeline stage in the processor pipeline that processes instructions first. The first pipelined processing unit refers to the processing unit located in the first pipeline stage, which is responsible for the initial processing of instructions. The second pipelined processing unit refers to the processing unit located after the first pipeline stage, which can detect and handle abnormal situations such as branch prediction errors. The pipeline flushing operation refers to the operation of clearing instructions in the subsequent pipeline and re-fetching instructions when a branch prediction error or abnormality is detected.
[0045] In one possible implementation, obtaining the RAS corresponding to the first pipelined processing unit and configuring the RAS corresponding to each of the at least one second pipelined processing unit refers to: during the processor initialization phase, allocating a main return address stack storage space for the first pipelined processing unit, and simultaneously allocating an independent backup return address stack storage space for each second pipelined processing unit; during processor operation, keeping the return address stack of the first pipelined processing unit synchronized with the return address stack of each second pipelined processing unit.
[0046] S102, Obtain the instruction sequence to be processed, and perform pipeline processing on the instruction sequence to be processed.
[0047] Specifically, the instruction sequence to be processed in this embodiment refers to a program instruction stream that includes function call instructions, function return instructions, and other instructions that may affect the prediction of the return address.
[0048] In one possible implementation, obtaining the sequence of instructions to be processed and performing pipelined processing on the sequence of instructions to be processed refers to: the processor sequentially reading instructions from the instruction cache and processing them through pipeline stages such as instruction fetch, decoding, and execution; when a function call instruction is encountered, the return address is pushed onto the return address stack of the first pipeline processing unit and each of the second pipeline processing units; when a function return instruction is encountered, the predicted return address is popped from the return address stack.
[0049] S103, during the pipelined processing of the instruction sequence to be processed, in response to the pipeline flushing operation initiated by the target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit, wherein the target pipeline processing unit is one of at least one of the second pipeline processing units.
[0050] Specifically, in this embodiment, the target pipeline processing unit refers to the second pipeline processing unit that detects a branch prediction error or anomaly and triggers a pipeline flushing operation; the RAS corresponding to the target pipeline processing unit refers to the backup return address stack maintained by the second pipeline processing unit; and the RAS corresponding to the first pipeline processing unit refers to the main return address stack.
[0051] In one possible implementation, during the pipelined processing of the instruction sequence to be processed, in response to a pipeline flushing operation initiated by the target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit. The target pipeline processing unit being one of at least one of the second pipeline processing units means that when a second pipeline processing unit detects a branch prediction error, it first saves the current processor state, then completely copies the contents of its maintained backup return address stack to the main return address stack of the first pipeline processing unit, and finally performs a pipeline flushing operation and fetches instructions again.
[0052] More specifically, refer to Figure 5 In the proposed scheme, a backup return address stack is designed for each pipeline stage that can initiate a flushing pipeline. These backup return stacks also perform push and pop operations respectively when encountering CALL and RETURN instructions, maintaining the return address stack of the corresponding pipeline. Once a pipeline initiates a flushing operation, the backup RAS of the corresponding pipeline stage completely restores its contents to the IFU's RAS, ensuring that the IFU's RAS stack always stores the contents of the RAS at the time of the flushing pipeline, without including the effects of push and pop operations caused by CALL and RETURN instructions flushed in the preceding pipeline. Therefore, the IFU's RAS can avoid the effects of pipeline flushing, ensuring the accuracy of the RAS's return address prediction.
[0053] In this embodiment, by configuring an independent backup return address stack for each second pipelined processing unit, and copying the backup return address stack of the detected abnormal second pipelined processing unit to the main return address stack of the first pipelined processing unit during a pipeline flush operation, the problem of inaccurate return address prediction after pipeline flushing in traditional processors is effectively solved. More specifically, this embodiment ensures the reliability of the return address stack through a multi-copy mechanism, enabling accurate recovery even in the event of branch prediction errors, thereby eliminating the impact of pipeline flushing on the RAS and improving the accuracy of return address prediction by the RAS.
[0054] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating the return address prediction process provided in one embodiment of this application. Figure 6 As shown, the method in this application embodiment may include the following step S104, which can be used as a step in... Figure 4 The example shown is executed after step S103.
[0055] S104, predict the return address based on the RAS corresponding to the first pipeline processing unit.
[0056] Specifically, the return address prediction involved in this application embodiment refers to the process of predicting and obtaining the address of the next instruction to be executed in advance based on the historical return address information stored in the return address stack when the processor executes a function return instruction. This prediction process is used to reduce pipeline pauses caused by waiting for the actual return address calculation and improve processor execution efficiency.
[0057] In one possible implementation, predicting the return address based on the RAS corresponding to the first pipeline processing unit means that when the pipeline processing unit encounters a function return instruction, it pops the return address stored at the top of the stack from the main return address stack corresponding to the first pipeline processing unit and sends this address as the prediction result to the instruction fetch unit. The instruction fetch unit prefetches instructions from the instruction cache based on the predicted return address and continues to execute subsequent pipeline processing. At the same time, the execution unit calculates the actual return address in parallel. If the predicted address is inconsistent with the actual address, a pipeline flushing operation is triggered and the return address stack is corrected.
[0058] In this embodiment, return address prediction is performed based on the RAS corresponding to the first pipeline processing unit. Through the synchronization and recovery mechanism of the multi-level return address stack, the accuracy of return address prediction and the execution efficiency of the processor are effectively improved.
[0059] based on Figure 4 The embodiment shown illustrates another embodiment of this application.
[0060] In this embodiment of the application, the sequence of instructions to be processed includes a CALL instruction, a RETURN instruction, and a return address prediction interference instruction, wherein the return address prediction interference instruction includes a conditional jump instruction.
[0061] Specifically, in the embodiments of this application, the CALL instruction refers to an instruction used to trigger a function call, the execution process of which includes pushing the return address onto the return address stack (RAS) and jumping to the target function address; the RETURN instruction refers to an instruction used to return from a function, the execution process of which includes popping the return address from the return address stack and jumping to that address; the return address prediction interference instruction refers to an instruction that may affect the accuracy of the return address stack, including but not limited to conditional jump instructions, indirect jump instructions, and exception handling instructions.
[0062] In one possible implementation, identifying the instruction type in the sequence of instructions to be processed and performing the corresponding operation means:
[0063] When a CALL instruction is detected, the address of the next instruction of the current instruction is used as the return address and is simultaneously pushed onto the main return address stack corresponding to the first pipeline processing unit and the backup return address stack corresponding to each second pipeline processing unit.
[0064] Alternatively, when a RETURN instruction is detected, the top return address is popped from the main return address stack corresponding to the first pipeline processing unit as the predicted address, and a prefetch operation is performed based on that address.
[0065] Alternatively, when a return address prediction interference instruction is detected, the update operation of the return address stack is paused until the actual execution path of the instruction is determined; if the conditional jump instruction jumps and the target address is inconsistent with the current function call stack, a correction operation is performed on the return address stack.
[0066] In another possible implementation Figure 4 Step S102 in the illustrated embodiment involves pipelined processing of the instruction sequence to be processed, including:
[0067] The instruction input order is determined according to the sequence of instructions to be processed. The CALL instruction, RETURN instruction, and conditional jump instruction in the sequence of instructions to be processed are sequentially input into the processor for instruction processing according to the instruction input order. The CALL instruction is used to control the execution of a push operation on the RAS, the RETURN instruction is used to perform a pop operation on the RAS, and the conditional jump instruction is used by the processor to perform a branch processing operation.
[0068] Specifically, the instruction input order described in this application embodiment refers to the original execution order of the instruction sequence to be processed in the program flow. The processor processes the CALL instruction, RETURN instruction and conditional jump instruction in sequence according to this order, and dynamically maintains the synchronization state of RAS.
[0069] Furthermore, during the CALL instruction processing stage, after the processor recognizes the CALL instruction, it first calculates the address of its next sequential instruction as the return address; then, it synchronously pushes the return address into the main RAS of the main pipelined processing unit and the backup RAS of other pipelined processing units; finally, it updates the stack top pointer and depth counter of all RAS.
[0070] During the RETURN instruction processing phase, the processor pops the return address from the top of the stack from the main RAS as the prediction target address; the processor can prefetch instructions based on the prediction address using the instruction fetch unit, and the execution unit verifies the address correctness in parallel; if a prediction error occurs, the backup RAS is used for state recovery.
[0071] During the conditional jump instruction processing phase, it is necessary to monitor the actual jump target address of the conditional jump instruction. When the jump target does not match the current function call chain, the push / pop operation of the main RAS is first paused. Then, the affected RAS entries are cleared. Finally, the stack state of each pipeline processing unit is resynchronized through the backup RAS.
[0072] This embodiment achieves high-precision RAS state management through strict adherence to instruction sequence and a dynamic maintenance mechanism. Specifically, the integrity of the function call chain is guaranteed through atomic stack operations of CALL / RETURN instructions.
[0073] based on Figure 4 The embodiment shown illustrates another embodiment of this application.
[0074] In the embodiments of this application, Figure 4 Step S101 in the implementation shown includes configuring the RAS corresponding to each of the at least one second pipeline processing unit, including:
[0075] During processor initialization, independent address stack storage space is allocated for each of the at least one second pipeline processing unit to configure the RAS corresponding to each of the at least one second pipeline processing unit.
[0076] In the embodiments of the application, the independent address stack storage space refers to a physical storage unit allocated separately in the processor storage area for each second pipeline processing unit. This storage unit is used to store the RAS data of the corresponding pipeline processing unit, including the return address sequence, stack pointer, and status flag bits. The capacity configuration of each independent address stack storage space is consistent with the main return address stack of the first pipeline processing unit, and it has an independent access control circuit.
[0077] In one possible implementation, during processor initialization, independent address stack storage space is allocated to each of the at least one second pipelined processing unit to configure the RAS corresponding to each of the at least one second pipelined processing unit. This refers to the hardware resource management unit allocating a dedicated register group or on-chip SRAM storage block for each second pipelined processing unit according to the processor architecture configuration parameters. The stack pointers of each return address stack are zeroed and the historical status flags are cleared through the microcode initialization program. A mapping table between the main return address stack and each backup return address stack is established, recording the base address and capacity information of each storage space.
[0078] based on Figure 4 The embodiment shown illustrates another embodiment of this application.
[0079] The return address backup method in this application embodiment further includes:
[0080] While the processor is executing instructions normally, the RAS corresponding to the first pipeline processing unit is kept synchronized with the at least one second pipeline processing unit.
[0081] Specifically, in this embodiment of the application, maintaining the synchronous update of the RAS corresponding to the first pipeline processing unit and the at least one second pipeline processing unit when the processor is executing instructions normally refers to sending the same operation instructions and data to the RAS corresponding to each of the second pipeline processing units in real time through a bus broadcast mechanism or a dedicated data path when the main return address stack of the first pipeline processing unit performs push or pop operations, so as to ensure that the stack top data, pointer position and depth counter of each stack remain strictly consistent.
[0082] Please see Figure 7 , Figure 7 This is a detailed flowchart illustrating the execution return address prediction process according to one embodiment of this application. Figure 7 As shown, the method in this embodiment may include the following steps S201-S202, and steps S201-S202 may be used as a method for... Figure 6 The detailed steps of step S104 in the illustrated embodiment.
[0083] S201, in response to the received RETURN instruction, obtain the target return address from the RAS corresponding to the first pipeline processing unit;
[0084] S202, predict the return address based on the target return address.
[0085] Specifically, in the embodiments of this application, the target return address refers to the instruction memory address read from the top of the main return address stack of the first pipeline processing unit. This address corresponds to the address of the next sequential instruction corresponding to the most recent CALL instruction that has not returned, and is used to predict the program jump target after the RETURN instruction is executed.
[0086] In one possible implementation, obtaining the target return address from the RAS corresponding to the first pipeline processing unit in response to the received RETURN instruction means that the instruction decoding unit triggers a return address prediction request when it detects the RETURN instruction opcode; or, the main return address stack controller outputs the return address stored at the top of the stack during the pipeline decoding stage; or, the target return address is transmitted to the instruction fetch unit through a dedicated data path; predicting the return address based on the target return address means that the processor first writes the target return address into the program counter through the instruction fetch unit, then the instruction cache module prefetches subsequent instructions based on this address, and finally, the execution unit verifies the consistency between the actual return address and the predicted address during the pipeline commit stage. If a deviation occurs, pipeline flushing is triggered and the backup return address stack state is restored.
[0087] This embodiment achieves high-precision prediction of the processor in complex control flow scenarios through the collaborative management mechanism of multi-level return address stacks. In addition, the synchronous update mechanism realizes atomic operation of the primary and backup stacks through a dedicated data path, which can achieve zero-cycle latency synchronization in multi-level pipelined processors.
[0088] Please see Figure 8 One embodiment of this application provides a return address backup device 800 applied to a processor. The processor includes multiple pipelined processing units, including a first pipelined processing unit at a first pipeline stage, and at least one second pipelined processing unit supporting the initiation of a pipeline flushing operation.
[0089] The configuration module 810 is used to obtain the return address stack (RAS) corresponding to the first pipeline processing unit and configure the RAS corresponding to each of the at least one second pipeline processing unit.
[0090] The processing module 820 is used to acquire a sequence of instructions to be processed and to perform pipelined processing on the sequence of instructions to be processed. During the pipelined processing of the sequence of instructions to be processed, in response to a pipeline flushing operation initiated by a target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit. The target pipeline processing unit is one of at least one of the second pipeline processing units.
[0091] Optionally, the return address backup device 800 is further configured to: predict the return address based on the RAS corresponding to the first pipeline processing unit.
[0092] Optionally, the instruction sequence to be processed includes a CALL instruction, a RETURN instruction, and a return address prediction interference instruction, wherein the return address prediction interference instruction includes a conditional jump instruction.
[0093] Optionally, the return address backup device 800 is further configured to: determine the instruction input order according to the instruction sequence to be processed, and sequentially input the CALL instruction, RETURN instruction and conditional jump instruction in the instruction sequence to be processed into the processor for instruction processing according to the instruction input order, wherein the CALL instruction controls the execution of a push operation on the RAS, the RETURN instruction controls the execution of a pop operation on the RAS, and the conditional jump instruction controls the execution of a branch processing operation by the processor.
[0094] Optionally, the return address backup device 800 is further configured to: allocate independent address stack storage space for each of the at least one second pipeline processing unit during processor initialization, so as to configure the RAS corresponding to each of the at least one second pipeline processing unit.
[0095] Optionally, the return address backup device 800 is further configured to: in response to a received RETURN instruction, obtain a target return address from the RAS corresponding to the first pipeline processing unit; and perform return address prediction based on the target return address.
[0096] Optionally, the return address backup device 800 is further configured to: maintain the synchronous update of the RAS corresponding to the first pipeline processing unit and the at least one second pipeline processing unit when the processor is executing instructions normally.
[0097] For the effects achievable in this embodiment, please refer to the relevant embodiments of the above-mentioned return address backup method, which will not be repeated here.
[0098] For specific limitations regarding the aforementioned return address backup device, please refer to the limitations of the return address backup method described above, which will not be repeated here. Each module in the aforementioned return address backup device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.
[0099] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 9 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements a return address backup method as described above. It includes: memory and a processor; the memory stores a computer program; and the processor executes the computer program to implement any step of the return address backup method described above.
[0100] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, can perform any of the steps in the above-described return address backup method.
[0101] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0102] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0103] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0104] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0105] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0106] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. A method for backing up a return address, characterized in that, Applied to a processor, the processor including multiple pipelined processing units, the multiple pipelined processing units including a first pipelined processing unit in a first pipeline stage, and at least one second pipelined processing unit supporting the initiation of a pipeline flushing operation, the method includes: Obtain the return address stack (RAS) corresponding to the first pipeline processing unit, and configure the RAS corresponding to each of the at least one second pipeline processing unit. Obtain the sequence of instructions to be processed, and perform pipeline processing on the sequence of instructions to be processed; During the pipeline processing of the instruction sequence to be processed, in response to the pipeline flushing operation initiated by the target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit, wherein the target pipeline processing unit is one of at least one of the second pipeline processing units. The first pipeline processing unit is an IFU instruction fetch unit, and the second pipeline processing unit includes at least an EXU execution unit.
2. The method according to claim 1, characterized in that, During the pipelined processing of the instruction sequence to be processed, in response to a pipeline flushing operation initiated by the target pipeline processing unit, after copying the RAS corresponding to the target pipeline processing unit to the RAS corresponding to the first pipeline processing unit, the process includes: Return address prediction is performed based on the RAS corresponding to the first pipeline processing unit.
3. The method according to claim 1, characterized in that, The sequence of instructions to be processed includes CALL instructions, RETURN instructions, and return address prediction interference instructions, the return address prediction interference instructions including conditional jump instructions.
4. The method according to claim 3, characterized in that, The pipelined processing of the instruction sequence to be processed includes: The instruction input order is determined according to the sequence of instructions to be processed. The CALL instruction, RETURN instruction, and conditional jump instruction in the sequence of instructions to be processed are sequentially input into the processor for instruction processing according to the instruction input order. The CALL instruction is used to control the execution of a push operation on the RAS, the RETURN instruction is used to perform a pop operation on the RAS, and the conditional jump instruction is used by the processor to perform a branch processing operation.
5. The method according to claim 1, characterized in that, The configuration of the RAS corresponding to each of the at least one second pipeline processing unit includes: During processor initialization, independent address stack storage space is allocated for each of the at least one second pipeline processing unit to configure the RAS corresponding to each of the at least one second pipeline processing unit.
6. The method according to claim 2, characterized in that, The step of predicting the return address based on the RAS corresponding to the first pipeline processing unit includes: In response to the received RETURN instruction, the target return address is obtained from the RAS corresponding to the first pipeline processing unit; Predict the return address based on the target return address.
7. The method according to claim 1, characterized in that, The method further includes: While the processor is executing instructions normally, the RAS corresponding to the first pipeline processing unit is kept synchronized with the at least one second pipeline processing unit.
8. A return address backup device, characterized in that, Applied to a processor, the processor including multiple pipelined processing units, the multiple pipelined processing units including a first pipelined processing unit in a first pipeline stage, and at least one second pipelined processing unit supporting the initiation of a pipeline flushing operation, including: The configuration module is used to obtain the return address stack (RAS) corresponding to the first pipeline processing unit and configure the RAS corresponding to each of the at least one second pipeline processing unit. A processing module is used to acquire a sequence of instructions to be processed and to perform pipeline processing on the sequence of instructions to be processed. During the pipeline processing of the sequence of instructions to be processed, in response to a pipeline flushing operation initiated by a target pipeline processing unit, the RAS corresponding to the target pipeline processing unit is copied to the RAS corresponding to the first pipeline processing unit. The target pipeline processing unit is one of at least one of the second pipeline processing units. The first pipeline processing unit is an IFU instruction fetch unit, and the second pipeline processing unit includes at least an EXU execution unit.
9. A computer device, comprising: The method includes a memory and a processor, the memory storing a computer program, characterized in that the processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.
Citation Information
Patent Citations
Recovery processing method and device, chip, computer equipment and storage medium
CN117008973A