Instruction fetching method and device based on multi-level branch prediction, equipment and storage medium

Abstract

The method, device and equipment for fetching instructions based on multi-stage branch prediction and the storage medium, the method comprises the following steps: obtaining the value of the program counter of the initial instruction; inputting the value of the program counter to a preset pipeline stage for processing, and obtaining a branch prediction result in combination with a branch prediction mechanism; verifying the consistency of the branch prediction result stage by stage to obtain a target instruction. The method combines multi-stage pipeline with branch instruction prediction under different access frequencies, which not only improves the efficiency of reading instructions, but also effectively improves the overall performance of the processor pipeline. Through the step-by-step confirmation of the branch prediction result, the accuracy and efficiency of the instruction stream are guaranteed, so that the processor can execute program instructions more smoothly.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and more specifically, to an instruction fetching method, apparatus, device, and storage medium based on multi-level branch prediction. Background Technology

[0002] The instruction fetch stage refers to the process by which the processor core reads instructions from memory. The address of each instruction in memory space is called the instruction's program counter. During instruction fetching, the memory address corresponding to the value of the instruction's program counter is used to fetch the instruction.

[0003] In existing technical solutions, the instruction fetch stage presents numerous challenges. For instance, address handling during instruction fetching involves various memory units, which can be broadly categorized into two types: Instruction Local Memory (ILM) with good timing but limited storage space, and Instruction Cache (ICache) with poor timing but large storage space. The choice of which memory unit to use during instruction fetch requires careful consideration. Similarly, the necessary branch prediction in the fetch stage employs various methods, including static and dynamic branch prediction. Dynamic branch prediction further includes schemes such as Branch Target Buffer (BTB) and Branch History Table (BHT). Existing solutions often utilize multi-stage prediction processing to maximize branch prediction probability without impacting the pipeline stage. However, balancing complexity, resource consumption, latency, and adaptability while leveraging multi-stage prediction mechanisms to improve branch prediction accuracy remains a crucial and challenging research direction in current processor design. Summary of the Invention

[0004] This application provides an instruction fetching method, apparatus, device, and storage medium based on multi-level branch prediction, aiming to solve the technical problem of how to effectively improve the overall performance of the processor pipeline stage while ensuring instruction fetching efficiency.

[0005] A first aspect of this application provides an instruction fetching method based on multi-level branch prediction, the method comprising:

[0006] Get the value of the program counter for the initial instruction;

[0007] The value of the program counter is input into a preset pipeline containing at least two pipeline stages. In each pipeline stage, the value of the program counter is processed by tackling, and a corresponding branch prediction result is generated based on the branch predictor corresponding to the same pipeline stage. At the same time, the value of the program counter and the branch prediction result are passed to the next pipeline stage.

[0008] Verify the consistency of branch prediction results step by step between adjacent pipeline stages;

[0009] If the verification results are inconsistent, the value of the program counter in the current pipeline stage is redirected.

[0010] If the verification results are consistent, the branch prediction result and the program counter value in the current pipeline stage are passed to the next pipeline stage.

[0011] Based on the branch prediction results that have passed the consistency verification and the corresponding program counter value, the address of the target instruction is determined and the target instruction is obtained.

[0012] In an optional embodiment of this application, the step of inputting the value of the program counter into a preset pipeline containing at least two pipeline stages, performing a timing process on the value of the program counter in each pipeline stage, and generating a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline stage includes:

[0013] In the first-stage pipeline, after the value of the program counter is clocked, a fetch request is sent to the instruction local memory or instruction cache to obtain the corresponding address instruction. The address instruction is then predicted using a preset first-stage predictor to obtain the first-stage branch prediction result and the corresponding value of the first-stage program counter.

[0014] In an optional embodiment of this application, the step of inputting the value of the program counter into a preset pipeline containing at least two pipeline stages, performing a timing process on the value of the program counter in each pipeline stage, and generating a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline stage further includes:

[0015] In the second-stage pipeline, the prediction result of the first-stage branch and the value of the first-stage program counter are timed together, and a preset second-stage predictor is used to predict based on the prediction result of the first-stage branch and the value of the program counter to obtain the prediction result of the second-stage branch and the corresponding value of the second-stage program counter.

[0016] In an optional embodiment of this application, the step of verifying the consistency of branch prediction results level by level between adjacent pipeline stages includes:

[0017] In the second-level pipeline, it is determined whether the prediction result of the second-level branch is consistent with the prediction result of the first-level branch;

[0018] If they are inconsistent, the value of the second-level program counter is redirected;

[0019] If they match, the prediction result of the second-level branch and the value of the second-level program counter are transmitted to the third-level pipeline.

[0020] In an optional embodiment of this application, the step of staking the value of the program counter in each pipeline stage and generating a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline stage further includes:

[0021] In the third-stage pipeline, the second-stage branch prediction result and the value of the second-stage program counter are tagged, and instruction code information returned by the instruction local memory or the instruction buffer is received, wherein the instruction code information is obtained by tagged the instruction fetch request after passing through the first-stage pipeline stage and the second-stage pipeline stage;

[0022] Using a preset three-level predictor, the second-level branch prediction result and the value of the program counter are predicted based on the instruction code information to obtain the third-level branch prediction result and the corresponding value of the third-level program counter.

[0023] In an optional embodiment of this application, the step of verifying the consistency of branch prediction results level by level between adjacent pipeline stages further includes:

[0024] Determine whether the third-level branch prediction result is consistent with the first-level branch prediction result and the second-level branch prediction result;

[0025] If they are inconsistent, the value of the third-level program counter is redirected;

[0026] If they match, the prediction result of the third-level branch, the value of the third-level program counter, and the instruction code information are input into the fourth-level pipeline.

[0027] In an optional embodiment of this application, the step of determining the fetch address of the target instruction based on the branch prediction result that has passed the consistency verification and the corresponding program counter value, and obtaining the target instruction, includes:

[0028] In the fourth-level pipeline, the third-level branch prediction result, the instruction code information, and the value of the third-level program counter are timed, the instruction code information is decoded, and decoded information is generated.

[0029] Based on the decoding information and the predicted jump information, the target instruction is generated and stored in the fifth-stage pipeline.

[0030] A second aspect of this application provides an instruction fetching device based on multi-level branch prediction, the instruction fetching device based on multi-level branch prediction comprising:

[0031] The acquisition module is used to acquire the value of the program counter for the initial instruction;

[0032] The processing module is used to input the value of the program counter into a preset pipeline containing at least two pipeline levels, perform tack processing on the value of the program counter in each pipeline level, generate a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline level, and pass the value of the program counter and the branch prediction result to the next pipeline level.

[0033] The validation module is used to validate the consistency of branch prediction results level by level between adjacent pipeline stages;

[0034] The verification module is also used to redirect the value of the program counter in the current pipeline stage if the verification results are inconsistent.

[0035] The verification module is further configured to, if the verification results are consistent, pass the branch prediction result and the program counter value in the current pipeline level to the next pipeline level.

[0036] The value retrieval module is used to determine the value address of the target instruction and obtain the target instruction based on the branch prediction result that has passed the consistency verification and the corresponding program counter value.

[0037] A third aspect of the embodiments of this application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above-mentioned multi-level branch prediction-based instruction fetching methods.

[0038] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, characterized in that, when executed by a processor, the computer program implements the instruction fetching step based on multi-level branch prediction as described above. Attached Figure Description

[0039] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0040] Figure 1A flowchart of the first embodiment of the instruction fetching method based on multi-level branch prediction provided in this application;

[0041] Figure 2 A flowchart of a second embodiment of the instruction fetching method based on multi-level branch prediction provided in this application;

[0042] Figure 3 A flowchart of a third embodiment of the instruction fetching method based on multi-level branch prediction provided in this application;

[0043] Figure 4 A flowchart of the fourth embodiment of the instruction fetching method based on multi-level branch prediction provided in this application;

[0044] Figure 5 A flowchart of the fifth embodiment of the instruction fetching method based on multi-level branch prediction provided in this application;

[0045] Figure 6 A flowchart of the sixth embodiment of the instruction fetching method based on multi-level branch prediction provided in this application;

[0046] Figure 7 A flowchart of the seventh embodiment of the instruction fetching method based on multi-level branch prediction provided in this application;

[0047] Figure 8 A schematic diagram of the five-stage pipeline fetching structure provided by the fetching method based on multi-stage branch prediction in this application;

[0048] Figure 9 A schematic diagram of an instruction fetching device based on multi-level branch prediction provided in one embodiment of this application;

[0049] Figure 10 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation

[0050] In implementing this application, the instruction fetch stage of existing technologies faces numerous challenges. For instance, address handling during instruction fetching involves two main storage units: Instruction Local Memory (ILM) with good timing but limited storage space, and Instruction Cache (ICache) with poor timing but large storage space. The choice of storage unit to use during memory access in the instruction fetch stage requires comprehensive consideration. Similarly, the necessary branch prediction in the instruction fetch stage employs various methods, including static and dynamic branch prediction. Dynamic branch prediction further includes schemes such as Branch Target Buffer (BTB) and Branch History Table (BHT). Existing technologies often utilize multi-stage prediction processing to maximize branch prediction probability without impacting the pipeline stage. However, balancing complexity, resource consumption, latency, and adaptability while leveraging multi-stage prediction mechanisms to improve branch prediction accuracy remains a crucial and challenging research direction in current processor design.

[0051] To address the aforementioned problems, this application provides an instruction fetching method, apparatus, device, and storage medium based on multi-level branch prediction. The method includes: obtaining the value of the program counter for an initial instruction; inputting the program counter value into a preset pipeline containing at least two pipeline stages; performing a timing process on the program counter value in each pipeline stage, generating a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline stage, and simultaneously passing the program counter value and the branch prediction result to the next pipeline stage; verifying the consistency of the branch prediction results level by level between adjacent pipeline stages; if the verification results are inconsistent, redirecting the program counter value in the current pipeline stage; if the verification results are consistent, passing the branch prediction result and the program counter value in the current pipeline stage to the next pipeline stage; and determining the address of the target instruction and obtaining the target instruction based on the consistent branch prediction result and the corresponding program counter value. This solution synchronizes the program counter value and branch prediction results in a multi-stage pipeline and verifies the consistency of branch prediction results level by level between adjacent pipeline stages. Once an inconsistency is found, the program counter of the current stage is redirected. This effectively reduces pipeline flushing caused by erroneous predictions, significantly improves the accuracy and execution efficiency of the instruction fetch stage, and enables the processor to execute program instructions more efficiently and stably.

[0052] The solutions in this application embodiment can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0053] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0054] The following is a brief description of the application environment of the instruction fetching method based on multi-level branch prediction provided in the embodiments of this application:

[0055] Please see Figure 1 The first embodiment provided in this application, in which the instruction fetching method based on multi-level branch prediction includes steps S10~S60:

[0056] Step S10: Obtain the value of the program counter for the initial instruction;

[0057] It's important to note that the Program Counter (PC) is a register in a computer's Central Processing Unit (CPU) that stores the address in memory of the next instruction to be executed. The value of the program counter is the address currently stored in the program counter register. In the following text, the value of the program counter will be referred to simply as the "PC value."

[0058] Specifically, when a computer starts up or a new program is about to begin execution, the system's CPU reads the first initial instruction and generates the PC value of the read initial instruction through the PC generation unit.

[0059] Step S20: Input the value of the program counter into a preset pipeline containing at least two pipeline levels. In each pipeline level, the value of the program counter is processed by staking, and a corresponding branch prediction result is generated based on the branch predictor corresponding to the same pipeline level. At the same time, the value of the program counter and the branch prediction result are passed to the next pipeline level.

[0060] It should be noted that the preset pipeline stages in this embodiment include at least a first-stage pipeline, a second-stage pipeline, a third-stage pipeline, a fourth-stage pipeline, and a fifth-stage pipeline. A pipeline refers to the process of decomposing the execution of instructions into a series of continuous small steps or stages in computer processor design, with each stage completing a specific task.

[0061] Specifically, firstly, in the first-stage pipeline, the value of the program counter (PC) is input. This value is then "stabilized" (i.e., the data is stabilized under the influence of a clock signal) by the first-stage pipeline, and a fetch request is sent to the instruction local memory or instruction cache to obtain the corresponding address instruction. Subsequently, a preset first-stage predictor predicts the address instruction, obtaining the first-stage branch prediction result and its corresponding program counter value. The first-stage branch prediction result and its corresponding first-stage program counter value obtained from the first-stage pipeline are then input into the second-stage pipeline.

[0062] In the second-stage pipeline, the prediction results of the first-stage branch and the corresponding value of the first-stage program counter are also "beaten". The preset second-stage predictor is used to further predict the prediction results of the first-stage branch and the value of the first-stage program counter to generate the prediction results of the second-stage branch and the corresponding value of the second-stage program counter.

[0063] In the third-level pipeline, the second-level branch prediction result and its corresponding second program counter value are processed and timed using the third-level pipeline. A pre-defined third-level predictor then predicts the second-level branch prediction result and the second-level program counter value based on the received instruction code information, thereby generating the third-level branch prediction result and the corresponding third-level program counter value. At this level, it is necessary not only to process data from the second-level pipeline but also to receive instruction code information returned from the instruction local memory or instruction cache.

[0064] In the fourth stage of the pipeline, the prediction results of the third-level branch, the instruction code information, and the corresponding value of the third-level program counter are input into the fourth-level pipeline for timing, and the decoding operation is performed to generate decoding information.

[0065] In the fifth-stage pipeline, the final target instruction is generated by combining the decoding information generated in the fourth-stage pipeline with the predicted jump information. This target instruction is then stored in the fifth-stage pipeline for subsequent execution.

[0066] By employing the above steps and combining them with branch prediction mechanisms, the efficiency of instruction fetching and execution can be significantly improved. Each stage of the pipeline undertakes a specific task, and through a step-by-step verification and correction mechanism, not only is the correctness and continuity of the instruction flow ensured, but the advantages of high-speed memory and pipelines in modern processors are also fully utilized. This ensures both prediction speed and prediction accuracy, thus providing a solid foundation for high-performance computing.

[0067] Step S30: Verify the consistency of branch prediction results level by level between adjacent pipeline stages;

[0068] It is understandable that during the processing of each pipeline level, due to possible errors in branch prediction (for example, the predicted target address does not match the actual execution path), the pipeline may load incorrect instructions. Therefore, by executing step S30 and verifying the branch prediction results generated at each level, prediction errors can be detected and corrected in a timely manner.

[0069] In this embodiment, in order to ensure that the branch prediction results of each pipeline stage are consistent with the results of other stages, thereby ensuring the correctness and continuity of the instruction flow.

[0070] In this embodiment, after each pipeline level completes its own branch prediction, the system extracts the branch prediction result of the current level and compares it with the branch prediction result of the previous pipeline level. The branch prediction result of the previous pipeline level represents the branch target address or path determined in the previous stage. The branch prediction result of the current pipeline level is the branch target address or path recalculated based on the input data of the current stage (such as program counter values, historical branch information, etc.).

[0071] Step S40: If the verification results are inconsistent, redirect the value of the program counter in the current pipeline stage;

[0072] Specifically, if an inconsistency is detected in step S30, i.e., the branch prediction results of the preceding and following pipeline levels do not match, it means that the previous prediction may be incorrect. In this case, the branch prediction result of the current pipeline level is redirected. The redirection operation typically involves updating the current branch prediction information to point to the correct instruction address. Furthermore, it is necessary to clean up instructions already loaded in the pipeline but based on incorrect predictions to prevent the execution of erroneous instructions.

[0073] Step S50: If the verification results are consistent, then the branch prediction result and the program counter value in the current pipeline level are passed to the next pipeline level.

[0074] Specifically, when step S31 confirms that the branch prediction results of the preceding and following pipeline stages are consistent, this indicates that the current prediction path is correct. Next, the system will pass the branch prediction result of the current pipeline stage along with the value of the program counter (PC) to the next pipeline stage. This process is called "pacing," meaning that data is stably transferred from one pipeline stage to the next.

[0075] By verifying the consistency of branch prediction results through the above steps, the accuracy of the instruction flow is ensured. This allows the processor to correct prediction errors at an early stage, reducing performance loss caused by misprediction. Simultaneously, this method improves pipeline processing efficiency, enabling the processor to execute programs more reliably as expected.

[0076] Step S60: Based on the branch prediction result that has passed the consistency verification and the corresponding program counter value, determine the address of the target instruction and obtain the target instruction.

[0077] It should be noted that the target instruction refers to the instruction that is ultimately confirmed as correct and needs to be executed in the pipeline. It is the instruction determined after verifying the branch prediction results at each level, ensuring that the processor can execute according to the correct program path.

[0078] In this embodiment, the branch prediction result that has passed consistency verification and is output from the third-stage pipeline, along with the corresponding program counter value, is used as the final jump basis. Combined with the instruction code information returned from the instruction cache, decoding is completed in the fourth-stage pipeline, and the decoded target instruction is passed to the fifth-stage pipeline for subsequent execution. This not only ensures the accuracy of the instruction fetch address but also improves the overall throughput efficiency of the instruction pipeline.

[0079] The method described in the above embodiments includes: obtaining the value of the program counter for an initial instruction; inputting the value of the program counter into a preset pipeline containing at least two pipeline stages; performing a timing process on the value of the program counter in each pipeline stage, and generating a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline stage; simultaneously passing the value of the program counter and the branch prediction result to the next pipeline stage; verifying the consistency of the branch prediction results level by level between adjacent pipeline stages; if the verification results are inconsistent, redirecting the value of the program counter in the current pipeline stage; if the verification results are consistent, passing the branch prediction result and the value of the program counter in the current pipeline stage to the next pipeline stage; and determining the address of the target instruction and obtaining the target instruction based on the branch prediction result that has passed the consistency verification and the corresponding value of the program counter. This solution synchronizes the program counter value and branch prediction results in a multi-stage pipeline and verifies the consistency of branch prediction results level by level between adjacent pipeline stages. Once an inconsistency is found, the program counter of the current stage is redirected. This effectively reduces pipeline flushing caused by erroneous predictions, significantly improves the accuracy and execution efficiency of the instruction fetch stage, and enables the processor to execute program instructions more efficiently and stably.

[0080] Please see Figure 2 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the second embodiment of this application to an instruction fetching method based on multi-level branch prediction. The instruction fetching method based on multi-level branch prediction provided in this embodiment further includes the following step A21:

[0081] Step A21: In the first-stage pipeline, after staking the value of the program counter, a fetch request is sent to the instruction local memory or instruction cache to obtain the corresponding address instruction. The address instruction is then predicted using a preset first-stage predictor to obtain the first-stage branch prediction result and the corresponding value of the first-stage program counter.

[0082] It's important to note that address instructions are a type of control flow instruction; they can change the order of program execution. An address instruction specifies a target address and instructs the processor to continue executing instructions from that new address.

[0083] Instruction Local Memory (ILM) is a high-speed storage area specifically designed to accelerate frequently accessed instructions in certain applications.

[0084] The instruction cache (ICache) is a high-speed cache used inside the CPU to temporarily store recently or frequently accessed instructions in order to speed up instruction retrieval.

[0085] Specifically, firstly, the PC value generated in step S10 is passed to the first-stage pipeline and a "stamping" operation is performed. "Stamping" refers to the stable transfer of data from one stage to the next, ensuring signal integrity and synchronization. Simultaneously, based on the PC value, a fetch request is sent to the instruction local memory or instruction cache to retrieve the instruction located at that address, i.e., the address instruction.

[0086] After obtaining the address instruction, a pre-defined first-level predictor is used to make a preliminary prediction as to whether the address instruction is a jump instruction (such as a conditional branch, unconditional jump, etc.). The first-level predictor is usually based on a simple prediction algorithm (such as static prediction, local history table, or global history table) to quickly determine the branch direction (jump or no jump).

[0087] If the prediction is no jump, the PC value is kept incremented, and instruction fetching continues sequentially. If the prediction is a jump, the predicted target jump address is sent to the PC generation unit to update the PC value so that subsequent pipelines can load the instruction at the target address.

[0088] Finally, the first-level branch prediction results (including jump direction and target address) generated by the preset first-level predictor and the current PC value are packaged into a set of information and passed to the second-level pipeline, and further stably passed through the "tapping" operation.

[0089] The above-described method, which involves passing instruction fetch requests, first-level branch prediction results, and the first-level pipeline to the second-level pipeline, achieves efficient instruction fetching and branch prediction. This method not only reduces the impact of pipeline stalls and prediction errors but also fully utilizes the advantages of high-speed memory and multi-stage pipelines, significantly improving the overall performance of the processor.

[0090] Please see Figure 3 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the third embodiment of this application to an instruction fetching method based on multi-level branch prediction. The key negotiation method provided in this embodiment further includes the following step B21:

[0091] Step B21: In the second-level pipeline, the first-level branch prediction result and the value of the first-level program counter are timed together, and a preset second-level predictor is used to predict based on the first-level branch prediction result and the value of the program counter to obtain the second-level branch prediction result and the corresponding value of the second-level program counter.

[0092] It should be noted that, in this embodiment, the preset second-level predictor is typically more complex and accurate than the preset first-level predictor. It can improve prediction accuracy based on more historical information, global patterns, or other advanced algorithms. For example, it may use more complex local or global history tables, or combine both methods to enhance predictive capabilities.

[0093] In this embodiment, a preset secondary predictor checks the accuracy of the first-level prediction result. This includes confirming whether the branch actually occurred and whether the target address is correct. Based on the analysis of the preset secondary predictor, a second-level branch prediction result is generated. This second-level branch prediction result may be a correction to the first-level branch prediction result or a completely new prediction. If an error is found in the first-level prediction, the preset secondary predictor will provide the correct branch path and target address.

[0094] Then, based on the second-level branch prediction, the PC value may be updated to point to the correct instruction address. If the second-level prediction confirms the first-level prediction, the PC value remains unchanged; otherwise, the PC value is updated to the new target address.

[0095] Finally, after processing by the second-level predictor, the resulting second-level branch prediction and its corresponding PC value are output. This information includes not only the final determined branch direction and target address, but also all necessary state information to ensure correct instruction execution in subsequent pipeline stages.

[0096] By employing the methods described above, and adding in-depth and detailed secondary verification (secondary prediction) on top of the initial rapid prediction (first-level prediction), the accuracy and reliability of branch prediction are effectively improved. Simultaneously, more powerful resources are utilized to handle complex or difficult-to-predict branch scenarios, thereby optimizing the efficiency and performance of the entire pipeline. Furthermore, by verifying and updating the PC value at each level, the correctness and continuity of the instruction flow are ensured, reducing pipeline cleanup or redirection due to prediction errors.

[0097] Please see Figure 4 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the fourth embodiment of this application to an instruction fetching method based on multi-level branch prediction. The instruction fetching method based on multi-level branch prediction provided in this application embodiment further includes the following steps A31~A33:

[0098] Step A31: In the second-level pipeline, determine whether the prediction result of the second-level branch is consistent with the prediction result of the first-level branch;

[0099] Step A32: If there is a discrepancy, redirect the value of the second-level program counter;

[0100] Step A33: If they match, then the second-level branch prediction result and the value of the second-level program counter are transmitted to the third-level pipeline.

[0101] It should be noted that the first-level branch prediction results are generated by a preset first-level predictor, and the second-level branch prediction results are generated by a preset second-level predictor.

[0102] Understandably, this embodiment primarily verifies whether the branch prediction results between the first-level pipeline and the second-level pipeline match. By comparing the branch prediction results of the two pipelines, potential prediction errors can be detected in a timely manner, thereby preventing subsequent pipelines from loading incorrect instructions.

[0103] Specifically, the branch direction (jump or no jump) of the first-level branch prediction result and the second-level branch prediction result is compared firstly. If it is a jump instruction, the target addresses of the two are further compared to see if they are the same.

[0104] If they match, it means that the branch prediction results of the two pipeline levels are matched, and the branch prediction result of the second level and the program counter (PC) value of the second level are input into the third pipeline for further prediction and verification.

[0105] If there is a discrepancy, it indicates a potential error in the first-stage predictor, requiring redirection of the second-stage program counter (PC) value to correct the erroneous prediction path. In this case, within the second-stage pipeline, the second-stage program counter (PC) value is updated based on the corrected branch direction and target address provided by the second-stage predictor. Instructions loaded based on the erroneous prediction are then cleared, and instructions are fetched again from the correct address.

[0106] By comparing the prediction results of the first-level branch and the prediction results of the second-level branch using the methods described above, not only is the impact of prediction errors on pipeline performance reduced, but the continuity of instruction flow and the overall efficiency of the processor are also optimized.

[0107] Please see Figure 5 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the fifth embodiment of this application to an instruction fetching method based on multi-level branch prediction. The instruction fetching method based on multi-level branch prediction provided in this application embodiment further includes the following steps C21~C22:

[0108] Step C21: In the third-stage pipeline, the second-stage branch prediction result and the second-stage program counter are timed, and instruction code information returned by the instruction local memory or the instruction cache is received. The instruction code information is obtained by timed after the instruction fetch request is timed through the first-stage pipeline and the second-stage pipeline.

[0109] Step C22: Using a preset three-level predictor, the second-level branch prediction result and the value of the second-level program counter are predicted based on the instruction code information to obtain the third-level branch prediction result and the corresponding value of the third-level program counter.

[0110] It should be noted that instruction code information refers to the actual instruction content to be executed, retrieved from the instruction local memory (ILM) or instruction cache (ICache), and includes the specific instruction content that the processor will actually execute.

[0111] It is understood that this embodiment aims to pass the branch prediction results (including branch direction and target address) of the first two pipeline stages and the program counter (PC) value to the third pipeline stage, while obtaining the actual instruction code information from the instruction local memory (ILM) or instruction cache (ICache).

[0112] Specifically, first, the second-level branch prediction results generated by the second-level predictor (including whether to jump and its target address) and the corresponding PC value of the second-level program counter are packaged and passed to the third-level pipeline through a "tapping" operation.

[0113] Since the initial PC value has already been sent to the instruction local memory or instruction cache in the first and second stages of the pipeline, the corresponding instruction code information is returned and received by the third stage of the pipeline after processing by the two pipeline stages.

[0114] Then, the second-level branch prediction result, its corresponding second-level program counter (PC) value, and the actual instruction code information received from the instruction local memory or instruction cache are input into a preset third-level predictor. The preset third-level predictor analyzes the received instruction code information, identifies the specific instruction type (e.g., conditional branch, unconditional jump), and, in conjunction with the instruction code information and the branch prediction results of the first two levels, comprehensively evaluates the branch behavior to determine the final branch direction and target address.

[0115] After processing by the third-level predictor, a third-level branch prediction result is generated, which includes whether a jump occurs and the correct jump target address. Furthermore, the value of the third-level program counter is updated based on the third-level branch prediction result to ensure that subsequent pipelines can correctly fetch and execute instructions.

[0116] By using the methods described above, the second-level branch prediction result and the value of the second-level program counter are passed to the third-level pipeline. Combined with the actual instruction code information obtained from the ILM or ICache, the third-level predictor can make more accurate predictions. This method not only improves the accuracy of branch prediction but also optimizes pipeline performance, ensuring the continuity and correctness of the instruction flow.

[0117] Please see Figure 6 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the sixth embodiment of this application to an instruction fetching method based on multi-level branch prediction. The instruction fetching method based on multi-level branch prediction provided in this application embodiment further includes the following steps B31~B33:

[0118] Step B31: Determine whether the prediction results of the third-level branch are consistent with the prediction results of the first-level branch and the second-level branch.

[0119] Step B32: If there is a discrepancy, the value of the third-level program counter is redirected;

[0120] Step B33: If they match, the third-level branch prediction result, the value of the third-level program counter, and the instruction code information are input into the fourth-level pipeline.

[0121] It is understood that the method in this embodiment aims to perform an eventual consistency check on the branch prediction results in the third-level pipeline. By comparing the branch prediction results of the first, second, and third levels, the accuracy of the current branch prediction path can be confirmed, avoiding instruction loading deviations caused by early prediction errors.

[0122] Specifically, first, compare the prediction results of the third-level branch with those of the first two levels. If it is a jump instruction, further compare whether the target addresses are the same. If it is not a jump instruction, only the branch direction needs to be confirmed.

[0123] If they match, it means that the prediction result of the third-level branch matches the prediction results of the first two levels of branches. The prediction result of the third-level branch, the value of the third-level program counter, and the instruction code information are then input into the fourth-level pipeline for prediction and verification.

[0124] If there is a discrepancy, the value of the third-level program counter is updated based on the corrected branch direction and target address provided by the third-level predictor. Instructions loaded based on incorrect predictions are cleared, and instructions are fetched again from the correct address.

[0125] By comparing the prediction results of the third-level branch, the first-level branch, and the second-level branch using the methods described above, not only is the accuracy and efficiency of branch prediction ensured, but performance loss due to prediction errors is also minimized. Furthermore, combining the actual instruction code for more accurate instruction prediction significantly improves the success rate of branch prediction.

[0126] Please see Figure 7 The following embodiments use the aforementioned personal computer as the execution subject, and specifically illustrate the application of the method provided in the seventh embodiment of this application to an instruction fetching method based on multi-level branch prediction. The instruction fetching method based on multi-level branch prediction provided in this application embodiment further includes the following steps D21~D22:

[0127] Step D21: In the fourth-level pipeline, the third-level branch prediction result, the instruction code information, and the value of the third-level program counter are saturated, and the instruction code information is decoded to generate decoded information.

[0128] Step D22: Based on the decoding information and the predicted jump information, generate the target instruction and store the target instruction in the fifth-level pipeline.

[0129] It should be noted that the predicted jump information refers to the prediction results generated by the branch predictor in the processor pipeline for control flow instructions such as conditional branches and unconditional jumps in the program. It includes at least: the determination result of whether a branch jump occurs, and the target address corresponding to the jump.

[0130] Specifically, the prediction results of the third-level branch (including whether to jump and its target address), the program counter (PC) value corresponding to the third-level pipeline, and the instruction code information returned from the instruction cache are packaged and synchronously transmitted to the fourth-level pipeline through pipeline clocking operation.

[0131] In the fourth-stage pipeline, the prediction results of the third-stage branch, the value of the third-stage program counter, and the instruction code information are sent to the decoding unit. Upon receiving the data from the fourth-stage pipeline, the decoding unit parses the instruction code information, identifies the opcode (indicating the specific operation type, such as arithmetic, logical, or jump operations), and extracts the operands (including register numbers, immediate values, or memory addresses). Based on the parsing results, the decoding unit generates structured decoding information to guide subsequent execution stages, such as: the registers involved in the computation, whether memory access is required, and whether a control flow transfer exists.

[0132] For branch instructions, the decoding unit further combines the third-level branch prediction result to determine whether to adopt the predicted path. If the prediction result indicates a jump, the predicted target address is used as the fetch address for the next instruction; if the prediction result indicates no jump, the current PC value is incremented sequentially to continue fetching instructions.

[0133] Accordingly, the target instruction is retrieved from the instruction cache according to the instruction fetch address determined above, and together with the decoding information, it is passed to the fifth-level pipeline stage for temporary storage through a padding operation, so that it can be processed by subsequent execution units, memory access units, etc.

[0134] Through the methods described in the above embodiments, this solution achieves deep collaboration between branch prediction results and instruction decoding: under the premise of ensuring that the prediction path has undergone multi-level consistency verification, high-confidence prediction jump information is used to guide decoding and instruction fetching decisions, effectively avoiding pipeline erosion caused by prediction errors, and significantly improving the processor's instruction fetching efficiency and execution stability in complex control flow scenarios.

[0135] For example, to help understand the implementation flow of the instruction fetching method based on multi-level branch prediction obtained by combining this embodiment with the above embodiments one to six, please refer to... Figure 8 , Figure 8 A schematic diagram of the instruction fetching structure for a five-stage pipeline based on a multi-stage branch prediction method is provided, specifically:

[0136] This five-stage pipelined instruction fetch architecture can simultaneously support instruction local memory or instruction cache for memory units. In other words, instructions can be fetched from either local memory or the instruction cache. Frequently used fixed programs and programs requiring real-time response can be placed in local memory for fast instruction code access. Instruction codes not in local memory can be cached in the instruction cache to shorten the access frequency of high-frequency instructions. This balances fast access to frequently used instructions with real-time performance without significantly increasing the capacity of SRAM (Static Random Access Memory).

[0137] Furthermore, because instruction fetching and branch prediction are processed separately, instructions fetched from memory units can have clean timing, allowing the fetch module circuitry to operate at a higher clock frequency. In addition, this five-stage pipelined fetch architecture utilizes a three-stage prediction unit to enhance prediction performance. The first-stage predictor can directly obtain the jump target address for frequently accessed branch instructions in the next clock cycle. The first-stage predictor only predicts a limited number of jump instructions, thus saving space and accelerating the jumps of frequently accessed branch instructions. The second-stage predictor uses multiple prediction mechanisms to predict various branch instructions, achieving a higher prediction rate than the first-stage predictor. It can jump to the target address after two cycles, allowing for more accurate predictions of more branch instructions, and the cost of branch prediction is relatively low. The third-stage predictor combines the actual instruction code to perform more accurate predictions, significantly improving the branch prediction success rate. By using multi-stage predictors to perform hierarchical prediction of branch instructions with different access frequencies, the jump speed of frequently accessed branch instructions is improved, while maintaining high branch prediction accuracy and saving area overhead.

[0138] This application's embodiments utilize a five-stage pipelined instruction fetch structure, enabling dual-mode instruction fetching by simultaneously using instruction local memory and instruction cache as memory units. Instruction fetching and branch prediction are decoupled and performed in parallel, resulting in better timing. Multiple levels and types of prediction are employed, minimizing branch jump and redirection costs and increasing prediction accuracy.

[0139] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0140] Please see Figure 9 One embodiment of this application provides an instruction fetching device based on multi-level branch prediction, comprising:

[0141] Module 10 is used to obtain the value of the program counter for the initial instruction;

[0142] Processing module 20 is used to input the value of the program counter into a preset pipeline containing at least two pipeline levels, perform tack processing on the value of the program counter in each pipeline level, generate a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline level, and pass the value of the program counter and the branch prediction result to the next pipeline level.

[0143] The verification module 30 is used to verify the consistency of branch prediction results step by step between adjacent pipeline stages;

[0144] The verification module 30 is further configured to redirect the value of the program counter in the current pipeline stage if the verification results are inconsistent.

[0145] The verification module 30 is further configured to, if the verification results are consistent, pass the branch prediction result and the program counter value in the current pipeline level to the next pipeline level.

[0146] The value retrieval module 40 is used to determine the value address of the target instruction and obtain the target instruction based on the branch prediction result that has passed the consistency verification and the corresponding program counter value.

[0147] For specific limitations regarding the instruction fetching device based on multi-level branch prediction, please refer to the method limitations above, which will not be repeated here. Each module in the aforementioned instruction fetching device based on multi-level branch prediction can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0148] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 10As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and the database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the above-described multi-level branch prediction-based instruction fetch method. It includes: memory and a processor; the memory stores the computer program; and the processor executes the computer program to implement any step of the above-described multi-level branch prediction-based instruction fetch method.

[0149] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can perform any of the steps in the instruction fetching method based on multi-level branch prediction as described above.

[0150] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0151] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0152] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0153] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0154] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0155] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for fetching instructions based on multi-level branch prediction, characterized in that, The method includes: Get the value of the program counter for the initial instruction; The value of the program counter is input into a preset pipeline containing at least two pipeline stages. In each pipeline stage, the value of the program counter is processed by tackling, and a corresponding branch prediction result is generated based on the branch predictor corresponding to the same pipeline stage. At the same time, the value of the program counter and the branch prediction result are passed to the next pipeline stage. Verify the consistency of branch prediction results step by step between adjacent pipeline stages; If the verification results are inconsistent, the value of the program counter in the current pipeline stage is redirected. If the verification results are consistent, the branch prediction result and the program counter value in the current pipeline stage are passed to the next pipeline stage. Based on the branch prediction results that have passed the consistency verification and the corresponding program counter value, the address of the target instruction is determined and the target instruction is obtained.

2. The method as described in claim 1, characterized in that, The steps of inputting the value of the program counter into a preset pipeline containing at least two pipeline stages, performing a timing process on the value of the program counter in each pipeline stage, and generating a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline stage include: In the first-stage pipeline, after the value of the program counter is clocked, a fetch request is sent to the instruction local memory or instruction cache to obtain the corresponding address instruction. The address instruction is then predicted using a preset first-stage predictor to obtain the first-stage branch prediction result and the corresponding value of the first-stage program counter.

3. The method as described in claim 2, characterized in that, The step of inputting the value of the program counter into a preset pipeline containing at least two pipeline stages, performing a timing process on the value of the program counter in each pipeline stage, and generating a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline stage further includes: In the second-stage pipeline, the prediction result of the first-stage branch and the value of the first-stage program counter are timed together, and a preset second-stage predictor is used to predict the prediction result of the first-stage branch and the value of the first-stage program counter to obtain the prediction result of the second-stage branch and the corresponding value of the second-stage program counter.

4. The method as described in claim 3, characterized in that, The step of verifying the consistency of branch prediction results level by level between adjacent pipeline stages includes: In the second-level pipeline, it is determined whether the prediction result of the second-level branch is consistent with the prediction result of the first-level branch; If they are inconsistent, the value of the second-level program counter is redirected; If they match, the prediction result of the second-level branch and the value of the second-level program counter are transmitted to the third-level pipeline.

5. The method as described in claim 4, characterized in that, The step of staking the value of the program counter in each stage of the pipeline and generating the corresponding branch prediction result based on the branch predictor of the same stage pipeline further includes: In the third-stage pipeline, the second-stage branch prediction result and the value of the second-stage program counter are tagged, and instruction code information returned by the instruction local memory or the instruction buffer is received, wherein the instruction code information is obtained by tagged the instruction fetch request after passing through the first-stage pipeline and the second-stage pipeline; Using a preset three-level predictor, the second-level branch prediction result and the value of the second-level program counter are predicted based on the instruction code information to obtain the third-level branch prediction result and the corresponding value of the third-level program counter.

6. The method as described in claim 5, characterized in that, The step of verifying the consistency of branch prediction results level by level between adjacent pipeline stages further includes: Determine whether the prediction result of the third-level branch is consistent with the prediction results of the first-level branch and the second-level branch; If they are inconsistent, the value of the third-level program counter is redirected; If they match, the third-level branch prediction result, the value of the third-level program counter, and the instruction code information are input into the fourth-level pipeline.

7. The method as described in claim 6, characterized in that, The step of determining the fetch address of the target instruction based on the branch prediction result that has passed the consistency verification and the corresponding program counter value, and obtaining the target instruction, includes: In the fourth-level pipeline, the third-level branch prediction result, the instruction code information, and the value of the third-level program counter are timed, and the instruction code information is decoded to generate decoded information. Based on the decoding information and the predicted jump information, the target instruction is generated and stored in the fifth-stage pipeline.

8. An instruction fetching device based on multi-level branch prediction, characterized in that, The instruction fetching device based on multi-level branch prediction includes: The acquisition module is used to acquire the value of the program counter for the initial instruction; The processing module is used to input the value of the program counter into a preset pipeline containing at least two pipeline levels, perform tack processing on the value of the program counter in each pipeline level, generate a corresponding branch prediction result based on the branch predictor corresponding to the same pipeline level, and pass the value of the program counter and the branch prediction result to the next pipeline level. The validation module is used to validate the consistency of branch prediction results level by level between adjacent pipeline stages; The verification module is also used to redirect the value of the program counter in the current pipeline stage if the verification results are inconsistent. The verification module is further configured to, if the verification results are consistent, pass the branch prediction result and the program counter value in the current pipeline level to the next pipeline level. The value retrieval module is used to determine the value address of the target instruction and obtain the target instruction based on the branch prediction result that has passed the consistency verification and the corresponding program counter value.

9. An instruction fetching device based on multi-level branch prediction, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and running on the processor, the computer program being configured to implement the steps of the instruction fetching method based on multi-level branch prediction as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the instruction fetching method based on multi-level branch prediction as described in any one of claims 1 to 7.

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