Data transmission method and device, data transmission controller and storage medium

Abstract

The invention provides a data transmission method and device, a data transmission controller and a storage medium, and relates to the technical field of data transmission. The method comprises the following steps: acquiring a preset number of addressing information through an addressing bus; analyzing each piece of addressing information in sequence, and acquiring and sending a data block corresponding to each piece of addressing information through a data bus according to a source address and a destination address of each piece of addressing information; according to each piece of response information received by the response bus, each piece of addressing information is discarded, new addressing information is obtained through the addressing bus, and each piece of response information is a response after each data block is sent. The data transmission efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, in particular to a data transmission method and device, a data transmission controller and a storage medium. BACKGROUND

[0002] Generally, the data transmission controller performs data transmission once for each descriptor, and sends a response flag to confirm the completion of transmission after the data transmission is completed, so that a complete data transmission is performed, and the subsequent data transmission also repeatedly performs the above steps.

[0003] It can be seen that the time for obtaining a descriptor and detecting the completion of a response flag is included between two data transmissions, resulting in discontinuous data transmission and a decrease in data transmission rate. SUMMARY

[0004] The present application aims to provide a data transmission processing method and device, a data transmission controller and a storage medium to improve data transmission efficiency in view of the deficiencies in the prior art.

[0005] To achieve the above object, the technical solutions adopted by the embodiments of the present application are as follows: In a first aspect, the embodiments of the present application provide a data transmission method applied to a data transmission controller, and the method comprises: obtaining a preset number of addressing information through an addressing bus; sequentially analyzing each of the addressing information, and obtaining and sending a data block corresponding to each of the addressing information through a data bus according to the source address and the destination address of each of the addressing information; discarding each of the addressing information according to each of the response information received through a response bus, and obtaining new addressing information through the addressing bus, wherein each of the response information is a response after each of the data blocks is sent.

[0006] Optionally, the obtaining of the new addressing information through the addressing bus comprises: obtaining one of the new addressing information through the addressing bus for each of the discarded addressing information, so that the number of the addressing information remains unchanged.

[0007] Optionally, if the data transmission controller is a DMA controller, the addressing information is descriptor information, and the obtaining of the preset number of addressing information through the addressing bus comprises: obtaining a first descriptor information through a descriptor bus; obtaining the clock frequency of the DMA controller, the total number of clock cycles for the DMA controller to transmit data of a preset length, and the single data transmission length of the first descriptor information; calculating a first prefetch number according to the clock frequency, the total number of clock cycles and the single data transmission length; acquiring remaining descriptor information through the descriptor bus according to the first prefetch number.

[0008] Optionally, the acquiring of new addressing information through the addressing bus according to each of the addressing information and each of the response information received through the response bus comprises: discarding the first descriptor information according to current response information received through the response bus; calculating a second prefetch number according to the single data transmission length of the second descriptor information currently parsed; determining a to-be-acquired number according to the remaining number of the first descriptor information after the first descriptor information is discarded according to the first prefetch number and the second prefetch number; acquiring new descriptor information of the to-be-acquired number through the descriptor bus according to the to-be-acquired number.

[0009] Optionally, if the data transmission controller is one SOC controller, the one SOC controller communicates with a plurality of external devices through a communication bus, and the addressing information is address information, the acquiring of the preset number of addressing information through the addressing bus comprises: calculating a third prefetch number according to a bus clock frequency of the communication bus, a total data transmission delay, a number of clock cycles of single data transmission, a single data transmission length and a number of the external devices; acquiring a plurality of the address information of each of the external devices through the address bus according to the third prefetch number.

[0010] Optionally, if the data transmission controller is a plurality of SOC controllers, the plurality of SOC controllers respectively communicate with a plurality of external devices through a communication bus one by one, and the addressing information is address information, the acquiring of the preset number of addressing information through the addressing bus comprises: calculating a fourth prefetch number according to a bus clock frequency of the communication bus, a total data transmission delay, a number of clock cycles of single data transmission and a single data transmission length; determining a fifth prefetch number of the plurality of SOC controllers according to the fourth prefetch number; acquiring a plurality of the address information of each of the SOC controllers through the address bus according to the fifth prefetch number.

[0011] Optionally, the determining of the fifth prefetch number of the plurality of SOC controllers according to the fourth prefetch number comprises: calculating the fifth prefetch number of the plurality of SOC controllers according to a data transmission rate of the plurality of external devices and the fourth prefetch number.

[0012] In a second aspect, the embodiments of the present application further provide a data transmission device, applied to a data transmission controller, the device comprising: an addressing information acquisition module, configured to acquire a preset number of addressing information through an addressing bus; a data block sending module, configured to sequentially analyze each of the addressing information, acquire and send a data block corresponding to each of the addressing information through a data bus according to a source address and a destination address of each of the addressing information; the addressing information acquisition module is further configured to discard each of the addressing information according to each response information received through a response bus, and acquire new addressing information through the addressing bus, each of the response information being a response after each of the data blocks is sent.

[0013] Optionally, the addressing information acquisition module is further configured to acquire one of the new addressing information through the addressing bus each time one of the addressing information is discarded, so that the number of the addressing information remains unchanged.

[0014] Optionally, if the data transmission controller is a DMA controller, the addressing information is descriptor information, and the addressing information acquisition module is specifically configured to acquire a first descriptor information through a descriptor bus, acquire a clock frequency of the DMA controller, a total number of clock cycles of the DMA controller in transmitting data of a preset length, and a single data transmission length of the first descriptor information, calculate a first prefetch number according to the clock frequency, the total number of clock cycles, and the single data transmission length, and acquire remaining descriptor information through the descriptor bus according to the first prefetch number.

[0015] Optionally, the addressing information acquisition module is further configured to discard a first descriptor information according to a current response information received through the response bus, calculate a second prefetch number according to a single data transmission length of a second descriptor information currently analyzed, determine a to-be-acquired number according to a remaining number of the first descriptor information after the first descriptor information is discarded according to the first prefetch number and the second prefetch number, and acquire new descriptor information of the to-be-acquired number through the descriptor bus according to the to-be-acquired number.

[0016] Optionally, if the data transmission controller is one SOC controller, the one SOC controller communicates with a plurality of external devices through a communication bus, the addressing information is address information, and the addressing information acquisition module is specifically configured to calculate a third prefetch number according to a bus clock frequency of the communication bus, a total data transmission delay, a number of clock cycles of single data transmission, a single data transmission length, and a number of the external devices, and acquire a plurality of the address information of each of the external devices through an address bus according to the third prefetch number.

[0017] Optionally, if the data transmission controller is a plurality of SOC controllers, the plurality of SOC controllers respectively communicate with a plurality of external devices through a communication bus one by one, the addressing information is address information, and the addressing information acquisition module is specifically configured to: calculate a fourth prefetch quantity according to a bus clock frequency of the communication bus, a total data transmission delay, a clock cycle number of single data transmission, and a single data transmission length; determine a fifth prefetch quantity of the plurality of SOC controllers according to the fourth prefetch quantity; and acquire a plurality of the address information of each of the SOC controllers through an address bus according to the fifth prefetch quantity.

[0018] Optionally, the addressing information acquisition module is further configured to calculate a fifth prefetch quantity of the plurality of SOC controllers according to a data transmission rate of the plurality of external devices and the fourth prefetch quantity.

[0019] In a third aspect, an embodiment of the present application further provides a data transmission controller, including: a processor, a storage medium, and a bus, the storage medium stores program instructions executable by the processor, when the data transmission controller is running, the processor and the storage medium communicate through the bus, and the processor executes the program instructions to perform the steps of the data transmission method according to any one of the first aspect.

[0020] In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, the storage medium stores a computer program, and the computer program performs the steps of the data transmission method according to any one of the first aspect when the computer program is run by a processor.

[0021] The present application has the following beneficial effects: The data transmission method, device, data transmission controller, and storage medium provided by the present application can obtain a plurality of addressing information for caching by pre-fetching, after transmitting each data, without waiting for sending a response to the cache and obtaining the next addressing information, the next addressing information can be directly read from the cache queue for the next data transmission, and the addressing information in the cache queue is updated according to the received response, so that there is always addressing information on standby in the cache queue, the time for waiting for sending a response to the cache and obtaining the next addressing information after each data transmission is saved, the continuity of data transmission is ensured, and the data transmission efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those of ordinary skill in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0023] Figure 1 The architecture diagram of the data transmission system; Figure 2 The existing data transmission timing diagram; Figure 3 The flow diagram of the data transmission method provided by the embodiments of the present application Figure 1 ; Figure 4 The architecture diagram of the data transmission system based on the DMA controller provided by the embodiments of the present application; Figure 5 The flow diagram of the data transmission method provided by the embodiments of the present application Figure 2 ; Figure 6 The flow diagram of the data transmission method provided by the embodiments of the present application Figure 3 ; Figure 7 The data transmission timing diagram based on the DMA controller provided by the embodiments of the present application; Figure 8 The architecture of the data transmission system based on the SOC controller provided by the embodiments of the present application Figure 1 ; Figure 9 The flow diagram of the data transmission method provided by the embodiments of the present application Figure 4 ; Figure 10 The architecture of the data transmission system based on the SOC controller provided by the embodiments of the present application Figure 2 ; Figure 11 The flow diagram of the data transmission method provided by the embodiments of the present application Figure 5 ; Figure 12 The data transmission timing diagram based on the SOC controller provided by the embodiments of the present application; Figure 13 The structure diagram of the data transmission device provided by the embodiments of the present application; Figure 14 The schematic diagram of the data transmission controller provided by the embodiments of the present application. DETAILED DESCRIPTION

[0024] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application.

[0025] Therefore, the detailed description of the embodiments of the present application provided below in the drawings is not intended to limit the scope of the present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work under the premise that the embodiments in the present application belong to the scope of protection of the present application.

[0026] In addition, the terms "first", "second", and the like in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0028] In order to better understand the present application, the following will first introduce the architecture of the data transmission system to which the present application is directed.

[0029] Figure 1 For the architecture diagram of the data transmission system, as shown in Figure 1 The data transmission system can include a central processing unit (CPU), a data transmission controller, a cache and an external device, and the CPU, the data transmission controller, the cache and the external device communicate with each other through an internal communication bus.

[0030] The CPU prepares a chain table of addressing information in the cache, the chain table of addressing information includes a plurality of addressing information, the addressing information indicates a source address, a destination address and a data transmission length of data transmission, the CPU sends a start instruction to the data transmission controller, the start instruction includes a start address of the chain table of addressing information, the data transmission controller acquires the addressing information from the cache according to the start address of the chain table of addressing information, and realizes data transmission between the cache and the external device according to the source address, the destination address and the data transmission length in the addressing information, and after the data transmission is completed, the data transmission controller sends a response information to the cache to update the state of the addressing information to completion.

[0031] For the case that the external device sends data blocks to the cache, the CPU prepares a plurality of addressing information in the cache in advance, the source address of the addressing information is the register address of the external device, the destination address is the address of the buffer area allocated from the cache in advance, and the data transmission length is the size of the cache queue, and the addressing information is marked as an “idle” state, and when the data transmission controller reads the addressing information according to the instruction of the CPU and writes data into the buffer of the cache according to the information of the addressing information, the addressing information is marked as a “completion” state.

[0032] For the case that the cache sends data blocks to the external device, in one case, the CPU can prepare a plurality of addressing information in the cache in advance, the source address of the addressing information is the address of the buffer area allocated from the cache in advance, the destination address is the register address of the external device, and the data transmission length is the size of the cache queue, and the addressing information is marked as an “idle” state, and when data needs to be sent to the external device, the data is stored in the buffer area, the data transmission controller reads the addressing information, acquires data from the buffer area and writes the data into the external device, and the addressing information is marked as a “completion” state; in another case, when the CPU receives a data transmission instruction, the CPU dynamically generates addressing information according to the buffer area address of the data and the register address of the external device and stores the addressing information in the cache, and then the data transmission controller reads the addressing information, acquires data from the buffer area and writes the data into the external device.

[0033] In addition to the source address, the destination address and the data transmission length, the addressing information also includes a cache address pointer for pointing to the next addressing information, so that the data transmission controller can acquire the next addressing information.

[0034] Different logical function channels of the internal communication bus are abstractly divided into an addressing bus, a data bus and a response bus, the data transmission controller acquires the addressing information from the cache through the addressing bus, performs data transmission between the cache and the external device through the data bus, and sends a response result to the cache through the response bus to update the state of the addressing information.

[0035] Figure 2For the existing data transmission timing diagram, as Figure 1 and as Figure 2 shown, the data transmission controller first obtains addressing information 0 from the cache through the addressing bus, parses the source address and destination address from the addressing information 0, reads data 0 from the source address through the data bus and sends data 1 to the data bus, sends response 0 to the cache through the response bus after the data transmission is completed, determines that a complete data transmission is completed, and then repeats the step to sequentially send addressing information 1, data 1, response 1, addressing information 2, data 2, response 2, …, addressing information n, data n, and response n.

[0036] As can be seen, this data transmission method needs to wait for sending a response to the cache and obtaining the next addressing information after each data transmission, and then the data can be transmitted again, resulting in discontinuous data transmission twice, and the data transmission rate is reduced.

[0037] Therefore, the present application provides a data transmission method, which obtains a plurality of addressing information through pre-fetching to cache, so that after each data transmission, the next addressing information can be directly read from the cache queue for the next data transmission without waiting for sending a response to the cache and obtaining the next addressing information, and the addressing information in the cache queue is updated according to the received response to ensure that there is always addressing information in the cache queue, saving the time of waiting for sending a response to the cache and obtaining the next addressing information after each data transmission, ensuring the continuity of data transmission, and improving the data transmission efficiency.

[0038] The data transmission method provided by the present application is applied to the data transmission controller of the above-mentioned data transmission system, and the specific implementation of the data transmission method provided by the present application will be described below in conjunction with the embodiments.

[0039] Figure 3 The flowchart of the data transmission method provided by the present application is shown in the embodiment Figure 1 As shown in Figure 3 , the method can include: S101, obtaining a preset number of addressing information through the addressing bus.

[0040] In this embodiment, a cache queue is provided in the data transmission controller, and the cache queue adopts the first in first out (FIFO) principle. After receiving the start address of the addressing information chain table sent by the CPU, the data transmission controller obtains a preset number of addressing information from the cache through the addressing bus according to the start address of the addressing information chain table.

[0041] The preset number can be a fixed number set by a user in advance, or a dynamically changing number, and the preset number is greater than or equal to 2.

[0042] S102, sequentially analyze each addressing information, and obtain and send the data block corresponding to each addressing information through the data bus according to the source address and the destination address of each addressing information.

[0043] In the embodiment, the data transmission controller sequentially analyzes each addressing information according to the storage order of the addressing information in the cache queue. For each addressing information, the source address and the destination address in the addressing information are analyzed. If the source address is an external device, the single data transmission length also needs to be analyzed.

[0044] The data transmission controller reads the data block from the device corresponding to the source address through the read data channel of the data bus according to the source address and the destination address, and writes the database into the device corresponding to the destination address through the write data channel of the data bus.

[0045] If the source address is an external device and the destination address is a cache, the data transmission controller reads the data block of the single data transmission length from the external device and writes it into the cache according to the single data transmission length. If the data length that the external device needs to write into the cache is greater than the single data transmission length, multiple data transmissions based on multiple addressing information are needed to complete the transmission of the complete data.

[0046] If the source address is a cache and the destination address is an external device, the CPU will divide the data to be transmitted into data blocks of lengths corresponding to the sizes of the buffer areas according to the sizes of the multiple buffer areas pre-allocated in the cache. The single data transmission length in each addressing information is the size of the corresponding buffer area.

[0047] After transmitting each data block, the data transmission controller immediately reads the next addressing information from the cache queue and performs the next data transmission according to the next addressing information, thereby realizing continuous data transmission.

[0048] S103, according to each response information received through the response bus, discard each addressing information, and obtain new addressing information through the addressing bus. Each response information is the response after sending each data block.

[0049] In the embodiment, after the data transmission controller writes the data block into the device corresponding to the destination address through the data bus, it will receive the response information sent by the device corresponding to the destination address through the response bus. The response information includes the data write state as complete, failure or decoding error. Decoding error indicates that the corresponding device is not found according to the destination address.

[0050] The data transmission controller discards the addressing information corresponding to the response information in the cache queue after receiving each response information, and simultaneously obtains new addressing information from the cache through the addressing bus to supplement the addressing information cached in the cache queue.

[0051] In some embodiments, the data transmission controller assigns a unique transaction identification to each data transmission transaction, each addressing information, each data block corresponding to the addressing information and each response information has a corresponding transaction identification, and when receiving the response information, the data transmission controller discards the addressing information having the same transaction identification as the response information according to the transaction identification of the response information, so as to ensure that the data transmission controller can find the corresponding addressing information and discard it through the transaction identification regardless of the order of the response.

[0052] Further, if the response information contains a data write state of failure or decoding error, the data transmission controller can record the transaction identification of the response information and continue to send other data blocks, so as to determine the failed data blocks after the data transmission is completed, or directly trigger an interrupt to stop the data transmission process.

[0053] In some embodiments, the addresses of the addressing information are continuous and equidistant, and the size of the addressing information is fixed, and the data transmission controller can calculate the addresses of the preset number of addressing information according to the starting address of the addressing information chain table and the size of the addressing information to obtain the preset number of addressing information.

[0054] When receiving a response information, the addressing information of the response information is invalidated, and the address of the new addressing information can be calculated in the above manner to obtain the new addressing information.

[0055] In other embodiments, the addressing information stores a cache address pointer for pointing to the next addressing information, and the data transmission controller parses the cache address pointer in the addressing information to obtain the next addressing information according to the cache address pointer after obtaining each addressing information, until the preset number of addressing information is obtained.

[0056] The cache address pointer in the last addressing information of the preset number of addressing information indicates the address of the new addressing information, and when receiving a response information, the addressing information of the response information is invalidated, and the new addressing information is obtained according to the cache address pointer in the last addressing information.

[0057] Further, when the cache address pointer in the pre-fetched addressing information is empty, it indicates that the addressing information is the end of the addressing information chain table, and after sending the corresponding data block based on the addressing information, a complete data transmission is completed.

[0058] Further, for continuous data stream, a circular linked list is set in the cache, and the cache address pointer of the addressing information at the end of the linked list points to the addressing information at the head of the linked list, so that the addressing information is continuously prefetched from the cache. The content in the buffer of the cache corresponding to the source address or the destination address of each addressing information is cleared after being read or written, so that new data enters the buffer.

[0059] The data transmission method provided by the above embodiment acquires multiple addressing information for caching by pre-fetching, after each data is transmitted, without waiting for sending a response to the cache and acquiring the next addressing information, the next addressing information can be directly read from the cache queue for the next data transmission, and the addressing information in the cache queue is updated according to the received response, so that there is always addressing information ready in the cache queue, the time for waiting for sending a response to the cache and acquiring the next addressing information after each data transmission is saved, the continuity of data transmission is ensured, and the data transmission efficiency is improved.

[0060] In a possible implementation, the process of acquiring the new addressing information through the addressing bus in S103 can include: A new addressing information is acquired through the addressing bus each time an addressing information is discarded, so that the number of the addressing information remains unchanged.

[0061] In the embodiment, the addressing information in the cache queue is supplemented in a discard-one-supplement-one manner, so that the prefetched addressing information in the cache queue always remains a fixed preset number.

[0062] In some embodiments, if the cache address pointer of the newly prefetched addressing information is empty, after receiving the response message and discarding the corresponding addressing information, no new addressing information is acquired until the prefetched addressing information in the cache queue is used up, and the data transmission process is ended.

[0063] The data transmission method provided by the above embodiment supplements the addressing information in the cache queue in a discard-one-supplement-one manner, so that there is always addressing information ready in the cache queue, the time for waiting for sending a response to the cache and acquiring the next addressing information after each data transmission is saved, the continuity of data transmission is ensured, and the data transmission efficiency is improved.

[0064] In a possible implementation, Figure 4 The architecture diagram of the data transmission system based on the DMA controller provided by the embodiments of the present application is shown in FIG. 1. Figure 4 If the data transmission controller is a direct memory access (DMA) controller, the addressing bus is a descriptor bus, and the addressing information is descriptor information.

[0065] Figure 5 Flowchart of data transmission method provided by embodiments of the present application Figure 2 As shown in Figure 5 The process of obtaining the preset number of pieces of addressing information through the addressing bus in S101 can include the following steps. S201: Obtain the first descriptor information through the descriptor bus.

[0066] In this embodiment, the first descriptor information is obtained from the cache through the addressing bus according to the start address of the addressing information chain sent by the CPU, and the descriptor information includes the source address, the destination address, the single data transmission length, and the cache address pointer of the next descriptor information.

[0067] S202: Obtain the clock frequency of the DMA controller, the total number of clock cycles of the DMA controller for transmitting data of the preset length, and the single data transmission length of the first descriptor information.

[0068] In this embodiment, the clock frequency fre of the DMA controller is the clock signal frequency of the DMA controller and the system bus for data transmission, which is the basic time unit of data transmission. The reciprocal of the clock frequency fre is the clock cycle, and the total number of clock cycles cycle is the total number of cycles required for the DMA controller to transmit data of the preset length, which can also be referred to as the total number of valid clock cycles of the transmission path.

[0069] The data bit width width refers to the number of data bits that can be transmitted through the data bus simultaneously by the DMA controller in one clock cycle. According to the data bit width width and the clock frequency fre, the absolute maximum data transmission rate that can be achieved by the DMA controller under ideal conditions, i.e., the theoretical bandwidth, can be determined. For example, the theoretical bandwidth = clock frequency fre * data bit width width.

[0070] S203: Calculate the first prefetch number according to the clock frequency, the total number of clock cycles, and the single data transmission length.

[0071] In this embodiment, the theoretical bandwidth * the total number of clock cycles cycle represents the maximum data transmission amount within cycle clock cycles. According to the maximum data transmission amount within cycle clock cycles, the single data transmission length, and the data bit width width, the first prefetch number can be calculated.

[0072] Specifically, the total number of clock cycles cycle is the product of the number of descriptor pre-fetches, the length of single data transmission, and the data bit width width, i.e., the clock frequency fre is the product of the data bit width width and the total number of clock cycles cycle, and thus the first pre-fetch number x1 is the product of the clock frequency fre and the total number of clock cycles cycle divided by the length of single data transmission.

[0073] S204, obtaining the remaining descriptor information through the descriptor bus according to the first pre-fetch number.

[0074] In some embodiments, since the first descriptor information has been pre-fetched, after the first pre-fetch number x1 is calculated, the data transmission control bus only needs to obtain x1-1 descriptor information through the descriptor bus.

[0075] In some other embodiments, after the first descriptor information is obtained, the DMA controller calculates the first pre-fetch number x1 while sending the first data block according to the first descriptor information, and obtains the other descriptor information of the first pre-fetch number x1.

[0076] The data transmission method provided by the above embodiments calculates the first pre-fetch number according to the clock frequency, the total number of clock cycles, and the length of single data transmission, ensures that the number of pre-fetched descriptor information is optimal, avoids discontinuous data transmission caused by too small pre-fetch number, or data congestion on the data channel caused by too large pre-fetch number, and improves the data transmission efficiency.

[0077] In a possible implementation manner, Figure 6 The flowchart of the data transmission method provided by the embodiments of the present application is shown in Figure 3 As shown in Figure 6 The process of discarding each addressing information according to each response information received through the response bus and obtaining new addressing information through the addressing bus in S103 can include the following steps. S301, discarding the first descriptor information according to the current response information received through the response bus.

[0078] In this embodiment, after the DMA controller receives the current response information, the first descriptor information corresponding to the current response information in the buffer queue is discarded.

[0079] In some embodiments, after the DMA controller receives the current response information, the first descriptor information with the same transaction identifier as the current response information is discarded according to the transaction identifier of the current response information.

[0080] S302, calculating the second pre-fetch number according to the length of single data transmission of the second descriptor information currently parsed.

[0081] In some embodiments, the single data transmission length indicated in the descriptor information is the same, so a fixed first prefetch quantity can be used to supplement the pre-fetched descriptor information, that is, one is supplemented for each discarded, ensuring that the prefetch quantity is maintained at the first preset quantity.

[0082] In other embodiments, the single data transmission length indicated by each descriptor information is different, and a dynamic compensation method is needed to compensate for the pre-fetched descriptor information. After the first descriptor information is discarded, the second prefetch quantity x2 is calculated according to the single data transmission length of the second descriptor information that is currently parsed and completed. The specific calculation method is consistent with the first prefetch quantity x2, and this embodiment will not be repeated here.

[0083] Among them, the second descriptor information that is currently parsed and completed can be the next descriptor information of the first descriptor information, or can be the descriptor information that is spaced by multiple after the first descriptor information. The actual received response information is used as the limit in this embodiment.

[0084] S303, determining the to-be-taken quantity according to the remaining quantity after the first descriptor information is discarded according to the first prefetch quantity and the second prefetch quantity.

[0085] In this embodiment, the remaining quantity after the first descriptor information is discarded according to the first prefetch quantity x1 is x1-1, and the to-be-taken quantity is determined according to the remaining quantity x1-1 and the second prefetch quantity x2.

[0086] Among them, if the remaining quantity x1-1 is greater than or equal to the second prefetch quantity x2, the new descriptor information can be selected not to be taken, and if the remaining quantity x1-1 is less than the second prefetch quantity x2, the to-be-taken quantity can be determined according to the difference between the remaining quantity x1-1 and the second prefetch quantity x2.

[0087] S304, acquiring the new descriptor information of the to-be-taken quantity through the descriptor bus according to the to-be-taken quantity.

[0088] In this embodiment, the DMA controller acquires the new descriptor information of the to-be-taken quantity from the cache through the descriptor bus. The way of determining the address of the new descriptor information is the same as the way of acquiring the address of the addressing information, which will not be repeated here.

[0089] The data transmission method provided by the above embodiments can dynamically calculate the prefetch quantity of the descriptor information, ensure that the quantity of the pre-fetched descriptor information is optimal, avoid that the data transmission is discontinuous due to too small prefetch quantity, or that the data on the data channel is back-pressured due to too large prefetch quantity, causing data congestion, and improve the data transmission efficiency.

[0090] Figure 7 The data transmission timing diagram based on the DMA controller provided in the embodiment of the present application is shown in Figure 7 The descriptor bus is used to pre-fetch x+1 descriptor information, and the data bus is used to send multiple data blocks in sequence. When response 0 is received, descriptor 0 is discarded, and descriptor x+1 is obtained. When response 1 is received, descriptor 1 is discarded, and descriptor x+2 is obtained. The process is repeated in sequence, and the total number of descriptor pre-fetching is ensured to be x+1. It can be seen that the sending of the data blocks is continuous in this process, and the data transmission efficiency is improved.

[0091] Further, the calculation formulas of the first pre-fetching quantity x1 and the second pre-fetching quantity x2 are pre-configured in the DMA controller. The clock frequency fre and the total number of clock cycles cycle are known values, which can be read through the corresponding configuration registers. The single data transmission length can be determined by reading the descriptor information, so that the number of descriptor pre-fetching is automatically updated according to the real-time transmission service of the DMA.

[0092] In a possible implementation manner, Figure 8 The architecture of the data transmission system based on the SOC controller provided in the embodiment of the present application is shown in Figure 1 As shown in Figure 8 If the data transmission controller is a system on chip (SOC) controller, one SOC controller communicates with multiple external devices through a communication bus, and the addressing information is address information.

[0093] The scenario in which one SOC controller is connected to multiple same external devices can be extended, for example, one host is connected to multiple displays, and one I2C controller is connected to multiple sensors distributed in different positions in a preset scenario.

[0094] Figure 9 The flowchart of the data transmission method provided in the embodiment of the present application is shown in Figure 4 As shown in Figure 9 The process of obtaining the preset number of addressing information through the addressing bus in S101 can include the following steps. S401. Calculate a third pre-fetching quantity according to a bus clock frequency of the communication bus, a total data transmission delay, a number of clock cycles of single data transmission, a single data transmission length, and a number of external devices.

[0095] In the embodiment, the bus clock frequency F of the SOC controller is the clock signal frequency of the communication bus between the SOC and the external device, the reciprocal of the bus clock frequency F is the clock cycle, the total data transmission delay A is the time required for transmitting data between the SOC controller and the external device, and the number of clock cycles B of single data transmission is the number of clock cycles consumed for completing one data transmission.

[0096] The bus data bit width W is the number of data bits that the SOC controller can transmit simultaneously through the communication bus in one clock cycle. According to the bus clock frequency F and the bus data bit width W, the absolute maximum data transmission rate that the SOC controller can reach under ideal conditions, that is, the bus theoretical bandwidth, can be determined. For example, the bus theoretical bandwidth = bus clock frequency F * bus data bit width W.

[0097] According to the total data transmission delay A and the number of clock cycles B of a single data transmission, the effective clock number C of the transmitted data can be determined, that is, effective clock number C = total data transmission delay A / number of clock cycles B.

[0098] According to the bus theoretical bandwidth and the effective clock number C, the maximum data transmission amount can be determined, that is, the maximum data transmission amount = the number of external devices n * the third prefetch number x3 * the single data transmission length L * the bus data bit width W.

[0099] Therefore, the bus theoretical bandwidth * effective clock number C = the third prefetch number x3 * the number of external devices n * the single transmission data length L * the bus data bit width W, that is, bus clock frequency F * bus data bit width W * (total data transmission delay A / number of clock cycles B) = the third prefetch number x3 * the number of external devices n * the single transmission data length L * the bus data bit width W, and therefore, the third prefetch number x3 = bus clock frequency F * (total data transmission delay A / number of clock cycles B) / (single transmission data length L * the number of external devices n).

[0100] S402, according to the third prefetch number, obtaining a plurality of address information of each external device through the address bus.

[0101] In the embodiment, since the SOC controller is externally connected to n identical external devices, according to the total third prefetch number x3 of the n external devices, the prefetch number of each external device is determined as x3 / n, and the SOC controller sets a cache queue for each external device, and x3 / n address information is prefetched from the cache for each external device, so as to realize data transmission between the external device and the cache according to the address information.

[0102] The data transmission method provided by the above embodiment ensures that there is always address information on standby in the cache queue of each external device when the SOC controller performs data transmission with each external device, saves the time for waiting for sending a response to the cache and obtaining the next address information after each data transmission, ensures the continuity of data transmission between the SOC controller and each external device, and improves the data transmission efficiency.

[0103] In another possible implementation manner, Figure 10Architecture of data transmission system based on SOC controller provided by the embodiment of the present application Figure 2 As shown in Figure 10 If the data transmission controller is a plurality of SOC controllers, the plurality of SOC controllers respectively communicate with a plurality of external devices through a communication bus one by one, and the addressing information is address information.

[0104] The plurality of SOC controllers respectively communicate with a plurality of different external devices, and are applied to an SOC chip providing a plurality of functions, and the plurality of SOC controllers are integrated in the same SOC chip.

[0105] Figure 11 Flowchart of data transmission method provided by the embodiment of the present application Figure 5 As shown in Figure 11 The process of S101 of obtaining a preset number of addressing information through an addressing bus can include the following steps. S501, according to the bus clock frequency of the communication bus, the total data transmission delay, the number of clock cycles of single data transmission, and the length of single data transmission, calculate the fourth prefetch number.

[0106] S502, according to the fourth prefetch number, determine the fifth prefetch number of the plurality of SOC controllers.

[0107] S503, according to the fifth prefetch number, obtain a plurality of address information of each SOC controller through an address bus.

[0108] In this embodiment, the way of calculating the fourth prefetch number x4 is the same as the way of calculating the third prefetch number x3, which will not be repeated here.

[0109] Since the plurality of SOC controllers are respectively hung on different external devices, the number of pre-fetching address information indicated by the data transmission between different SOC controllers and different external devices may be different, and it is necessary to allocate a reasonable fifth prefetch number x5 for each SOC controller or each external device from the fourth prefetch number x4.

[0110] In some embodiments, the weight of the plurality of external devices can be calculated according to the preset hardware parameters of the plurality of external devices, and the fifth prefetch number x5 of the plurality of SOC controllers can be determined according to the weight of the plurality of external devices and the fourth prefetch number x4.

[0111] Each SOC controller sets a cache queue for each external device, and respectively pre-fetches x5 address information from the cache for each external device, so as to realize data transmission between the external device and the cache according to the address information.

[0112] In some embodiments, the process of determining the fifth prefetch number of the plurality of SOC controllers according to the fourth prefetch number in S502 can include: The fifth prefetch number of the plurality of SOC controllers is calculated according to the data transmission rate of the plurality of external devices and the fourth prefetch number.

[0113] In this embodiment, since the plurality of external devices are hung under different SOC controllers, the data transmission rates between each other are different, for example, the PCIE controller and the SD controller have a large difference in rate, and in the case of ensuring that the total number of transmission prefetches is unchanged, a larger prefetch number can be allocated to the controller with a high rate, and a smaller prefetch number can be allocated to the controller with a low rate.

[0114] According to the data transmission rate between the plurality of external devices and the plurality of controllers, the weight of the plurality of external devices is calculated, and the fifth prefetch number x5 of the plurality of SOC controllers is determined according to the weight of the plurality of external devices and the fourth prefetch number x4.

[0115] For example, the external device a is a PCIE3.0X1 device with a rate of 8Gbps, and the external device B is a USB3.0 device with a rate of 5Gbps. In the case of ensuring that the total number of transmission prefetches is unchanged, the data request is as evenly distributed on the bus as possible, and the data prefetch number ratio of the external device a and the external device b can be configured to 8:5 according to the rate comparison of 8G:5G.

[0116] The data transmission method provided by the above embodiment can also determine the optimal prefetch number of address information between each SOC controller and the corresponding external device in the case of a plurality of SOC controllers respectively hung with a plurality of different external devices, avoid too small prefetch number leading to discontinuous data transmission, or too large prefetch number leading to data back pressure on the data channel, causing data congestion, and improve data transmission efficiency.

[0117] Figure 12 The data transmission timing diagram based on the SOC controller provided by the embodiment of the present application is shown in Figure 12 As shown, x+1 address information is prefetched through the address bus, and a plurality of data blocks are sequentially transmitted through the data bus. When response 0 is received, address 0 is discarded, and address x+1 is obtained. When response 1 is received, address 1 is discarded, and address x+2 is obtained. In this way, the total number of address prefetches is ensured to be x+1. It can be seen that in this process, the transmission of data blocks is continuous, which improves the data transmission efficiency.

[0118] Further, the calculation formulas of the third prefetch quantity x3 and the fourth prefetch quantity x4 are pre-configured into the SOC controller or the SOC chip, wherein the bus clock frequency F, the total data transmission delay A, the clock cycle number B, and the single transmission data length L are known values, which can be read through corresponding configuration registers, the number n of the external devices, and the data transmission rate can be determined by detecting the mounting condition of the external devices, and the corresponding address information prefetch quantity is allocated to each external device, that is, the address information prefetch quantity can be automatically updated according to the number of the external devices and the different data transmission rates.

[0119] On the basis of the method embodiments, the embodiments of the present application further provide a data transmission device applied to a data transmission controller. Figure 13 A structural schematic diagram of the data transmission device provided by the embodiments of the present application is shown in FIG. 1. Figure 13 As shown in FIG. 1, the device can include: An addressing information acquisition module 601, configured to acquire a preset number of addressing information through an addressing bus; A data block sending module 602, configured to sequentially analyze each addressing information, acquire and send a data block corresponding to each addressing information through a data bus according to a source address and a destination address of each addressing information; The addressing information acquisition module 601 is further configured to discard each addressing information according to each response information received through a response bus, and acquire new addressing information through the addressing bus, wherein each response information is a response after each data block is sent.

[0120] Optionally, the addressing information acquisition module 601 is further configured to acquire one new addressing information through the addressing bus each time one addressing information is discarded, so that the number of the addressing information remains unchanged.

[0121] Optionally, if the data transmission controller is a DMA controller, the addressing information is descriptor information, and the addressing information acquisition module 601 is specifically configured to acquire a first descriptor information through a descriptor bus, acquire a clock frequency of the DMA controller, a total number of clock cycles of the DMA controller for transmitting a preset length of data, and a single data transmission length of the first descriptor information, calculate a first prefetch quantity according to the clock frequency, the total number of clock cycles, and the single data transmission length, and acquire the remaining descriptor information through the descriptor bus according to the first prefetch quantity.

[0122] Optionally, the addressing information acquisition module 601 is further configured to discard the first descriptor information according to a current response information received through the response bus, calculate a second prefetch quantity according to a single data transmission length of a second descriptor information currently analyzed, determine a to-be-acquired quantity according to a remaining quantity of the first descriptor information after the first descriptor information is discarded according to the first prefetch quantity and the second prefetch quantity, and acquire new descriptor information of the to-be-acquired quantity through the descriptor bus according to the to-be-acquired quantity.

[0123] Optionally, if the data transmission controller is one SOC controller, the SOC controller communicates with the plurality of external devices through the communication bus, the addressing information is address information, and the addressing information acquisition module 601 is specifically configured to calculate a third prefetch quantity according to a bus clock frequency of the communication bus, a total data transmission delay, a clock cycle number of single data transmission, a single data transmission length, and a number of the external devices; and acquire a plurality of address information of each external device through the address bus according to the third prefetch quantity.

[0124] Optionally, if the data transmission controller is a plurality of SOC controllers, the plurality of SOC controllers respectively communicate with the plurality of external devices through the communication bus one by one, the addressing information is address information, and the addressing information acquisition module 601 is specifically configured to calculate a fourth prefetch quantity according to a bus clock frequency of the communication bus, a total data transmission delay, a clock cycle number of single data transmission, and a single data transmission length; determine a fifth prefetch quantity of the plurality of SOC controllers according to the fourth prefetch quantity; and acquire a plurality of address information of each SOC controller through the address bus according to the fifth prefetch quantity.

[0125] Optionally, the addressing information acquisition module 601 is further configured to calculate the fifth prefetch quantity of the plurality of SOC controllers according to a data transmission rate of the plurality of external devices and the fourth prefetch quantity.

[0126] The apparatus is used for executing the method provided by the foregoing embodiments, and has similar implementation principles and technical effects, which are not described in detail here.

[0127] The modules can be one or more integrated circuits configured to implement the above method, for example, one or more application specific integrated circuits (ASICs), or one or more microprocessors, or one or more field programmable gate arrays (FPGAs), etc. For another example, when a certain module above is implemented in the form of a processing element scheduling code, the processing element can be a general-purpose processor, for example, a central processing unit (CPU) or other processor that can invoke program code. For another example, the modules can be integrated together in the form of a system on a chip (SOC).

[0128] Figure 14 A schematic diagram of the data transmission controller provided by the embodiments of the present application is shown in FIG. 1. Figure 14As shown, the data transmission controller 700 can include a processor 701, a storage medium 702 and a bus, the storage medium 702 stores program instructions executable by the processor 701, when the data transmission controller 700 is running, the processor 701 and the storage medium 702 communicate through the bus, the processor 701 executes the program instructions to perform the above method embodiments. The specific implementation and technical effects are similar, and will not be repeated here.

[0129] Optionally, the present application also provides a computer readable storage medium, the storage medium stores a computer program, the computer program is executed by a processor to perform the above method embodiments.

[0130] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0131] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0132] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware, or in the form of hardware plus software functional unit.

[0133] The integrated unit in the form of software function unit can be stored in a computer readable storage medium. The software function unit is stored in a storage medium, and includes a plurality of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute part of steps of the method described in various embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various storage medium capable of storing program codes.

[0134] The above merely describes the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data transmission method, characterized by, The method is applied to a data transmission controller and comprises the following steps: acquiring a preset number of addressing information through an addressing bus; sequentially analyzing each piece of the addressing information, acquiring and sending a data block corresponding to each piece of the addressing information through a data bus according to a source address and a destination address of each piece of the addressing information; discarding each piece of the addressing information according to each piece of response information received through a response bus, and acquiring new addressing information through the addressing bus, each piece of the response information being a response after each piece of the data block is sent.

2. The method of claim 1, wherein, The step of acquiring the new addressing information through the addressing bus comprises the following steps: acquiring one piece of the new addressing information through the addressing bus each time one piece of the addressing information is discarded, so that the number of the addressing information remains unchanged.

3. The method of claim 1, wherein, If the data transmission controller is a DMA controller and the addressing information is descriptor information, the step of acquiring the preset number of addressing information through the addressing bus comprises the following steps: acquiring a first descriptor information through a descriptor bus; acquiring a clock frequency of the DMA controller, a total number of clock cycles of the DMA controller in transmitting data of a preset length, and a single data transmission length of the first descriptor information; calculating a first prefetch number according to the clock frequency, the total number of clock cycles, and the single data transmission length; acquiring remaining descriptor information through the descriptor bus according to the first prefetch number.

4. The method of claim 3, wherein, The step of discarding each piece of the addressing information according to each piece of response information received through the response bus and acquiring new addressing information through the addressing bus comprises the following steps: discarding the first descriptor information according to a current piece of response information received through the response bus; calculating a second prefetch number according to a single data transmission length of a second descriptor information currently analyzed; determining a to-be-prefetched number according to a remaining number of the first descriptor information after the first descriptor information is discarded according to the first prefetch number and the second prefetch number; acquiring new descriptor information of the to-be-prefetched number through the descriptor bus according to the to-be-prefetched number.

5. The method of claim 1, wherein, If the data transmission controller is a SOC controller and the SOC controller communicates with a plurality of external devices through a communication bus, the addressing information is address information, and the step of acquiring the preset number of addressing information through the addressing bus comprises the following steps: calculating a third prefetch number according to a bus clock frequency of the communication bus, a total data transmission delay, a number of clock cycles of single data transmission, a single data transmission length, and a number of the external devices; acquiring a plurality of pieces of the address information of each of the external devices through an address bus according to the third prefetch number.

6. The method of claim 1, wherein, If the data transmission controller is a plurality of SOC controllers and the plurality of SOC controllers respectively communicate with a plurality of external devices through a communication bus, the addressing information is address information, and the step of acquiring the preset number of addressing information through the addressing bus comprises the following steps: calculating a fourth prefetch number according to a bus clock frequency of the communication bus, a total data transmission delay, a number of clock cycles of single data transmission, and a single data transmission length; determining a fifth prefetch number of the plurality of SOC controllers according to the fourth prefetch number; and According to the fifth prefetch quantity, a plurality of address information of each SOC controller is obtained through an address bus.

7. The method of claim 6, wherein, The fifth prefetch quantity of the plurality of SOC controllers is determined according to the fourth prefetch quantity, comprising: According to the data transmission rate of the plurality of external devices and the fourth prefetch quantity, the fifth prefetch quantity of the plurality of SOC controllers is calculated.

8. A data transmission apparatus, characterized by comprising: The device is applied to a data transmission controller, and comprises: An addressing information acquisition module is configured to obtain a preset number of addressing information through an addressing bus; A data block sending module is configured to sequentially analyze each addressing information, and obtain and send a data block corresponding to each addressing information through a data bus according to a source address and a destination address of each addressing information. The addressing information acquisition module is further configured to discard each addressing information according to each response information received through a response bus, and obtain new addressing information through the addressing bus, wherein each response information is a response after each data block is sent.

9. A data transmission controller, characterized in that Comprise: A processor, a storage medium and a bus, the storage medium stores program instructions executable by the processor, when the data transmission controller is running, the processor and the storage medium communicate through the bus, the processor executes the program instructions to execute the steps of the data transmission method as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the computer program is executed by the processor to execute the steps of the data transmission method as claimed in any one of claims 1 to 7.

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