AXI bus interleaved data recovery methods, devices, storage media, and electronic equipment

Abstract

This application discloses an AXI bus interleaved data recovery method, apparatus, storage medium, and electronic device. The AXI bus interleaved data recovery method includes: establishing a node pool with a preset depth; upon receiving a read transaction request, selecting an idle node from the node pool based on a first transaction identifier of the read transaction request and updating the corresponding main linked list; upon receiving read return data, searching for the corresponding address chain tail node in the node pool based on a second transaction identifier of the read return data to determine the data write address, and performing an address chain update operation upon completion of the read return data transmission; and upon receiving a transaction completion response, releasing the corresponding node in the main linked list based on a third transaction identifier of the transaction completion response. This application can improve hardware resource utilization efficiency.

Description

Technical Field

[0001] This application relates to the field of on-chip system bus management technology, specifically to an AXI bus interleaved data recovery method, apparatus, storage medium, and electronic device. Background Technology

[0002] As on-chip system complexity increases, the Advanced eXtensible Interface (AXI) bus, with its support for multi-identity concurrency and out-of-order returns, has become crucial for improving system throughput. However, this mechanism requires the data receiver to correctly sort and recover the interleaved data, a requirement that is particularly prominent in multi-channel, high-concurrency scenarios, becoming a key technical challenge restricting system performance and resource efficiency.

[0003] The current mainstream solution adopts a static resource allocation strategy based on identity identifiers. Specifically, each identity identifier is allocated an independent first-in-first-out queue or address pointer queue. When data is returned, it is written to the corresponding queue according to its identity identifier and read in the order the command was issued, thereby achieving data recovery.

[0004] However, in the current solution, because the identity identifier is statically bound to the storage resources, it is impossible to dynamically schedule according to the actual load, resulting in low resource utilization. Summary of the Invention

[0005] This application provides an AXI bus interleaved data recovery method, apparatus, storage medium, and electronic device, which can improve hardware resource utilization efficiency.

[0006] In a first aspect, embodiments of this application provide an AXI bus interleaved data recovery method, including:

[0007] Establish a node pool with a preset depth;

[0008] When a read transaction request is received, an idle node is selected from the node pool based on the first transaction identifier of the read transaction request, and the corresponding main linked list is updated.

[0009] When read return data is received, the corresponding address chain tail node is searched in the node pool according to the second transaction identifier of the read return data to determine the data write address, and the address chain update operation is performed when the read return data transmission is completed.

[0010] When a transaction completion response is received, the corresponding node in the main linked list is released based on the third transaction identifier of the transaction completion response.

[0011] In the AXI bus interleaved data recovery method provided in this application embodiment, updating the corresponding main linked list includes:

[0012] Based on the first transaction identifier, determine whether a corresponding main linked list exists in the node pool;

[0013] If it does not exist, the corresponding pointer of the free node is updated so that the free node is used as the corresponding main linked list;

[0014] If it exists, the free node is connected to the tail of the corresponding main linked list, and the corresponding pointer is updated.

[0015] In the AXI bus interleaved data recovery method provided in this application embodiment, updating the corresponding pointer of the idle node includes:

[0016] Set the head pointer, tail pointer, and address chain tail pointer of the free node to valid;

[0017] Set the transaction identifier field of the idle node to the first transaction identifier.

[0018] In the AXI bus interleaved data recovery method provided in this application embodiment, the step of connecting the idle node to the tail of the main linked list and updating the corresponding pointer includes:

[0019] The tail pointer of the tail node corresponding to the first transaction identifier is invalidated, and the next node index of the tail node is set to the idle node, so as to set the idle node as the new tail node.

[0020] In the AXI bus interleaved data recovery method provided in this application embodiment, the step of determining the corresponding address chain tail node based on the second transaction identifier of the read return data to determine the data write address includes:

[0021] Based on the second transaction identifier of the read returned data, the corresponding address chain tail node is found in the node pool;

[0022] Write the index of the tail node of the address chain as data into the address.

[0023] In the AXI bus interleaved data recovery method provided in this application embodiment, the step of performing an address chain update operation when the read return data transmission is completed includes:

[0024] When it is determined that the read return data transmission is complete, the address chain tail flag of the corresponding address chain tail node is set to invalid;

[0025] Based on the index of the next node of the address chain tail node, the address chain tail marker of the next node is set to valid.

[0026] In the AXI bus interleaved data recovery method provided in this application embodiment, the step of releasing the corresponding node in the main linked list according to the third transaction identifier of the transaction completion response includes:

[0027] Based on the third transaction identifier, the node with the head mark in the corresponding main linked list is taken as the head node to be released;

[0028] Clear the header tag and valid bits of the header node to be released to release the node;

[0029] If the head node to be released is not the tail node of the corresponding main linked list, then the node pointed to by the next node index of the head node to be released is set as the new head node of the corresponding main linked list.

[0030] Secondly, embodiments of this application provide an AXI bus interleaved data recovery device, comprising:

[0031] A creation unit is used to create a node pool with a preset depth;

[0032] The request unit is used to select an idle node from the node pool based on the first transaction identifier of the read transaction request when a read transaction request is received, and update the corresponding main linked list.

[0033] The return unit is used to, when receiving read return data, search for the corresponding address chain tail node in the node pool according to the second transaction identifier of the read return data to determine the data write address, and perform an address chain update operation when the read return data transmission is completed;

[0034] The release unit is used to release the corresponding node in the main linked list according to the third transaction identifier of the transaction completion response when a transaction completion response is received.

[0035] Thirdly, this application provides a storage medium storing a plurality of instructions adapted for loading by a processor to execute the AXI bus interleaved data recovery method described in any of the preceding claims.

[0036] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the AXI bus interleaved data recovery method described in any of the preceding claims.

[0037] In summary, the AXI bus interleaved data recovery method provided in this application includes establishing a node pool with a preset depth; when a read transaction request is received, an idle node is selected from the node pool based on the first transaction identifier of the read transaction request, and the corresponding main linked list is updated; when read return data is received, the corresponding address chain tail node is searched in the node pool according to the second transaction identifier of the read return data to determine the data write address, and an address chain update operation is performed when the read return data transmission is completed; when a transaction completion response is received, the corresponding node in the main linked list is released according to the third transaction identifier of the transaction completion response. This application embodiment can improve hardware resource utilization efficiency. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram illustrating an application scenario of the AXI bus interleaved data recovery method provided in this application embodiment.

[0040] Figure 2 This is a flowchart illustrating the AXI bus interleaved data recovery method provided in this application embodiment.

[0041] Figure 3 This is a schematic diagram of the structure of the AXI bus interleaved data recovery device provided in the embodiments of this application.

[0042] Figure 4 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0043] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0044] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0045] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0046] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0047] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0048] As on-chip system complexity increases, the Advanced Scalable Interface Bus (ASME) has become crucial for improving system throughput due to its support for concurrent multi-identity and out-of-order returns. However, this mechanism requires the data receiver to correctly sort and recover the interleaved data, a requirement that is particularly prominent in multi-channel, high-concurrency scenarios, becoming a key technical challenge restricting system performance and resource efficiency.

[0049] The current mainstream solution adopts a static resource allocation strategy based on identity identifiers. Specifically, each identity identifier is allocated an independent first-in-first-out queue or address pointer queue. When data is returned, it is written to the corresponding queue according to its identity identifier and read in the order the command was issued, thereby achieving data recovery.

[0050] However, such solutions have significant shortcomings: first, hardware resource overhead is linearly related to the number of identities, leading to a large amount of idle and wasted storage resources; second, identities are statically bound to storage resources, making dynamic scheduling based on actual load impossible, resulting in low resource utilization; and third, the control logic becomes drastically more complex as the number of identities increases, increasing the difficulty of system timing convergence and creating performance bottlenecks. Therefore, a solution that can decouple resource overhead from the number of identities and balance recovery correctness with resource efficiency is urgently needed.

[0051] Based on this, embodiments of this application provide an AXI bus interleaved data recovery method, apparatus, storage medium, and electronic device. Specifically, the AXI bus interleaved data recovery apparatus can be integrated into an electronic device, which can be a server or a terminal, etc. The terminal can include mobile phones, wearable smart devices, tablets, laptops, and personal computers (PCs), etc., as well as other computers and auxiliary devices. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0052] For example, such as Figure 1 As shown, the electronic device can establish a node pool with a preset depth. When a read transaction request is received, an idle node is selected from the node pool based on the first transaction identifier of the read transaction request, and the corresponding main linked list is updated. When read return data is received, the corresponding address chain tail node is searched in the node pool according to the second transaction identifier of the read return data to determine the data write address, and the address chain update operation is performed when the read return data transmission is completed. When a transaction completion response is received, the corresponding node in the main linked list is released according to the third transaction identifier of the transaction completion response.

[0053] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0054] Please see Figure 2 , Figure 2 This is a flowchart illustrating the AXI bus interleaved data recovery method provided in this embodiment. The specific flow of the AXI bus interleaved data recovery method is as follows:

[0055] 101. Establish a node pool with a preset depth.

[0056] The preset depth refers to the total number of nodes in the node pool. In this embodiment, the preset depth is typically determined based on the maximum number of outstanding read transactions supported by the electronic device, thereby ensuring that the size of the node pool can meet the system's maximum concurrent processing capacity requirements, while guaranteeing that the overhead of hardware resources is independent of the total number of transaction identifiers supported by the bus.

[0057] In this embodiment of the application, each node in the node pool is a logical storage unit used to store and manage information related to an ongoing read transaction.

[0058] Specifically, each node may include the following key fields:

[0059] Transaction Identifier Field: Used to store the transaction identifier of the read transaction currently being served by this node.

[0060] Valid bit: Used to indicate whether the node is currently occupied. When the valid bit is in the first state (e.g., logic "1"), it means the node is idle and available; when it is in the second state (e.g., logic "0"), it means the node is occupied.

[0061] Head marker: Serves as the head pointer of the main linked list, indicating whether the node is the starting node of the main linked list corresponding to a certain transaction identifier.

[0062] Tail marker: Serves as the tail pointer of the main linked list, indicating whether the node is the end node of the main linked list corresponding to a certain transaction identifier.

[0063] Address chain tail marker: As the tail pointer of an independent address chain, it is specifically used during the data return phase to indicate the node corresponding to the data storage address that the transaction should currently use.

[0064] Next node index: Points to the position index of the next node after the current node in the main linked list corresponding to the same transaction identifier.

[0065] The node pool can be physically implemented using an on-chip static random access memory (SRAM) and peripheral control logic. During initialization, all valid bits of all nodes are set to idle, and their header, tail, and address chain tail markers are invalidated. The next node index can be any value. Electronic devices can quickly find available idle nodes by maintaining a list of idle nodes or by traversing the valid bits.

[0066] 102. When a read transaction request is received, an idle node is selected from the node pool based on the first transaction identifier of the read transaction request, and the corresponding main linked list is updated.

[0067] When a read transaction request carrying a first transaction identifier appears on the command path of the Advanced Extensible Interface, the electronic device can dynamically manage its corresponding transaction sequence linked list, i.e., the main linked list, based on the first transaction identifier.

[0068] First, a node with a valid bit indicating it is idle can be selected as the idle node. Then, based on the first transaction identifier, it is determined whether a corresponding main linked list exists in the node pool. This determination can be made by checking if a node exists whose transaction identifier field is the first transaction identifier and whose valid bit indicates it is in an occupied state.

[0069] If no corresponding main linked list exists, this indicates that the currently received data is the first incomplete read transaction under this first transaction identifier. In this case, the corresponding pointers of the idle node need to be updated to initialize the idle node with the main linked list corresponding to this first transaction identifier.

[0070] Specifically, we can first set the head pointer, tail pointer, and address chain tail pointer of the idle node to valid, thus making the idle node the head node, tail node of the main linked list, and tail node of the address chain simultaneously. Then, we set the transaction identifier field of the idle node to the first transaction identifier. Finally, we set the valid position of the idle node to occupied. At this point, a new main linked list containing only a single node and its corresponding independent address chain are constructed.

[0071] If a corresponding main linked list exists, this indicates that there are already incomplete transactions under this first transaction identifier, and newly arriving read transactions need to be linked sequentially to the end of the existing main linked list. At this point, it is necessary to connect the free node to the end of the corresponding main linked list and update the corresponding pointer.

[0072] Specifically, first, the tail node of the main linked list corresponding to the first transaction identifier can be found in the node pool. This tail node is characterized by its transaction identifier field being the first transaction identifier and its tail tag being valid. Then, the tail tag of the tail node is invalidated, because at this point, the tail node is no longer the end of the main linked list. Next, the index of the next node of the tail node is set to point to the free node, thus establishing a linked list connection. Finally, the free node is configured as follows: its head tag is invalidated (because this node is not the head node of the main linked list), its tail tag and address chain tail tag are valid, its transaction identifier field is set to the first transaction identifier, and its valid position is set to occupied. At this point, the free node becomes the new tail node of the main linked list and the new address chain tail node.

[0073] In other words, the step "update the corresponding main linked list" may specifically include: determining whether the corresponding main linked list exists in the node pool based on the first transaction identifier; if it does not exist, updating the corresponding pointers of the idle nodes to make the idle nodes the corresponding main linked list; if it exists, connecting the idle nodes to the tail of the corresponding main linked list and updating the corresponding pointers.

[0074] The step "update the corresponding pointers of the idle node" may include: setting the head pointer, tail pointer, and address chain tail pointer of the idle node to valid; and setting the transaction identifier field of the idle node to the first transaction identifier.

[0075] The step "connecting the idle node to the tail of the main linked list and updating the corresponding pointer" may include: invalidating the tail pointer of the tail node corresponding to the first transaction identifier and pointing the next node index of the tail node to the idle node, so as to set the idle node as the new tail node.

[0076] In this embodiment, the main linked list can grow dynamically as read transaction requests arrive, strictly maintaining the initiation order of multiple read transactions under the same transaction identifier.

[0077] 103. When read return data is received, the corresponding address chain tail node is searched in the node pool according to the second transaction identifier of the read return data to determine the data write address, and the address chain update operation is performed when the read return data transmission is completed.

[0078] Understandably, when there is read return data carrying a second transaction identifier on the read data return path of the advanced extensible interface, it is necessary to provide the correct data write address for the read return data and manage a separate address chain for address allocation.

[0079] In the specific implementation process, it can be divided into two stages:

[0080] First, determine the data write address. Based on the second transaction identifier of the read return data, find the corresponding tail node in the node pool. The search criteria are: the node's address chain tail marker is valid, and its transaction identifier field is the second transaction identifier. This tail node is the node that should currently receive the read return data. Then, use the index of this tail node (i.e., its position in the node pool) as the data write address. The data write logic can then store the read return data into the corresponding storage location based on this data write address.

[0081] That is, the step "determine the corresponding address chain tail node based on the second transaction identifier of the read returned data, so as to determine the data write address" may include: searching for the corresponding address chain tail node in the node pool based on the second transaction identifier of the read returned data; and using the index of the address chain tail node as the data write address.

[0082] Then, the address chain update operation is performed. It is understood that data from a single read transaction may be returned over multiple cycles. In some embodiments, this can be achieved by determining whether the currently returned read data indicates that the read transaction has been completed. This is typically done by detecting the validity of a "last transfer" signal (e.g., the RLAST signal) on the bus. When it is determined that the read return data transmission is complete, the address chain needs to be updated to allocate a new data write address for the next read return data to be returned for the same transaction identifier.

[0083] The address chain update operation can specifically include: setting the address chain tail flag of the current address chain tail node to invalid; finding the next node in the main linked list based on the next node index of the current address chain tail node; and setting the address chain tail flag of that next node to valid, making it the new address chain tail node.

[0084] That is, the step "when the read return data transmission is complete, perform the address chain update operation" may include: when it is determined that the read return data transmission is complete, setting the address chain tail mark of the corresponding address chain tail node to invalid; and setting the address chain tail mark of the next node to valid according to the next node index of the address chain tail node.

[0085] It should be noted that if the current address chain tail node also happens to be the tail node of its main linked list (i.e., its tail mark is valid), this means that there are no subsequent unfinished transactions under this second transaction identifier. In this case, the address chain update operation will only perform the step of clearing the current node's address chain tail mark, and will not perform the operation of setting the next node's address chain tail mark, because there is no valid next node.

[0086] 104. When a transaction completion response is received, release the corresponding node in the main linked list according to the third transaction identifier in the transaction completion response.

[0087] It is understandable that when the upper-level consumer of a transaction (such as a processor core or direct memory access controller) finishes consuming the data returned by a read under a certain transaction identifier, it will send a transaction completion response carrying a third transaction identifier. Based on this third transaction identifier, the node resources occupied by the corresponding transaction will be reclaimed to achieve the reuse of the node pool.

[0088] In some embodiments, the step "releasing the corresponding node in the main linked list based on the third transaction identifier of the transaction completion response" may include:

[0089] First, based on the third transaction identifier, the node with the head mark in the corresponding main linked list is designated as the head node to be released. This head node represents the earliest transaction issued under this third transaction identifier that has not yet been consumed by the upper layer.

[0090] Next, the header flag and valid bit of the head node to be released are cleared to release the node. That is, the valid bit of the head node to be released is set to "free", so that the node can be reallocated by the node pool, marking that the node and its stored resources have been released.

[0091] Then, by checking the tail marker of the head node to be released, it is determined whether to update the new head node of the main linked list.

[0092] Specifically, if the head node to be released is not the tail node of the corresponding main linked list (i.e., its tail tag is invalid), it means that there are still subsequent unfinished transactions under this second transaction identifier. In this case, it is necessary to find the node pointed to by the next node index of the head node to be released, and set the head tag of that node to be valid, making it the new head node of the main linked list. That is, if the head node to be released is not the tail node of the corresponding main linked list, then the node pointed to by the next node index of the head node to be released is set as the new head node of the corresponding main linked list.

[0093] If the head node to be released is the tail node of the corresponding main linked list (i.e., its tail marker is valid), then this transaction is the last incomplete transaction under this second transaction identifier. After the node is released, the main linked list corresponding to this second transaction identifier will become empty. Therefore, no node needs to be set as the new head node.

[0094] In this embodiment, by repeatedly executing steps 102 to 104 above, a node pool with a fixed depth and a size independent of the total number of transaction identifiers is used in the advanced scalable interface bus scenario with multiple transaction identifiers and out-of-order data return. This is combined with dual collaborative management of the main linked list and independent address chain to dynamically, correctly, and efficiently complete the recovery of interleaved data and resource reuse.

[0095] In summary, the AXI bus interleaved data recovery method provided in this application includes establishing a node pool with a preset depth; when a read transaction request is received, an idle node is selected from the node pool based on the first transaction identifier of the read transaction request, and the corresponding main linked list is updated; when read return data is received, the corresponding address chain tail node is searched in the node pool according to the second transaction identifier of the read return data to determine the data write address, and the address chain update operation is performed when the read return data transmission is completed; when a transaction completion response is received, the corresponding node in the corresponding main linked list is released according to the third transaction identifier of the transaction completion response. This application embodiment, by establishing a node pool decoupled from the number of transaction identifiers and only linked to the actual concurrency depth, and adopting a dual-chain collaborative mechanism of the main linked list and independent address chains, achieves dynamic allocation and efficient reuse of storage resources. This reduces hardware resource overhead from a linear increase proportional to the number of identifiers in traditional schemes to a constant level only related to concurrency depth. While ensuring correct recovery of out-of-order data with multiple identifiers, it significantly improves the utilization rate of on-chip storage resources, reduces system costs, and enhances the scalability of the solution in high-concurrency interleaved scenarios. In other words, the embodiments of this application can improve the efficiency of hardware resource utilization.

[0096] To facilitate better implementation of the AXI bus interleaved data recovery method provided in this application, this application also provides an AXI bus interleaved data recovery apparatus. The meanings of the terms used are the same as in the AXI bus interleaved data recovery method described above, and specific implementation details can be found in the descriptions within the method embodiments.

[0097] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of the AXI bus interleaved data recovery device provided in an embodiment of this application. The AXI bus interleaved data recovery device may include an establishment unit 201, a request unit 202, a return unit 203, and a release unit 204.

[0098] Establishment unit 201 is used to establish a node pool with a preset depth;

[0099] The request unit 202 is used to select an idle node from the node pool based on the first transaction identifier of the read transaction request when a read transaction request is received, and update the corresponding main linked list.

[0100] The return unit 203 is used to, when receiving read return data, search for the corresponding address chain tail node in the node pool according to the second transaction identifier of the read return data to determine the data write address, and perform an address chain update operation when the read return data transmission is completed;

[0101] Release unit 204 is used to release the corresponding node in the main linked list according to the third transaction identifier of the transaction completion response when a transaction completion response is received.

[0102] For specific implementation methods of each of the above units, please refer to the embodiments of the AXI bus interleaved data recovery method described above, which will not be repeated here.

[0103] In summary, the AXI bus interleaved data recovery device provided in this application embodiment can establish a node pool with a preset depth through the establishment unit 201; when the request unit 202 receives a read transaction request, it selects an idle node from the node pool based on the first transaction identifier of the read transaction request and updates the corresponding main linked list; when the return unit 203 receives read return data, it searches for the corresponding address chain tail node in the node pool according to the second transaction identifier of the read return data to determine the data write address, and performs an address chain update operation when the read return data transmission is completed; when the release unit 204 receives a transaction completion response, it releases the corresponding node in the corresponding main linked list according to the third transaction identifier of the transaction completion response. This application embodiment can improve the utilization rate of hardware resources.

[0104] This application also provides an electronic device that may integrate the AXI bus interleaved data recovery device of this application, such as... Figure 4 As shown, it illustrates a structural schematic diagram of the electronic device involved in the embodiments of this application, specifically:

[0105] The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art will understand that... Figure 4 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein:

[0106] The processor 301 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs stored in the memory 302 and / or this application, and by calling data stored in the memory 302, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operation of the storage medium, user interface, and application programs, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 301.

[0107] The memory 302 can be used to store software programs and this application. The processor 301 executes various functional applications and data processing by running the software programs and this application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area. The program storage area may store applications required for operating the storage medium and at least one function; the data storage area may store data created based on the use of the electronic device. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0108] Although not shown, the electronic device may also include a display unit, an input unit, and a power supply, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 301 in the electronic device loads the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 runs the application programs stored in the memory 302 to realize various functions, as follows:

[0109] Establish a node pool with a preset depth;

[0110] When a read transaction request is received, an idle node is selected from the node pool based on the first transaction identifier of the read transaction request, and the corresponding main linked list is updated.

[0111] When read return data is received, the corresponding address chain tail node is searched in the node pool according to the second transaction identifier of the read return data to determine the data write address, and the address chain update operation is performed when the read return data transmission is completed.

[0112] When a transaction completion response is received, the corresponding node in the main linked list is released based on the third transaction identifier in the transaction completion response.

[0113] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0114] Therefore, embodiments of this application provide a storage medium storing a plurality of instructions that can be loaded by a processor to execute steps in any of the methods provided in embodiments of this application. For example, the instructions can execute the following steps:

[0115] Establish a node pool with a preset depth;

[0116] When a read transaction request is received, an idle node is selected from the node pool based on the first transaction identifier of the read transaction request, and the corresponding main linked list is updated.

[0117] When read return data is received, the corresponding address chain tail node is searched in the node pool according to the second transaction identifier of the read return data to determine the data write address, and the address chain update operation is performed when the read return data transmission is completed.

[0118] When a transaction completion response is received, the corresponding node in the main linked list is released based on the third transaction identifier in the transaction completion response.

[0119] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0120] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0121] Since the instructions stored in the storage medium can execute the steps of any method provided in the embodiments of this application, the beneficial effects that any method provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.

[0122] The foregoing has provided a detailed description of the AXI bus interleaved data recovery method, apparatus, storage medium, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An AXI bus interleaved data recovery method, characterized in that, The method comprises the steps of: establishing a node pool with a preset depth; when a read transaction request is received, selecting an idle node from the node pool based on a first transaction identifier of the read transaction request, and determining whether a corresponding main chain table exists in the node pool according to the first transaction identifier; if not, setting the head pointer, tail pointer and address chain tail pointer of the idle node as valid, setting the transaction identifier field of the idle node as the first transaction identifier, and taking the idle node as the corresponding main chain table; if yes, setting the tail pointer of the tail node corresponding to the first transaction identifier as invalid, and pointing the next node index of the tail node to the idle node, so as to set the idle node as a new tail node; when read return data is received, searching for a corresponding address chain tail node in the node pool according to a second transaction identifier of the read return data, so as to determine a data write address, and performing an address chain update operation when the read return data transmission is completed; when a transaction completion response is received, releasing a corresponding node in the corresponding main chain table according to a third transaction identifier of the transaction completion response.

2. The AXI bus interleaved data recovery method of claim 1, wherein, The method further comprises the steps of: searching for the corresponding address chain tail node in the node pool according to the second transaction identifier of the read return data; taking the index of the address chain tail node as the data write address.

3. The AXI bus interleaved data recovery method of claim 1, wherein, The method further comprises the steps of: when it is determined that the read return data transmission is completed, setting the address chain tail marker of the corresponding address chain tail node as invalid; setting the address chain tail marker of the next node as valid according to the next node index of the address chain tail node.

4. The AXI bus interleaved data recovery method of claim 1, wherein, The method further comprises the steps of: taking the node with the head marker in the corresponding main chain table as a to-be-released head node according to the third transaction identifier; clearing the head marker and valid bit of the to-be-released head node, so as to release the node; if the to-be-released head node is not the tail node of the corresponding main chain table, setting the node pointed to by the next node index of the to-be-released head node as a new head node of the corresponding main chain table.

5. An AXI bus interleaved data recovery apparatus, characterized by, The method comprises the steps of: establishing a node pool with a preset depth by a establishing unit; when a read transaction request is received, selecting an idle node from the node pool based on a first transaction identifier of the read transaction request by a request unit, and determining whether a corresponding main chain table exists in the node pool according to the first transaction identifier; if not, setting the head pointer, tail pointer and address chain tail pointer of the idle node as valid, setting the transaction identifier field of the idle node as the first transaction identifier, and taking the idle node as the corresponding main chain table; if yes, setting the tail pointer of the tail node corresponding to the first transaction identifier as invalid, and pointing the next node index of the tail node to the idle node, so as to set the idle node as a new tail node; when read return data is received, searching for a corresponding address chain tail node in the node pool according to a second transaction identifier of the read return data, so as to determine a data write address, and performing an address chain update operation when the read return data transmission is completed. The returning unit is configured to, when receiving read return data, find a corresponding address chain tail node in the node pool according to a second transaction identifier of the read return data, to determine a data write address, and perform an address chain updating operation when transmission of the read return data is completed. The releasing unit is configured to, when receiving a transaction completion response, release a corresponding node in a corresponding main chain table according to a third transaction identifier of the transaction completion response.

6. A storage medium, characterized by The storage medium stores a plurality of instructions, which are adapted to be loaded by the processor to execute the AXI bus interleaved data recovery method of any one of claims 1-4.

7. An electronic device, comprising: The computer program product comprises a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein the processor implements the AXI bus interleaved data recovery method of any one of claims 1-4 when executing the computer program.

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